Cypress CY62168EV30 16-mbit (2 m x 8) static ram automatic power-down when deselected Datasheet

CY62168EV30 MoBL®
16-Mbit (2 M × 8) Static RAM
16-Mbit (2 M × 8) Static RAM
Features
automatic power-down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (Chip Enable 1 (CE1) HIGH or
Chip Enable 2 (CE2) LOW). The input and output pins (I/O0
through I/O7) are placed in a high impedance state when: the
device is deselected (Chip Enable 1 (CE1) HIGH or
Chip Enable 2 (CE2) LOW), outputs are disabled (OE HIGH), or
a write operation is in progress (Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and WE LOW).
■
Very high speed: 45 ns
■
Wide voltage range: 2.20 V to 3.60 V
■
Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
■
Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power-down when deselected
■
CMOS for optimum speed/power
■
Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin
TSOP I package, refer to CY62167EV30 datasheet.
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through A20).
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
Functional Description
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table on page 11 for a complete description
of read and write modes.
The CY62168EV30 is a high performance CMOS static RAM
organized as 2 M words by 8-bits. This device features advanced
circuit design to provide an ultra low active current. This is ideal
for providing More Battery Life (MoBL) in portable
applications such as cellular telephones. The device also has an
Logic Block Diagram
SENSE AMPS
ROW DECODER
I/O 1
2M x 8
ARRAY
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
COLUMN DECODER
WE
POWER
DOWN
I/O 7
A18
A13
A14
A15
A16
A17
OE
Cypress Semiconductor Corporation
Document #: 001-07721 Rev. *D
I/O 0
DATA IN DRIVERS
A19
A20
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 10, 2011
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CY62168EV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Document #: 001-07721 Rev. *D
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY62168EV30 MoBL®
Pin Configuration
Figure 1. 48-ball FBGA Top View [1]
1
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
NC
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
A20
A12
A13
WE
NC
G
A18
A8
A9
A10
A11
A19
H
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62168EV30LL
Speed
(ns)
Min
Typ[2]
Max
2.2
3.0
3.6
45
Operating ICC (mA)
f = 1 MHz
Standby ISB2 (A)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
2.2
4.0
25
30
1.5
12
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document #: 001-07721 Rev. *D
Page 3 of 16
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CY62168EV30 MoBL®
DC input voltage[3, 4] .................. –0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground
potential ....................................... –0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in high Z state[3, 4] ........................–0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... > 2001 V
(MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature (TA)[5]
VCC[6]
Industrial
–40 °C to +85 °C
2.2 V to 3.6 V
DC Electrical Characteristics
Over the operating range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
CY62168EV30-45
Min
Typ[7]
Max
2.2 < VCC < 2.7
IOH = 0.1 mA
2.0
–
–
2.7 < VCC < 3.6
IOH = 1.0 mA
2.4
–
–
2.2 < VCC < 2.7
IOL = 0.1 mA
–
–
0.4
2.7 < VCC < 3.6
IOH = 2.1 mA
–
–
0.4
2.2 < VCC < 2.7
1.8
–
VCC + 0.3
2.7 < VCC < 3.6
2.2
–
VCC + 0.3
2.2 < VCC < 2.7
–0.3
–
0.6
2.7 < VCC < 3.6
–0.3
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
µA
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
µA
ICC
VCC operating supply current
f = fMAX = 1/tRC
–
25
30
mA
–
2.2
4.0
f = 1 MHz
VCC = 3.6 V,
IOUT = 0 mA,
CMOS level
ISB1[8]
Automatic CE power-down
current – CMOS inputs
CE1 > VCC  0.2 V or CE2 < 0.2 V,
VIN > VCC  0.2 V, VIN < 0.2 V,
f = fMAX (address and data only),
f = 0 (OE, WE)
–
1.5
12
µA
ISB2[8]
Automatic CE power-down
current – CMOS inputs
CE1 > VCC  0.2 V or CE2 < 0.2 V,
VIN > VCC  0.2 V or VIN < 0.2 V, f = 0,
VCC = 3.6 V
–
1.5
12
µA
Notes
3. VIL(min) = –0.2 V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. TA is the “Instant-On” case temperature.
6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 001-07721 Rev. *D
Page 4 of 16
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CY62168EV30 MoBL®
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
8
pF
10
pF
Test Conditions
48-ball FBGA
Unit
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
55
C/W
16
C/W
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter[9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC
OUTPUT
30 pF
GND
R2
90%
10%
90%
10%
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
Fall time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
16600
1103

R2
15400
1554

RTH
8000
645

VTH
1.2
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Typ[10]
Max
1.5
–
3.6
V
–
–
10
µA
Min
Unit
VDR
VCC for data retention
ICCDR[11]
Data retention current
tCDR[12]
Chip deselect to data retention
time
0
–
–
ns
tR[13]
Operation recovery time
45
–
–
ns
VCC = 1.5 V
CE1 > VCC 0.2 V or CE2 < 0.2 V
VIN > VCC 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE1
or
CE2
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min)  100 µs.
Document #: 001-07721 Rev. *D
Page 6 of 16
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CY62168EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter [14]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
5
–
ns
–
18
ns
OE LOW to low
tLZOE
Z[15]
OE HIGH to high
tHZOE
Z[15, 16]
Z[15]
tLZCE
CE1 LOW and CE2 HIGH to low
10
–
ns
tHZCE
CE1 HIGH or CE2 LOW to high Z[15, 16]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
CE1 HIGH or CE2 LOW to power-down
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z[15, 16]
–
18
ns
tLZWE
WE HIGH to low Z[15]
10
–
ns
tPD
Write Cycle
[17]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5.
15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
16. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [18, 19]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
18. The device is continuously selected. OE, CE1 = VIL, and CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [21, 22, 23]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
OE
tHD
tSD
DATA I/O
NOTE 24
VALID DATA
tHZOE
Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [21, 22, 23]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tHA
tPWE
WE
OE
DATA I/O
tAW
tSD
NOTE 24
tHD
VALID DATA
tHZOE
Notes
21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
22. Data I/O is high impedance if OE = VIH.
23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
24. During this period the I/Os are in output state. Do not apply input signals.
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [25]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 26
tHD
VALID DATA
tHZWE
tLZWE
Notes
25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period the I/Os are in output state. Do not apply input signals.
Document #: 001-07721 Rev. *D
Page 10 of 16
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CY62168EV30 MoBL®
Truth Table
CE1
WE
OE
[27]
X
X
High Z
Deselect/power-down
Standby (ISB)
[27]
L
X
X
High Z
Deselect/power-down
Standby (ISB)
L
H
H
L
Data out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
H
High Z
Output disabled
Active (ICC)
L
H
L
X
Data in (I/O0–I/O7)
Write
Active (ICC)
H
X
CE2
X
I/O
Mode
Power
Note
27. The ‘X’ (Do not care) state for the chip enables in the truth table refers to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not
permitted.
Document #: 001-07721 Rev. *D
Page 11 of 16
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CY62168EV30 MoBL®
Ordering Information
The below table lists the CY62168EV30 MoBL key package features and ordering codes. The table contains only the parts that are
currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the
Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Speed (ns)
45
Ordering Code
CY62168EV30LL-45BVXI
Package
Diagram
Package Type
51-85150 48-ball VFBGA (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 621 6
8
E V30 LL - 45 BV X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: BV = 48-ball VFBGA
Speed Grade: 45 ns
LL = Low Power
Voltage Range = 3 V typical
Process Technology: 90 nm
Bus width = × 8
Density = 16-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document #: 001-07721 Rev. *D
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CY62168EV30 MoBL®
Package Diagram
Figure 9. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150
51-85150 *F
Document #: 001-07721 Rev. *D
Page 13 of 16
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CY62168EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
FBGA
fine-pitch ball grid array
MHz
Mega Hertz
I/O
input/output
µA
micro Amperes
OE
output enable
s
micro seconds
SRAM
static random access memory
mA
milli Amperes
TSOP
thin small outline package
mm
milli meter
VFBGA
very fine-pitch ball grid array
ns
nano seconds
WE
write enable

ohms
%
percent
pF
pico Farad
V
Volts
W
Watts
Document #: 001-07721 Rev. *D
Symbol
Unit of Measure
Page 14 of 16
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CY62168EV30 MoBL®
Document History Page
Document Title: CY62168EV30 MoBL®, 16-Mbit (2 M × 8) Static RAM
Document Number: 001-07721
Rev.
ECN No.
Orig. of
Change
Issue Date
**
457686
NXR
See ECN
New Data Sheet
*A
464509
NXR
See ECN
Removed TSOP I package; Added reference to CY62167EV30 TSOP I package
which can be used as a 2 M × 8 SRAM
Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA
Changed the ICC(Typ) value from 2 mA to 2.2 mA for f=1 MHz Test condition
Changed the ICC(Typ) value from 15 mA to 22 mA and ICC(Max) value from
40 mA to 25 mA for f = 1 MHz Test condition
Changed the ICCDR(Max) value from 8.5 µA to 8 µA
*B
1138883
VKN
See ECN
Converted from preliminary to final
Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1 MHz
Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax
Changed ICC(max) spec from 25 mA to 30 mA for f=fmax
Added footnote# 8 related to ISB2 and ICCDR
Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA
Changed ICCDR spec from 8 µA to 10 µA
*C
2934385
VKN
06/03/10
Corrected typo in Functional Description section
Corrected VCC stabilization time to 200 µsec
Updated template.
Added footnote #28 related to chip enable
Updated package diagram
*D
3279426
RAME
06/10/2011
Document #: 001-07721 Rev. *D
Description of Change
Removed the Note “For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.” in page 1 and its reference
in Functional Description.
Updated Package Diagram.
Updated in new template.
Page 15 of 16
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CY62168EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07721 Rev. *D
Revised June 10, 2011
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