MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3803/3804 group is the 8-bit microcomputer based on the 740 family core technology. The 3803/3804 group is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A-D converter and D-A converters. The 3804 group is the version of the 3803 group to which an I 2CBUS control function has been added. FEATURES ●Basic machine-language instructions ...................................... 71 ●Minimum instruction execution time ................................ 0.24 µs (at 16.8 MHz oscillation frequency) ●Memory size ROM ............................................................... 16 K to 60 K bytes RAM ................................................................. 640 to 2048 bytes ●Programmable input/output ports ............................................ 56 ●Software pull-up resistors ................................................. Built-in ●Interrupts 21 sources, 16 vectors ............................................... 3803 group (external 8, internal 12, software 1) 23 sources, 16 vectors ............................................... 3804 group (external 9, internal 13, software 1) ●Timers ........................................................................... 16-bit ✕ 1 8-bit ✕ 4 (with 8-bit prescaler) ●Watchdog timer ............................................................ 16-bit ✕ 1 ●Serial I/O ...................... 8-bit ✕ 2 (UART or Clock-synchronized) 8-bit ✕ 1 (Clock-synchronized) ●PWM ............................................ 8-bit ✕ 1 (with 8-bit prescaler) ●I 2C-BUS interface (3804 group only) ........................... 1 channel ●A-D converter ............................................. 10-bit ✕ 16 channels (8-bit reading enabled) ●D-A converter ................................................. 8-bit ✕ 2 channels ●LED direct drive port .................................................................. 8 ●Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) ●Power source voltage In high-, middle-speed mode At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V At 8.38 MHz oscillation frequency) ........................ 2.7 to 5.5 V ✽ In low-speed mode At 32 kHz oscillation frequency .............................. 2.7 to 5.5 V ✽ (✽ This value of flash memory version is 4.0 to 5.5 V.) ●Power dissipation In high-speed mode ................................................ 60 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ................................................... 60 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) ●Operating temperature range .................................... –20 to 85°C ●Packages SP .................................................. 64P4B (64-pin 750 mil SDIP) FP ....................................... 64P6N-A (64-pin 14 ✕ 14 mm QFP) HP ..................................... 64P6Q-A (64-pin 10 ✕ 10 mm LQFP) <Flash memory mode> ●Supply voltage ................................................. VCC = 5 V ± 10 % ●Program/Erase voltage ........................... VPP = 11.7 V to 12.6 V ●Programming method ...................... Programming in unit of byte ●Erasing method Batch erasing ........................................ Parallel/Serial I/O mode Block erasing .................................... CPU reprogramming mode ●Program/Erase control by software command ●Number of times for programming/erasing ............................ 100 ● Operating temperature range (at programming/erasing) ........... ........................................................................ Room temperature ■Notes 1. The flash memory version cannot be used for application embedded in the MCU card. 2. Supply voltage Vcc of the flash memory version is 4.0 to 5.5 V. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER P11/INT01 P12 P13 P14 P15 P16 P17 39 38 37 36 35 34 33 P07/AN15 P10/INT41 40 P06/AN14 42 41 P04/AN12 P03/AN11 45 P05/AN13 P02/AN10 46 43 P01/AN9 47 44 P00/AN8 48 PIN CONFIGURATION (TOP VIEW) P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33 53 28 P24(LED4) P32 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT AVSS 59 22 XIN P67/AN7 60 21 P40/INT40/XCOUT P66/AN6 61 20 P41/INT00/XCIN P65/AN5 62 19 RESET P64/AN4 63 18 CNVSS VPP P63/AN3 64 17 P42/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 M38039FFFP/HP M38037M8-XXXFP/HP : Flash memory version Package type : 64P6N-A/64P6Q-A Fig. 1 3803 group pin configuration PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38039FFSP M38037M8-XXXSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 VPP CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Package type : 64P4B Fig. 2 3803 group pin configuration 2 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) : Flash memory version MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION P11/INT01 P12 P13 P14 P15 P16 P17 39 38 37 36 35 34 33 P06/AN14 P07/AN15 P05/AN13 42 P10/INT41 P04/AN12 43 40 P03/AN11 45 44 41 P01/AN9 P02/AN10 46 P00/AN8 47 48 PIN CONFIGURATION (TOP VIEW) P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33/SCL 53 28 P24(LED4) P32/SDA 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT AVSS 59 22 XIN P67/AN7 60 21 P40/INT40/XCOUT P66/AN6 61 20 P41/INT00/XCIN P65/AN5 62 19 RESET P64/AN4 63 18 CNVSS VPP P63/AN3 64 17 P42/INT1 4 5 6 7 8 9 10 11 12 13 14 15 16 P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 3 P60/AN0 P57/INT3 2 P61/AN1 P56/PWM 1 P62/AN2 M38049FFFP/HP M38047M8-XXXFP/HP : Flash memory version Package type : 64P6N-A/64P6Q-A Fig. 3 3804 group pin configuration PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38049FFSP M38047M8-XXXSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 VPP CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) : Flash memory version Package type : 64P4B Fig. 4 3804 group pin configuration 3 4 28 29 Fig. 5 3803 group functional block diagram 3 VREF AVSS 2 A-D converter (10) I/O port P6 4 5 6 7 8 9 10 11 P6(8) Clock generating circuit 31 INT3 PWM(8) RAM I/O port P5 12 13 14 15 16 17 18 19 P5(8) SI/O2(8) ROM A P4(8) INT00 INT1 INT2 INT40 P3(8) I/O port P4 27 I/O port P3 P2(8) I/O port P2 (LED drive) I/O port P1 I/O port P0 49 50 51 52 53 54 55 56 P0(8) Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) INT01 INT41 41 42 43 44 45 46 47 48 P1(8) Timer Z (16) Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) CNTR2 CNTR1 26 CNVSS 33 34 35 36 37 38 39 40 CNTR0 SI/O3(8) 57 58 59 60 61 62 63 64 D-A D-A converter converter 2 (8) 1 (8) PS PC L S Y X 20 21 22 23 24 25 28 29 SI/O1(8) PC H C P U Data bus 1 32 RESET 30 Reset input V CC X IN X OUT X CIN X COUT V SS Clock Clock Sub-clock Sub-clock input output input output FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK 28 29 VREF AVSS 2 3 A-D converter (10) I/O port P6 4 5 6 7 8 9 10 11 P6(8) Clock generating circuit 31 INT3 PWM(8) RAM I/O port P5 12 13 14 15 16 17 18 19 P5(8) SI/O2(8) ROM A P4(8) INT00 INT1 INT2 INT40 P3(8) I/O port P4 27 I/O port P3 P2(8) I/O port P2 (LED drive) P1(8) I/O port P1 I/O port P0 49 50 51 52 53 54 55 56 P0(8) Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) INT01 INT41 41 42 43 44 45 46 47 48 I 2C Timer Z (16) Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) CNTR2 CNTR1 26 CNVSS 33 34 35 36 37 38 39 40 CNTR0 SI/O3(8) 57 58 59 60 61 62 63 64 D-A D-A converter converter 2 (8) 1 (8) PS PC L S Y X 20 21 22 23 24 25 28 29 SI/O1(8) PC H C P U Data bus 1 32 RESET 30 Reset input V CC X IN X OUT X CIN X COUT V SS Clock Clock Sub-clock Sub-clock input output input output FUNCTIONAL BLOCK DIAGRAM (Package: 64P4B) MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 6 3804 group functional block diagram 5 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description (3803 group) Pin VCC, VSS Power source CNV SS CNV SS input VREF AVSS Reference voltage Analog power source RESET XIN Reset input XOUT Clock output P00/AN8 – P07/AN15 P10/INT01 P11/INT41 P12–P17 P20–P27 I/O port P0 P30/DA1 P31/DA2 P32, P3 3 P34/RxD 3 P35/TxD 3 P36/S CLK3 P37/S RDY3 P40/INT40 / XCOUT P41/INT00 / XCIN P42/INT1 P43/INT2 P44/RxD 1 P45/TxD 1 P46/S CLK1 P47/S RDY1 /CNTR2 P50/S IN2 P51/S OUT2 P52/S CLK2 P53/S RDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN 0– P67/AN 7 6 Name Clock input I/O port P1 I/O port P2 I/O port P3 Functions Function except a port function •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss •This pin controls the operation mode of the chip. •Normally connected to VSS . •In the flash memory version, this becomes V PP power source input pin. •Reference voltage input pin for A-D and D-A converters. •Analog power source input pin for A-D and D-A converters. •Connect to VSS . •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the X OUT pin open. •A-D converter input pin •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually •Interrupt input pin programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •P2 0–P27 are enabled to output large current for LED drive. •8-bit CMOS I/O port. •D-A converter input pin •I/O direction register allows each pin to be individually programmed as either input or output. •P30, P31, P3 4–P37 are CMOS 3-state output structure. •Serial I/O3 function pin •P3 2, P33 are N-channel open-drain output structure. •Pull-up control of P3 0, P31 , P34–P37 is enabled in a bit unit. I/O port P4 •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Interrupt input pin •Sub-clock generating I/O pin (resonator connected) •Interrupt input pin •Serial I/O1 function pin •Serial I/O1, timer Z function pin I/O port P5 I/O port P6 •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Serial I/O2 function pin •Timer X function pin •Timer Y function pin •PWM output pin •Interrupt input pin •A-D converter input pin MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 2 Pin description (3804 group) Pin Name VCC, VSS Power source CNV SS CNVSS input VREF AVSS Reference voltage Analog power source RESET XIN Reset input XOUT Clock output P00/AN 8– P07/AN 15 I/O port P0 P10 /INT01 P11/INT41 P12–P17 P20–P27 I/O port P1 P30/DA 1 P31/DA 2 P32 /SDA P33/SCL P34 /RxD3 P35/TxD 3 P36/S CLK3 P37/S RDY3 Clock input I/O port P2 I/O port P3 P40 /INT40 / I/O port P4 XCOUT P41 /INT00 / XCIN P42 /INT1 P43 /INT2 P44 /RxD1 P45 /TxD1 P46 /SCLK1 P47 /SRDY1 /CNTR2 P50 /SIN2 I/O port P5 P51 /SOUT2 P52 /SCLK2 P53 /SRDY2 P54 /CNTR0 P55 /CNTR1 P56 /PWM P57 /INT3 P60 /AN0– I/O port P6 P67 /AN7 Functions Function except a port function •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss •This pin controls the operation mode of the chip. •Normally connected to VSS . •In the flash memory version, this becomes V PP power source input pin. •Reference voltage input pin for A-D and D-A converters. •Analog power source input pin for A-D and D-A converters. •Connect to V SS. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit CMOS I/O port. •A-D converter input pin •I/O direction register allows each pin to be individually •Interrupt input pin programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •P2 0–P27 are enabled to output large current for LED drive. •8-bit CMOS I/O port. •D-A converter input pin •I/O direction register allows each pin to be individually programmed as either input or output. •I2 C-BUS interface function pins •P32 to P3 3 can be switched between CMOS compatible input level or SMBUS input level in the I2 C-BUS •Serial I/O3 function pin interface function. •P30, P31 , P34–P37 are CMOS 3-state output structure. •P3 2, P33 are N-channel open-drain output structure. •Pull-up control of P3 0, P3 1, P34–P37 is enabled in a bit unit. •8-bit CMOS I/O port. •Interrupt input pin •I/O direction register allows each pin to be individually •Sub-clock generating I/O pin programmed as either input or output. (resonator connected) •CMOS compatible input level. •Interrupt input pin •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Serial I/O1 function pin •Serial I/O1, timer Z function pin •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. •Serial I/O2 function pin •Timer X function pin •Timer Y function pin •PWM output pin •Interrupt input pin •A-D converter input pin 7 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product name M3803 7 M 8 – XXX SP Package type SP : 64P4B FP : 64P6N-A HP : 64P6Q-A ROM number Omitted in the flash memory version. – : standard Omitted in the flash memory version. ROM size 9 : 36864 bytes 1 : 4096 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Group 3803: 3803 group 3804: 3804 group Fig. 7 Part numbering 8 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION GROUP EXPANSION Packages Mitsubishi plans to expand the 3803/3804 group as follows. 64P4B ......................................... 64-pin shrink plastic-molded DIP 64P6N-A .................................... 0.8 mm-pitch plastic molded QFP 64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP Memory Type Support for mask ROM and flash memory versions. Memory Size Flash memory size ......................................................... 60 K bytes Mask ROM size ................................................. 16 K to 60 K bytes RAM size ............................................................ 640 to 2048 bytes Memory Expansion Plan ROM size (bytes) ROM exteranal : Under development As of May 2000 : Mass production M38039MF, M38049MF 60K M38039FF, M38049FF M38039MC M38049MC 48K M38037M8 M38047M8 32K 28K M38037M6 M38047M6 24K 20K M38034M4 M38044M4 16K 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig. 8 Memory expansion plan 9 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Currently planning products are listed below. As of May 2000 Table 3 Support products Product name M38034M4-XXXSP M38034M4-XXXFP M38034M4-XXXHP M38044M4-XXXSP M38044M4-XXXFP M38044M4-XXXHP M38037M6-XXXSP M38037M6-XXXFP M38037M6-XXXHP M38047M6-XXXSP M38047M6-XXXFP M38047M6-XXXHP M38037M8-XXXSP M38037M8-XXXFP M38037M8-XXXHP M38047M8-XXXSP M38047M8-XXXFP M38047M8-XXXHP M38039MC-XXXSP M38039MC-XXXFP M38039MC-XXXHP M38049MC-XXXSP M38049MC-XXXFP M38049MC-XXXHP M38039MF-XXXSP M38039MF-XXXFP M38039MF-XXXHP M38049MF-XXXSP M38049MF-XXXFP M38049MF-XXXHP M38039FFSP M38039FFFP M38039FFHP M38049FFSP M38049FFFP M38049FFHP 10 ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 16384 (16254) 640 24576 (24446) 1024 32768 (32638) 1024 49152 (49022) 2048 61440 (61310) 2048 61440 2048 Package 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A 64P4B 64P6N-A 64P6Q-A Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3803/3804 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 10. Store registers other than those described in Figure 10 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL . It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig.9 740 Family CPU register structure 11 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) – 1 M (S) (PCL) (S) (S)– 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) – 1 (PCL) Push return address on stack (S) – 1 (PS) Push contents of processor status register on stack (S) – 1 Interrupt Service Routine Execute RTS (S) (PCH) I Flag is set from “0” to “1” Fetch the jump vector Execute RTI Note: Condition for acceptance of an interrupt (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 10 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register 12 Push instruction to stack Pop instruction from stack PHA PHP PLA PLP MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – 13 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B 16. b7 b0 1 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig.11 Structure of CPU mode register 14 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 12 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 0010 16: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3803/3804 group has the built-in function which automatically switches from low to middle-speed mode either by the SCL/SDA interrupt (only for the 3804 group) or by program. b7 ●Middle-speed mode automatic switch by SCL/SDA Interrupt (only for 3804 group) The SCL/SDA interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of MISRG (address 001016) is set to “1”. The conditions for an automatic switch execution depend on the settings of bits 5 and 6 of the I2C start/stop condition control register (address 001616). Bit 5 is the SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/ SDA interrupt pin selection bit. The main clock oscillation stabilizing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the MISRG. ●Middle-speed mode automatic switch by program(for 3804/ 3803 group) The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to “1” in the condition that the middle-speed mode automatic switch set bit is “1” while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). b0 MISRG (MISRG : address 001016) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set disabled Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enabled (Notes 1, 2) Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start (Note 2) Not used (return “0” when read) (Do not write “1” to this bit) Notes 1: During operation in low-speed mode, it is possible automatically to switch to middle-speed mode owing to SCL/SDA interrupt. This is valid only for the 3804 group. 2: When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B16) change. Fig.12 Structure of MISRG 15 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Special Page RAM Access to this area with only 2 bytes is possible in the special page addressing mode. RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 000016 SFR area Zero page 004016 010016 RAM XXXX16 Not used 0FF016 0FFF16 SFR area Not used YYYY16 ROM area Reserved ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Fig. 13 Memory map diagram 16 (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer Z low-order (TZL) 000916 Port P4 direction register (P4D) 002916 Timer Z high-order (TZH) 000A16 Port P5 (P5) 002A16 Timer Z mode register (TZM) 000B16 Port P5 direction register (P5D) 002B16 PWM control register (PWMCON) 000C16 Port P6 (P6) 002C16 PWM prescaler (PREPWM) 000D16 Port P6 direction register (P6D) 002D16 PWM register (PWM) 000E16 Timer 12, X count source selection register (T12XCSS) 002E16 000F16 Timer Y, Z count source selection register (TYZCSS) 002F16 Baud rate generator 3 (BRG3) 001016 MISRG 003016 Transmit/Receive buffer register 3 (TB3/RB3) 001116 Reserved ✽ 003116 Serial I/O3 status register (SIO3STS) 001216 Reserved ✽ 003216 Serial I/O3 control register (SIO3CON) 001316 Reserved ✽ 003316 UART3 control register (UART3CON) 001416 Reserved ✽ 003416 AD/DA control register (ADCON) 001516 Reserved ✽ 003516 A-D conversion register 1 (AD1) 001616 Reserved ✽ 003616 D-A1 conversion register (DA1) 001716 Reserved ✽ 003716 D-A2 conversion register (DA2) 001816 Transmit/Receive buffer register 1 (TB1/RB1) 003816 A-D conversion register 2 (AD2) 001916 Serial I/O1 status register (SIO1STS) 003916 Interrupt source selection register (INTSEL) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART1 control register (UART1CON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG1) 003C16 Interrupt request register 1 (IREQ1) 001D16 Serial I/O2 control register (SIO2CON) 003D16 Interrupt request register 2 (IREQ2) 001E16 Watchdog timer control register (WDTCON) 003E16 Interrupt control register 1 (ICON1) 001F16 Serial I/O2 register (SIO2) 003F16 Interrupt control register 2 (ICON2) 0FF016 Port P0 pull-up control register (PULL0) 0FF116 Port P1 pull-up control register (PULL1) 0FF216 Port P2 pull-up control register (PULL2) 0FF316 Port P3 pull-up control register (PULL3) 0FF416 Port P4 pull-up control register (PULL4) 0FF516 Port P5 pull-up control register (PULL5) 0FF616 Port P6 pull-up control register (PULL6) 0FFE16 Flash memory control register (FCON) 0FFF16 Flash command register (FCMD) ✽ Reserved area: Do not write any data to this addresses, because these areas are reserved. Fig. 14 Memory map of 3803 group’s special function register (SFR) 17 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer Z low-order (TZL) 000916 Port P4 direction register (P4D) 002916 Timer Z high-order (TZH) 000A16 Port P5 (P5) 002A16 Timer Z mode register (TZM) 000B16 Port P5 direction register (P5D) 002B16 PWM control register (PWMCON) 000C16 Port P6 (P6) 002C16 PWM prescaler (PREPWM) 000D16 Port P6 direction register (P6D) 002D16 PWM register (PWM) 000E16 Timer 12, X count source selection register (T12XCSS) 002E16 000F16 Timer Y, Z count source selection register (TYZCSS) 002F16 Baud rate generator 3 (BRG3) 001016 MISRG 003016 Transmit/Receive buffer register 3 (TB3/RB3) 001116 I2C 003116 Serial I/O3 status register (SIO3STS) 001216 I2C special mode status register (S3) 003216 Serial I/O3 control register (SIO3CON) 001316 I2C status register (S1) 003316 UART3 control register (UART3CON) 001416 I2C control register (S1D) 003416 AD/DA control register (ADCON) 001516 I2C clock control register (S2) 003516 A-D conversion register 1 (AD1) 001616 I2C START/STOP condition control register (S2D) 003616 D-A1 conversion register (DA1) 001716 I2C special mode control register (S3D) 003716 D-A2 conversion register (DA2) 001816 Transmit/Receive buffer register 1 (TB1/RB1) 003816 A-D conversion register 2 (AD2) 001916 Serial I/O1 status register (SIO1STS) 003916 Interrupt source selection register (INTSEL) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART1 control register (UART1CON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG1) 003C16 Interrupt request register 1 (IREQ1) 001D16 Serial I/O2 control register (SIO2CON) 003D16 Interrupt request register 2 (IREQ2) 001E16 Watchdog timer control register (WDTCON) 003E16 Interrupt control register 1 (ICON1) 001F16 Serial I/O2 register (SIO2) 003F16 Interrupt control register 2 (ICON2) 0FF016 Port P0 pull-up control register (PULL0) 0FF116 Port P1 pull-up control register (PULL1) 0FF216 Port P2 pull-up control register (PULL2) 0FF316 Port P3 pull-up control register (PULL3) 0FF416 Port P4 pull-up control register (PULL4) 0FF516 Port P5 pull-up control register (PULL5) 0FF616 Port P6 pull-up control register (PULL6) 0FF716 I2C slave address register 0 (S0D0) 0FF816 I2C slave address register 1 (S0D1) 0FF916 I2C slave address register 2 (S0D2) 0FFE16 Flash memory control register (FCON) 0FFF16 Flash command register (FCMD) data shift register (S0) Fig. 15 Memory map of 3804 group’s special function register (SFR) 18 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 6 I/O port function of 3803 group Pin P00/AN8–P07/AN15 P10/INT41 P11/INT01 P12–P17 P20/LED0– P27/LED7 P30/DA1 P31/DA2 P32 P33 P34/RxD3 P35/TxD3 P36/SCLK3 P37/SRDY3 P40/INT00/XCIN P41/INT40/XCOUT Name Port P0 Port P1 I/O Structure CMOS compatible input level CMOS 3-state output Non-Port Function A-D converter input External interrupt input Related SFRs Ref.No. AD/DA control register Interrupt edge selection register (1) (2) (3) Port P2 Port P3 Port P4 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output D-A converter output Serial I/O3 function I/O Serial I/O3 control register UART3 control register (6) (7) (8) (9) CMOS compatible input level CMOS 3-state output External interrupt input Sub-clock generating circuit Interrupt edge selection register CPU mode register Interrupt edge selection register (10) (11) Serial I/O1 function I/O Serial I/O1 control register UART1 control register Serial I/O1 function I/O Timer Z function I/O Serial I/O1 control register Timer Z mode register Serial I/O2 control register (6) (7) (8) (12) P42/INT1 P43/INT2 P44/RxD1 P45/TxD1 P46/SCLK1 P47/SRDY1/CNTR2 Port P5 P60/AN0–P67/AN7 Port P6 CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output (4) (5) External interrupt input P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 AD/DA control register Serial I/O2 function I/O Timer X, Y function I/O Timer XY mode register PWM output External interrupt input PWM control register Interrupt edge selection register AD/DA control register A-D converter input (2) (13) (14) (15) (16) (17) (18) (2) (1) Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 19 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 7 I/O port function of 3804 group Name Pin P00 /AN8–P07/AN15 Port P0 Port P1 P10/INT41 P11/INT01 P12 –P17 Port P2 P20 /LED0– P27 /LED7 Port P3 P30/DA 1 P31/DA 2 P32 /SDA P33 /SCL P34 /RxD3 P35 /TxD3 P36 /SCLK3 P37 /SRDY3 P40 /INT00 /XCIN P41 /INT40 /XCOUT Port P4 I/O Structure CMOS compatible input level CMOS 3-state output Port P5 P60 /AN0–P67/AN7 Port P6 Related SFRs Ref.No. AD/DA control register Interrupt edge selection register (1) (2) (3) CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output CMOS/SMBUS input level (when selecting I2C-BUS interface function) CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output P42 /INT1 P43 /INT2 P44 /RxD1 P45 /TxD1 P46 /SCLK1 P47 /SRDY1/CNTR2 P50 /SIN2 P51 /SOUT2 P52 /SCLK2 P53 /SRDY2 P54 /CNTR0 P55 /CNTR1 P56 /PWM P57 /INT3 Non-Port Function A-D converter input External interrupt input CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output D-A converter output AD/DA control register (4) I 2C-BUS interface function I/O I 2C control register (5) Serial I/O3 function I/O Serial I/O3 control register UART3 control register (6) (7) (8) (9) External interrupt input Sub-clock generating circuit External interrupt input Interrupt edge selection register CPU mode register Interrupt edge selection register (10) (11) Serial I/O1 function I/O Serial I/O1 control register UART1 control register (6) (7) (8) Serial I/O1 function I/O Timer Z function I/O Serial I/O1 control register Timer Z mode register Serial I/O2 control register (12) Serial I/O2 function I/O Timer X, Y function I/O Timer XY mode register PWM output External interrupt input PWM control register Interrupt edge selection register AD/DA control register A-D converter input Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from V CC to VSS through the input-stage gate. 20 (2) (13) (14) (15) (16) (17) (18) (2) (1) MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0, P6 (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Pull-up control bit Direction register Data bus Direction register Port latch Data bus Port latch A-D converter input Analog input pin selection bit (3) Ports P12 to P17, P2 Interrupt input (4) Ports P30, P31 Pull-up control bit Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (6) Ports P34, P44 (5) Ports P32, P33 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 (8) Ports P36, P46 Pull-up control bit Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit Serial I/O enable bit Transmit enable bit P-channel output disable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Direction register Data bus Port latch Serial I/O output Data bus Port latch Serial I/O clock output Serial I/O external clock input Fig. 16 Port block diagram of 3803 group (1) 21 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Port P37 (10) Port P40 Pull-up control bit Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Port XC switch bit Direction register Data bus Direction register Data bus Port latch Port latch Oscillator Port P41 Serial I/O3 ready output Port XC switch bit INT40 interrupt input (11) Port P41 (12) Port P47 Pull-up control bit Pull-up control bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Port XC switch bit Direction register Data bus Direction register Data bus Port latch Port latch Sub-clock generating circuit input Pulse output mode Serial I/O1 ready output INT00 interrupt input Timer output CNTR2 interrupt input (13) Port P50 (14) Port P51 Pull-up control bit Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 17 Port block diagram of 3803 group (2) 22 P-channel output disable bit MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (15) Port P52 (16) Port P53 Pull-up control bit Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit SRDY2 enable bit Direction register Direction register Port latch Data bus Data bus Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Data bus Direction register Data bus Port latch Pulse output mode Port latch PWM output Timer output CNTR interrupt input Fig. 18 Port block diagram of 3803 group (3) 23 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0, P6 (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Pull-up control bit Direction register Data bus Direction register Port latch Data bus Port latch A-D converter input Analog input pin selection bit (3) Ports P12 to P17, P2 Interrupt input (4) Ports P30, P31 Pull-up control bit Pull-up control bit Direction register Direction register Data bus Data bus Port latch Port latch D-A converter output DA1 output enable (P30) DA2 output enable (P31) (6) Ports P34, P44 (5) Ports P32, P33 Pull-up control bit I2C-BUS interface enable bit Serial I/O enable bit Receive enable bit Direction register Data bus Direction register Port latch Data bus SDA output SCL output Port latch SDA input SCL input Serial I/O input (7) Ports P35, P45 (8) Ports P36, P46 Pull-up control bit Serial I/O synchronous clock selection bit Pull-up control bit Serial I/O enable bit Serial I/O enable bit Transmit enable bit P-channel output disable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Direction register Data bus Port latch Serial I/O output Data bus Port latch Serial I/O clock output Serial I/O external clock input Fig. 19 Port block diagram of 3804 group (1) 24 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Port P37 (10) Port P40 Pull-up control bit Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Port XC switch bit Direction register Data bus Direction register Data bus Port latch Port latch Oscillator Port P41 Serial I/O3 ready output Port XC switch bit INT40 interrupt input (11) Port P41 (12) Port P47 Pull-up control bit Pull-up control bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Port XC switch bit Direction register Data bus Direction register Data bus Port latch Port latch Sub-clock generating circuit input Pulse output mode Serial I/O1 ready output INT00 interrupt input Timer output CNTR2 interrupt input (13) Port P50 (14) Port P51 Pull-up control bit Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register P-channel output disable bit Direction register Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 20 Port block diagram of 3804 group (2) 25 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (15) Port P52 (16) Port P53 Pull-up control bit Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit SRDY2 output enable bit Direction register Direction register Port latch Data bus Data bus Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM output enable bit Direction register Data bus Direction register Data bus Port latch Pulse output mode PWM output Timer output CNTR interrupt input Fig. 21 Port block diagram of 3804 group (3) 26 Port latch MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 22 Structure of port pull-up control register (1) 27 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return “0” when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Fig. 23 Structure of port pull-up control register (2) 28 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig. 24 Structure of port pull-up control register (3) 29 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Fig. 25 Structure of port pull-up control register (4) 30 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS ■ Notes The 3803 group’s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software. The 3804 group’s interrupts occur by 16 sources among 23 sources: nine external, thirteen internal, and one software. When setting of the following register or bit is changed, the interrupt request bit may be set to “1.” • Interrupt edge selection register (address 003A16 ) • Interrupt source selection register (address 003916 ) Accept the interrupt after clearing the interrupt request bit to “0” after interrupt is disabled and the above register or bit is set. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt. When several interrupt requests occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Source Selection Which of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916 ). 1. INT0 or Timer Z 2. Serial I/O1 transmission or SCL, SDA (for 3804 group) 3. CNTR0 or SCL, SDA (for 3804 group) 4. CNTR1 or Serial I/O3 reception 5. Serial I/O2 or Timer Z 6. INT 2 or I2C (for 3804 group) 7. INT 4 or CNTR2 8. A-D converter or serial I/O3 transmission External Interrupt Pin Selection The occurrence sources of the external interrupt INT 0 and INT 4 can be selected from either input from INT00 and INT 40 pin, or input from INT01 and INT41 pin by the INT0 , INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16 ). 31 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 8 Interrupt vector addresses and priority of 3803 group Interrupt Source Priority Vector Addresses (Note 1) High Low FFFD 16 FFFC16 FFFB16 FFFA16 Reset (Note 2) INT0 1 2 Timer Z INT1 3 FFF916 FFF816 4 FFF716 FFF616 5 FFF516 FFF416 Timer X Timer Y Timer 1 Timer 2 CNTR 0 6 7 8 9 10 FFF316 FFF116 FFEF 16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 CNTR 1 11 FFE916 FFE816 Serial I/O3 reception Serial I/O2 12 FFE716 FFE616 Timer Z INT 2 13 FFE516 FFE416 INT 3 14 FFE316 FFE216 INT 4 15 FFE116 FFE016 A-D converter Serial I/O3 transmission 16 FFDF16 BRK instruction 17 Serial I/O1 reception Serial I/O1 transmission At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception Non-maskable External interrupt (active edge selectable) At completion of serial I/O1 transmission shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow Valid when serial I/O1 is selected External interrupt (active edge selectable) Valid when serial I/O1 is selected STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) FFDE 16 At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A-D conversion Valid when serial I/O3 is selected FFDC16 At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 32 Remarks At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow CNTR2 FFDD16 Interrupt Request Generating Conditions Valid when serial I/O2 is selected Non-maskable software interrupt MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 9 Interrupt vector addresses and priority of 3804 group Interrupt Source Priority Vector Addresses (Note 1) High Low FFFD 16 FFFC16 FFFB16 FFFA16 Reset (Note 2) INT0 1 2 Timer Z INT1 3 FFF916 FFF816 4 FFF716 FFF616 5 FFF516 FFF416 Serial I/O1 reception Serial I/O1 transmission SCL, SDA 6 7 8 9 10 FFF316 FFF116 FFEF 16 FFED 16 FFEB16 FFF216 FFF016 FFEE 16 FFEC16 FFEA 16 CNTR1 11 FFE916 FFE816 Serial I/O3 reception Serial I/O2 12 FFE716 FFE616 Timer Z INT 2 13 FFE516 FFE416 I 2C INT 3 14 FFE316 FFE216 INT 4 15 FFE116 FFE016 A-D converter Serial I/O3 transmission 16 FFDF16 FFDE 16 BRK instruction 17 Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR2 FFDD16 FFDC16 Interrupt Request Generating Conditions Remarks At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception Non-maskable External interrupt (active edge selectable) At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow Valid when serial I/O1 is selected At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A-D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution External interrupt (active edge selectable) Valid when serial I/O1 is selected External interrupt (active edge selectable) STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 33 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Fig. 26 Interrupt control 34 Interrupt request MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns “0” when read) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) b7 b0 INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns “0” when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write “1” to these bits.) (Do not write “1” to these bits simultaneously.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write “1” to this bit.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 27 Structure of interrupt-related registers of 3803 group 35 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns “0” when read) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16) b7 INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit/SCL, SDA interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit/SCL, SDA interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0/SCL, SDA interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2/I2C interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0/SCL, SDA interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2/I2C interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns “0” when read) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write “1” to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Serial I/O1 transmit/SCL, SDA interrupt source selection bit 0 : Serial I/O1 transmit interrupt 1 : SCL, SDA interrupt (Do not write “1” to these bits simultaneously.) CNTR0/SCL, SDA interrupt source selection bit 0 : CNTR0 interrupt 1 : SCL, SDA interrupt INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt INT2/I2C interrupt source selection bit 0 : INT2 interrupt 1 : I2C interrupt CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A-D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 28 Structure of interrupt-related registers of 3804 group 36 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS ●8-bit Timers The 3803/3804 group has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches “0016 ”, an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. ●Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B 16). When these bits are “00” (high-speed mode) or “01” (middle-speed mode), XIN is selected. When these bits are“10” (low-speed mode), X CIN is selected. ●Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. ●Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN ). The count source is selected by the timer 12, X count source selection register (address 000E 16) and the timer Y, Z count source selection register (address 000F 16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN ); and f(XCIN ). Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316 ). (1) Timer mode ●Mode selection This mode can be selected by setting “00” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). ●Explanation of operation The timer count operation is started by setting “0” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse output mode ●Mode selection This mode can be selected by setting “01” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). ●Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR 1 pin. When the CNTR 0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. When the value of the CNTR0/CNTR 1 active edge switch bit is changed during pulse output, the output level of the CNTR 0 / CNTR1 pin is inverted. ■Precautions Set the double-function port of CNTR0/CNTR 1 pin and port P54 / P55 to output in this mode. 37 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (3) Event counter mode ●Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316 ). ●Explanation of operation The operation is the same as the timer mode’s except that the timer counts signals input from the CNTR0 or CNTR 1 pin. The valid edge for the count operation depends on the CNTR 0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. ■Precautions Set the double-function port of CNTR0 /CNTR1 pin and port P54 / P55 to input in this mode. (4) Pulse width measurement mode ●Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316 ). ●Explanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR 1 active edge switch bit (bit 6) of the timer XY mode register (address 002316 ) is “1”, the timer counts during the term of one falling edge of CNTR 0/CNTR1 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H” term). ■Precautions Set the double-function port of CNTR0 /CNTR1 pin and port P54 / P55 to input in this mode. The count operation can be stopped by setting “1” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 0023 16). The interrupt request bit is set to “1” each time the timer underflows. •Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. 38 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN “00” “01” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Clock for timer 12 Clock for timer Y XCIN Main clock division ratio selection bits Count source selection bit Clock for timer X “10” Data bus Prescaler X latch (8) f(XCIN) Pulse width measurement mode Prescaler X (8) CNTR0 active edge switch bit “0” P54/CNTR0 Event counter mode Timer X latch (8) Timer mode Pulse output mode Timer X (8) Timer X count stop bit To CNTR0 interrupt request bit “1 ” CNTR0 active edge switch bit “1” Port P54 direction register To timer X interrupt request bit “0” Port P54 latch Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Pulse output mode Data bus Count source selection bit Clock for timer Y Prescaler Y latch (8) Pulse width measurement mode f(XCIN) Prescaler Y (8) P55/CNTR1 CNTR1 active edge switch bit “0” Event counter mode Timer Y latch (8) Timer mode Pulse output mode Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit “1” CNTR1 active edge switch bit “1” Q Toggle flip-flop T Q Port P55 direction register Port P55 latch “0” R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 29 Block diagram of timer X, timer Y, timer 1, and timer 2 39 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0 : Count start 1 : Count stop Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge switch bit 0 : Interrupt at falling edge Count at rising edge in event counter mode 1 : Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0 : Count start 1 : Count stop Fig. 30 Structure of timer XY mode register 40 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3b2b1b0 1010 : 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used b0 Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3b2b1b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 1011 : 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 1100 : 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 1101 : 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 1110 : 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 1111 : 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7b6b5b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) 1011 : 1100 : 1101 : 1110 : 1111 : Not used Not used Fig. 31 Structure of timer 12, X and timer Y, Z count source selection registers 41 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ●16-bit Timers (2) Event counter mode The timer Z is a 16-bit timer. When the timer reaches “000016 ”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to “1”. Read and write operation to a 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first, followed by the low-order byte. When writing to a 16-bit timer, write to the low-order byte first, followed by the high-order byte. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16 ). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16 ). ●Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “1” to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16 ). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. ●Explanation of operation The operation is the same as the timer mode’s. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 34 shows the timing chart of the timer/event counter mode. (3) Pulse output mode (1) Timer mode ●Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 ). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. ●Interrupt When an underflow occurs, the INT0 /timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16 ) is set to “1”. ●Explanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16 ). When the timer reaches “000016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. 42 ●Mode selection This mode can be selected by setting “001” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. ●Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 ) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. ■Precautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. [During timer operation stop] The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. [During timer operation enabled] When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 35 shows the timing chart of the pulse output mode. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (4) Pulse period measurement mode (5) Pulse width measurement mode ●Mode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 ). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(X CIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse period measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D 16) is set to “1”. ●Explanation of operation [During timer operation stop] Select the count source. Next, select the term of the pulse period to be measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16 ) is “0”, the timer counts during the term of one falling edge of CNTR 2 pin input until the next falling edge of input. When it is “1”, the timer counts during the term of one rising edge input until the next rising edge input. [During timer operation enabled] The pulse period measurement starts by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16), and the timer counts down from the value that was set to the timer before the start of measurement. When the valid edge of measurement completion/start is detected, the 1’s complement of the timer value is written to the timer latch and “FFFF16 ” is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and “FFFF16” is set to the timer. The measured value is retained until the next measurement completion. ■Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16 ” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. Figure 36 shows the timing chart of the pulse period measurement mode. ●Mode selection This mode can be selected by setting “011” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN ) can be selected as the count source. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse widths measurement is completed, the INT 4 / CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16 ) is set to “1”. ●Explanation of operation [During timer operation stop] Select the count source. Next, select the term of the pulse width to be measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “1”, the timer counts during the term of one falling edge of CNTR2 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H” term). [During timer operation enabled] The pulse width measurement starts by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16), and the timer counts down from the value that was set to the timer before the start of measurement. When the valid edge of measurement completion is detected, the 1’s complement of the timer value is written to the timer latch. When the valid edge of measurement start/completion is detected, “FFFF16” is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and “FFFF16” is set to the timer. The measured value is retained until the next measurement completion. ■Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. Figure 37 shows the timing chart of the pulse width measurement mode. 43 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (6) Programmable waveform generating mode ●Mode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 ). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(X CIN) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/ 512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. ●Explanation of operation The operation is the same as the timer mode’s. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A 16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR 2 pin. ■Precautions Set the double-function port of CNTR2 pin and port P47 to output in this mode. Figure 38 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode ●Mode selection This mode can be selected by setting “101” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16 ). ●Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/ 128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN ) can be selected as the count source. ●Interrupt The interrupt at an underflow is the same as the timer mode’s. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A 16). When it is “0”, the falling edge active is selected; when it is “1”, the rising edge active is selected. When the valid edge of the INT1 pin is detected, the INT 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to “1”. ●Explanation of operation •“H” one-shot pulse; Bit 5 of timer Z mode register = “0” [During timer operation stop] The output level of CNTR 2 pin is initialized to “L” at mode selection. Set the one-shot pulse width to the registers of timer Z low-order and high-order. Trigger generating during timer stop (input signal to INT 1 pin) is invalid. 44 [During timer operation enabled] When trigger generating is detected, “H” is output from the CNTR2 pin. When an underflow occurs, “L” is output. •“L” one-shot pulse; Bit 5 of timer Z mode register = “1” [During timer operation stop] The output level of CNTR 2 pin is initialized to “H” at mode selection. Set the one-shot pulse width to the registers of timer Z low-order and high-order. Trigger generating during timer stop (input signal to INT1 pin) is invalid. [During timer operation enabled] When trigger generating is detected, “L” is output from the CNTR2 pin. When an underflow occurs, “H” is output. ■Precautions Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P4 2 to input in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 39 shows the timing chart of the programmable one-shot generating mode. ■Notes regarding all modes ●Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. ●Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. ●Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR 2 active edge switch bit and the INT1 active edge selection bit. ●Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CNTR2 active edge Data bus switch bit Programmable one-shot “1” P42/INT1 Programmable one-shot generating circuit Programmable one-shot generating mode generating mode “0” To INT1 interrupt request bit Programmable waveform generating mode D Output level latch Q T Pulse output mode CNTR2 active edge switch bit S Q T “0” Q “1” Pulse output mode “001” “100” “101” Timer Z operating mode bits Timer Z low-order latch Timer Z high-order latch Timer Z low-order Timer Z high-order Port P47 latch To timer Z interrupt request bit Port P47 direction register Pulse period measurement mode Pulse width measurement mode Edge detection circuit “1” “0” CNTR2 active edge switch bit X IN XCIN Clock for timer Z P47/CNTR2 To CNTR2 interrupt request bit “1” f(XCIN) “0” Timer/Event counter mode switch bit Timer Z count stop bit Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig. 32 Block diagram of timer Z 45 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2b1b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : “L” output 1 : “H” output CNTR2 active edge switch bit 0 : •Event counter mode: Count at rising edge •Pulse output mode: Start outputting “H” •Pulse period measurement mode: Measurement between two falling edges •Pulse width measurement mode: Measurement of “H” term •Programmable one-shot generating mode: After start outputting “L”, “H” one-shot pulse generated •Interrupt at falling edge 1 : •Event counter mode: Count at falling edge •Pulse output mode: Start outputting “L” •Pulse period measurement mode: Measurement between two rising edges •Pulse width measurement mode: Measurement of “L” term •Programmable one-shot generating mode: After start outputting “H”, “L” one-shot pulse generated •Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (Note) 0 : Timer mode 1 : Event counter mode Note: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig. 33 Structure of timer Z mode register 46 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 34 Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 35 Timing chart of pulse output mode 47 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 TR T2 T3 FFFF16 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 36 Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of “L” width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 37 Timing chart of pulse width measurement mode (Measuring “L” term) 48 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L T3 T1 T2 TR TR TR TR CNTR2 CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 38 Timing chart of programmable waveform generating mode FFFF16 L TR Signal input from INT1 pin Signal output from CNTR2 pin L TR L CNTR2 TR L CNTR2 L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 39 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) 49 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Clock Synchronous Serial I/O Mode SERIAL I/O Serial I/O1 Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 001816 Receive buffer register 1 P44/RXD1 Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 1 Shift clock Clock control circuit P46/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 Address 001C16 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Clock control circuit Falling-edge detector Shift clock P45/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 40 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD1 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 41 Operation of clock synchronous serial I/O1 50 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 P44/RXD1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register 1 OE Character length selection bit ST detector 7 bits Receive shift register 1 1/16 8 bits PE FE UART control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 001C16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P45/TXD1 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Character length selection bit Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 42 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 TBE=0 TSC=1] TBE=1 ST D0 D1 SP ST D0 SP D1 ] 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 Serial input RXD1 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 43 Operation of UART serial I/O1 51 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P4 5/TXD1 pin. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 52 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIO1STS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART1 control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 44 Structure of serial I/O1 control registers 53 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ■ Notes concerning serial I/O1 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation ● Note Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, S CLK, and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. 1.2 Stop of receive operation ● Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation ● Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) ● Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0” (serial I/O disabled) (refer to 1.1). 54 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation ● Note Clear the transmit enable bit to “0” (transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK , and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. 2.2 Stop of receive operation ● Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation ● Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK , and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. ● Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3. SRDY output of reception side ● Note When signals are output from the S RDY pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O control register again ● Note Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit 7. Transmit interrupt request when transmit enable bit is set ● Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled). ● Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. (TE) and the receive enable bit (RE) to “0” ↓ Set the bits 0 to 3 and bit 6 of the serial I/O control register ↓ Set both the transmit enable bit Can be set with the LDM instruction at the same time (TE) and the receive enable bit (RE), or one of them to “1” 5. Data transmission control with referring to transmit shift register completion flag ● Note The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected ● Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the S CLK input level. Also, write data to the transmit buffer register at “H” of the SCLK input level. 55 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 b7 b0 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) [Serial I/O2 Control Register (SIO2CON)] 001D16 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 signal output The serial I/O2 control register contains eight bits which control various serial I/O2 functions. SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig. 45 Structure of serial I/O2 control register 1/8 Internal synchronous clock selection bits Divider 1/16 f(XIN) (f(XCIN) in low-speed mode) 1/32 Data bus 1/64 1/128 1/256 P53 latch P53/SRDY2 Serial I/O2 synchronous clock selection bit “1” SRDY2 “1 ” SRDY2 output enable bit Synchronization circuit SCLK2 “0 ” “0 ” External clock P52 latch “0 ” P52/SCLK2 “1 ” Serial I/O2 port selection bit Serial I/O counter 2 (3) P51 latch “0 ” P51/SOUT2 “1 ” Serial I/O2 port selection bit P50/SIN2 Fig. 46 Block diagram of serial I/O2 56 Serial I/O shift register 2 (8) Serial I/O2 interrupt request MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig. 47 Timing of serial I/O2 57 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O3 (1) Clock Synchronous Serial I/O Mode Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Address 003016 Receive buffer register 3 P34/RXD3 Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register 3 Shift clock Clock control circuit P36/SCLK3 Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 Address 002F16 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P37/SRDY3 Clock control circuit Falling-edge detector F/F Shift clock P35/TXD3 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 3 Transmit buffer register 3 Address 003016 Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Data bus Fig. 48 Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD3 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD3 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 49 Operation of clock synchronous serial I/O3 58 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Serial I/O3 control register Address 003216 Address 003016 P34/RXD3 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register 3 OE Character length selection bit ST detector 7 bits Receive shift register 3 1/16 8 bits PE FE UART3 control register SP detector Address 003316 Clock control circuit Serial I/O3 synchronous clock selection bit P36/SCLK3 BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator 3 (f(XCIN) in low-speed mode) Address 002F16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P35/TXD3 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 3 Character length selection bit Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Transmit buffer register 3 Address 003016 Data bus Fig. 50 Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD3 TBE=0 TSC=1] TBE=1 ST D0 D1 SP ST D0 SP D1 ] 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 Serial input RXD3 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 51 Operation of UART serial I/O3 59 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P3 5/TXD3 pin. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 60 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O3 status register (SIO3STS : address 003116) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O enabled (pins P34 to P37 operate as serial I/O pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 52 Structure of serial I/O3 control registers 61 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ■ Notes concerning serial I/O3 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation ● Note Clear the serial I/O enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, S CLK, and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. 1.2 Stop of receive operation ● Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation ● Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) ● Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0” (serial I/O disabled) (refer to 1.1). 62 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation ● Note Clear the transmit enable bit to “0” (transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK , and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. 2.2 Stop of receive operation ● Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation ● Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). ● Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK , and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. ● Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 3. SRDY output of reception side ● Note When signals are output from the S RDY pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O control register again ● Note Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit 7. Transmit interrupt request when transmit enable bit is set ● Note When using the transmit interrupt, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instruction has executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled). ● Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. (TE) and the receive enable bit (RE) to “0” ↓ Set the bits 0 to 3 and bit 6 of the serial I/O control register ↓ Set both the transmit enable bit Can be set with the LDM instruction at the same time (TE) and the receive enable bit (RE), or one of them to “1” 5. Data transmission control with referring to transmit shift register completion flag ● Note The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected ● Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the S CLK input level. Also, write data to the transmit buffer register at “H” of the SCLK input level. 63 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) PWM Operation The 3803/3804 group has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” term = PWM period ✕ m / 255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz) 31.875 ✕ m ✕(n+1) µs 255 PWM output T = [31.875 5 (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source is f(XIN)) Fig. 53 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit “0” XIN Port P56 or XCIN 1/2 “1” Port P56 latch PWM enable bit Fig. 54 Block diagram of PWM function 64 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 PWM control register (PWMCON : address 002B16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return “0” when read) Fig. 55 Structure of PWM control register A B B = C T2 T C PWM output T PWM register write signal PWM prescaler write signal T T2 (Changes “H” term from “A” to “B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 56 PWM output timing when PWM register or PWM prescaler is changed 65 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Register 1, 2 (AD1, AD2)] 003516, 003816 The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. Bit 7 of the A-D conversion register 2 is the conversion mode selection bit. When this bit is set to “0,” the A-D converter becomes the 10-bit A-D mode. When this bit is set to “1,” that becomes the 8-bit A-D mode. The conversion result of the 8-bit A-D mode is stored in the A-D conversion register 1. As for 10-bit A-D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the A-D conversion registers 1, 2 after A-D conversion is completed (in Figure 58). As for 10-bit A-D mode, the 8-bit reading inclined to MSB is performed when reading the A-D converter register 1 after A-D conversion is started; and when the A-D converter register 1 is read after reading the A-D converter register 2, the 8-bit reading inclined to LSB is performed. Channel Selector The channel selector selects one of ports P67 /AN7 to P60 /AN0 or P07/AN15 to P00 /AN8, and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the A-D conversion registers 1, 2. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 0 0 0 0 1 1 1 1 [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A-D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. 0: P60/AN0 or P00/AN8 1: P61/AN1 or P01/AN9 0: P62/AN2 or P02/AN10 1: P63/AN3 or P03/AN11 0: P64/AN4 or P04/AN12 1: P65/AN5 or P05/AN13 0: P66/AN6 or P06/AN14 1: P67/AN7 or P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSS into 1024, and that outputs the comparison voltage in the 10-bit A-D mode (256 division in 8-bit A-D mode). The A-D converter successively compares the comparison voltage Vref in each mode, dividing the VREF voltage (see below), with the input voltage. • 10-bit A-D mode (10-bit reading) Vref = VREF ✕ n (n = 0–1023) 1024 • 10-bit A-D mode (8-bit reading) Vref = VREF ✕ n (n = 0–255) 256 • 8-bit A-D mode Vref = VREF ✕ (n–0.5) (n = 1–255) 256 =0 (n = 0) 0 0 1 1 0 0 1 1 Not used (returns “0” when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig. 57 Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) b7 A-D conversion register 2 0 (AD2: address 003816) A-D conversion register 1 (AD1: address 003516) b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become “0” at reading. 8-bit reading (Read only address 003516) b7 b0 A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (AD1: address 003516) Fig. 58 Structure of 10-bit A-D mode reading 66 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus AD/DA control register (Address 003416) b7 b0 4 A-D control circuit Comparator Channel selector P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 A-D conversion register 2 A-D conversion register 1 AD converter interrupt request (Address 003816) (Address 003516) 10 Resistor ladder VREF AVSS Fig. 59 Block diagram of A-D converter 67 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER The 3803/3804 group has two internal D-A converters (DA1 and DA2) with 8-bit resolution. The D-A conversion is performed by setting the value in each D-A conversion register. The result of D-A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to “1”. When using the D-A converter, the corresponding port direction register bit (P3 0/DA1 or P3 1/DA2 ) must be set to “0” (input status). The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows: Data bus D-A1 conversion register (8) V = VREF ✕ n/256 (n = 0 to 255) Where V REF is the reference voltage. DA1 output enable bit R-2R resistor ladder P30/DA1 D-A2 conversion register (8) At reset, the D-A conversion registers are cleared to “0016 ”, and the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. DA2 output enable bit R-2R resistor ladder P31/DA2 Fig. 60 Block diagram of D-A converter “0” DA1 output enable bit R R R R R R R 2R P30/DA1 “1” 2R 2R MSB D-A1 conversion register “0” 2R 2R 2R 2R 2R LSB “1” AVSS VREF Fig. 61 Equivalent connection circuit of D-A converter (DA1) 68 2R MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Watchdog Timer Initial Value Watchdog timer L is set to “FF16” and watchdog timer H is set to “FF16” by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the above-mentioned value will be set to each timer. Watchdog Timer Operations The watchdog timer stops at reset and a countdown is started by the writing to the watchdog timer control register. An internal reset occurs when watchdog timer H underflows. The reset is released after its release time. After the release, the program is restarted from the reset vector address. Usually, write to the watchdog timer control register by software before an underflow of the watchdog timer H. The watchdog timer does not function if the watchdog timer control register is not written to at least once. XCIN “10” Main clock division ratio selection bits (Note) XIN “FF16” is set when watchdog timer control register is written to. When bit 6 of the watchdog timer control register is kept at “0”, the STP instruction is enabled. When that is executed, both the clock and the watchdog timer stop. Count re-starts at the same time as the release of stop mode (Note). The watchdog timer does not stop while a WIT instruction is executed. In addition, the STP instruction is disabled by writing “1” to this bit again. When the STP instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. Once a “1” is written to this bit, it cannot be programmed to “0” again. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 µs Note: The watchdog timer continues to count even while waiting for a stop release. Therefore, make sure that watchdog timer H does not underflow during this period. Data bus “FF16” is set when watchdog timer control register is written to. “0” Watchdog timer L (8) 1/16 “1” “00” “01” Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit RESET Internal reset Reset release time waiting Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 62 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 63 Structure of Watchdog timer control register 69 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MULTI-MASTER I2C-BUS INTERFACE Table 10 Multi-master I2 C-BUS interface functions The 3804 group has the multi-master I2 C-BUS interface. The multi-master I 2C-BUS interface is a serial communications circuit, conforming to the Philips I2 C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 64 shows a block diagram of the multi-master I2C-BUS interface and Table 10 lists the multi-master I 2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I 2C slave address registers 0 to 2, the I 2C data shift register, the I2 C clock control register, the I2C control register, the I2C status register, the I 2C START/STOP condition control register, the I2 C special mode control register, the I 2C special mode status register, and other control circuits. When using the multi-master I 2C-BUS interface, set 1 MHz or more to system clock φ. Interrupt generating circuit Interrupt request signal (SCL, SDA, IRQ) Item Format Communication mode SCL clock frequency Function In conformity with Philips I2 C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2 C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ= 4 MHz) System clock φ = f(X IN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) b7 I2C slave address registers 0 to 2 b0 Interrupt generating circuit SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB S0D0–2 Interrupt request signal (I2CIRQ) Address comparator Noise elimination circuit Serial data (SDA) Data control circuit b7 b0 I2C data shift register b7 b0 S0 AL AAS AD0 LRB MST TRX BB PIN SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 AL circuit S1 I2C status register S2D I2C START/STOP condition control register Internal data bus BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK F AST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE S2 I2C clock control register Clock division System clock (φ) b7 b0 SPCF PIN2 A AS2 A AS1 A AS0 S3 I2C special mode status register b7 b7 TISS S1D b0 TS EL I2C 10BIT SAD ALS SPCFL b0 PIN2 HD PIN2 IN HSLAD ACKI CON ES0 BC2 BC1 BC0 S3D I2 C special mode control register control register Bit counter Fig. 64 Block diagram of multi-master I2C-BUS interface ✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2 C components conveys a license under the Philips I 2C Patent Rights to use these components an I2 C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 70 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I2C Data Shift Register (S0)] 001116 The I2 C data shift register (S0: address 0011 16) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 cycles of system clock φ are required from the rising of the SCL until input to this register. The I2C data shift register is in a write enable status only when the I 2C-BUS interface enable bit (ES0 bit) of the I2 C control register (S1D: address 0014 16) is “1”. The bit counter is reset by a write instruction to the I 2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (S1: address 0013 16) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. b7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB I2C slave address register 0 (S0D0: address 0FF716) I2C slave address register 1 (S0D1: address 0FF816) I2C slave address register 2 (S0D2: address 0FF916) Read/write bit Slave address Fig. 65 Structure of I2C slave address registers 0 to 2 [I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)] 0FF716 to 0FF916 The I 2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF7 16 to 0FF916) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. •Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, set RWB to “0” because the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I 2C slave address registers 0 to 2. When 2-byte address data match slave address, a 7-bit slave address which is received after restart condition has detected and R/W data can be matched by setting “1” to RWB with software. The RWB is cleared to “0” automatically when the stop condition is detected. •Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits’ contents. 71 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: Do not write data into the I2 C clock control register during transfer. If data is written during transfer, the I 2 C clock generator is reset, so that data cannot be transferred normally. 72 F AST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 001516) SCL frequency control bits Refer to Table 11. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 66 Structure of I2C clock control register Table 11 Set values of I2 C clock control register and SCL frequency SCL frequency Setting value of (at φ = 4 MHz, unit : kHz) (Note 1) CCR4–CCR0 Standard clock High-speed clock CCR4 CCR3 CCR2 CCR1 CCR0 mode mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 333 0 0 1 1 0 0 1 0 0 – (Note 2) 250 0 0 1 0 1 100 400 (Note 3) 0 0 1 1 0 83.3 166 … 0 – (Note 2) … •Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to “0,” the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving device. ACK b0 A CK B IT … ✽ACK clock: Clock for acknowledgment b7 … The I2C clock control register (S2: address 0015 16) is used to set ACK control, SCL mode and SCL frequency. •Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 11. •Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is selected. When the bit is set to “1,” the high-speed clock mode is selected. When connecting the bus of the high-speed mode I 2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) in the high-speed mode (2 division clock). •Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned). … [I2C Clock Control Register (S2)] 001516 500/CCR value (Note 3) 1 1 1 0 1 17.2 1000/CCR value (Note 3) 34.5 1 1 1 1 0 16.6 33.3 1 1 1 1 1 16.1 32.3 Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3: The data formula of SCL frequency is described below: φ/(8 ✕ CCR value) Standard clock mode φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I2C Control Register (S1D)] 0014 16 The I2C control register (S1D: address 0014 16) controls data communication format. •Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I 2 C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of S2, address 0015 16) have been transferred, and BC0 to BC2 are returned to “0002 ”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. •Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0,” the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ES0 = “0,” the following is performed. • PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C status register, S1, at address 0013 16 ). • Writing data to the I2 C data shift register (S0: address 001116 ) is disabled. •Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “I2 C Status Register,” bit 1) is received, transfer processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. •Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C slave address registers 0 to 2 are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, and all the bits of the I2 C slave address registers 0 to 2 are compared with address data. •Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. b7 TISS b0 10 B IT S AD ALS ES0 BC2 BC1 BC0 I2C control register (S1D : address 001416) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 I2C-BUS interface enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Not used (return “0” when read) I2C-BUS interface pin input level selection bit 0 : CMOS input 1 : SMBUS input Fig. 67 Structure of I2C control register 73 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I2C Status Register (S1)] 0013 16 The I2C status register (S1: address 0013 16) controls the I 2C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “00002 ” to the low-order 4 bits, because these bits become the reserved bits at writing. •Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (S0: address 0011 16). •Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call ✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition, or reset. ✽General call: The master transmits the general call address “0016” to all slaves. •Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. ➀ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions: • The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2 C slave address register. • A general call is received. ➁ In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition: • When the address data is compared with the I2 C slave address register (8 bits consisting of slave address and RWB bit), the first bytes agree. ➂ This bit is set to “0” by executing a write instruction to the I2 C data shift register (S0: address 001116 ) when ES0 is set to “1” or reset. •Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. 74 The AL bit is set to “0” in one of the following conditions: •Executing a write instruction to the I2C data shift register (S0: address 001116 ) •When the ES0 bit is “0” •At reset ✽Arbitration lost :The status in which communication as a master is disabled. •Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 69 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions: • Executing a write instruction to the I2 C data shift register (S0: address 001116). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) • When the ES0 bit is “0” • At reset • When writing “1” to the PIN bit by software The PIN bit is set to “0” in one of the following conditions: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception •Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the START condition, and is set to “0” by detecting the STOP condition. The condition of these detecting is set by the START/STOP condition setting bits (SSC4–SSC0) of the I 2C START/STOP condition control register (S2D: address 0016 16). When the ES0 bit of the I2 C control register (bit 3 of S1D, address 001416) is “0” or reset, the BB flag is set to “0.” For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Generating Method” described later. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER •Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied: • When ALS is “0” • In the slave reception mode or the slave transmission mode • When the R/W bit reception is “1” This bit is set to “0” in one of the following conditions: • When arbitration lost is detected. • When a STOP condition is detected. • When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset •Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to “0” in one of the following conditions. • Immediately after completion of the byte which has lost arbitration when arbitration lost is detected • When a STOP condition is detected. • Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • At reset Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. b7 b0 MST TRX BB PIN AL AAS AD0 LRB I2C status register (S1 : address 001316) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected SCL pin low hold bit 0 : SCL pin low hold 1 : SCL pin low release Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode Note: These bits and flags can be read out, but cannot be written. Write “0” to these bits at writing. Fig. 68 Structure of I2C status register SCL PIN I2CIRQ Fig. 69 Interrupt request signal generating timing 75 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER START Condition Generating Method STOP Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I 2C status register (S1: address 0013 16) at the same time after writing the slave address to the I 2C data shift register (S0: address 001116 ) with the condition in which the ES0 bit of the I 2C control register (S1D: address 0014 16) and the BB flag are “0”, a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 70, the START condition generating timing diagram, and Table 12, the START condition generating timing table. When the ES0 bit of the I 2 C control register (S1D: address 0014 16 ) is “1,” write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2 C status register (S1: address 001316 ) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 71, the STOP condition generating timing diagram, and Table 13, the STOP condition generating timing table. I2C status register write signal SCL I2C status register write signal SCL SDA SDA Setup time Hold time Hold time Fig. 70 START condition generating timing diagram Table 12 START condition generating timing table Standard clock mode High-speed clock mode Item 5.0 µs (20 cycles) 2.5 µs (10 cycles) Setup time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. 76 Setup time Fig. 71 STOP condition generating timing diagram Table 13 STOP condition generating timing table Standard clock mode High-speed clock mode Item 5.0 µs (20 cycles) 3.0 µs (12 cycles) Setup time 4.5 µs (18 cycles) 2.5 µs (10 cycles) Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 72, 73, and Table 14. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 14). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 14, the BB flag set/ reset time. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “I2 CIRQ” occurs to the CPU. SCL release time SCL SDA SCL release time Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 µs) Hold time BB flag set time BB flag Fig. 72 START/STOP condition detecting timing diagram SCL release time SCL SDA BB flag Table 14 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode Setup time Setup time Hold time BB flag reset time Fig. 73 STOP condition detecting timing diagram 4 cycles (1.0 µs) SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (1.0 µs) 2 SSC value + 1 cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs) 2 SSC value –1 + 2 cycles (3.375 µs) 3.5 cycles (0.875 µs) 2 Note: Unit : Cycle number of system clock φ SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2 C START/ STOP condition control register is set to “1816” at φ = 4 MHz. 77 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I2C START/STOP Condition Control Register (S2D)] 001616 The I 2C START/STOP condition control register (S2D: address 001616 ) controls START/STOP condition detection. •Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(X IN) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 14. Do not set “000002 ” or an odd number to the START/STOP condition set bit (SSC4 to SSC0). Refer to Table 15, the recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency. •Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. b7 •Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2 C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/ SDA interrupt pin selection bit, or the I 2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. b0 SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C START/STOP condition control register (S2D : address 001616) START/STOP condition set bits SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid Not used (Fix this bit to “0”.) Fig. 74 Structure of I2C START/STOP condition control register Table 15 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Oscillation frequency f(XIN) (MHz) Main clock divide ratio System clock φ (MHz) 8 2 4 8 8 1 4 2 2 2 2 1 START/STOP condition control register SCL release time (µs) Setup time (µs) Hold time (µs) XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) 3.5 µs (14 cycles) 3.25 µs (13 cycles) 3.0 µs (3 cycles) 3.5 µs (7 cycles) 3.0 µs (6 cycles) 3.0 µs (3 cycles) 3.25 µs (13 cycles) 3.0 µs (12 cycles) 2.0 µs (2 cycles) 3.0 µs (6 cycles) 2.5 µs (5 cycles) 2.0 µs (2 cycles) Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0) and “000002 ”. 78 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I 2 C Special Mode Status Register (S3)] 001216 The I 2C special mode status register (S3: address 0012 16) consists of the flags indicating I 2C operating state in the I2C special mode, which is set by the I2C special mode control register (S3D: address 001716). The stop condition flag is valid in all operating modes. •Bit 0: Slave address 0 comparison flag (AAS0) Bit 1: Slave address 1 comparison flag (AAS1) Bit 2: Slave address 2 comparison flag (AAS2) These flags indicate a comparison result of address data. These flags are valid only when the slave address control bit (MSLAD) is “1”. In the 7-bit addressing format of the slave reception mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I 2C slave address registers 0 to 2 are set to “1” when an address data immediately after an occurrence of a START condition agrees with the high-order 7-bit slave address stored in the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916 ). In the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I 2C slave address registers are set to “1” when an address data is compared with the 8 bits consisting of the slave address stored in the I 2C slave address registers 0 to 2 and the RWB bit, and the first byte agrees. These flags are initialized to “0” at reset, when the slave address control bit (MSLAD) is “0”, or when writing data to the I 2C data shift register (S0: address 001116 ). b7 SPCF •Bit 5: SCL pin low hold 2 flag (PIN2) When the ACK interrupt control bit (ACKICON) and the ACK clock bit (ACK) are “1”, this flag is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2 C interrupt request occurs. This flag is initialized to “1” at reset, when the ACK interrupt control bit (ACKICON) is “0”, or when writing “1” to the SCL pin low hold 2 flag set bit (PIN2IN). The SCL pin is held low when either the SCL pin low hold bit (PIN) or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold state of the SCL pin is released when both the SCL pin low hold bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”. •Bit 7: Stop condition flag (SPCF) This flag is set to “1” when a STOP condition occurs. This flag is initialized to “0” at reset, when the I 2C-BUS interface enable bit (ES0) is “0”, or when writing “1” to the STOP condition flag clear bit (SPFCL). b0 PIN2 AA S2 AA S1 AA S0 I2C special mode status register (S3 : address 001216) Slave address 0 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 1 comparison flag 0 : Address disagreement 1 : Address agreement Slave address 2 comparison flag 0 : Address disagreement 1 : Address agreement Not used (return “0” when read) Not used (return “0” when read) SCL pin low hold 2 flag 0 : SCL pin low hold 1 : SCL pin low release (Note) Not used (return “0” when read) STOP condition flag 0 : No detection 1 : Detection Note: In order that the low hold state of the SCL pin may release, it is necessary that the SCL pin low hold 2 flag and the SCL pin low hold bit (PIN) are “1” simultaneously. Fig. 75 Structure of I2C special mode status register 79 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [I 2C Special Mode Control Register (S3D)] 001716 The I2 C special mode control register (S3D: address 001716 ) controls special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. •Bit 1: ACK interrupt control bit (ACKICON) This bit controls the timing of I2 C interrupt request occurrence at completion of data receiving due to master reception or slave reception. When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in synchronization with the falling of the last SCL clock, including the ACK clock. The SCL pin is simultaneously held low, and the I2 C interrupt request occurs. When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin low hold 2 flag (PIN2) is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs again. The ACK bit can be changed after the contents of data are confirmed by using this function. b7 SPFCL •Bit 2: I2C slave address control bit (MSLAD) This bit controls a slave address. When this bit is “0”, only the I2C slave address register 0 (address 0FF716) becomes valid as a slave address and a read/write bit. When this bit is “1”, all of the I2 C slave address registers 0 to 2 (addresses 0FF7 16 to 0FF9 16 ) become valid as a slave address and a read/write bit. In this case, when an address data agrees with any one of the I2 C slave address registers 0 to 2, the slave address comparison flag (AAS) is set to “1” and the I2C slave address comparison flag corresponding to the agreed I2 C slave address registers 0 to 2 is also set to “1”. •Bit 5: SCL pin low hold 2 flag set bit (PIN2IN) Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2) to “1”. When writing “0”, nothing is generated. •Bit 6: SCL pin low hold set bit (PIN2HD) When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is held low. However, the SCL pin low hold bit (PIN) cannot be set to “0” by software. The SCL pin low hold set bit (PIN2HD) is used to , hold the SCL pin in the low state by software. When writing “1” to this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the SCL pin is held low. When writing “0”, nothing occurs. •Bit 7: STOP condition flag clear bit (SPFCL) Writing “1” to this bit initializes the STOP condition flag (SPCF) to “0”. When writing “0”, nothing is generated. b0 PIN2- PIN2IN HD MSLAD ACK I CON I2C special mode control register (S3D : address 001716) Not used (Fix this bit to “0”.) ACK interrupt control bit 0 : At communication completion 1 : At falling of ACK clock and communication completion Slave address control bit 0 : One-byte slave address compare mode 1 : Three-byte slave address compare mode Not used (return “0” when read) Not used (Fix this bit to “0”.) SCL pin low hold 2 flag set bit (Notes 1, 2) Writing “1” to this bit initializes the SCL pin low hold 2 flag to “1”. SCL pin low hold set bit (Notes 1, 2) When writing “1” to this bit, the SCL pin low hold 2 flag becomes “0” and the SCL pin is held low. STOP condition flag clear bit (Note 2) Writing “1” to this bit initializes the STOP condition flag to “0”. Notes 1: Do not write “1” to these bits simultaneously. 2: return “0” when read Fig. 76 Structure of I2C special mode control register 80 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Data Communication parison, an address comparison between the RWB bit of the I 2C slave address register and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2 C status register (S1: address 001316 ) is set to “1.” After the second-byte address data is stored into the I 2 C data shift register (S0: address 001116), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I 2C slave address register to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I 2C slave address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure 77, (3) and (4). There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. ➀ 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (S1D: address 001416) to “0”. The first 7bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I 2C slave address register. At the time of this comparison, address comparison of the RWB bit of the I2C slave address register is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 75, (1) and (2). ➁ 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I 2C control register (S1D: address 0014 16) to “1.” An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C slave address register. At the time of this com- (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W 7 bits A “0” Data A 1 to 8 bits Data A/A P A P 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 7 bits A “1” Data A 1 to 8 bits Data 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits 7 bits A “0” Slave address 2nd bytes A Data 1 to 8 bits 8 bits Data A A/A P 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S Slave address R/W 1st 7 bits 7 bits S : START condition A : ACK bit Sr : Restart condition “0” A Slave address 2nd bytes 8 bits P : STOP condition R/W : Read/Write bit A Sr Slave address R/W 1st 7 bits 7 bits “1” A Data 1 to 8 bits A Data A P 1 to 8 bits : Master to slave : Slave to master Fig. 77 Address data communication format 81 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Example of Master Transmission Example of Slave Reception An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C slave address register and “0” into the RWB bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516 ” in the I2C clock control register (S2: address 001516 ). ➂ Set “0016” in the I2 C status register (S1: address 0013 16) so that transmission/reception mode can become initializing condition. ➃ Set a communication enable status by setting “0816” in the I2 C control register (S1D: address 001416 ). ➄ Confirm the bus free condition by the BB flag of the I2C status register (S1: address 0013 16). ➅ Set the address data of the destination of transmission in the high-order 7 bits of the I 2C data shift register (S0: address 001116) and set “0” in the least significant bit. ➆ Set “F016” in the I 2 C status register (S1: address 001316) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. ➇ Set transmit data in the I2 C data shift register (S0: address 0011 16). At this time, an SCL and an ACK clock automatically occur. ➈ When transmitting control data of more than 1 byte, repeat step ➇. ➉ Set “D0 16” in the I2 C status register (S1: address 001316) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends. An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C slave address register and “0” in the RWB bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516 ” in the I2C clock control register (S2: address 0015 16). ➂ Set “0016” in the I2 C status register (S1: address 001316) so that transmission/reception mode can become initializing condition. ➃ Set a communication enable status by setting “0816 ” in the I2C control register (S1D: address 001416). ➄ When a START condition is received, an address comparison is performed. ➅ •When all transmitted addresses are “0” (general call): AD0 of the I2C status register (S1: address 001316 ) is set to “1” and an interrupt request signal occurs. • When the transmitted addresses agree with the address set in ➀: AAS of the I 2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs. • In the cases other than the above AD0 and AAS of the I2 C status register (S1: address 001316 ) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2 C data shift register (S0: address 001116). ➇ When receiving control data of more than 1 byte, repeat step ➆. ➈ When a STOP condition is detected, the communication ends. 82 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ■Precautions when using multi-master I 2CBUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I 2C-BUS interface are described below. • I 2C data shift register (S0: address 001116 ) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. • I 2 C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to0FF916 ) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. • I 2C status register (S1: address 001316 ) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. • I 2C control register (S1D: address 0014 16) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. • I 2C clock control register (S2: address 0015 16) The read-modify-write instruction can be executed for this register. • I 2C START/STOP condition control register (S2D: address 0016 16) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5. :: LDA — (Taking out of slave address value) SEI (Interrupt disabled) BBS 5, S1, BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) :: BUSBUSY: CLI (Interrupt enabled) :: 5. Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is “0.” :: LDM #$00, S1 (Select slave receive mode) LDA — (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) :: 2. Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2 C data shift register. 4. Disable interrupts during the following two process steps: • Writing of slave address value • Trigger of RESTART condition generating (4) Writing to I 2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. 2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag confirming and branch process. 3. Use “STA $12, STX $12” or “STY $12” of the zero page addressing instruction for writing the slave address value to the I2 C data shift register. 4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure example. 83 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an "L" level for 16 cycles or more of XIN. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Poweron RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage ; Vcc=2.7 V RESET VCC Power source voltage detection circuit Fig. 78 Reset circuit example XIN φ RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. ? Data ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 79 Reset sequence 84 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents Address Register contents (1) Port P0 (P0) 000016 0016 (34) Timer Z (low-order) (TZL) 002816 FF16 (2) Port P0 direction register (P0D) 000116 0016 (35) Timer Z (high-order) (TZH) 002916 FF16 (3) Port P1 (P1) 000216 0016 (36) Timer Z mode register (TZM) 002A16 0016 (4) Port P1 direction register (P1D) 000316 0016 (37) PWM control register (PWMCON) 002B16 0016 (5) Port P2 (P2) 000416 0016 (38) PWM prescaler (PREPWM) 002C16 X X X X X X X X (6) Port P2 direction register (P2D) 000516 0016 (39) PWM register (PWM) 002D16 X X X X X X X X (7) Port P3 (P3) 000616 0016 (40) Baud rate generator 3 (BRG3) 002F16 X X X X X X X X (8) Port P3 direction register (P3D) 000716 0016 (41) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (9) Port P4 (P4) 000816 0016 (42) Serial I/O3 status register (SIO3STS) 003116 1 0 0 0 0 0 0 0 (10) Port P4 direction register (P4D) 000916 0016 (43) Serial I/O3 control register (SIO3CON) 003216 (11) Port P5 (P5) 000A16 0016 (44) UART3 control register (SIO3CON) 003316 1 1 1 0 0 0 0 0 (12) Port P5 direction register (P5D) 000B16 0016 (45) AD/DA control register (ADCON) 003416 0 0 0 0 1 0 0 0 (13) Port P6 (P6) 000C16 0016 (46) A-D conversion register 1 (AD1) 003516 X X X X X X X X (14) Port P6 direction register (P6D) 000D16 0016 (47) D-A1 conversion register (DA1) 003616 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (48) D-A2 conversion register (DA2) 003716 0016 (16) Timer Y, Z count source selection register (TYZCSS) 000F16 0 0 1 1 0 0 1 1 (49) A-D conversion register 2 (AD2) 003816 0 0 0 0 0 0 X X (50) Interrupt source selection register (INTSEL) 003916 0016 0016 0016 (17) MISRG 001016 (18) Transmit/Receive buffer register 1 (TB1/RB1) 001816 X X X X X X X X (51) Interrupt edge selection register (INTEDGE) 003A16 (19) Serial I/O1 status register (SIO1STS) 001916 1 0 0 0 0 0 0 0 (52) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (20) Serial I/O1 control register (SIO1CON) 001A16 (53) Interrupt request register 1 (IREQ1) 003C16 0016 (21) UART1 control register (UART1CON) 001B16 1 1 1 0 0 0 0 0 (54) Interrupt request register 2 (IREQ2) 003D16 0016 (22) Baud rate generator 1 (BRG1) 001C16 X X X X X X X X (55) Interrupt control register 1 (ICON1) 003E16 0016 (23) Serial I/O2 control register (SIO2CON) 001D16 (56) Interrupt control register 2 (ICON2) 003F16 0016 (24) Watchdog timer control register (WDTCON) 001E16 0 0 1 1 1 1 1 1 (57) Port P0 pull-up control register (PULL0) 0FF016 0016 (25) Serial I/O2 register (SIO2) 001F16 X X X X X X X X (58) Port P1 pull-up control register (PULL1) 0FF116 0016 (26) Prescaler 12 (PRE12) 002016 FF16 (59) Port P2 pull-up control register (PULL2) 0FF216 0016 (27) Timer 1 (T1) 002116 0116 (60) Port P3 pull-up control register (PULL3) 0FF316 0016 (28) Timer 2 (T2) 002216 FF16 (61) Port P4 pull-up control register (PULL4) 0FF416 0016 (29) Timer XY mode register (TM) 002316 0016 (62) Port P5 pull-up control register (PULL5) 0FF516 0016 (30) Prescaler X (PREX) 002416 FF16 (63) Port P6 pull-up control register (PULL6) 0FF616 0016 (31) Timer X (TX) 002516 FF16 (64) Flash memory control register (FCON) 0FFE16 0016 (32) Prescaler Y (PREY) 002616 FF16 (65) Flash command register (FCMD) 0FFF16 0016 (33) Timer Y (TY) 002716 FF16 (66) Processor status register (PS) (67) Program counter (PCH) FFFD16 contents (PCL) FFFC16 contents 0016 0016 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. X X X X X 1 X X Fig. 80 Internal status at reset (3803 group) 85 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents (1) 000016 0016 (41) Timer Z (low-order) (TZL) 002816 FF16 Port P0 direction register (P0D) 000116 0016 (42) Timer Z (high-order) (TZH) 002916 FF16 Port P1 (P1) 000216 0016 (43) Timer Z mode register (TZM) 002A16 0016 (4) Port P1 direction register (P1D) 000316 0016 (44) PWM control register (PWMCON) 002B16 0016 (5) Port P2 (P2) 000416 0016 (45) PWM prescaler (PREPWM) 002C16 X X X X X X X X (6) Port P2 direction register (P2D) 000516 0016 (46) PWM register (PWM) 002D16 X X X X X X X X (7) Port P3 (P3) 000616 0016 (47) Baud rate generator 3 (BRG3) 002F16 X X X X X X X X (8) Port P3 direction register (P3D) 000716 0016 (48) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (9) Port P4 (P4) 000816 0016 (49) Serial I/O3 status register (SIO3STS) 003116 1 0 0 0 0 0 0 0 000916 0016 (50) Serial I/O3 control register (SIO3CON) 003216 (11) Port P5 (P5) 000A16 0016 (51) UART3 control register (SIO3CON) 003316 1 1 1 0 0 0 0 0 (12) Port P5 direction register (P5D) 000B16 0016 (52) AD/DA control register (ADCON) 003416 0 0 0 0 1 0 0 0 (13) Port P6 (P6) 000C16 0016 (53) A-D conversion register 1 (AD1) 003516 X X X X X X X X (14) Port P6 direction register (P6D) 000D16 0016 (54) D-A1 conversion register (DA1) 003616 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (55) D-A2 conversion register (DA2) 003716 0016 (16) Timer Y, Z count source selection register (TYZCSS) 000F16 0 0 1 1 0 0 1 1 (56) A-D conversion register 2 (AD2) 003816 0 0 0 0 0 0 X X (2) (3) Port P0 (P0) (10) Port P4 direction register (P4D) 0016 (17) MISRG 001016 (57) Interrupt source selection register (INTSEL) 003916 0016 (18) I2C data shift register (S0) 001116 X X X X X X X X (58) Interrupt edge selection register (INTEDGE) 003A16 0016 (19) I2C special mode status register (S3) 001216 0 0 1 0 0 0 0 0 (59) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (20) I2C status register (S1) 001316 0 0 0 1 0 0 0 X (60) Interrupt request register 1 (IREQ1) 003C16 0016 (21) I2C control register (S1D) 001416 0016 (61) Interrupt request register 2 (IREQ2) 003D16 0016 001516 0016 (62) Interrupt control register 1 (ICON1) 003E16 0016 (23) I2C START/STOP condition control register (S2D)001616 0 0 0 1 1 0 1 0 (63) Interrupt control register 2 (ICON2) 003F16 0016 (24) (64) Port P0 pull-up control register (PULL0) 0FF016 0016 001816 X X X X X X X X (65) Port P1 pull-up control register (PULL1) 0FF116 0016 (26) Serial I/O1 status register (SIO1STS) 001916 1 0 0 0 0 0 0 0 (66) Port P2 pull-up control register (PULL2) 0FF216 0016 (27) Serial I/O1 control register (SIO1CON) 001A16 (67) Port P3 pull-up control register (PULL3) 0FF316 0016 (22) I2C clock control register (S2) I 2C special mode control register (S3D) (25) Transmit/Receive buffer register 1 (TB1/RB1) 001716 0016 0016 0016 (28) UART1 control register (UART1CON) 001B16 1 1 1 0 0 0 0 0 (68) Port P4 pull-up control register (PULL4) 0FF416 0016 (29) Baud rate generator 1 (BRG1) 001C16 X X X X X X X X (69) Port P5 pull-up control register (PULL5) 0FF516 0016 (30) Serial I/O2 control register (SIO2CON) (70) Port P6 pull-up control register (PULL6) 0FF616 0016 (71) I2C slave address register 0 (S0D0) 0FF716 0016 001D16 0016 (31) Watchdog timer control register (WDTCON) 001E16 0 0 1 1 1 1 1 1 (32) Serial I/O2 register (SIO2) 001F16 X X X X X X X X (72) I2C slave address register 1 (S0D1) 0FF816 0016 002016 FF16 (73) I2C 0FF916 0016 002116 0116 (74) Flash memory control register (FCON) 0FFE16 0016 (35) Timer 2 (T2) 002216 FF16 (75) Flash command register (FCMD) 0FFF16 (36) Timer XY mode register (TM) 002316 0016 (76) Processor status register (PS) (37) Prescaler X (PREX) 002416 FF16 (77) Program counter (PCH) FFFD16 contents (38) Timer X (TX) 002516 FF16 (PCL) FFFC16 contents (39) Prescaler Y (PREY) 002616 FF16 (40) Timer Y (TY) 002716 FF16 (33) Prescaler 12 (PRE12) (34) Timer 1 (T1) Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 81 Internal status at reset (3804 group) 86 Address Register contents slave address register 2 (S0D3) 0016 X X X X X 1 X X MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The M38039FFSP/FP has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (X CIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and X OUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT. Immediately after power on, only the X IN oscillation circuit starts oscillating, and XCIN and X COUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN . (3) Low-speed mode The internal clock φ is half the frequency of XCIN . ■Note If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN ). Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and X CIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF16 ” and timer 1 is set to “0116 .” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to “1” before the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts when an interrupt is received or reset. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. 87 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT Rf CCIN XIN XOUT Rd CCOUT CIN COUT Fig. 82 Ceramic resonator circuit XCIN XCOUT XIN Open Open External oscillation circuit External oscillation circuit VCC VSS VCC VSS Fig. 83 External clock input circuit 88 XOUT MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCOUT XCIN “0” “1” Port XC switch bit XOUT XIN Main clock division ratio selection bits (Note 1) Divider Low-speed mode 1/2 Prescaler 12 1/4 High-speed or middle-speed mode Timer 1 Reset or 0116 STP instruction FF16 (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode Timing φ (internal clock) High-speed or low-speed mode Main clock stop bit Q S R S Q STP instruction WIT instruction R Q S R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: f(XIN)/16 or f(XCIN)/16 is supplied as the count source to the prescaler 12 at executing the STP instruction or reset. Fig. 84 System clock generating circuit block diagram (Single-chip mode) 89 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) C “0 M4 CM ”← “1 6 →“ 1” ”← → “0 ” ” “0 → M C ”← 0” “1 M6 →“ C ”← “1 4 CM6 “1”←→“0” C “0 M7 CM ”←→ “1 6 “1 ”← ” → “0 ” C M4 “1”←→“0” C M4 “1”←→“0” CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped) Middle-speed mode (f(φ)=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) High-speed mode (f(φ)=4 MHz) C M6 “1”←→“0” High-speed mode (f(φ)=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) C M7 “1”←→“0” Middle-speed mode (f(φ)=1 MHz) Low-speed mode (f(φ)=16 kHz) C M5 “1”←→“0” CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating) Low-speed mode (f(φ)=16 kHz) CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 85 State transitions of system clock 90 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FLASH MEMORY MODE Functional Outline (parallel input/output mode) The 3803/3804 group has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this mode to perform read, program, and erase operations for the internal flash memory. The 3803/3804 group has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external programmer, and the CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). The following explains these modes. In the parallel input/output mode, the 3803/3804 group allow the user to choose an operation mode between the read-only mode and the read/write mode (software command control mode) depending on the voltage applied to the VPP pin. When V PP = VPPL, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) depending on ___ ___ ___ inputs to the CE, OE, and WE pins. When V PP = V PPH, the read/ write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on inputs __ __ ___ to the CE, OE, and WE pins. Table 17 shows assignment states of control input and each state. (1) Flash memory mode 1 (parallel I/O mode) ● Read __ The microcomputer enters the read state by driving the CE, and __ ___ OE pins low and the WE pin high; and the contents of memory corresponding to the address to be input to address input pins (A0–A16 ) are output to the data input/output pins (D0–D7 ). The parallel I/O mode can be selected by connecting wires as shown in Figures 86, 87 and supplying power to the V CC and V PP pins. In this mode, the M38039FFSP/FP/HP operates as an equivalent of MITSUBISHI’s CMOS flash memory M5M28F101. However, because the M38039FFSP/FP/HP’s internal memory has a capacity of 60 Kbytes, programming is available for addresses 0100016 to 0FFFF16, and make sure that the data in addresses 00000 16 to 00FFF16 and addresses 10000 16 to 1FFFF 16 are FF 16 . Note also that the M38039FFSP/FP/HP does not contain a facility to read out a device identification code by applying a high voltage to address input (A9). Be careful not to erratically set program conditions when using a general-purpose PROM programmer. Table 16 shows the pin assignments when operating in the parallel input/output mode. ● Output disable The microcomputer enters the output disable state by driving the __ ___ __ CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state. ● Standby __ The microcomputer enters the standby state by driving the CE pin high. the 3803/3804 group is placed in a power-down state consuming only a minimum supply current. At this time, the data input/ output pins enter the floating state. Table 16 Pin assignments of M38039FFSP/FP/HP when operating in the parallel input/output mode VCC VPP VSS Address input Data I/O __ CE ___ OE ___ WE M38039FFSP/FP/HP VCC CNVSS VSS Ports P0, P1, P31 Port P2 P36 P37 P33 ● Write The microcomputer enters the write state by driving the V PP pin ___ __ high (V PP = V PP H) and then the WE pin low when the CE pin is __ low and the OE pin is high. In this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this software command. M5M28F101 VCC VPP VSS A0–A16 D0–D7 __ CE __ OE ___ WE Table 17 Assignment states of control input and each state Pin Mode Read-only Read/Write State Read Output disable Standby Read Output disable Standby Write CE __ OE __ ___ WE VPP Data I/O VIL VIL VIH VIL VIL VIH VIL VIL VIH × VIL VIH × VIH VIH VIH × VIH VIH × VIL VPPL VPPL VPPL VPPH VPPH VPPH VPPH Output Floating Floating Output Floating Floating Input Note: × can be V IL or VIH. 91 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 18 Pin description (flash memory parallel I/O mode) Pin Name VCC, VSS CNVSS _____ RESET XIN XOUT AVSS VREF P00–P07 P10–P17 P20 –P27 P30–P37 Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Address input (A0–A7) Address input (A8–A15) Data I/O (D0–D7) Control signal input P40–P47 P50 –P57 P60 –P67 Input port P4 Input port P5 Input port P6 92 Input /Output — Input Input Input Output — Input Input Input I/O Input Input Input Input Functions Supply 5 V ± 10 % to VCC and 0 V to VSS. Supply 5 V ± 10 % in read-only mode, supply 11.7 V to 12.6 V in read/write mode. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Connect to VSS. Port P0 functions as 8-bit address input (A0–A7). Port P1 functions as 8-bit address input (A8–A15). Function as 8-bit data’s I/O pins__ (D0__ –D7). ___ P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as the A16 input pin. Connect P3 0 and P32 to VSS. Input “H” or “L” to P34, P35, or keep them open. Connect P44, P4 6 to VSS. Input “H” or “L” to P40 - P43, P45, P4 7, or keep them open. Input “H” or “L”, or keep them open. Input “H” or “L”, or keep them open. MITSUBISHI MICROCOMPUTERS 3803/3804 Group P17 33 A15 P16 34 A14 P15 35 A13 P14 36 A11 P13 37 A12 P12 38 A9 P11 39 A10 P10 40 A8 P07/AN15 41 A7 A5 P06/AN14 42 A6 A4 P05/AN13 43 A3 P03/AN11 P04/AN12 45 44 P02/AN10 46 A2 P01/AN9 47 A0 P00/AN8 48 OE P37 49 32 P20(LED0) D0 CE P36 50 31 P21(LED1) D1 P35 51 30 P22(LED2) D2 P34 52 29 P23(LED3) D3 P33 53 28 P24(LED4) D4 P32 54 27 P25(LED5) D5 P31/DA2 55 26 P26(LED6) D6 P30/DA1 56 25 P27(LED7) D7 VCC 57 24 VSS VREF 58 23 XOUT M38039FFFP/HP 15 16 P43/INT2 P46/SCLK1 14 12 13 P47/SRDY1 P45/TXD1 11 P50/SIN2 P44/RXD1 10 P42/INT1 P51/SOUT2 17 9 64 P52/SCLK2 P63/AN3 8 RESET CNVSS P53/SRDY2 18 7 63 P54/CNTR0 P64/AN4 6 19 P55/CNTR1 62 5 P41/INT0/XCIN P65/AN5 P56/PWM 20 4 61 P57/INT3 P40/INT4/XCOUT P66/AN6 3 XIN 21 P60/AN0 22 60 2 59 1 AVSS P67/AN7 P61/AN1 A16 P62/AN2 WE VCC A1 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VSS ✽ VPP to the ceramic oscillation circuit. * :Connect indicates the flash memory pin. Outline 64P6N-A/64P6Q-A Fig. 86 Pin connection of M38039FFFP/HP when operating in parallel input/output mode 93 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38039FFSP VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS VPP RESET P41/INT0/XCIN P40/INT4/XCOUT XIN ✽ XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34 P35 P36 P37 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10 P11 P12 P13 P14 P15 P16 P17 P20/(LED0) P21/(LED1) P22/(LED2) P23/(LED3) P24/(LED4) P25/(LED5) P26/(LED6) P27/(LED7) A16 WE CE OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 to the ceramic oscillation circuit. * :Connect indicates the flash memory pin. Outline 64P4B Fig. 87 94 Pin connection of M38039FFSP when operating in parallel input/output mode MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Read-only Mode shown in Figure 88, and the M38039FFSP/FP/HP will output the contents of the user’s specified address from data I/O pin to the external. In this mode, the user cannot perform any operation other than read. The microcomputer enters the read-only mode by applying V PPL to the V PP pin. In this mode, the user can input the address of a memory location to be read and the control signals at the timing VIH Address Valid address VIL tRC VIH CE VIL ta(CE) VIH OE VIL tWRR tDF VIH WE VIL VOH Data ta(OE) Floating Dout tCLZ VOL tDH tOLZ Floating ta(AD) Fig. 88 Read timing Read/Write Mode The microcomputer enters the read/write mode by applying VPP H to the VPP pin. In this mode, the user must first input a software command to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called the second cycle). When this is done, the 3803/3804 group executes the specified operation. Table 19 shows the software commands and the input/output information in the first and the second cycles. The input address is ___ latched internally at the falling edge of the WE input; software commands and other input data are latched internally at the rising ___ edge of the WE input. The following explains each software command. Refer to Figures 89 to 91 for details about the signal input/output timings. Table 19 Software command (Parallel input/output mode) Symbol Read Program Program verify Erase Erase verify Reset Device identification First cycle Address input × × × × Verify address × × Data input 0016 4016 C0 16 2016 A016 FF16 9016 Second cycle Address input Data I/O Read address Read data (Output) Program address Program data (Input) × Verify data (Output) × 2016 (Input) × Verify data (Output) × FF16 (Input) ADI DDI (Output) Note: ADI = Device identification address : manufacturer’s code 00000 16, device code 00001 16 DDI = Device identification data : manufacturer’s code 1C 16, device code D0 16 X can be VIL or VIH. 95 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Read command The microcomputer enters the read mode by inputting command code “00 16” in the first cycle. The command code is latched into ___ the internal command latch at the rising edge of the WE input. When the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in Figure 89, the 3803/3804 group outputs the contents of the specified address from the data I/O pins to the external. The read mode is retained until any other command is latched into the command latch. Consequently, once the 3803/3804 group enters the read mode, the user can read out the successive memory contents simply by changing the input address and executing the second cycle only. Any command other than the read command must be input beginning from its command code over again each time the user execute it. The contents of the command latch immediately after power-on is 0016 . VIH Address Valid address VIL tRC tWC VIH CE VIL tCH ta(CE) tCS VIH OE VIL tRRW tWP tWRR tDF VIH WE VIL ta(OE) tDS VIH Data VIL tDH tVSC VPPH VPP VPPL Fig. 89 Timings during reading 96 tOLZ 0016 tCLZ ta(AD) Dout tDH MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Program command The microcomputer enters the program mode by inputting command code “4016 ” in the first cycle. The command code is latched ___ into the internal command latch at the rising edge of the WE input. When the address which indicates a program location and data is input in the second cycle, the 3803/3804 group internally latches ___ the address at the falling edge of the WE input and the data at the ___ rising edge of the WE input. The 3803/3804 group starts program___ ming at the rising edge of the WE input in the second cycle and finishes programming within 10 µs as measured by its internal timer. Programming is performed in units of bytes. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 92 for the programming flowchart. ● Program verify command The microcomputer enters the program verify mode by inputting command code “C016 ” in the first cycle. This command is used to verify the programmed data after executing the program command. The command code is latched into the internal command ___ latch at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 90, the 3803/3804 group outputs the programmed address’s contents to the external. Since the address is internally latched when the program command is executed, there is no need to input it in the second cycle. Program verify VIH Program address Address VIL tAS tWC Program tAH VIH CE VIL tCS tCS tCS tCH tCH tCH VIH OE VIL tRRW tWP tWPH tWP tDP tWP tWRR VIH WE VIL tDS tDS tDS VIH 4016 Data VIL DIN tDH C016 tDH Dout tDH Verify data output tVSC VPPH VPP VPPL Fig. 90 Input/output timings during programming (Verify data is output at the same timing as for read.) 97 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Erase command The erase command is executed by inputting command code 2016 in the first cycle and command code 2016 again in the second cycle. The command code is latched into the internal command ___ latch at the rising edges of the WE input in the first cycle and in the second cycle, respectively. The erase operation is initiated at ___ the rising edge of the WE input in the second cycle, and the memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 00 16 must be written to all memory locations before executing the erase command. Note: An erase operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 92 for the erase flowchart. ● Erase verify command The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase verify mode by inputting the verify address and command code A016 in the first cycle. The address is internally latched at the fall___ ing edge of the WE input, and the command code is internally ___ latched at the rising edge of the WE input. When control signals are input in the second cycle at the timing shown in Figure 91, the 3803/3804 group outputs the contents of the specified address to the external. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing. Erase verify VIH Address Erase VIL Verify address tAS tWC tAH VIH CE VIL tCS tCS tCS tCH tCH tCH VIH OE VIL tRRW tWP tWPH tWP tDE tWP tWRR VIH WE VIL tDS tDS tDS VIH 2016 Data 2016 A016 VIL tVSC tDH tDH tDH VPPH VPP VPPL Fig. 91 Input/output timings during erasing (Verify data is output at the same timing as for read.) 98 Dout Verify data output MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Reset command The reset command provides a means of stopping execution of the erase or program command safely. If the user inputs command code FF 16 in the second cycle after inputting the erase or program command in the first cycle and again input command code FF 16 in the third cycle, the erase or program command is disabled (i.e., reset), and the 3803/3804 group is placed in the read mode. If the reset command is executed, the contents of the memory does not change. ● Device identification code command By inputting command code 9016 in the first cycle, the user can read out the device identification code. The command code is latched into the internal command latch at the rising edge of the ___ WE input. At this time, the user can read out manufacture’s code 1C16 (i.e., MITSUBISHI) by inputting 0000016 to the address input pins in the second cycle; the user can read out device code D0 16 (i. e., 1M-bit flash memory) by inputting 0000116 . These command and data codes are input/output at the same timing as for read. 99 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Program Erase START START VCC = 5 V, VPP = VPPH VCC = 5 V, VPP = VPPH ADRS = first location ALL BYTES = 0016 ? YES X=0 NO WRITE PROGRAM COMMAND 4016 WRITE PROGRAM DATA DIN PROGRAM ALL BYTES = 0016 ADRS = first location X=0 DURATION = 10 µs X=X+1 WRITE PROGRAM-VERIFY COMMAND C016 WRITE ERASE COMMAND 2016 WRITE ERASE COMMAND 2016 DURATION = 9.5 ms DURATION = 6 µs YES X=X+1 X = 25 ? WRITE ERASE-VERIFY COMMAND NO PASS FAIL VERIFY BYTE ? DURATION = 6 µs VERIFY BYTE ? PASS FAIL YES X = 1000 ? NO INC ADRS A016 LAST ADRS ? NO YES WRITE READ COMMAND PASS FAIL VERIFY BYTE ? 0016 VERIFY BYTE ? FAIL PASS VPP = VPPL NO INC ADRS DEVICE PASSED DEVICE FAILED LAST ADRS ? YES WRITE READ COMMAND 0016 VPP = VPPL DEVICE PASSED Fig. 92 Programming/Erasing algorithm flow chart 100 DEVICE FAILED MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 20 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol Parameter Test conditions Limits Typ. Max. 1 __ ISB1 ISB2 Min. VCC = 5.5 V, CE = VIH V CC = 5.5 V, __ CE = VCC ± 0.2 V __ VCC = 5.5 V, CE = VIL, tRC = 150 ns, I OUT = 0 mA VPP = VPPH VPP = VPPH 0≤VPP≤VCC VCC <VPP≤VCC + 1.0 V VPP = VPPH VPP = VPPH VPP = VPPH VCC supply current (at standby) ICC1 VCC supply current (at read) ICC2 ICC3 VCC supply current (at program) VCC supply current (at erase) IPP1 VPP supply current (at read) IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VPPL VPPH VPP supply current (at program) VPP supply current (at erase) “L” input voltage “H” input voltage “L” output voltage 0 2.0 IOL = 2.1 mA I OH = –400 µA I OH = –100 µA “H” output voltage VPP supply voltage (read only) VPP supply voltage (read/write) 2.4 VCC –0.4 VCC 11.7 12.0 Unit mA 100 µA 15 mA 15 15 10 100 100 30 30 0.8 VCC 0.45 mA mA µA µA µA mA mA V V V V V V V VCC + 1.0 12.6 AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted) Table 21 Read-only mode Symbol tRC ta(AD) ta(CE) ta(OE) tCLZ tOLZ tDF tDH tWRR Parameter Read cycle time Address access time __ CE access time __ OE access time __ Output enable time (after CE) __ Output enable time (after OE) __ Output floating time (after OE) __ __ Output valid time (after CE, OE, address) Write recovery time (before read) Limits Min. 250 Max. 250 250 100 0 0 35 0 6 Unit ns ns ns ns ns ns ns ns µs Table 22 Read/Write mode Symbol tWC tAS tAH tDS tDH tWRR tRRW tCS tCH tWP tWPH tDP tDE tVSC Parameter Write cycle time Address set up time Address hold time Data setup time Data hold time Write recovery time (before read) Read recovery time (before write) __ CE setup time __ CE hold time Write pulse width Write pulse waiting time Program time Erase time VPP setup time Limits Min. 150 0 60 50 10 6 0 20 0 60 20 10 9.5 1 Max. Unit ns ns ns ns ns µs µs ns ns ns ns µs ms µs Note: Read timing of Read/Write mode is same as Read-only mode. 101 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER __ (2) Flash memory mode 2 (serial I/O mode) and OE pins high after connecting wires as shown in Figures 93, 94 and powering on the VCC pin and then applying VPP H to the VPP pin. In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and error check. Serial input/output is accomplished synchronously with the clock, beginning from the LSB (LSB first). P07/AN15 P10 P11 P12 P13 P14 P15 P16 P17 40 39 38 37 36 35 34 33 P06/AN14 42 41 P04/AN12 P05/AN13 43 45 44 P02/AN10 P03/AN11 46 P00/AN8 P01/AN9 47 49 32 P20(LED0) P36 50 31 P21(LED1) P35 51 30 P22(LED2) P34 52 29 P23(LED3) P33 53 28 P24(LED4) P32 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT M38039FFFP/HP 13 14 15 P46/SCLK1 P45/TXD1 P44/RXD1 SCLK 16 12 P47/SRDY1 BUSY Vpp P43/INT2 11 P50/SIN2 VSS ✽ SDA 10 P51/SOUT2 P42/INT1 9 17 P52/SCLK2 64 8 CNVSS P63/AN3 7 18 P53/SRDY2 63 P54/CNTR0 RESET P64/AN4 6 19 5 62 P56/PWM P41/INT0/XCIN P65/AN5 P55/CNTR1 20 4 61 3 P40/INT4/XCOUT P66/AN6 P60/AN0 XIN 21 P57/INT3 22 60 2 59 1 AVSS P67/AN7 P62/AN2 VCC P37 P61/AN1 OE 48 The flash memory version of the 3803/3804 group has a function to serially input/output the software commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a few pins. This is called the serial I/O (input/output) mode. This mode can be selected by driving the SDA (serial data input/output), SCLK (serial clock input ), ✽ :Connect to the ceramic oscillation circuit. indicates the flash memory pin. Outline 64P6N-A/64P6Q-A Fig. 93 Pin connection of M38039FFFP/HP when operating in serial I/O mode 102 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38039FFSP VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 BUSY P47/SRDY1 P46/SCLK1 SCLK P45/TXD1 SDA P44/RXD1 P43/INT2 P42/INT1 Vp p CNVSS RESET P41/INT0/XCIN P40/INT4/XCOUT XIN ✽ XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34 P35 P36 P37 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10 P11 P12 P13 P14 P15 P16 P17 P20/(LED0) P21/(LED1) P22/(LED2) P23/(LED3) P24/(LED4) P25/(LED5) P26/(LED6) P27/(LED7) OE ✽ :Connect to the ceramic oscillation circuit. indicates the flash memory pin. Outline 64P4B Fig. 94 Pin connection of M38039FFSP when operating in serial I/O mode 103 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 23 Pin description (flash memory serial I/O mode) Pin Name VCC, VSS CNVSS _____ RESET XIN XOUT AVSS VREF P00–P07 P10–P17 P20–P27 Power supply VPP input Reset input Clock input Clock output Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 P30–P36 P37 P40–P43, P45 P44 P46 P47 P50–P57 P60–P67 Input port P3 Control signal input Input port P4 104 SDA I/O SCLK input BUSY output Input port P5 Input port P6 Input /Output — Input Input Input Output — Input Input Input Input Input Input Input I/O Input Output Input Input Functions Supply 5 V ± 10 % to VCC and 0 V to VSS. Supply 11.7 V to 12.6 V. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Connect to VSS. Input an arbitrary level between the range of VSS and V CC. Input “H” or “L”, or keep them open. Input “H” or “L”, or keep them open. Input “H” or “L”, or keep them open. Input “H” or “L”, or keep them open. __ OE input pin Input “H” or “L” to P40 - P43, P45, or keep them open. This pin is for serial data I/O. This pin is for serial clock input. This pin is for BUSY signal output. Input “H” or “L”, or keep them open. Input “H” or “L”, or keep them open. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Functional Outline (serial I/O mode) In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the contents of the command. Table 24 shows the software commands used in the serial I/O mode. The following explains each software command. In the serial I/O mode, data is transferred synchronously with the clock using serial input/output. The input data is read from the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of eight bits. Table 24 Software command (serial I/O mode) Number of transfers First command Second Command code input Read 0016 Read address L (Input) Program 4016 Program address L (Input) Program verify C0 16 Verify data (Output) Erase 2016 2016 (Input) Erase verify A016 Verify address L (Input) Error check 8016 Error code (Output) Third Fourth Read address H (Input) Program address H (Input) ————— ————— Verify address H (Input) ————— Read data (Output) Program data (Input) ————— ————— Verify data (Output) ————— __ ● Read command Input command code 0016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and __ pull the OE pin low. When this is done, the 3803/3804 group reads out the contents of the specified address, and then latchs it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been latched into the data latch is serially output from the SDA pin. tCH tCH SCLK A0 SDA A7 0 0 0 0 0 0 0 0 Command code input (0016) Read address input (L) A8 A15 Read address input (H) tCR D0 tWR tRC D7 Read data output OE Read BUSY “L” Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 95 Timings during reading 105 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Program command Input command code 4016 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. Programming is initiated at the last rising edge of the serial clock during program data transfer. The BUSY pin is driven high during program operation. Programming is completed within 10 µs as measured by the internal timer, and the BUSY pin is pulled low. tCH Note : A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the verification. Refer to Figure 92 for the programming flowchart. tCH tCH SCLK tPC A0 SDA 0 0 0 0 0 0 1 0 Command code input (4016) A7 A8 D0 A15 Program address input (L) Program address input (H) D7 Program data input OE tWP Program BUSY Fig. 96 Timings during programming ● Program verify command Input command code C016 in the first transfer. Proceed and drive __ the OE pin low. When this is done, the 3803/3804 group verifyreads the programmed address’s contents, and then latchs it into __ the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been latched into the data latch is serially output from the SDA pin. SCLK D0 SDA 0 0 0 0 0 0 1 1 Command code input (C016) D7 Verify data output tCRPV tWR tRC OE Verify read BUSY “L” Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 97 Timings during program verify 106 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Erase command Input command code 2016 in the first transfer and command code 20 16 again in the second transfer. When this is done, the 3803/ 3804 group executes an erase command. Erase is initiated at the last rising edge of the serial clock. The BUSY pin is driven high during the erase operation. Erase is completed within 9.5 ms as measured by the internal timer, and the BUSY pin is pulled low. Note that data 0016 must be written to all memory locations before executing the erase command. Note: A erase operation is not completed by executing the erase command once. Always be sure to execute a erase verify command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification. Refer to Figure 92 for the erase flowchart. tCH SCLK tEC SDA 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Command code input (2016) Command code input (2016) “H” OE twE BUSY Erase Fig. 98 Timings at erasing ● Erase verify command The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first transfer. Proceed and input the low-order 8 bits and the high-order __ 8 bits of the address and pull the OE pin low. When this is done, the 3803/3804 group reads out the contents of the specified ad__ dress, and then latchs it into the internal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, tCH the verify data that has been latched into the data latch is serially output from the SDA pin. Note: If any memory location where the contents have not been erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case, however, the user does not need to write data 0016 to memory locations before erasing. tCH SCLK A0 SDA A7 0 0 0 0 0 1 0 1 Command code input (A016) Verify address input (L) A8 A15 Verify address input (H) tCREV D0 tWR tRC D7 Verify data output OE Verify read BUSY “L” Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit). Fig. 99 Timings during erase verify 107 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Error check command Input command code 8016 in the first transfer, and the 3803/3804 group outputs error information from the SDA pin, beginning at the next falling edge of the serial clock. If the LSB bit of the 8-bit error information is 1, it indicates that a command error has occurred. A command error means that some invalid commands other than commands shown in Table 24 has been input. When a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). Therefore, if the user wants to execute an error check command, temporarily drop the VPP pin input to the V PPL level to terminate the serial input/output mode. Then, place the 3803/3804 group into the serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error flag alone is not cleared by this operation, so the user can examine the serial communication circuit’s error conditions before reset. This examination is done by the first execution of an error check command after the reset. The error flag is cleared when the user has executed the error check command. Because the error flag is undefined immediately after power-on, always be sure to execute the error check command. tCH SCLK E0 SDA OE 0 0 0 0 0 0 0 1 Command code input (8016) ? ? ? ? ? ? ? Error flag output “H” BUSY “L” Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit). Fig. 100 Timings at error checking 108 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 V to 12.6 V, unless otherwise noted) I CC, IPP -relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL , IIH, and __ I IL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes. Table 25 AC Electrical characteristics (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 V to 12.6 V, f(XIN) = 10 MHz, unless otherwise noted) Symbol tCH tCR tWR tRC tCRPV tWP tPC tCREV tWE tEC tc(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) td(C-Q) th(C-Q) th(C-E) tsu(D-C) th(C-D) Limits Min. Max. 500(Note 1) 500(Note 1) 400(Note 2) 500(Note 1) 6 10 500(Note 1) 6 9.5 500(Note 1) 250 100 100 20 20 0 90 0 150(Note 3) 250(Note 4) 30 90 Parameter Serial transmission interval Read waiting time after transmission Read pulse width Transfer waiting time after read Waiting time before program verify Programming time Transfer waiting time after programming Waiting time before erase verify Erase time Transfer waiting time after erase SCLK input cycle time SCLK high-level pulse width SCLK low-level pulse width SCLK rise time SCLK fall time SDA output delay time SDA output hold time SDA output hold time (only the 8th bit) SDA input set up time SDA input hold time Unit ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 1. 5000 × 106 f(XIN) 2: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 2. Formula 1 : 4000 × 106 f(XIN) 3: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 3. Formula 2 : 1500 × 106 f(XIN) 4: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 4 Formula 3 : Formula 4 : 2500 f(XIN) × 106 AC waveforms tf(CK) tw(CKL) tc(CK) tr(CK) tw(CKH) SCLK th(C-Q) td(C-Q) th(C-E) Test conditions for AC characteristics SDA output • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(D-C) th(C-D) • Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC SDA input 109 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (3) Flash memory mode 3 (CPU reprogramming mode) The 3803/3804 group has the CPU reprogramming mode where a built-in flash memory is handled by the central processing unit (CPU). In CPU reprogramming mode, the flash memory is handled by writing and reading to/from the flash memory control register (see Figure 101) and the flash command register (see Figure 102). The CNV SS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage of VPP H from the external to this pin. Whether these operations have been completed or not is judged by checking this flag after each command of erase and the program is executed. Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and program is operated. When the erase command is executed after an area is specified by these bits, only the specified area is erased. Only for the specified area, programming is enabled; for the other areas, programming is disabled. Figure 103 shows the CPU mode register bit configuration in the CPU reprogramming mode. Functional Outline (CPU reprogramming mode) Figure 101 shows the flash memory control register bit configuration. Figure 102 shows the flash command register bit configuration. Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to “1” and V PPH is applied to the CNVss/V PP pin, the CPU reprogramming mode is selected. Whether the CPU reprogramming mode is realized or not is judged by reading the CPU reprogramming mode monitor flag (bit 2 of the flash memory control register). Bit 1 is a busy flag which becomes “1” during erase and program execution. 7 6 0 5 4 3 0 2 1 0 Flash memory control register (FCON : address 0FFE16) CPU reprogramming mode select bit (Note) 0 : CPU reprogramming mode is invalid. (Normal operation mode) 1 : When applying 0 V to CNVSS/VPP pin, CPU reprogramming mode is invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid. Erase/Program busy flag 0 : Erase and program are completed or not have been executed. 1 : Erase/program is being executed. CPU reprogramming mode monitor flag 0 : CPU reprogramming mode is invalid. 1 : CPU reprogramming mode is valid. Fix this bit to “0.” Erase/Program area select bits 0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes) 0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes) 1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes) 1 1 : Not available Fix this bit to “0.” Not used (returns "0" when read) Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin. Fig. 101 Flash memory control register bit configuration 110 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● CPU reprogramming mode operation procedure The operation procedure in CPU reprogramming mode is described below. < Beginning procedure > ➀ Apply 0 V to the CNVss/V PP pin for reset release. ➁ Set the CPU mode register (see Figure 103). ➂ After CPU reprogramming mode control program is transferred to internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program). ➃ Set “1" to the CPU reprogramming mode select bit. ➄ Apply V PPH to the CNVSS/VPP pin. ➅ Wait till CNVSS/V PP pin becomes 12V. ➆ Read the CPU reprogramming mode monitor flag to confirm whether the CPU reprogramming mode is valid. ➇ The operation of the flash memory is executed by software-command-writing to the flash command register . Note: The following are necessary other than this: •Control for data which is input from the external (serial I/O etc.) and to be programmed to the flash memory •Initial setting for ports etc. •Writing to the watchdog timer < Release procedure > ➀ Apply 0 V to the CNVSS/VPP pin. ➁ Wait till CNVSS /VPP pin becomes 0 V. ➂ Set the CPU reprogramming mode select bit to “0.” Each software command is explained as follows. ● Read command When “0016 " is written to the flash command register, the 3803/ 3804 group enters the read mode. The contents of the corresponding address can be read by reading the flash memory (For instance, with the LDA instruction etc.) under this condition. The read mode is maintained until another command code is written to the flash command register. Accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. After reset and after the reset command is executed, the read mode is set. b7 7 6 5 4 3 2 1 0 Flash command register (FCMD : address 0FFF16) Writing of software command b0 1 0 0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Not available 1 X : Not available <Software command name> <Command code> • Read command “0016” Stack page selection bit 0 : 0 page 1 : 1 page • Program command “4016” Fix this bit to “1”. • Program verify command “C016” • Erase command “2016” + “2016” • Erase verify command “A016” • Reset command “FF16” + “FF16” Note: The flash command register is write-only register. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 102 Flash command register bit configuration Fig. 103 CPU mode register bit configuration in CPU rewriting mode 111 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Program command When “4016” is written to the flash command register, the 3803/ 3804 group enters the program mode. Subsequently to this, if the instruction (for instance, STA or LDM instruction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the program. The erase/program busy flag of the flash memory control register is set to “1” when the program starts, and becomes “0" when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the program by polling this bit. The programmed area must be specified beforehand by the erase/ program area select bits. During programming, watchdog timer stops with “FFFF16” set. Note: A programming operation is not completed by executing the program command once. Always be sure to execute a program verify command after executing the program command. When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer to Figure 104 for the flow chart of the programming. ● Program verify command When “C016 " is written to the flash command register, the 3803/ 3804 group enters the program verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been written to the address actually is read. CPU compares this read data with data which has been written by the previous program command. In consequence of the comparison, if not agreeing, the operation of “program → program verify” must be executed again. ● Erase command When writing “2016 ” twice continuously to the flash command register, the flash memory control circuit performs erase to the area specified beforehand by the erase/program area select bits. Erase/program busy flag of the flash memory control register becomes “1” when erase begins, and it becomes “0" when erase completes. Accordingly, CPU can recognize the completion of erase by polling this bit. Data “0016 ” must be written to all areas to be erased by the program and the program verify commands before the erase command is executed. During erasing, watchdog timer stops with “FFFF16 ” set. Note: The erasing operation is not completed by executing the erase command once. Always be sure to execute an erase verify command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 104 for the erasing flowchart. 112 ● Erase verify command When “A0 16" is written to the flash command register, the 3803/ 3804 group enters the erase verify mode. Subsequently to this, if the instruction (for instance, LDA instruction) for reading byte data from the address to be verified, the contents of the address is read. CPU must erase and verify to all erased areas in a unit of address. If the address of which data is not “FF 16” (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of “erase → erase verify” again. Note: By executing the operation of “erase → erase verify” again when the memory not erased is found. It is unnecessary to write data “0016” before erasing in this case. ● Reset command The reset command is a command to discontinue the program or erase command on the way. When “FF16” is written to the command register two times continuously after “4016” or “2016” is written to the flash command register, the program, or erase command becomes invalid (reset), and the 3803/3804 group enters the reset mode. The contents of the memory does not change even if the reset command is executed. DC Electric Characteristics Note: The characteristic concerning the flash memory part are the same as the characteristic of the parallel I/O mode. AC Electric Characteristics Note: The characteristics are the same as the characteristic of the microcomputer mode. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Program Erase START START ADRS = first location ALL BYTES = 0016 ? YES X=0 NO WRITE PROGRAM COMMAND 4016 WRITE PROGRAM DATA DIN PROGRAM ALL BYTES = 0016 ADRS = first location X=0 WAIT 1µs NO ERASE PROGRAM BUSY FLAG = 0 YES X=X+1 WRITE ERASE COMMAND 2016 WRITE ERASE COMMAND 2016 WAIT 1µs WRITE PROGRAM-VERIFY COMMAND C016 NO ERASE PROGRAM BUSY FLAG = 0 DURATION = 6 µs YES X=X+1 X = 25 ? YES WRITE ERASE-VERIFY COMMAND NO PASS FAIL VERIFY BYTE ? DURATION = 6 µs VERIFY BYTE ? PASS A016 FAIL YES X = 1000 ? INC ADRS NO LAST ADRS ? NO YES WRITE READ COMMAND PASS FAIL VERIFY BYTE ? VERIFY BYTE ? 0016 FAIL PASS DEVICE PASSED DEVICE FAILED NO INC ADRS LAST ADRS ? YES WRITE READ COMMAND DEVICE PASSED 0016 DEVICE FAILED Fig. 104 Flowchart of program/erase operation at CPU reprogramming mode 113 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1.” Serial I/O continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial I/O2, an external clock is used as synchronous clock, write transmission data to the transmit buffer register or serial I/O2 register, during transfer clock is “H.” A-D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP instruction during an A-D conversion. D-A Converter The accuracy of the D-A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of V CC ≥ 4.0 V is recommended. When a D-A converter is not used, set all values of D-Ai conversion registers (i=1, 2) to “0016 .” Instruction Execution Time Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The instruction with the addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. 114 The instruction execution time is obtained by multiplying the period of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock φ is double of the XIN period in high-speed mode. MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON USAGE Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recommended. Flash memory version The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNV SS pin and VSS pin or VCC pin with 1 to 10 kΩ resistance. The mask ROM version track of CNV SS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) 115 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 26 Absolute maximum ratings Symbol VCC VI VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltageS Input voltage P00–P07, P10 –P17, P20–P27 , P30, P31, P3 4–P37, P40–P47 , P50–P57, P60 –P67, VREF Input voltage P32, P33 Input voltage RESET, XIN Input voltage CNVSS (Mask ROM version) Input voltage CNVSS (Flash memory version) Output voltage P00–P07, P10 –P17, P20–P27 , P30, P31, P3 4–P37, P40–P47 , P50–P57, P60 –P67, XOUT Output voltage P32 , P33 Power dissipation Operating temperature Storage temperature Note: In flat package, this value is 300 mV. 116 Conditions All voltages are based on VSS. Output transistors are cut off. Ta = 25 °C Ratings –0.3 to 6.5 Unit V –0.3 to V CC +0.3 V –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 V V V V –0.3 to VCC +0.3 V –0.3 to 5.8 1000 (Note) –20 to 85 –65 to 125 V mW °C °C MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 27 Recommended operating conditions (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VCC VSS VREF AVSS VIA VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL Parameter Power source voltage (f(XIN) ≤ 8.4 MHz) Power source voltage (f(XIN) ≤ 12.5 MHz) Power source voltage (f(XIN) ≤ 16.8 MHz) Power source voltage (flash memory version) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0–AN 15 “H” input voltage P00–P07, P10–P17 , P20–P27, P30 , P33, P34–P37 , P40–P47, P50–P57 , P60–P67 “H” input voltage P32, P33 “H” input voltage (when I2C-BUS input level is selected) SDA , SCL “H” input voltage (when SMBUS input level is selected) SDA , SCL “H” input voltage RESET, XIN, XCIN , CNVSS “L” input voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 “L” input voltage (when I2 C-BUS input level is selected) SDA , SCL “L” input voltage (when SMBUS input level is selected) SDA , SCL “L” input voltage RESET, CNV SS “L” input voltage XIN , XCIN Min. 2.7 4.0 4.5 4.0 Limits Typ. 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 Unit V AVSS VCC V V V V V V 0.8V CC VCC V 0.8V CC 5.5 V 0.7V CC 5.5 V 2.0 2.7 VCC VCC 0 1.4 5.5 V 0.8V CC VCC V 0 0.2V CC V 0 0.3V CC V 0.6 V 0.2V CC 0.16VCC V V 0 117 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 28 Recommended operating conditions (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ΣI OH(peak) ΣI OH(peak) ΣI OL(peak) ΣI OL(peak) ΣI OL(peak) ΣI OH(avg) ΣI OH(avg) ΣI OL(avg) ΣI OL(avg) ΣI OL(avg) I OH(peak) I OL(peak) I OL(peak) I OH(avg) I OL(avg) Parameter “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current “H” peak output current “L” peak output current “L” peak output current “H” average output current “L” average output current I OL(avg) “L” average output current f(XIN) Main clock input oscillation frequency (Note 4) f(XCIN ) Min. Limits Typ. P00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) P40 –P47, P50–P57, P6 0–P67 (Note 1) P00–P07, P10–P17, P3 0–P37 (Note 1) P20 –P27 (Note 1) P40 –P47,P50 –P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30, P31, P34–P37 (Note 1) P40 –P47,P50 –P57, P60–P67 (Note 1) P00–P07, P10–P17, P3 0–P37 (Note 1) P20 –P27 (Note 1) P40 –P47,P50 –P57, P60–P67 (Note 1) P00 –P07, P10–P17 , P20–P27, P30 . P31, P34–P37 , P40 –P47, P50–P57, P6 0–P67 (Note 2) P00 –P07, P10–P17 , P30–P37, P40 –P47, P50–P57, P60 –P67 (Note 2) P20 –P27 (Note 2) P00 –P07, P10–P17 , P20–P27, P30 , P31, P34–P37 , P40 –P47, P50–P57, P6 0–P67 (Note 3) P00 –P07, P10–P17 , P30–P37, P40 –P47, P50–P57, P60 –P67 (Note 3) P20 –P27 (Note 3) Vcc = 4.5–5.5 V Vcc = 4.0–4.5 V mA mA mA mA mA mA mA mA mA mA mA 10 mA 20 mA –5 mA 5 mA 8.6Vcc–21,9 32.768 Unit –10 10 16.8 Vcc = 2.7–4.0 V Sub-clock input oscillation frequency (Notes 4, 5) Max. –80 –80 80 80 80 –40 –40 40 40 40 mA MHz MHz 41 Vcc– 3 26 13 MHz 50 kHz Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current IOL (avg), IOH(avg) are average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50%. 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 118 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 29 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH VOL VT+ –VT– VT+ –VT– VT+ –VT– I IH I IH I IH I IL I IL I IL I IL VRAM Parameter “H” output voltage P00–P07 , P10–P17, P20–P27 , P30, P31 , P34–P37, P40 –P47, P50–P57, P6 0–P67 (Note 1) “L” output voltage P00–P07 , P10–P17, P20–P27 , P30–P37 , P40–P47, P50–P57 , P60–P67 Hysteresis CNTR0 , CNTR1, CNTR2 , INT0 –INT4 Hysteresis RxD1, S CLK1, SIN2 , SCLK2, RxD3, SCLK3 Hysteresis RESET “H” input current P00–P07 , P10–P17, P20–P27 , P30–P37 , P40–P47, P50–P57 , P60–P67 “H” input current RESET, CNV SS “H” input current XIN “L” input current P00–P07 , P10–P17, P20–P27 , P30–P37 , P40–P47, P50–P57 , P60–P67 “L” input current RESET,CNVSS “L” input current XIN “L” input current (at Pull-up) P00–P07 , P10–P17, P20–P27 , P30, P31 , P34–P37, P40 –P47, P50–P57 , P60–P67 RAM hold voltage Test conditions I OH = –10 mA VCC = 4.0–5.5 V I OH = –1.0 mA VCC = 2.7–5.5 V I OL = 10 mA VCC = 4.0–5.5 V I OL = 1.6 mA VCC = 2.7–5.5 V Min. Typ. Unit VCC–2.0 V VCC–1.0 V VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors “off”) 2.0 V 0.4 V 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating. Pull-up transistors “off”) VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped Max. 5.0 µA 5.0 µA µA –5.0 µA –5.0 µA µA 4 –4 –80 –210 –420 µA –30 –70 –140 µA 2.0 5.5 V Note 1: P35 is measured when the P35 /TxD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. P45 is measured when the P45/TxD 1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16 ) is “0”. 119 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 30 Electrical characteristics (flash memory version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol I CC Parameter Power source current Limits Test conditions High-speed mode f(XIN) = 16.8 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 12.5 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8.4 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN) = 16.8 MHz f(XCIN ) = stopped Output transistors “off” Middle-speed mode f(XIN) = 16.8 MHz (in WIT state) f(XCIN ) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN) = 16.8 MHz All oscillation stopped (in STP state) Output transistors “off” 120 Ta = 25 °C Ta = 85 °C Min. Unit Typ. Max. 12 22 mA 10 18 mA 7 13.5 mA 3.5 6 mA 60 200 µA 30 60 µA 6 12 mA 3 5.5 mA µA 500 0.1 1.0 µA 10 µA MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 31 Electrical characteristics (mask ROM version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol I CC Parameter Power source current Test conditions High-speed mode f(XIN ) = 16.8 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN ) = 12.5 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN ) = 8.4 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN ) = 16.8 MHz (in WIT state) f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN ) = stopped f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN ) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN ) = stopped f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN ) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN ) = 16.8 MHz f(XCIN ) = stopped Output transistors “off” Middle-speed mode f(XIN ) = 16.8 MHz (in WIT state) f(XCIN ) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN ) = 16.8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Min. Unit Typ. Max. 8 15 mA 6.5 12 mA 5 9 mA 2 3.6 mA 55 200 µA 40 70 µA 15 40 µA 8 15 µA 4 7 mA 1.8 3.3 mA µA 500 0.1 1.0 µA 10 µA 121 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 32 A-D converter characteristics (1) (VCC = 2.7 to 5.5 V, VREF = 2.0 V to V CC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 10-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816 ) is “0”) Symbol Parameter – – Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor at A-D converter operated Reference power source input current at A-D converter stopped t CONV RLADDER I VREF I I(AD) Test conditions Min. Limits Typ. VCC = VREF = 5.0 V VREF = 5.0 V VREF = 5.0 V 12 50 35 150 A-D port input current Max. 10 ±4 61 100 200 5 5.0 Unit bit LSB 2tc(XIN ) kΩ µA µA µA Table 33 A-D converter characteristics (2) (VCC = 2.7 to 5.5 V, VREF = 2.0 V to V CC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 8-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816 ) is “1”) Symbol Parameter – – Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor at A-D converter operated Reference power source input current at A-D converter stopped t CONV RLADDER I VREF I I(AD) Test conditions Min. Limits Typ. VCC = VREF = 5.0 V VREF = 5.0 V VREF = 5.0 V 12 50 35 150 A-D port input current Max. 8 ±2 50 100 200 5 5.0 Unit bit LSB 2tc(XIN ) kΩ µA µA µA Table 34 D-A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to V CC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol – – tsu RO I VREF Parameter Test conditions Limits Min. Resolution Absolute accuracy VCC = 4.0–5.5 V VCC = 2.7–4.0 V Setting time Output resistor Reference power source input current (Note 1) 2 Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “00 16”. 122 Typ. 3.5 Max. 8 1.0 2.5 3 5 3.2 Unit Bits % % µs kΩ mA MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 35 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) Parameter Reset input “L” pulse width Main clock input cycle time (Vcc = 4.5–5.5 V) tC (XIN) Main clock input cycle time (Vcc = 4.0–4.5 V) Main clock input “H” pulse width (Vcc = 4.5–5.5 V) tWH (XIN) Main clock input “H” pulse width (Vcc = 4.0–4.5 V) Main clock input “L” pulse width (Vcc = 4.5–5.5 V) tWL (XIN) tC (XCIN) tWH (XCIN ) tWL (XCIN ) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC(SCLK1), t C(SCLK3) tWH(S CLK1), tWH(S CLK3) tWL(S CLK1), t WL(SCLK3 ) tsu(Rx D1-SCLK1 ), tsu(Rx D3-SCLK3 ) th (SCLK1-R xD1), th (SCLK3-R xD3) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2 -SCLK2 ) th (SCLK2-S IN2) Main clock input “L” pulse width (Vcc = 4.0–4.5 V) Sub-clock input cycle time Sub-clock input “H” pulse width Sub-clock input “L” pulse width CNTR0–CNTR 2 input cycle time CNTR0–CNTR 2 input “H” pulse width CNTR0–CNTR 2 input “L” pulse width INT00 , INT01 , INT1, INT2, INT3, INT40, INT 41 input “H” pulse width INT00 , INT01 , INT1, INT2, INT3, INT40, INT 41 input “L” pulse width Serial I/O1, serial I/O3 clock input cycle time (Note) Serial I/O1, serial I/O3 clock input “H” pulse width (Note) Serial I/O1, serial I/O3 clock input “L” pulse width (Note) Min. 16 59.5 10000 86Vcc–219 25 4000 86Vcc–219 25 4000 86Vcc–219 20 5 5 200 80 80 80 80 800 370 370 Limits Typ. Max. Unit XIN cycle ns ns ns ns ns ns µs µs µs ns ns ns ns ns ns ns ns Serial I/O1, serial I/O3 input setup time 220 ns Serial I/O1, serial I/O3 input hold time 100 ns Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input setup time Serial I/O2 input hold time 1000 400 400 200 200 ns ns ns ns ns Note : When bit 6 of address 001A 16 and bit 6 of address 0032 16 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A 16 and bit 6 of address 0032 16 are “0” (UART). 123 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 36 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter tW (RESET) Reset input “L” pulse width tC (XIN) Main clock input cycle time tWH (XIN) Main clock input “H” pulse width tWL (XIN) Main clock input “L” pulse width tC (XCIN ) tWH (XCIN ) tWL (XCIN ) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC(SCLK1 ), tC (SCLK3 ) tWH(S CLK1), tWH(S CLK3) tWL (SCLK1), t WL(S CLK3) tsu(Rx D1-SCLK1 ), tsu(Rx D3-SCLK3 ) th (SCLK1 -RxD1), th (SCLK3 -RxD3) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(S IN2-SCLK2 ) th (SCLK2 -SIN2) Sub-clock input cycle time Sub-clock input “H” pulse width Sub-clock input “L” pulse width CNTR0–CNTR2 input cycle time CNTR0–CNTR2 input “H” pulse width CNTR0–CNTR2 input “L” pulse width INT00, INT 01, INT1, INT 2, INT 3, INT40 , INT41 input “H” pulse width INT00, INT 01, INT1, INT 2, INT 3, INT40 , INT41 input “L” pulse width Serial I/O1, serial I/O3 clock input cycle time (Note) Serial I/O1, serial I/O3 clock input “H” pulse width (Note) Serial I/O1, serial I/O3 clock input “L” pulse width (Note) Typ. Max. Unit XIN cycle ns ns ns µs µs µs ns ns ns ns ns ns ns ns Serial I/O1, serial I/O3 input setup time 400 ns Serial I/O1, serial I/O3 input hold time 200 ns Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input setup time Serial I/O2 input hold time 2000 ns ns ns ns ns Note : When bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). 124 Limits Min. 16 26 ✕ 103 82Vcc–3 10000 82Vcc–3 10000 82Vcc–3 20 5 5 500 230 230 230 230 2000 950 950 950 950 400 300 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 37 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1), tWH (SCLK3) tWL (SCLK1 ), tWL (SCLK3 ) td (S CLK1-TXD1) , td (S CLK3-TXD3) tv (S CLK1-T XD1) , tv (S CLK3-T XD3) tr (S CLK1) , tr (S CLK3) tf (S CLK1), tf (SCLK3 ) tWH (SCLK2) tWL (SCLK2 ) td (S CLK2-SOUT2) tV (SCLK2 -SOUT2) tf (SCLK2 ) tr (CMOS) tf (CMOS) Parameter Test conditions Serial I/O1, serial I/O3 clock output “H” pulse width Serial I/O1, serial I/O3 clock output “L” pulse width Limits Min. Typ. t C(SCLK1 )/2–30 t C(SCLK3 )/2–30 t C(SCLK1 )/2–30 t C(SCLK3 )/2–30 Serial I/O1, serial I/O3 output delay time (Note 1) Unit ns ns 140 Serial I/O1, serial I/O3 output valid time (Note 1) Serial I/O1, serial I/O3 clock output rising time Serial I/O1, serial I/O3 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Max. –30 ns ns 30 30 Fig. 105 tC(SCLK2)/2–160 tC(SCLK2)/2–160 200 0 10 10 30 30 30 ns ns ns ns ns ns ns ns ns Notes 1: When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. When the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 0033 16) is “0”. 2: The XOUT pin is excluded. Table 38 Switching characteristics 2 (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t WH (SCLK1 ), t WH (SCLK3 ) t WL (SCLK1), t WL (SCLK3) t d (SCLK1 -TXD1) , t d (SCLK3 -TXD3) t v (SCLK1 -TXD1) , t v (SCLK3 -TXD3) tr (SCLK1) , t r (S CLK3) tf (S CLK1), tf (SCLK3) t WH (SCLK2 ) t WL (SCLK2) t d (SCLK2 -SOUT2) t V (S CLK2-SOUT2) t f (S CLK2) t r (CMOS) t f (CMOS) Parameter Test conditions Serial I/O1, serial I/O3 clock output “H” pulse width Serial I/O1, serial I/O3 clock output “L” pulse width Limits Typ. Min. tC (SCLK1)/2–50 tC (SCLK3)/2–50 tC (SCLK1)/2–50 tC (SCLK3)/2–50 Serial I/O1, serial I/O3 output delay time (Note 1) Unit ns ns 350 Serial I/O1, serial I/O3 output valid time (Note 1) Serial I/O1, serial I/O3 clock output rising time Serial I/O1, serial I/O3 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Max. –30 ns ns 50 50 Fig. 105 tC(SCLK2)/2–240 tC(SCLK2)/2–240 400 0 20 20 50 50 50 ns ns ns ns ns ns ns ns ns Notes 1: When the P45/TX D1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. When the P35/TX D3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. 2: The XOUT pin is excluded. 125 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1kΩ Measurement output pin Measurement output pin 100pF CMOS output Fig. 105 Circuit for measuring output switching characteristics (1) 126 100pF N-channel open–drain output Fig. 106 Circuit for measuring output switching characteristics (2) MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing diagram in single-chip mode tC(CNTR) tWL(CNTR) tWH(CNTR) C N T R 0 , C N T R 1, C N T R 2 INT1, INT2, INT3 INT00, INT40 INT01, INT41 0.8VCC 0.2VCC tWL(INT) tWH(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) XIN 0.8VCC 0.2VCC tC(XCIN) tWL(XCIN) tWH(XCIN) XCIN 0.8VCC 0.2VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) SCLK1 SCLK2 SCLK3 RXD1 RXD3 SIN2 0.8VCC 0.2VCC tsu(RxD1-SCLK1), tsu(SIN2-SCLK2), tsu(RxD3-SCLK3) th(SCLK1-RxD1), th(SCLK2-SIN2), th(SCLK3-RxD3) 0.8VCC 0.2VCC td(SCLK1-TXD1),td(SCLK2-SOUT2),td(SCLK3-TXD3) TXD1 TXD3 SOUT2 tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) Fig. 107 Timing diagram (in single-chip mode) 127 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 39 Multi-master I2C-BUS bus line characteristics Standard clock mode High-speed clock mode Symbol Parameter Min. Max. Max. Unit t BUF Bus free time 4.7 Min. 1.3 t HD;STA Hold time for START condition 4.0 0.6 µs t LOW Hold time for SCL clock = “0” 4.7 1.3 µs µs tR 20+0.1Cb Rising time of both S CL and SDA signals 300 ns t HD;DAT Data hold time 0 0 0.9 µs t HIGH Hold time for SCL clock = “1” 4.0 0.6 tF Falling time of both SCL and SDA signals t SU;DAT Data setup time 250 100 ns t SU;STA Setup time for repeated START condition 4.7 0.6 µs t SU;STO Setup time for STOP condition 4.0 0.6 µs 1000 300 µs 20+0.1Cb 300 ns Note: C b = total capacitance of 1 bus line SDA tHD:STA tBUF tLOW SCL P tR tF S tHD:STA Sr tHD:DAT tsu:STO tHIGH tsu:DAT P tsu:STA S : START condition Sr: RESTART condition P : STOP condition Fig. 108 Timing diagram of multi-master I2C-BUS 128 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 64P6N-A Plastic 64pin 14✕14mm body QFP EIAJ Package Code QFP64-P-1414-0.80 Weight(g) 1.11 Lead Material Alloy 42 MD e JEDEC Code – HD 64 b2 ME D 49 1 I2 48 Recommended Mount Pad HE E Symbol A A1 A2 b c D E e HD HE L L1 x y 33 16 A 32 L1 c A2 17 b x A1 F e M y b2 I2 MD ME L Detail F MMP 64P4B JEDEC Code – Plastic 64pin 750mil SDIP Weight(g) 7.9 Lead Material Alloy 42/Cu Alloy 33 1 32 E 64 e1 c EIAJ Package Code SDIP64-P-750-1.78 Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 – – 2.8 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 – 0.8 – 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 – – – – 0.2 – – 0.1 – 0° 10° 0.5 – – – – 1.3 – – 14.6 14.6 – – Symbol A1 L A A2 D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.08 0.38 – – – 3.8 – 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 – 1.778 – – 19.05 – 2.8 – – 0° – 15° 129 MITSUBISHI MICROCOMPUTERS 3803/3804 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MMP EIAJ Package Code LQFP64-P-1010-0.50 Plastic 64pin 10✕10mm body LQFP Weight(g) – Lead Material Cu Alloy MD ME JEDEC Code – e 64P6Q-A b2 HD D 64 49 1 I2 Recommended Mount Pad 48 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 33 16 17 32 A F e x L M Detail F Lp c A1 y b A3 A2 L1 A3 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 – – 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 0.5 – – 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 – – 0.1 – 0° 10° – – 0.225 1.0 – – 10.4 – – – – 10.4 HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • • © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Jun. 2000. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 3803/3804 GROUP DATA SHEET Revision Description Rev. date 0.1 First Edition; Only including overview. The issue including all information will be released in April. 990315 1.0 Functional descriptions are added. 990525 2.0 All pages; “PRELIMINARY Notice: This is...” eliminated. 990909 Page 9; Product names are added into Figure 8. Page 10; Product names are added into Table 3. Page 34; Explanation of “Timer divider” of “8-bit Timers” is revised. Page 52; Explanation of Note 7 is revised. Page 60; Explanation of Note 7 is revised. Page 63; Explanation of “A-D CONVERTER” is revised. Explanations of Figure 56 are partly revised. Page 66; Explanations of “Watchdog Timer Initial Value” and “Watchdog Timer Operations” are revised. Explanations of Figure 60 are partly revised. Page 67; Explanation of “MULTI-MASTER I2C-BUS INTERFACE” is revised. Explanation of Note eliminated. Explanations of Figure 62 are partly revised. Page 68; Explanations of “I 2C Data Shift Register” and “I2C Address Registers 0 to 2” are revised. Page 69; Explanation of Bit 5 of “I2C Clock Control Register” is revised. Page 75; Value of “Setup time” and “Hold time” into Table 13 are revised. Page 76; Explanation of Bit 5 of “I2C Special Mode Status Register” is added. Note is added into Figure 73. Page 77; Explanation of Bit 1 of “I2C Special Mode Control Register” is added. Explanation of Bit 6 of “I 2C Special Mode Control Register” is revised. Note is added into Figure 74. Page 82; Register Contents of (21) into Figure 78 is revised. Page 86; Explanations of Figure 82 are partly revised. Note 2 into Figure 82 is revised. (1/5) REVISION DESCRIPTION LIST Rev. No. 2.0 3.0 3803/3804 GROUP DATA SHEET Revision Description Page 117; Table 28 is revised for only flash memory version. Table 29 is added. Page 1; “●Minimum instruction execution time” of “FEATURES” is revised. Page 1; “●Memory size” of “FEATURES” is revised. Page 1; “<Flash memory mode>” of “FEATURES” is revised. Page 1; “■Notes” of “FEATURES” is revised. Page 9; Figure 8 is partly revised. Pages 11–13; Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added. Page 14; Explanation of bit 3 of “CPU mode register” is revised. Page 21; (7) into Figure 16 is partly revised. Page 22; (14) into Figure 17 is partly revised. Page 24; (7) into Figure 19 is partly revised. Page 25; (14) into Figure 20 is partly revised. Page 37; Explanations of “Timer divider” are partly eliminated. Page 37; “●Prescaler 12” is added. Page 37; Explanations of “Timer 1 and Timer 2” are partly eliminated. Page 37; “Prescaler X and prescaler Y” is added. Page 37; Explanations of “Timer X and Timer Y” are partly eliminated. Page 37; Explanations of “●Mode selection” and “●Explanation of operation” of “(1) Timer mode” of “Timer X and Timer Y” are partly eliminated. Page 37; “●Count source selection” and “●Interrupt” of “(1) Timer mode” of “Timer X and Timer Y” are eliminated. Page 37; “●Count source selection” and “●Interrupt” of “(2) Pulse output mode” of “Timer X and Timer Y” are eliminated. Page 37; Explanations of “●Explanation of operation” of “(2) Pulse output mode” of “Timer X and Timer Y” are partly added. Page 37; Explanations of “■Precautions” of “(2) Pulse output mode” of “Timer X and Timer Y” are partly eliminated. (2/5) Rev. date 990909 000628 REVISION DESCRIPTION LIST Rev. No. 3.0 3803/3804 GROUP DATA SHEET Revision Description Page 38; Explanations of “●Mode selection” and “●Explanation of operation” of “(3) Event counter mode” of “Timer X and Timer Y” are revised. Page 38; “●Interrupt” of “(3) Event counter mode” of “Timer X and Timer Y” are eliminated. Page 38; “■Precautions” of “(3) Event counter mode” of “Timer X and Timer Y” are added. Page 38; “●Count source selection” of “(4) Pulse width measurement mode” of “Timer X and Timer Y” are eliminated. Page 38; Explanations of “●Explanation of operation” of “(4) Pulse width measurement mode” of “Timer X and Timer Y” are partly eliminated. Page 38; Explanations of “■Precautions” of “(4) Pulse width measurement mode” of “Timer X and Timer Y” are revised. Page 39; Bit name into Figure 29 is partly added. Page 42; Explanations of “●Mode selection” of “(1) Timer mode” of “●16-bit Timers” are partly added. Page 42; Explanations of “●Explanation of operation” of “(1) Timer mode” of “●16-bit Timers” are partly eliminated. Page 42; Explanations of “●Mode selection” of “(3) Pulse output mode” of “●16-bit Timers” are partly added. Page 43; Explanations of “●Mode selection” of “(4) Pulse period measurement mode” of “●16-bit Timers” are partly added. Page 43; Explanations of “●Mode selection” of “(5) Pulse width measurement mode” of “●16-bit Timers” are partly added. Page 44; Explanations of “●Mode selection” of “(6) Programmable waveform generating mode” of “●16-bit Timers” are partly added. Page 44; Explanations of “●Mode selection” of “(7) Programmable one-shot generating mode” of “●16-bit Timers” are partly added. Page 45; Figure 32 is partly revised. Page 46; Note into Figure 33 is added. Page 55; Explanations of “7. Transmit interrupt request when transmit enable bit is set” are revised. (3/5) Rev. date 000628 REVISION DESCRIPTION LIST Rev. No. 3.0 3803/3804 GROUP DATA SHEET Revision Description Page 63; Explanations of “7. Transmit interrupt request when transmit enable bit is set” are revised. Page 68; Explanations of “D-A CONVERTER” are partly eliminated. Page 70; Figure 64 is partly revised. Page 71; Explanations of “[I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)]” are partly added. Page 74; Explanations of “•Bit 3: Arbitration lost detecting flag (AL)” of “[I 2C Status Register (S1)]” are partly added. Page 75; Explanations of “•Bit 7: Communication mode specification bit (master/slave specification bit: MST)” of “[I2C Status Register (S1)]” are partly revised. Page 78; “•Bit 7: Data receive mode at Stop/Low-speed mode bit (STR)” of “[I 2C START/STOP Condition Control Register (S2D)]” is eliminated. Page 78; Explanations of b7 into Figure 74 are revised. Page 79; “•Bit 4: Time out flag (TIOUT)” of “[I 2C Special Mode Status Register (S3)]” is eliminated. Page 79; Figure 75 is partly revised. Page 80; “•Bit 0: I2C time out control bit (TOEN)” is eliminated. Page 80; “•Bit 4: Time out flag clear bit (TOFCL)” is eliminated. Page 80; Figure 76 is partly revised. Page 80; Note into Figure 76 is added. Page 84; Explanations of “RESET CIRCUIT” are partly revised. Page 110; Explanations of “Functional Outline (CPU reprogramming mode)” of “(3) Flash memory mode 3 (CPU reprogramming mode)” are partly eliminated. Page 111; Explanations of b3, b1, b0 into Figure 103 are partly revised. Page 114; Explanations of “Instruction Execution Time” are partly reviesd. Page 121; Table 31 is partly eliminated. Page 122; Limits of RO into Table 34 are revised. Page 123; Limits and unit of tw(RESET) into Table 35 are revised. Page 123; Symbol of th(SCLK3–RxD3) into Table 35 is revised. (4/5) Rev. date 000628 REVISION DESCRIPTION LIST Rev. No. 3.0 3803/3804 GROUP DATA SHEET Revision Description Page 124; Limits and unit of tw(RESET) into Table 36 are revised. Page 125; Limits of tWH(SCLK1), tWH(SCLK3) into Tables 37 and 38 are partly added. (5/5) Rev. date 000628