256Kx16 LP SRAM EM6156K600V Series GENERAL DESCRIPTION The EM6156K600V is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The EM6156K600V is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The EM6156K600V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible FEATURES z z z z z Fast access time: 45/55/70ns Low power consumption: Operating current: 40/30/20mA (TYP.) Standby current: -L/-LL version 20/2µA (TYP.) Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation z z z z Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage: 1.5V (MIN.) Package: 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A17 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# DECODER I/O DATA CURCUIT 256Kx16 MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT PIN DESCRIPTION SYMBOL A0 - A17 DQ0 – DQ17 CE# WE# OE# LB# UB# Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Lower Byte Control Upper Byte Control Power Supply Ground 1 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series PIN CONFIGURATION TSOP-II A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CE# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 16 29 DQ8 WE# 17 28 NC A17 18 27 A8 A16 19 26 A9 A15 20 25 A10 A14 21 24 A11 A13 22 23 A12 TFBGA A B C D E F G H LB# DQ8 DQ9 Vss Vcc DQ14 DQ15 NC 1 OE# UB# DQ10 DQ11 DQ12 DQ13 NC A8 2 A0 A3 A5 A17 NC A14 A12 A9 3 2 A1 A4 A6 A7 A16 A15 A13 A10 4 A2 CE# DQ1 DQ3 DQ4 DQ5 WE# A11 5 NC DQ0 DQ2 Vcc Vss DQ6 DQ7 NC 6 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT VTERM -0.5 to 4.6 V Terminal Voltage with Respect to Vss 0 to 70(C grade) Operating Temperature -20 to 80(E grade) TA °C -40 to 85(I grade) Storage Temperature TSTG -65 to 150 °C Power Dissipation PD 1 W DC Output Current IOUT 50 mA TSOLDER 260 °C Soldering Temperature (under 10 sec) *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# OE# WE# LB# UB# H X L L L L L L L L X X H H L L L X X X X X H H H H H L L L X H L X L H L L H L X H X L H L L H L L Standby Output Disable Read Write I/O OPERATION DQ0-DQ7 DQ8-DQ15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z DOUT DOUT DOUT DIN High-Z High-Z DIN DIN DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Note: H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage SYMBOL Vcc VIH*1 Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current VIL*2 ILI Standby Power ILO TEST CONDITION Vcc ≧ VIN ≧ Vss VOH VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -1mA VOL IOL = 2mA ICC Cycle time = Min. CE# = VIL , II/O = 0mA ICC1 Cycle time = 1µs CE#≦0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH ISB 3 -45 -55 -70 MIN. 2.7 2.0 TYP. *5 3.0 - -0.2 -1 UNIT V V - MAX. 3.6 Vcc+ 0.3 0.6 +1 -1 - 1 µA 2.2 2.7 - V - - 0.4 V - 40 30 20 4 50 40 30 5 mA mA mA mA - 0.3 0.5 mA V µA DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series Supply Current ISB1 CE# V ≧ VCC - 0.2V -L -LL - 20 2 80 15 µA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. 10µA for special request 5. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C CAPACITANCE (TA = 25°C , f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX. 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS READ CYCLE PARAMETER SYM. Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* WRITE CYCLE PARAMETER SYM. Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write MIN. 45 10 5 10 10 -45 MAX. 45 45 25 15 15 45 20 - MIN. 55 10 5 10 10 -45 MAX. 15 - MIN. 55 50 50 0 45 0 25 0 5 45 MIN. 45 40 40 0 35 0 20 0 5 35 tWC tAW tCW tAS tWP twr tDW tDH tOW* tWHZ* tBW -55 MAX. 55 55 30 20 20 55 25 - 70 MAX. 70 70 35 25 25 70 30 - UNIT MIN. 70 10 5 10 10 -55 MAX. 20 - 70 MAX. 25 - UNIT MIN. 70 60 60 0 55 0 30 0 5 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. 4 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOH tOE tOLZ tCLZ Dout High-Z tOHZ tCHZ Valid Data tBLZ tBA tBHZ LB#, UB# Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. 5 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#, UB# WE# tAS tWP tWR tWHZ tOW High-Z Dout (4) (4) tDW tDH High-Z Din Valid Data WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW LB#, UB# tBW WE# tWP tWHZ High-Z Dout tDW tDH High-Z Din Valid Data 6 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series WRITE CYCLE 3 (LB#, UB# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW LB#, UB# tBW WE# tWP tWHZ High-Z Dout tDW tDH High-Z Din Valid Data Notes : 1. WE#, CE# must be high during all address transitions. 2. A write occurs during the overlap of a low CE#, low WE#. 3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 7 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL VDR TEST CONDITION CE# V ≧ VCC - 0.2V IDR VCC = 1.5V CE# V ≧ VCC - 0.2V tCDR See Data Retention Waveforms (below) -L -LL -LLE -LLI tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 1 0.5 0.5 50 8 12 µA µA µA 0 - - ns tRC* ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tR tCDR CE# ≧ Vcc-0.2V CE# VIH VIH Low Vcc Data Retention Waveform (2) (LB#, UB# controlled) VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tR tCDR LB#, UB# ≧ Vcc-0.2V LB#, UB# VIH VIH 8 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-II Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.00 1.20 0.05 0.15 0.95 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.76 11.836 11.838 10.058 10.160 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 0° 10° 9 DIMENSIONS IN INCHS MIN. NOM. 0.039 0.002 0.037 0.039 0.012 0.014 0.0047 0.721 0.725 0.460 0.466 0.398 0.400 0.0315 0.0157 0.020 0.0317 0.000 0° MAX. 0.047 0.006 0.041 0.018 0.083 0.728 0.470 0.404 0.0236 0.003 10° DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series 48-ball 6mm × 8mm TFBGA Package Outline Dimension 10 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series Product ID Information EM 61 56K SRAM Family 61: Standard 6 0 0 V T A – 45 IF* Version Option Configuration: Option 8: x8 Voltage: 16: x16 V: 3V W: 2.7V Address Density ~5.5V 56K: 256K EOREX T: 5V Package: Manufactured S: sTSOP Memory P: PDIP F: SOP B: TFBGA T: TSOP Speed: 45ns 55ns 70ns TEMP: Blank: Normal I: Industrial Pb-Free PKG: Blank: Normal F: Pb-free * Product ID example 11 DCC-SR-041003-A 256Kx16 LP SRAM EM6156K600V Series ©COPYRIGHT 2004 EOREX CORPORATION Printed in Canada The information in this document is subject to change without notice. EOREX makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of EOREX. EOREX subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. EOREX CORPORATION http://www.eorex.com [email protected] 2F., No. 301-3, Guang-Ming 6th Rd., Chu-Pei City, Hsinchu County, Taiwan 302, ROC TEL: +886-3-5585138 FAX: +886-3-5585139 12 DCC-SR-041003-A