ALSC AS7C4098A 5.0 v 256 k ã 16 cmos sram Datasheet

AS7C4098A
February 2006
®
5.0 V 256 K × 16 CMOS SRAM
Features
• Pin compatible with AS7C4098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 990mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
• Individual byte read/write controls
I/O
buffer
WE
UB
OE
LB
CE
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
VCC
1024 × 256 × 16
Array
(4,194,304)
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
GND
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
Row Decoder
Logic block diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
–10
–12
–15
–20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
6
6
ns
Maximum operating current
180
160
140
120
mA
Maximum CMOS standby current
10
10
10
10
mA
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AS7C4098A
®
Functional description
The AS7C4098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/
O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 5.0V (AS7C4098A) supply. The device is
available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2 packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.5
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
±20
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O1–I/O8
I/O9–I/O16
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB, ISB1)
L
H
H
X
X
L
X
X
H
H
High Z
High Z
Output disable (ICC)
L
H
DOUT
High Z
L
H
L
H
L
High Z
DOUT
L
L
DOUT
DOUT
L
H
DIN
High Z
H
L
High Z
DIN
L
L
DIN
DIN
L
L
X
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High.
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AS7C4098A
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Recommended operating conditions
Parameter
Symbol
Min
Typical
Max
Unit
VCC (10/12/15/20)
4.5
5.0
5.5
V
VIH*
VIL**
2.2
–
VCC + 0.5
V
–0.5
–
0.8
V
commercial
TA
0
–
70
°C
industrial
TA
–40
–
85
°C
Supply voltage
Input voltage
Ambient operating temperature
*
VIH max = VCC + 1.5V for pulse width less than 5 nS.
**V min = –1.0V for pulse width less than 5 nS.
IL
DC operating characteristics (over the operating range)1
–10
Parameter Symbol
Input leakage
current
Test conditions
–12
–15
–20
Min Max Min Max Min Max Min Max Unit Notes
|ILI|
VCC = Max
VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
Output
leakage
current
|ILO|
VCC = Max
CE = VIH or OE = VIH
or WE = VIL
VI/O = GND to VCC
–
1
–
1
–
1
–
1
µA
Operating
power supply
current
ICC
VCC = Max
CE < VIL, f = fmax, IOUT = 0 mA
-
180
-
160
-
140
-
120 mA
ISB
VCC = Max
CE > VIH, f = Max
-
60
-
55
-
50
-
45
mA
ISB1
VCC = Max
CE ≥ VCC – 0.2V, VIN ≥ VCC
– 0.2V or VIN ≤ 0.2V, f = 0
-
10
-
10
-
10
-
10
mA
IOL = 6 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
IOL = 8 mA, VCC = Min
–
0.5
–
0.5
–
0.5
–
0.5
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
Standby
power supply
current
VOL
Output
voltage
VOH
V
4
V
4
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE, UB, LB
VIN = 0V
6
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
8
pF
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Read cycle (over the operating range)2,8
–10
Parameter
–12
–15
–20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
Output enable (OE) access time
tOE
–
5
–
6
–
6
–
6
ns
Output hold from address change
tOH
3
–
3
–
3
–
3
–
ns
4
CE Low to output in low Z
tCLZ
3
–
3
–
3
–
3
–
ns
3, 4
CE High to output in high Z
tCHZ
–
5
–
6
–
7
–
9
ns
3, 4
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
3, 4
OE High to output in high Z
tOHZ
–
5
–
6
–
7
–
9
ns
3, 4
LB, UB access time
tBA
–
5
–
6
–
7
–
8
ns
LB, UB Low to output in low Z
tBLZ
0
–
0
–
0
–
0
–
ns
LB, UB High to output in high Z
tBHZ
–
5
–
6
–
7
–
9
ns
Power up time
tPU
0
–
0
–
0
–
0
–
ns
4
Power down time
tPD
–
10
–
12
–
15
–
20
ns
4
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)5,6,8
tRC
Address
tOH
DataOUT
2/21/06, v 1.2
tAA
Previous data valid
tOH
Data valid
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Read waveform 2 (CE, OE, UB, LB controlled)5,7,8
tRC
Address
tAA
OE
tOHZ
tOE
tOLZ
tOH
CE
tACE
tCLZ
tCHZ
LB, UB
tBA
tBLZ
tBHZ
DataOUT
Data valid
Write cycle (over the operating range)9
–10
Parameter
Symbol Min
–12
–15
–20
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10
–
12
–
ns
Address setup to write end
tAW
7
–
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width (OE = High)
tWP1
7
–
8
–
10
–
12
–
ns
Write pulse width (OE = Low)
tWP2
10
–
12
–
15
–
20
–
ns
Write recovery time
tWR
0
–
0
–
0
–
0
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
7
–
9
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
3, 4
Write enable to output in High-Z
tWZ
2
5
2
6
2
7
2
9
ns
3, 4
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
3, 4
Byte enable Low to write end
tBW
7
–
8
–
10
–
12
–
ns
3, 4
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AS7C4098A
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Write waveform 1(WE controlled)9
tWC
tAH
tWR
Address
tCW
CE
tBW
LB, UB
tAS
tAW
tWP
WE
tDW
DataIN
Data valid
tWZ
DataOUT
tDH
tOW
Data undefined
High Z
Write waveform 2 (CE controlled)9
tWC
tAH
tWR
Address
tAS
CE
tCW
tAW
tBW
LB, UB
WE
tWP
tDW
Data valid
DataIN
2/21/06, v 1.2
tDH
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Write waveform 3 9
tWC
tAH
tWR
Address
tAS
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDW
DataIN
Data valid
tDH
tWZ
DataOUT
High Z
Data undefined
High Z
AC test conditions
-
Output load: see Figure B.
Input pulse level: GND to VCC - 0.5V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
VCC - 0.5V
GND
90%
90%
10%
10%
2 ns
Figure A: Input pulse
DOUT
255Ω
+5.0V
480Ω
Thevenin equivalent:
C10
GND
Figure B:5.0V Output load
168Ω
DOUT
+1.728V
Notes
1
2
3
4
5
6
7
8
9
10
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions, Figures A and B.
tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF.
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AS7C4098A
®
Package dimensions
c
44 434241403938373635343332313029282726252423
e He
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
A2
A
A1
l
0–5°
E
b
e
E1E2
Pin 1
c
B
A
A1
2/21/06, v 1.2
A
A1
A2
B
b
c
D
E
E1
E2
e
44-pin SOJ 400 mils
Min(mils) Max(mils)
0.128
0.148
0.025
0.105
0.115
0.026
0.032
0.015
0.020
0.007
0.013
1.120
1.130
0.370 NOM
0.395
0.405
0.435
0.445
0.050 NOM
D
44-pin SOJ
b
A
A1
A2
b
c
d
e
He
E
l
44-pin TSOP 2
Min (mm) Max (mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
Seating
Plane
A2
E
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AS7C4098A
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Ordering Codes
Package
SOJ
TSOP 2
Version
10 ns
12 ns
15 ns
20 ns
5.0V commercial AS7C4098A-10JC
AS7C4098A-12JC
AS7C4098A-15JC
AS7C4098A-20JC
5.0V industrial
AS7C4098A-10JI
AS7C4098A-12JI
AS7C4098A-15JI
AS7C4098A-20JI
5.0V commercial AS7C4098A-10TC
AS7C4098A-12TC
AS7C4098A-15TC
AS7C4098A-20TC
5.0V industrial
AS7C4098A-12TI
AS7C4098A-15TI
AS7C4098A-20TI
AS7C4098A-10TI
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts. (EX: AS7C4098A - 10TCN)
Part numbering system
AS7C
SRAM prefix
2/21/06, v 1.2
4098A
–XX
Device Access
number time
J or T
X
X
Packages:
J: SOJ 400 mil
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
N = Lead Free Parts
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Revision History
Rev. No.
v1.0
v1.1
v1.2
History
Initial release
11/08/04
Included ICC, ISB & ISB1 parameters
Corrected the following: TOE, VIH, VOL & tWZ
Removed the title “PRELIMINARY INFORMATION”
2/21/06, v 1.2
Revised Date
Alliance Semiconductor
05/27/05
02/21/06
P. 10 of 11
®
AS7C4098A
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C4098A
Document Version: v 1.2
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