Samsung K5D5657ACM-F015 256mb nand and 256mb mobile sdram Datasheet

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Preliminary
MCP MEMORY
K5D5657ACM-F015
MCP Specification of
256Mb NAND and 256Mb Mobile SDRAM
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MCP MEMORY
K5D5657ACM-F015
Document Title
Multi-Chip Package MEMORY
256M Bit(32Mx8) Nand Flash / 256M Bit(4Mx16x4Banks) Mobile SDRAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue.
May
12, 2003 Preliminary
0.1
<NAND Flash> .... ver 2.6
- Added the new definition of the number of invalid blocks : page 11
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
- Changed tREA : page 12
30ns ---> 35ns
September 2, 2003 Preliminary
<Mobile SDRAM> .... ver 0.5
- Corrected errata : page 33
tRC ---> tARFC
- Changed comment related with tRDL & tDAL : page 35
- Corrected MRS table : page 38
- Corrected errata : page 45
tSRFC ---> tSRFX
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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MCP MEMORY
K5D5657ACM-F015
Multi-Chip Package MEMORY
256M Bit (32Mx8) Nand Flash / 256M Bit (4Mx16x4Banks) Mobile SDRAM
FEATURES
<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 107-ball FBGA Type - 10.5x13mm, 0.8mm pitch
<Mobile SDRAM>
• Power Supply Voltage : 1.65~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
<NAND>
• Power Supply Voltage : 1.7~1.95V
• Organization
- Memory Cell Array : (32M + 1024K)bit x 8bit
- Data Register : (512 + 16)bit x 8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• Page Read Operation
- Page Size : (512 + 16)Byte
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
GENERAL DESCRIPTION
The K5D5657ACM is a Multi Chip Package Memory which combines 256Mbit Nand Flash Memory and 256Mbit synchronous high
data rate Dynamic RAM.
256Mbit NAND Flash memory is organized as 32M x8 bits and 256Mbit SDRAM is organized as 4M x16 bits x4 banks.
In 256Mbit NAND Flash, a 528-Byte page program can be typically achieved within 200us and an 16K-Byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. DQ pins serve as the ports for address and data
input/output as well as command inputs. Even the write-intensive systems can take advantage of FLASH′s extended reliability of
100K program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage
applications.
In 256Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The K5D5657ACM is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 107-ball FBGA Type.
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MCP MEMORY
K5D5657ACM-F015
PIN CONFIGURATION
1
A
B
2
3
4
5
6
7
8
DNU
9
DNU
DNU
DNU
NC
DQ0d
Vdd
Vss
Vcc
NC
A3
NC
C
Vss
DQ2d
DQ1d
CLE
/CE
A0
A1
A2
D
Vddq
DQ4d
DQ3d
ALE
/WE
BA0
BA1
A10
E
Vssq
DQ6d
DQ5d
/RE
R/B
/RAS
NC
/CS
F
Vddq
NC
DQ7d
/WP
NC
/CAS
/WEd
Vss
G
Vss
LDQM
NC
NC
NC
A12
CKE
Vdd
H
Vdd
UDQM
CLK
NC
NC
A8
A9
A11
J
Vssq
NC
DQ8d
IO0
IO2
IO4
IO6
A7
K
Vddq
DQ9d
DQ10d
NC
NC
NC
NC
A6
L
Vssq
DQ11d
DQ12d
IO1
IO3
IO5
IO7
A5
M
Vdd
DQ13d
DQ14d
NC
NC
NC
NC
A4
NC
DQ15d
Vss
Vss
Vccq
Vcc
Vss
NC
DNU
N
DNU
P
DNU
10
DNU
NAND
DNU
DNU
DNU
MSDRAM
107 FBGA: Top View (Ball Down)
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MCP MEMORY
K5D5657ACM-F015
PIN DESCRIPTION
Pin Name
Pin Name
Pin Function(Mobile SDRAM)
Pin Function(NAND Flash)
/CE
Chip Enable
Clock Enable
/RE
Read Enable
Chip Select
/WP
Write Protection
/RAS
Row Address Strobe
/WE
Write Enable
/CAS
Column Address Strobe
ALE
Address Latch Enable
/WEd
Write Enable
CLE
Command Latch Enable
A0 ~ A12
Address Input
R/B
Ready/Busy Output
CLK
System Clock
CKE
/CS
BA0 ~ BA1
IO0 ~ IO7
Bank Address Input
Data Input/Output
LDQM
Lower Input/Output Data Mask
Vcc
Power Supply
UDQM
Upper Input/Output Data Mask
Vccq
Data Out Power
Data Input/Output
Vss
Ground
DQ0d ~ DQ15d
Vdd
Power Supply
Vddq
Data Out Power
Vss
Vssq
Pin Name
NC
Ground
DNU
DQ Ground
Pin Function
No Connection
Do Not Use
ORDERING INFORMATION
K 5 D 56 57 A C M - F
Samsung
MCP Memory(2chips)
0 15
Mobile SDRAM Speed
15 = 15ns, CL=2
Device Type
NAND Flash + Mobile SDRAM
NAND Flash Speed
0 = None
NAND Flash Density,
Organization
56 : 256Mbit, x8
Package
F = FBGA(Leaded)
Mobile SDRAM Density, Organization
57 : 256Mbit, x16
Version
M= 1st Generation
Operating Voltage
A: 1.8V / 1.8V
Flash Block Architecture
C = Uniform Block
NOTE :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
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MCP MEMORY
K5D5657ACM-F015
FUNCTIONAL BLOCK DIAGRAM
RE
X-Buffers
Latches
& Decoders
ALE
256M+8M Bit
NAND flash
ARRAY
Y-Buffers
Latches
& Decoders
CLE
WP
(512 + 16)Byte x 65536
IO0 to IO7
CE
page Register & S/A
Y-Gating
R/B
Command
Register
WE
I/O Buffers & Latches
Vcc
Control Logic
& High Voltage
Generator
Vccq
Output
Driver
Global Buffers
Vss
CLK
Bank Select
CS
Col. Buffer
LCBR
Vdd
Vddq
4M x 16
4M x 16
4M x 16
Column Decoder
LRAS
UDQM
Timing Register
LDQM
4M x 16
Sense AMP
A0~A12
BA0~BA1
Address Register
WEd
Row Decoder
CAS
Row Buffer
Refresh Counter
RAS
Data Input Register
I/O Control Output Buffer
CKE
DQ0d to DQ15d
Latency & Burst Length
Programming Register
Vss
Vssq
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MCP MEMORY
K5D5657ACM-F015
256Mb(32Mb x 8)
NAND Flash C-Die
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MCP MEMORY
K5D5657ACM-F015
Figure 1. NAND Flash ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
1st half Page Register 2nd half Page Register
(=256 Bytes)
(=256 Bytes)
8 bit
512Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
Column Address
Row Address
(Page Address)
NOTE: 1. Column Address : Starting Address of the Register.
2. 00h Command(Read) : Defines the starting address of the 1st half of the register.
3. 01h Command(Read) : Defines the starting address of the 2nd half of the register.
4. A8 is set to "Low" or "High" by the 00h or 01h Command.
5. The device ignores any additional input of address cycles than reguired.
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MCP MEMORY
K5D5657ACM-F015
PRODUCT INTRODUCTION
This device is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The
memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited on
this device.
This device has addresses multiplexed into 8 I/O‘s. This device allows sixteen bit wide data transport into and out of page registers.
This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by
maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low
while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to
multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copyback Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte physical
space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high
row address, in that order. Page Read and Page Program need the same three address cycles following the required command
input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of this device.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Read 1
00h/01h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
00h
8Ah
Block Erase
60h
D0h
Read Status
70h
-
Acceptable Command during Busy
O
O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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MCP MEMORY
K5D5657ACM-F015
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Symbol
Rating
VIN/OUT
-0.6 to + 2.45
Unit
VCC
-0.2 to + 2.45
VCCQ
-0.2 to + 2.45
V
Temperature Under Bias
TBIAS
-40 to +125
°C
Storage Temperature
TSTG
-65 to +150
°C
Short Circuit Current
Ios
5
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbo
Min
Typ.
Max
Unit
Supply Voltage
VCC
1.7
1.8
1.95
V
Supply Voltage
VCCQ
1.7
1.8
1.95
V
Supply Voltage
VSS
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
tRC=50ns, CE=VIL
IOUT=0mA
Min
Typ
Max
-
8
15
Sequential Read
ICC1
Program
ICC2
-
-
8
15
Erase
ICC3
-
-
8
15
-
-
1
Stand-by Current(TTL)
ISB1
Stand-by Current(CMOS)
ISB2
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
-
10
50
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
VCCQ-0.4
-
Input High Voltage
VIH
VCCQ+0.3
VCC-0.4
-
VCC+0.3
Input Low Voltage, All inputs
VIL
-0.3
-
0.4
I/O pins
Except I/O pins
-
Output High Voltage Level
VOH
IOH=-100µA
VCCQ-0.1
-
-
Output Low Voltage Level
VOL
IOL=100uA
-
-
0.1
Output Low Current(R/B)
IOL(R/B)
VOL=0.1V
3
4
-
- 10 -
Unit
mA
µA
V
mA
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MCP MEMORY
K5D5657ACM-F015
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
2013
-
2048
Blocks
NOTE :
1. This device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. The 2nd and 3rd blocks are good upon shipping.
4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
( Vcc=1.7V~1.95V , TA=-25 to 85°C unless otherwise noted)
Parameter
Value
Input Pulse Levels
0V to VccQ
Input Rise and Fall Times
5ns
Input and Output Timing Levels
VccQ/2
Output Load (VccQ:1.8V +/-10%)
1 TTL GATE and CL=30pF
CAPACITANCE(TA=25°C, VCC=1.8V , f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
GND
WP
Mode
H
L
L
H
X
X
L
H
L
H
X
X
H
L
L
H
X
H
L
H
L
H
X
H
L
L
L
H
L
H
Data Input
Read Mode
Command Input
Address Input(3clock)
Write Mode
Command Input
Address Input(3clock)
L
L
L
H
L
X
Data Output
X
X
X
X
X
L
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V
0V/V
CC(2)
Stand-by
NOTE :
1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Main Array
Spare Array
Symbol
Min
Typ
Max
Unit
tPROG
-
200
500
µs
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
Nop
tBERS
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K5D5657ACM-F015
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE Setup Time
tCS
0
.-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
-
ns
25
(1)
ALE Setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data Setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
45
-
ns
WE High Hold Time
tWH
15
-
ns
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
tR
-
10
µs
Data Transfer from Cell to Register
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
CE Access Time
tCEA
-
45
ns
RE Access Time
tREA
-
35
ns
RE High to Output Hi-Z
tRHZ
-
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE or CE High to Output hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
tIR
0
-
ns
WE High to RE Low
tWHR
60
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
5/10/500(1)
µs
Output Hi-Z to RE Low
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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K5D5657ACM-F015
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 2). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 2. Flow chart to create invalid block table.
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NAND Flash Technical Notes(Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of
memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Wait for tR Time
Write Data
Write 10h
Verify Data
No
*
Program Error
Read Status Register
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
I/O 0 = 0 ?
Yes
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K5D5657ACM-F015
NAND Flash Technical Notes(Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
Erase Error
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
Buffer memory of the controller.
{
Block B
1
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
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Preliminary
MCP MEMORY
K5D5657ACM-F015
Pointer Operation
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 3. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
10h
’50h’ command can be omitted.
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Preliminary
MCP MEMORY
K5D5657ACM-F015
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/Ox
80h
Start Add.(3Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
tWP
RE
WE
tOH
I/Ox
out
Figure 5. Read Operation with CE don’t-care.
CLE
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/Ox
00h
Data Output(sequential)
Start Add.(3Cycle)
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Preliminary
MCP MEMORY
K5D5657ACM-F015
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/Ox
* Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tCH
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tALH
ALE
tDS
I/Ox
tDH
tDS
tDH
A9~A16
AO~A7
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tDS
tDH
A17~A24
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Preliminary
MCP MEMORY
K5D5657ACM-F015
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/Ox
DIN n
DIN 1
≈
DIN 0
Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREH
≈
tREA
tREA
tRP
RE
I/Ox
Dout
Dout
≈
tRHZ*
tREA
tCHZ*
tOH
tRHZ*
tOH
Dout
≈
tRR
R/B
NOTE :
1. Transition is measured ±200mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
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MCP MEMORY
K5D5657ACM-F015
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR
RE
tDS
I/Ox
tDH
tIR
tRHZ
tOH
tREA
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
CEn
tCHZ
tWC
tOH
WE
tWB
tAR
ALE
≈
RE
tRHZ
tOH
tRC
tR
N Address
I/Ox
A0 ~ A7
A9 ~ A16
Column
Address
R/Bn
A17 ~ A24
Dout N
Page(Row)
Address
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
00h
or
01h
Dout 528
Busy
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Preliminary
MCP MEMORY
K5D5657ACM-F015
READ1 OPERATION (INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tRC
tR
RE
N Address
tRR
I/Ox
Read
CMD
Col. Add
Row Add1
Column
Address
Dout N
Row Add2
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Busy
R/B
READ2 OPERATION (READ ONE PAGE)
CLE
CE
WE
tR
tWB
tAR
ALE
≈
tRR
I/Ox
50h
Col. Add
Row Add1
Dout
512+M
Row Add2
R/B
Dout
512+M+1
≈
RE
Dout 528
Selected
Row
M Address
A0~A3 are Valid Address & A4~A7 are Don′t care
512
16
Start
address M
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Preliminary
MCP MEMORY
K5D5657ACM-F015
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tWB
tPROG
ALE
RE
80h
Col. Add
Row Add1
Sequential Data Column
Input Command Address
≈ ≈
I/Ox
N Address
Din
Din
N+1
N
1 up to m Data
Serial Input
Row Add2
Page(Row)
Address
Din
528
10h
70h
Program
Command
Read Status
Command
≈
R/B
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
COPY-BACK PROGRAM OPERATION
CLE
CE
tWC
WE
tWB
tWB
tPROG
ALE
tR
RE
00h
Col. Add
Row Add1
8Ah
Row Add2
CommandAddress
≈
R/B
70h
A0~A7 A9~A16 A17~A24
Program Column Page(Row)
Column Page(Row)
Address Address
Address
Busy
Busy
- 22 -
I/O0
Read Status
Command
≈
I/Ox
I/O0=0 Successful Program
I/O0=1 Error in Program
Revision 0.1
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MCP MEMORY
K5D5657ACM-F015
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
60h
A9~A16
DOh
A17~A24
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
≈
Page(Row)
Address
Erase Command
Read Status
Command
I/O0=0 Successful Erase
I/O0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
tAR
RE
tREA
I/Ox
90h
Read ID Command
00h
ECh
35h
Address. 1cycle
Maker Code
Device Code
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Preliminary
MCP MEMORY
K5D5657ACM-F015
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address[column 511/ 527 depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A3 set the starting
address of the spare area while addresses A4~A7 are ignored in X8 device case. The Read1 command is needed to move the pointer
back to the main area. Figures6,7 show typical sequence and timings for each read operation.
Figure 6. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
Data Output(Sequential)
(00h Command)
1)
(01h Command)
1st half array
Main array
Data Field
Spare Field
2st half array
Data Field
Spare Field
NOTE :
1. After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
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MCP MEMORY
K5D5657ACM-F015
Figure 7. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
50h
Start Add.(3Cycle)
Data Output(Sequential)
Spare Field
A0 ~ A3 & A9 ~ A24
A4 ~ A7 Don’t care
Main array
Data Field
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Spare Field
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Preliminary
MCP MEMORY
K5D5657ACM-F015
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 8. Program Operation
tPROG
R/B
I/Ox
80h
Address & Data Input
10h
I/O0
70h
Pass
Fail
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The
data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is
internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. Thus, A14, the
plane address, of source and destination page address must be the same.
Figure 9. Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
00h
Add.(3Cycles)
Source Address
8Ah
Add.(3Cycles)
70h
I/O0
Pass
Destination Address
Fail
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Preliminary
MCP MEMORY
K5D5657ACM-F015
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence.
Figure 10. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A9 ~ A24
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table3. Read Status Register Definition
I/O #
I/O 0
Status
Definition
"0" : Successful Program / Erase
Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
"0"
Reserved for Future
Use
"0"
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
- 27 -
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
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MCP MEMORY
K5D5657ACM-F015
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 11 shows the operation sequence.
Figure 11. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
I/Ox
tWHR
tREA
ECh
00h
90h
Address. 1cycle
Maker code
35h
Device code
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 12 below.
Figure 12. RESET Operation
tRST
R/B
I/Ox
FFh
Table4. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
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MCP MEMORY
K5D5657ACM-F015
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart. Its value can be determined by the following guidance.
Rp
ibusy
Vccqn
Ready Vccqn
R/Bn
open drain output
Vccqn-0.4V
0.4V
Busy
tf
tr
GND
Device
Figure 13. Rp vs tr ,tf & Rp vs ibusy
Ibusy
300n
200n
1.7
2m
tr
100n
3m
30
0.85
120
90
60
0.57
1.7
1K
tf
1.7
1.7
2K
3K
Rp(ohm)
Ibusy [A]
tr,tf [s]
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
1m
0.43
1.7
4K
Rp value guidance
Rp(min, 1.8V part) =
1.9V
Vccq(Max.) - VOL(Max.)
IOL + ΣIL
=
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
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MCP MEMORY
K5D5657ACM-F015
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 14. The two step command sequence for program/erase provides additional software protection.
≈
Figure 14. AC Waveforms for Power Transition
~ 1.5V
~ 1.5V
High
≈
VCC
≈
WP
10µs
≈
WE
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Preliminary
MCP MEMORY
K5D5657ACM-F015
256Mb(16Mb x 16)
Mobile SDRAM E-Die
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Preliminary
MCP MEMORY
K5D5657ACM-F015
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 2.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 2.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Storage temperature
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD
1.65
1.8
1.95
V
VDDQ
1.65
1.8
1.95
V
Input logic high voltage
VIH
0.8 x VDDQ
1.8
VDDQ + 0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.3
V
2
Output logic high voltage
VOH
VDDQ -0.2
-
-
V
IOH = -0.1mA
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
)NOTES :
1. VIH (max) = 2.2V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 1.8V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Unit
CCLK
TBD
TBD
pF
CIN
TBD
TBD
pF
Address
CADD
TBD
TBD
pF
DQ0 ~ DQ15
COUT
TBD
TBD
pF
Clock
RAS, CAS, WE, CS, CKE, DQM
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Note
Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial)
Version
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Symbol
ICC1
ICC2P
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
-IL
-15
40
40
CKE ≤ VIL(max), tCC = 10ns
ICC3NS
mA
1
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
10
mA
1
CKE ≤ VIL(max), tCC = 10ns
5
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
Note
0.3
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P
Unit
0.3
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
Precharge Standby Current
in non power-down mode
Test Condition
1
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
20
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
5
mA
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
60
50
mA
1
ICC5
tARFC ≥ tARFC(min)
65
65
mA
2
TCSR
Max 40°°C
Max 85°°C
°C
4 Banks
200
480
2 Banks
160
300
1 Bank
130
220
ICC6
CKE ≤ 0.2V
uA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
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MCP MEMORY
K5D5657ACM-F015
AC OPERATING TEST CONDITIONS(VDD = 1.8V ± 0.15V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for CommerParameter
AC input levels (Vih/Vil)
Value
Unit
0.9 x VDDQ / 0.2
V
0.5 x VDDQ
V
tr/tf = 1/1
ns
0.5 x VDDQ
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Figure 2
1.8V
13.9KΩ
Vtt=0.5 x VDDQ
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
Output
VOL (DC) = 0.2V, IOL = 0.1mA
10.6KΩ
50Ω
30pF
Output
Z0=50Ω
30pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
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September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-IL
-15
Unit
Note
Row active to row active delay
tRRD(min)
19
30
ns
1
RAS to CAS delay
tRCD(min)
28.5
30
ns
1
Row precharge time
tRP(min)
28.5
30
ns
1
tRAS(min)
60
60
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
88.5
us
90
ns
1
2
CLK
2
tDAL(min)
tRDL + tRP
-
3
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
105
ns
Exit self refresh to active command
tSRFX(min)
120
ns
Col. address to col. address delay
tCCD(min)
1
CLK
4
ea
5
Number of valid output data
CAS latency=3
2
Number of valid output data
CAS latency=2
1
Number of valid output data
CAS latency=1
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. Minimum 3CLK of tDAL(= tRDL + tRP) is required because it need minimum 2CLK for tRDL and minimum 1CLK for tRP.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
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Preliminary
MCP MEMORY
K5D5657ACM-F015
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
-1L
Parameter
-15
Symbol
Min
Max
Min
Unit
Note
ns
1
ns
1,2
ns
2
Max
CLK cycle time
CAS latency=3
tCC
9.5
CLK cycle time
CAS latency=2
tCC
15
CLK cycle time
CAS latency=1
tCC
25
CLK to valid output delay
CAS latency=3
tSAC
7
9
CLK to valid output delay
CAS latency=2
tSAC
8
9
CLK to valid output delay
CAS latency=1
tSAC
20
24
Output data hold time
CAS latency=3
tOH
2.5
2.5
Output data hold time
CAS latency=2
tOH
2.5
2.5
Output data hold time
CAS latency=1
tOH
2.5
2.5
CLK high pulse width
tCH
3.5
3.5
ns
3
CLK low pulse width
tCL
3.5
3.5
ns
3
Input setup time
tSS
3.0
4.0
ns
3
Input hold time
tSH
1.5
2.0
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
2
CAS latency=3
CLK to output in Hi-Z
CAS latency=2
tSHZ
CAS latency=1
15
1000
15
1000
30
7
9
8
9
20
24
ns
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
Auto Refresh
X
Entry
Self
Refresh
RAS
CAS
WE
L
L
L
L
X
OP CODE
L
L
L
H
X
X
3
L
3
L
Exit
H
H
H
3
L
H
H
X
X
X
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
Burst Stop
H
X
L
H
H
L
X
X
H
X
L
L
H
L
X
Entry
H
H
X
X
X
L
V
V
V
X
X
X
X
L
Exit
L
H
Entry
H
L
H
Column
Address
(A0~A7)
H
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
X
X
Exit
No Operation Command
Column
Address
(A0~A7)
L
Precharge Power Down
Mode
DQM
Row Address
L
All Banks
Clock Suspend or
Active Power Down
X
3
Bank Selection
Precharge
Note
1, 2
H
H
Refresh
DQM BA0,1 A10/AP
A11,
A9 ~ A0
CS
L
H
X
H
H
X
H
X
X
X
L
H
H
H
X
V
X
X
X
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
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Revision 0.1
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Preliminary
MCP MEMORY
K5D5657ACM-F015
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
BA0 ~ BA1*1
BA0
A11 ~ A10/
AP
A9*2
"0" Setting for Normal
MRS
RFU
W.B.L
Address
Function
A8
A7
A6
Test Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
A9
Length
Mode Select
BA1 BA0
0
0
Burst
1
1
0
Reserved
1
Single Bit
1
1
1
Reserved
Mode
Setting
for Normal MRS
0
Full Page Length x16 : 64Mb(256), 128Mb(512),256Mb(512),512Mb(1024)
Register Programmed with Extended MRS
Address
BA1
Function
BA0
A11 ~ A10/AP
Mode Select
A9
A8
A7
A6
RFU
A5
A4
DS
A3
A2
RFU
A1
A0
PASR
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Driver Strength
PASR
BA1
BA0
Mode
A6
A5
Driver Strength
A2
A1
A0
# of Banks
0
0
Normal MRS
0
0
Full
0
0
0
4 Banks
0
1
Reserved
0
1
1/2
0
0
1
2 Banks
1
0
EMRS for Mobile SDRAM
1
0
1/4
0
1
0
1 Bank
1
1
Reserved
1
1
1/8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Reserved Address
A11~A10/AP
A9
A8
A7
A4
A3
0
0
0
0
0
0
NOTES:
1.RFU(Reserved for future use) should stay "0" during MRS cycle.
2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : 4 Banks, 2 Banks and 1 Bank.
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- 4 Banks
- 2 Banks
- 1 Bank
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
Note :
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; Max. 40 °C, Max. 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc 6)
Temperature Range
Unit
4 Banks
2 Banks
1 Bank
Max. 40 °C
200
160
130
Max. 85 °C
480
300
220
uA
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is half driver strength, all 4 banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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Revision 0.1
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Preliminary
MCP MEMORY
K5D5657ACM-F015
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
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Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
D. DEVICE OPERATIONS
ADDRESSES of 256Mb
ADDRESSES of 512Mb
BANK ADDRESSES (BA0 ~ BA1)
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
: In case x 16
This SDRAM is organized as four independent banks of
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
8,388,608 words x 16 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
and precharge operations.
: In case x 32
: In case x 32
This SDRAM is organized as four independent banks of
This SDRAM is organized as four independent banks of
2,097,152 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
4,194,304 words x 32 bits memory arrays. The BA0 ~ BA1 inputs
are latched at the time of assertion of RAS and CAS to select the
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
BA1 during bank activate command. The 10 bit column
are latched along with CAS, WE and BA0 ~ BA1 during read or
addresses are latched along with CAS, WE and BA0 ~ BA1 dur-
write command.
ing read or write command.
: In case x 32
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 12 bit row addresses are latched along with RAS and BA0 ~
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
write command.
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Preliminary
MCP MEMORY
K5D5657ACM-F015
D. DEVICE OPERATIONS (continued)
CLOCK (CLK)
DQM OPERATION
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order to
function well Q perform and ICC specifications.
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature of
CLOCK ENABLE (CKE)
the internal write, the DQM operation is critical to avoid unwanted
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
or incomplete writes when the complete burst write is not
required. Please refer to DQM timing diagram also.
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks are
in the idle state and CKE goes low synchronously with clock, the
SDRAM enters the power down mode from the next clock cycle.
The SDRAM remains in the power down mode ignoring the other
inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes
high at least "1CLK + tSS" before the high going edge of the
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ An and BA0 ~ BA1 in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode reg-
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but is
needed to complete operations which require more than single
clock cycle like bank activate, burst read, auto refresh, etc. The
device deselect is also a NOP and is entered by asserting CS
high. CS high disables the command decoder so that RAS, CAS,
WE and all the address inputs are ignored.
MODE REGISTER SET (MRS)
ister. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A0 ~ A2, burst type uses
A3, CAS latency (read latency from column address) use A4 ~
A6, vendor specific options or test mode use A7 ~ A8, A10/AP ~
An and BA0 ~ BA1. The write burst length is programmed using
A9. A7 ~ A8, A10/AP ~ An and BA0 ~ BA1 must be set to low for
normal SDRAM operation. Refer to the table for specific codes
for various burst length, burst type and CAS latencies.
- 42 -
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September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
D. DEVICE OPERATIONS (continued)
EXTENDED MODE REGISTER SET (EMRS)
The SDRAM has four internal banks in the same chip and shares
The extended mode register stores the data for selecting driver
strength and partial self refresh. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when DS or
PASR is used. The default state without EMRS command issued
is half driver strength and all 4 banks refreshed. The extended
mode register is written by asserting low on CS, RAS, CAS, WE
and high on BA1 ,low on BA0(The SDRAM should be in all bank
precharge with CKE already high prior to writing into the
extended mode register). The state of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS and WE going low is written in
the extended mode register. Two clock cycles are required to
complete the write operation in the extended mode register. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as
all banks are in the idle state. A0 - A2 are used for partial self
refresh , A5 - A6 are used for Driver strength, "Low" on BA1 and
"High" on BA0 are used for EMRS. All the other address pins
except A0,A1,A2, BA1, BA0 must be set to low for proper EMRS
operation. Refer to the table for specific codes.
part of the internal circuitry to reduce chip area, therefore it
restricts the activation of four banks simultaneously. Also the
noise generated during sensing of each bank of SDRAM is high,
requiring some time for power supplies to recover before another
bank can be sensed reliably. tRRD(min) specifies the minimum
time required between activating different bank. The number of
clock cycles required between different bank activation must be
calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and restoring
the complete row of dynamic cells is determined by tRAS(min).
Every SDRAM bank activate command must satisfy tRAS(min)
specification before a precharge command to that active bank
can be asserted. The maximum time any bank can be in the
active state is determined by tRAS(max). The number of cycles for
both tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
BANK ACTIVATE.
with WE being high on the positive edge of the clock. The bank
The bank activate command is used to select a random row in an
must be active for at least tRCD(min) before the burst read com-
idle bank. By asserting low on RAS and CS with desired row and
mand is issued. The first output appears in CAS latency number
bank address, a row access is initiated. The read or write opera-
of clock cycles after the issue of burst read command. The burst
tion can occur after a time delay of tRCD(min) from the time of
length, burst sequence and latency from the burst read command
bank activation. tRCD is an internal timing parameter of SDRAM,
is determined by the mode register which is already pro-
therefore it is dependent on operating clock frequency. The mini-
grammed. The burst read can be initiated on any column address
mum number of clock cycles required between bank activate and
of the active row. The address wraps around if the initial address
read or write command should be calculated by dividing
does not start from a boundary such that number of outputs from
tRCD(min) with cycle time of the clock and then rounding off the
each I/O are equal to the burst length programmed in the mode
result to the next higher integer.
register. The output goes into high-impedance at the end of the
burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another
burst read or burst write in the same bank or the other active
bank or a precharge command to the same bank. The burst stop
command is valid at every page burst length.
- 43 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
D. DEVICE OPERATIONS (continued)
BURST WRITE
AUTO PRECHARGE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after
performing precharge to all the banks, all banks are in idle state.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1
of the bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.
AUTO REFRESH
The storage cells of 64Mb, 128Mb, 256Mb and 512Mb SDRAM
need to be refreshed every 64ms to maintain data. An auto
refresh cycle accomplishes refresh of a single row of storage
cells. The internal counter increments automatically on every
auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high
on CKE and WE. The auto refresh command can only be
asserted with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified by
tRC(min). The minimum number of clock cycles required can be
calculated by driving tRC with clock cycle time and them rounding
up to the next higher integer. The auto refresh command must be
followed by NOP's until the auto refresh operation is completed.
All banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the
SDRAM is being used for normal data transactions. The 64Mb
and 128Mb SDRAM’s auto refresh cycle can be performed once
in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.
The 256Mb and 512Mb SDRAM’s auto refresh cycle can be performed once in 7.8us or a burst of 8192 auto refresh cycles once
in 64ms.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
D. DEVICE OPERATIONS(continued)
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE. Once
the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order
to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and then
asserting high on CKE. This must be followed by NOP's for a
minimum time of tSRFX before the SDRAM reaches idle state to
begin normal operation. In case that the system uses burst auto
refresh during normal operation, it is recommended to use burst
8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096
auto refresh cycles for 128Mb and 64Mb immediately before
entering self refresh mode and after exiting in self refresh mode.
On the other hand,
if the system uses the distributed auto
refresh, the system only has to keep the refresh duty cycle.
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September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
E. BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write
2) Clock Suspended During Read (BL=4)
CLK
CLK
CMD
WR
CMD
CKE
RD
CKE
Masked by CKE
Masked by CKE
Internal
CLK
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL2)
DQ(CL3)
D0
D1
D2
D3
DQ(CL3)
Q0
Not Written
D
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Suspended Dout
2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
CLK
CMD
CMD
WR
RD
DQM
DQM
Masked by CKE
DQ(CL2)
D0
DQ(CL3)
D0
D1
DQ(CL2)
D3
D1
Q0
Hi-Z
DQ(CL3)
D3
Masked by CKE
Hi-Z
DQM to Data-in Mask = 0
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) *2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Q2
Q1
Hi-Z
Hi-Z
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*NOTE :
1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4) *1
CLK
CMD
RD
RD
ADD
A
B
QA0 QB0 QB1 QB1 QB3
DQ(CL2)
QA0 QB0 QB1 QB1 QB3
DQ(CL3)
tCCD
*2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CLK
CMD
WR WR
CMD
WR
tCCD *2
tCCD *2
ADD
DQ
A
ADD
B
DA0 DB0 DB1
tCDL *3
RD
A
B
DQ(CL2)
DA0
DQ(CL3)
DA0
tCDL
QB0 QB1
QB0 QB1
*3
*NOTE:
1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
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Revision 0.1
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Preliminary
MCP MEMORY
K5D5657ACM-F015
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
*1
D0
D3
(b) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
iii) CMD
D0
RD
WR
DQM
DQ
iv) CMD
D0
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
*1
D0
D3
*NOTE:
1. To prevent bus contention, there should be at least one gap between data in and data out.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
5. Write Interrupted by Precharge & DQM
1) tRDL = 2CLK
CLK
CMD
WR
PRE
*2
DQM
DQ
*3
D0
D1
D2
Masked by DQM
*NOTE:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation.
6. Precharge
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
DQ
D0
PRE
D1
D2
D3
tRDL*1
2) Normal Read (BL=4)
CLK
*2
RD
CMD
PRE
Q0
DQ(CL2)
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
2) Normal Read (BL=4)
1) Normal Write (BL=4)
CLK
CLK
CMD
WR
DQ
D0
ACT
D1
D2
CMD
DQ(CL2)
D3
RD
Q0
DQ(CL3)
tRDL =2CLK
Q1
Q2
Q3
Q0
Q1
Q2
Q3
tDAL =tRDL + tRP*4
Auto Precharge Starts *3
Auto Precharge Starts@tRDL=2CLK *3
*NOTE:
1. SAMSUNG can support tRDL=1CLK and tRDL=2CLK for all memory devices. SAMSUNG recommends tRDL=2 CLK.
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
4. tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP .
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
8. Burst Stop & Interrupted by Precharge
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
PRE
DQM
DQ
D0
D1
D2
tRDL*1
2) Write Burst Stop (BL=8)
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
CLK
WR
STOP
CMD
DQ(CL2)
DQM
DQ
RD
D0
D1
D2
D3
DQ(CL3)
PRE
Q0
Q1
Q0
1
Q1
2
tBDL *2
4) Read Burst Stop (BL=4)
CLK
CMD
RD
STOP
Q0
DQ(CL2)
Q1
Q0
DQ(CL3)
1
Q1
2
9. MRS
1) Mode Register Set
CLK
*4
CMD
PRE
MRS
tRP
ACT
2CLK
*NOTE:
1. SAMSUNG can support tRDL=2 CLK.
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectively.
4. PRE : All banks precharge is necessary.
MRS can be issued only at all banks precharge state.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
CKE
tSS
Internal
CLK
*1
RD
CMD
tSS
*2
CMD
NOP ACT
11. Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the
clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external
address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed,
all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto
refresh command must be greater than or equal to the tARFC(min).
∼
Auto
Refresh
PRE
CMD
∼
Command
∼
CLK
CKE = High
tRP
tARFC(min) = 105ns
Self Refresh
Command
Self
Refresh
NOP
∼ ∼
Stable Clock
∼
CLK
∼
∼ ∼
A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once
the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self
refresh command, all of the external control signals including system clock(CLK) can be disabled except CKE. The clock is internally
disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before returning
CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal
opreation, it is recommended to use burst 4096 auto refresh cycle immediately before entering self refresh mode and after exiting in
self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty
cycle.
ACT
∼
tSRFX(min) = 120ns
∼
CKE
tSS
tSS
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
12. About Burst Type Control
Sequential Counting
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
Interleave Counting
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting.
Basic
MODE
Random
MODE
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010".
8
At MRS A2,1,0 = "011".
Full Page
Special
MODE
BRSW
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS Interrupt
At MRS A2,1,0 = "111".
Wrap around mode(infinite burst length) should be stopped by burst stop.
RAS interrupt or CAS interrupt.
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1.
At auto precharge of write, tRAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
- 52 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS
RAS
CAS
WE
BA
Address
Action
Note
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA, A10/AP ILLEGAL
2
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
L
L
L
H
X
X
L
L
L
L
OP code
OP code
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
L
H
L
H
BA
CA, A10/AP Begin Read ; latch CA ; determine AP
L
H
L
L
BA
CA, A10/AP Begin Read ; latch CA ; determine AP
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP
Precharge
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP Term burst, New Read, Determine AP
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
Row (& Bank) Active ; Latch RA
NOP
4
Auto Refresh or Self Refresh
5
Mode Register Access
5
2
2
3
ILLEGAL
2
Term burst, Precharge timing for Reads
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP Term burst, New read, Determine AP
3
L
H
L
L
BA
CA, A10/AP Term burst, New Write, Determine AP
3
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
L
L
L
X
X
X
ILLEGAL
ILLEGAL
2
Term burst, precharge timing for Writes
3
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
CA, A10/AP ILLEGAL
2
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
CA, A10/AP ILLEGAL
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2
Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
FUNCTION TRUTH TABLE (TABLE 1)
Current
Precharging
Row
Activating
Refreshing
Mode
Register
Accessing
CS
RAS
CAS
WE
BA
Address
H
X
X
X
X
X
NOP --> Idle after tRP
Action
L
H
H
H
X
X
NOP --> Idle after tRP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
NOP --> Idle after tRP
4
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Row Active after tRCD
L
H
H
H
X
X
NOP --> Row Active after tRCD
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after tRC
L
H
H
X
X
X
NOP --> Idle after tRC
L
H
L
X
X
X
ILLEGAL
L
L
H
X
X
X
ILLEGAL
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after 2 clocks
L
H
H
H
X
X
NOP --> Idle after 2 clocks
L
H
H
L
X
X
ILLEGAL
L
H
L
X
X
X
ILLEGAL
L
L
X
X
X
X
ILLEGAL
Abbreviations : RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
Note
AP = Auto Precharge
*NOTE:
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
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Revision 0.1
September 2003
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Preliminary
MCP MEMORY
K5D5657ACM-F015
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
(n-1)
CKE
n
CS
RAS
CAS
WE
Address
Action
Note
H
X
X
X
X
X
X
Exit Self Refresh --> Idle after tsRFX(ABI)
L
H
H
X
X
X
X
Exit Self Refresh --> Idle after tsRFX (ABI)
6
L
H
L
H
H
H
X
Exit Self Refresh --> Idle after tsRFX (ABI)
6
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Power Down --> ABI
L
H
L
H
H
H
X
Exit Power Down --> ABI
7
L
H
L
H
H
L
X
ILLEGAL
7
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
8
H
L
L
H
H
L
X
ILLEGAL
8
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
H
RA
H
L
L
L
L
H
H
L
L
L
L
L
X
Row (& Bank) Active
Enter Self Refresh
8
OP Code Mode Register Access
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
9
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
9
L
L
X
X
X
X
X
Maintain Clock Suspend
Abbreviations : ABI = All Banks Idle, RA = Row Address
*NOTE:
6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
- 55 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Power Up Sequence
Single Bit Read - Write - Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
Page Read Cycle at Different Bank @Burst Length=4
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
Read & Write Cycle at Different Bank @Burst Length=4
Read & Write Cycle With Auto Precharge l @Burst Length=4
Read & Write Cycle With Auto Precharge ll @Burst Length=4
Clock Suspension & DQM Operation Cycle @CAS Letency=2, Burst Length=4
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst, tRDL=2CLK
Burst Read Single bit Write Cycle @Burst Length =2
Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4
Self Refresh Entry & Exit Cycle & Exit Cycle
Mode Register Set Cycle and Auto Refresh Cycle
Extended Mode Register Set Cycle
- 56 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Power Up Sequence for Mobile SDRAM
0
1
2
3
4
5
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈ ≈
≈
tARFC
Auto
Refresh
12
13
14
15
16
Key
17
18
19
20
21
Key
22 23
24
25
RAa
RAa
≈
Precharge
(All Bank)
≈ ≈
tRP
≈
High level is necessary
≈
DQM
Hi-Z
≈ ≈
WE
≈
Hi-Z
≈
DQ
≈ ≈
A10/AP
≈ ≈
BA1
≈ ≈
BA0
≈ ≈
ADDR
≈ ≈
CAS
11
≈ ≈
RAS
10
≈ ≈
CS
9
≈
Hi
8
≈
CKE
7
≈ ≈
CLOCK
6
tARFC
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
*NOTE:
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is half driver strength, all 4 banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again
at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
- 57 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
0
1
2
tCH
4
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCC
tCL
CKE
HIGH
tRAS
tRC
tRP
tSH
*Note 1
CS
tRCD
tSS
tSH
RAS
tSS
tSH
CAS
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
Rb
tSS
*Note 2
*Note 2,3
*Note 2,3
BA0,BA1
BS
BS
BS
A10/AP
Ra
*Note 3
*Note 2,3 *Note 4
BS
*Note 3
*Note 2
BS
*Note 3
BS
*Note 4
Rb
tSAC
DQ
Qa
tSLZ
tOH
tSH
Db
Qc
tSS
tSS tSH
WE
tSS tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
*NOTE:
1. All input except CKE & DQM can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA0,BA1.
- 58 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS
RAS
*Note 2
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
tOH
{
CL=2
Qa0
tRCD
DQ
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
- 59 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10/AP
Ra
Rb
tRDL
{
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
tRCD
DQ
tDAL
*Note 4
CL=3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don’t care
*NOTE:
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. tDAL ,last data in to active delay, is 2CLK + tRP.
- 60 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA0
BA1
A10/AP
RCc
{
CL=2
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
CL=3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Precharge
(B-Bank)
: Don’t care
*NOTE:
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
- 61 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
RAb
RAa
RBb
CAa
CBb
RCc
RDd
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
tRDL
WE
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Write
(C-Bank)
: Don’t care
*NOTE:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
- 62 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RDb
CDb
RBc
CBc
BA0
BA1
A10/AP
RAa
RDb
RBc
tCDL
{
CL=2
QAa0 QAa1 QAa2 QAa3
*Note 1
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
DQ
QAa0 QAa1 QAa2 QAa3
CL=3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Row Active
(D-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
: Don’t care
*NOTE:
1. tCDL should be met to complete write.
- 63 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
RAc
CAc
BA0
BA1
A10/AP
RAc
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DQ CL=2
CL=3
DAc0 DAc1
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
WE
DQM
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Read without Auto
Precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note1
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don’t care
*NOTE:
1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A-Bank auto precharge starts, A-Bank
auto precharge will start at B-Bank read command input point .
- any command can not be issued at A-Bank during tRP after A-Bank auto precharge starts.
- 64 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
DQ CL=2
Qa0
CL=3
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Qb3
WE
DQM
*Note1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don’t care
*NOTE:
1. Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
- 65 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A10/AP
Ra
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Write
DQM
Clock
Suspension
: Don’t care
*NOTE:
1. DQM is needed to prevent bus contention.
- 66 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page Burst
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
{
RAa
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
CL=3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. At full page mode, burst is finished by burst stop or precharge.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
- 67 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst,
tRDL=2CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
tBDL
tRDL
*Note 1
DQ
*Note 1,2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
*NOTE:
1. At full page mode, burst is finished by burst stop or precharge.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
- 68 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Burst Read Single bit Write Cycle @Burst Length=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
{
RAa
RBb
CL=2
DAa0
CL=3
DAa0
RCc
QAb0 QAb1
DBc0
QCd0 QCd1
DQ
QAb0 QAb1
DBc0
QCd0 QCd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
Read with
(A-Bank) Auto Precharge
(A-Bank)
Read
(C-Bank)
Precharge
(C-Bank)
Write with
Auto Precharge
(B-Bank)
: Don’t care
*NOTE:
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
- 69 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
1
2
6
7
*Note 1
8
tSS
17
18
19
Ra
Ca
Ra
≈ ≈
≈
≈
Qa0
Qa1
Qa2
tSHZ
≈ ≈
≈ ≈
≈ ≈
≈ ≈
Precharge
Power-down
Entry
16
≈ ≈
≈ ≈
DQ
15
tSS
≈ ≈
≈ ≈
A10/AP
14
≈ ≈
≈ ≈
BA
13
≈ ≈
≈ ≈
ADDR
12
≈ ≈
≈ ≈
CAS
11
≈
≈ ≈
RAS
DQM
10
*Note 2
*Note 3
CS
WE
9
*Note 2
≈
CKE
5
≈
tSS
4
≈ ≈
CLOCK
3
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Read
Precharge
Active
Power-down
Exit
: Don’t care
*NOTE:
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
- 70 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
8
9
10
11
12
*Note 4
CKE
15
16
17
18
19
tSRFX
*Note 6
≈
*Note 3
tSS
≈
≈ ≈
CS
≈ ≈
≈ ≈
RAS
≈ ≈
≈ ≈
CAS
≈ ≈
≈ ≈
ADDR
≈ ≈
≈ ≈
BA0,BA1
Hi-Z
≈ ≈
≈ ≈
WE
≈ ≈
≈ ≈
DQM
≈
≈
Hi-Z
≈ ≈
≈ ≈
A10/AP
DQ
14
≈
*Note 1
13
≈
*Note 2
7
≈ ≈
CLOCK
6
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don’t care
*NOTE:
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle(64Mb ,128Mb) or 8K cycle(256Mb, 512Mb) of burst auto refresh is required before self refresh entry and
after self refresh exit if the system uses burst refresh.
- 71 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Mode Register Set Cycle
0
1
2
3
4
Auto Refresh Cycle
5
6
0
1
2
3
4
5
7
8
9
10
≈
CLOCK
6
≈
HIGH
CKE
HIGH
≈
CS
tARFC
*Note 2
≈ ≈
RAS
≈ ≈
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
≈
Hi-Z
DQ
≈ ≈
WE
≈ ≈
DQM
MRS
New Command
Auto Refresh
New Command
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
: Don’t care
*NOTE:
MODE REGISTER SET CYCLE
1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
- 72 -
Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
Extended Mode Register Set Cycle
0
1
2
3
4
5
6
CLOCK
HIGH
CKE
CS
*Note 2
RAS
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
DQ
WE
DQM
EMRS
New Command
: Don’t care
*NOTE:
EXTENDED MODE REGISTER SET CYCLE
1. CS, RAS, CAS, BA0, BA1 & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
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Revision 0.1
September 2003
Advance
Preliminary
MCP MEMORY
K5D5657ACM-F015
PACKAGE DIMENSION
107-Ball Fine pitch Ball Grid Array Package (measured in millimeters)
Units:millimeters
#A1 INDEX MARK
10.50±0.10
0.10 MAX
10.50±0.10
A
0.80x9=7.20
(Datum A)
B
10 9 8 7 6 5 4 3 2 1
A
B
#A1
D
0.80
E
0.80x13=10.40
13.00±0.10
(Datum B)
0.80
0.45±0.05
13.00±0.10
13.00±0.10
C
F
G
H
5.20
J
K
L
M
N
P
0.32±0.05
3.60
1.30±0.10
TOP VIEW
107-∅ 0.45±0.05
BOTTOM VIEW
∅ 0.20 M A B
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Revision 0.1
September 2003