ALD ALD500RAU-20SEI Precision integrating analog processor with precision voltage reference Datasheet

ADVANCED
LINEAR
DEVICES, INC.
ALD500RAU/ALD500RA/ALD500R
PRECISION INTEGRATING ANALOG PROCESSOR
WITH PRECISION VOLTAGE REFERENCE
APPLICATIONS
BENEFITS
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Low cost, simple functionality
Wide dynamic signal range
Very high noise immunity
Automatic compensation and cancellation
of error sources
• Easy to use to acquire bipolar signals
• Up to 19 bit (18 bit + sign bit) single conversion
or 21 bit (20 bit + sign bit) multiple conversion
and noise performance
• Inherently linear and stable with temperature
and component variations
4 1/2 digits to 5 1/2 digits plus sign measurements
Precision analog signal processor
Precision sensor interface
High accuracy DC measurement functions
Portable battery operated instruments
Computer peripheral
PCMCIA
FEATURES
•
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Resolution up to 18 bits plus sign bit and over-range bit
Accuracy independent of input source impedances
Accurate on-chip voltage reference
Tempco as low as 10 ppm/°C guaranteed
Chip select - power down mode
High input impedance of 1012 Ω
Inherently filters and integrates any external noise spikes
Differential analog input
Wide bipolar analog input voltage range ±3.5V
Automatic zero offset compensation
Low linearity error - as low as 0.001% typical
Fast zero-crossing comparator - 1µs
Low power dissipation - 6mW typical
Automatic internal polarity detection
Low input current - 2pA typical
Optional digital control from a microcontroller, an ASIC, or
a dedicated digital circuit
• Flexible conversion speed vs. resolution trade-off
PIN CONFIGURATION
ALD500R
IB
1
20
CS
CINT
2
19
V+
V-
3
18
DGND
CAZ
4
17
COUT
B
BUF
5
16
AGND
6
15
A
C-REF
7
14
V+IN
C+REF
8
13
V-IN
N/C
9
12
V+REF
N/C
10
11
V-REF
QE, PE, SE PACKAGE
* N/C pin is connected internally. Connect to V-.
Ordering Information
Resolution Endpoint
Linearity
Voltage Reference
Accuracy/Tempco
Package Type
20L PDIP
16 bit
20L SOIC
20L QSOP
Operating
Temperature
20LCDIP
0.015%
0.5% 50ppm/C
ALD500R-50PE
ALD500R-50SE
ALD500R-50QE
0°C to 70°C
17 bit
0.01%
0.3% 20ppm/C
ALD500RA-20PE
ALD500RA-20SE
ALD500RA-20QE
0°C to 70°C
18 bit
0.005%
ALD500RAU-20PE
ALD500RAU-20SE
ALD500RAU-20QE
17 bit
0.01%
0.2% 10ppm/C
ALD500RA-10PE
ALD500RA-10SE
ALD500RA-10QE
18 bit
0.005%
ALD500RAU-10PE
ALD500RAU-10SE
ALD500RAU-10QE
17 bit
0.01%
0.3% 20ppm/C
ALD500RA-20PEI
ALD500RA-20SEI
ALD500RA-20QEI
18 bit
0.005%
ALD500RAU-20PEI
ALD500RAU-20SEI
ALD500RAU-20QEI
18 bit
0.005%
0.3% 20ppm/C
0°C to 70°C
-40°C to +85°C
ALD500RAU-20DE
-55°C to +125°C
* Contact factory for customized voltage reference voltage levels, accuracy and tempco specifications.
Rev. 1.01 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155, Fax: (408) 747-1286
http://www.aldinc.com
FIGURE 1. ALD500R Functional Block Diagram
V-REF
(11)
V+REF
(12)
RREF = 100KΩ
CB = 0.1µF
RREF
C+REF
CINT
RINT
CREF
CAZ
C-REF
(7)
(8)
CAZ
(4)
BUF
(5)
CINT
(2)
REFINT
SWR
SWR
Buffer
+
SWIN
V+IN
Integrator
-
(14)
SW-R
SW+R
+
+
Comp1
-
Level
Shift
Comp2
+
COUT
(17)
SWAz
SW+R
AGND
(6)
SWIN
SW-R
SWS
SWAZ
Polarity
Detection
DGND
(18)
SWG
V-IN
(13)
REF
Control
VSS VDD N/C N/C
(3) (19) (10) (9)
Bias
IB
(1)
CB
Analog
Switch
Control
Signals
CS
(20)
Phase
Decoding
Logic
A
B
(15)
(16)
Control Logic
GENERAL DESCRIPTION
GENERAL THEORY OF OPERATION
The ALD500RAU/ALD500RA/ALD500R are integrating
dual slope analog processors, designed to operate on ±5V
power supplies for building precision analog-to-digital
converters. The ALD500RAU/ALD500RA/ALD500R
feature specifications suitable for 18 bit/17 bit/16 bit
resolution conversion, respectively. Together with three
capacitors, two resistors, and a digital controller, a precision
Analog to Digital converter with auto zero can be
implemented. The digital controller can be implemented
by an external microcontroller, under either hardware
(fixed logic) or software control. For ultra high resolution
applications, up to 23 bit conversion can be implemented
with an appropriate digital controller and software.
Dual-Slope Conversion Principles of Operation
The ALD500R series of analog processors accept
differential inputs and the external digital controller first
counts the number of pulses at a fixed clock rate that a
capacitor requires to integrate against an unknown analog
input voltage, then counts the number of pulses required
to deintegrate the capacitor against a known internal
reference voltage. This unknown analog voltage can then
be converted by the microcontroller to a digital word, which
is translated into a high resolution number, representing
an accurate reading. This reading, when ratioed against
the reference voltage, yields an accurate, absolute voltage
measurement reading.
The ALD500R analog processors consist of on-chip digital
control circuitry to accept control inputs, integrating buffer
amplifiers, analog switches, and voltage comparators and
a highly accurate, ultra-stable voltage reference. It
functions in four operating modes, or phases, namely auto
zero, integrate, deintegrate, and integrator zero phases.
At the end of a conversion, the comparator output goes
from high to low when the integrator crosses zero during
deintegration. ALD500R analog processors also provide
direct logic interface to CMOS logic families.
2
The basic principle of dual-slope integrating analog to digital
converter is simple and straightforward. A capacitor, CINT , is
charged with the integrator from a starting voltage, VX, for a
fixed period of time at a rate determined by the value of an
unknown input voltage, which is the subject of measurement.
Then the capacitor is discharged at a fixed rate, based on an
external reference voltage, back to VX where the discharge
time, or deintegration time, is measured precisely. Both the
integration time and deintegration time are measured by a
digital counter controlled by a crystal oscillator. It can be
demonstrated that the unknown input voltage is determined
by the ratio of the deintegration time and integration time, and
is directly proportional to the magnitude of the external reference
voltage.
The major advantages of a dual-slope converter are:
a. Accuracy is not dependent on absolute values of
integration time tINT and deintegration time tDINT, but is
dependent on their relative ratios. Long-term clock frequency
variations will not affect the accuracy. A standard crystal
controlled clock running digital counters is adequate to generate
very high accuracies.
b. Accuracy is not dependent on the absolute values of
RINT and C INT, as long as the component values do not vary
through a conversion cycle, which typically lasts less than 1
second.
c. Offset voltage values of the analog components, such
as VX, are cancelled out and do not affect accuracy.
d. Accuracy of the system depends mainly on the accuracy
and the stability of the voltage reference value.
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
e. Very high resolution, high accuracy measurements
can be achieved simply and at very low cost.
An inherent benefit of the dual slope converter system is noise
immunity. The input noise spikes are integrated (averaged to
near zero) during the integration periods. Integrating ADCs
are immune to the large conversion errors that plague
successive approximation converters and other high resolution
converters and perform very well in high-noise environments.
The slow conversion speed of the integrating converter provides
inherent noise rejection with at least a 20dB/decade attenuation
rate. Interference signals with frequencies at integral multiples
of the integration period are, theoretically, completely removed.
Integrating converters often establish the integration period to
reject 50/60Hz line frequency interference signals.
The relationship of the integrate and deintegrate (charge
and discharge) of the integrating capacitor values are
shown below:
(1)
VX = VINT - (VREF . tDINT / RINT . CINT)
(deintegrate cycle)
(2)
Combining equations 1 and 2 results in:
VIN / VREF = -tDINT / tINT
Actual data conversion is accomplished in two phases: Input
Signal Integration Phase and Reference Voltage Deintegration
Phase.
The integrator output is initialized to 0V prior to the start of
Input Signal Integration Phase. During Input Signal Integration
Phase, internal analog switches connect VIN to the buffer
input where it is maintained for a fixed integration time period
(tINT). This fixed integration period is generally determined by
a digital counter controlled by a crystal oscillator. The
application of VIN causes the integrator output to depart 0V at
a rate determined by VIN and a direction determined by the
polarity of VIN.
The Reference Voltage Deintegration Phase is initiated
immediately after tINT , within 1 clock cycle. During
ReferenceVoltage Deintegration Phase, internal analog
switches connect a reference voltage having a polarity opposite
that of VIN to the integrator input. Simultaneously the same
digital counter controlled by the same crystal oscillator used
above is used to start counting clock pulses. The Reference
Voltage Deintegration Phase is maintained until the comparator
output inside the dual slope analog processor changes state,
indicating the integrator has returned to 0V. At that point the
digital counter is stopped. The Deintegration time period
(tDINT ), as measured by the digital counter, is directly
proportional to the magnitude of the applied input voltage.
VINT = VX - (VIN . tINT / RINT . CINT )
(integrate cycle)
reference voltage is integrated
VREF = Reference Voltage
CINT = Integrating Capacitor value
RINT = Integrating Resistor value
(3)
where:
Vx = An offset voltage used as starting voltage
VINT = Voltage change across CINT during tINT and
during tDINT (equal in magnitude)
VIN = Average, or an integrated, value of input voltage
to be measured during tINT (Constant VIN )
tINT = Fixed time period over which unknown voltage is
integrated
tDINT = Unknown time period over which a known
After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
reset to zero through an Integrator Zero Phase and an Auto
Zero Phase so that the next conversion can begin again. In
practice, this process is usually automated so that analog-todigital conversion is continuously updated. The digital control
is handled by a microprocessor or a dedicated logic controller.
The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.
CINT
RINT
INTEGRATOR
-
ANALOG
INPUT
(VIN)
VINT
-
COMPARATOR
+
S1
VOLTAGE
REFERENCE
REF
SWITCHES
COUT
+
POLARITY
DETECTION
SWITCH DRIVER
PHASE
CONTROL CONTROL
LOGIC
POLARITY CONTROL
INTEGRATOR
OUTPUT
A
VIN ≈ VFULL SCALE
VINT = 4.1V MAX
VIN ≈ 1/2VFULL SCALE
Vx ≈ 0
tDINT
tINT
B
MICROCONTROLLER
(CONTROL LOGIC
+ COUNTER)
tDINT
Figure 2. Basic Dual-Slope Converter
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
3
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
Differential input voltage range
Power dissipation
Operating temperature range PE, SE package
Operating temperature range QE package
Storage temperature range
Lead temperature, 10 seconds
13.2V
-0.3V to V+ +0.3V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25°C V+ = +5V V- = -5V (V supply ± 5V) unless otherwise specified; CAZ = CREF = 0.47µf
500RAU
Parameter
Symbol
Resolution
Typ
500RA
Max
15
Zero-Scale
Error
ZSE
End Point
Linearity
ENL
Best Case
Straight Line
Linearity
NL
Zero-Scale
Temperature
Coefficient
TCZS
Full-Scale
Symmetry Error
(Rollover Error)
SYE
Full-Scale
Temperature
Coefficient
TCFS
Input
Current
IIN
Common-Mode
Voltage Range
Min
Min
Typ
Min
30
0.001
Typ
Max
Unit
Test Conditions
µV
Notes 1, 7
0.005
0.008
%
%
0°C to 70°C
60
0.0025
0.003
0.003
0.005
0.005
0.007
0.003
0.010
0.015
0.005
0.015
0.020
%
Notes 1, 2
0°C to +70°C
0.0025
0.003
0.005
0.003
0.008
%
Notes 1, 2
0.004
CMVR VSS+1.5
500R
Max
0.008
0.015
0.3
0.6
0.3
0.7
0.3
0.7
0.15
0.3
0.15
0.35
0.15
0.35
0°C to +70°C
µV/°C
0°C to +70°C
ppm/°C
Notes 1, 7
0°C to 70°C
0.005
0.008
0.01
%
0.008
0.010
0.012
%
1.3
1.3
1.3
2
2
2
ppm/°C
0°C to +70°C
Note 7
pA
VIN = 0V
VDD-1.5 V SS+1.5
VDD-1.5 VSS+1.5
VDD-1.5
V
Integrator
Output Swing
VINT
VSS+0.9
VDD-0.9 V SS+0.9
VDD-0.9 VSS+0.9
VDD-0.9
V
Analog Input
Signal Range
VIN
VSS+1.5
VDD-1.5 V SS+1.5
VDD-1.5 VSS+1.5
VDD-1.5
V
Voltage
Reference
Range
VREF
VDD-1
V
4
VSS+1
VDD-1
VSS+1
VDD-1 VSS+ 1
Advanced Linear Devices
AGND = 0V
ALD500RAU/ALD500RA/ALD500R
DC & AC ELECTRICAL CHARACTERISTICS
TA = 25°C V supply = ±5.0V unless otherwise specified; CAZ = CREF = 0.47µf
500RAU
Parameter
Symbol
Min
Typ
500RA
Max
0.6
Min
Typ
1.0
500R
Max
0.6
Min
Typ
Unit
Test Conditions
1.0
mA
V+ = 5V , A =1,B=1
10
mW
V supply= ±5V
4.5
5.5
V
Note 4
-4.5
-5.5
V
Note 4
V
ISOURCE = 400µA
V
ISINK = 1.1mA
1.0
IS
Power Dissipation
PD
Positive Supply Range
V+S
4.5
5.5
4.5
5.5
Negative Supply Range
V-S
-4.5
-5.5
-4.5
-5.5
Comparator Logic 1,
Output High
VOH
Comparator Logic 0,
Output Low
VOL
Logic 1, Input High
Voltage
VIH
Logic 0, Input Low
Voltage
VIL
Logic Input Current
IL
0.01
0.01
0.01
Comparator Delay
tD
1
1
1
10
10
4
4
4
0.4
3.5
Max
0.6
Supply Current
0.4
3.5
0.4
3.5
1
V
1
1
V
µA
µsec
Note 5
Figure 3. ALD500R TIMING DIAGRAM
1 Conversion Cycle
~
~
~
~
~
~
1.8432 MHz Clock
123,093
Clock Pulses
~
~
0.5416 µs
123,093
Clock Pulses
~
~
~
~
66.667 msec.
A INPUT
~
~
66.667 msec.
COUT
Positive Input Signal
NOT VALID
COUT
Negative Input Signal
NOT VALID
START
CONVERSION
CYCLE
~
~
~
~
B INPUT
Auto Zero
Phase
Input Signal
Integration
Phase
Reference
Voltage
Deintegration
Phase
Integrator Zero
Phase
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed number
of clock pulses
by design.
Variable
number of
clock pulses.
Fixed period of
approx.1 msec.
At VIN MAX,
max. number of
clock pulses
~ 246,185
=
Auto Zero
Phase
Stop counter upon
detection of comparator
output going from high
to low state.
REPEAT
CONVERSION
CYCLE
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
START INTEGRATOR ZERO CYCLE
5
DC ELECTRICAL CHARACTERISTICS
TA = 25°C V supply = +5.0V unless otherwise specified; CAZ = CREF = 0.47µf, RREF = 100KΩ (1% metal film)
Parameter
Symbol
Min
0.998
500RAU-10
500RAU-20
500RA-10
500RA-20
Typ
Max
Min
Typ
1.000
1.002
0.997
1.000
Voltage Reference
VR
Supply Voltage
Rejection Ratio
VRSR
95
Temperature
Coefficient
VRTC
3
Long Term Drift
∆VREF /
∆t
Warm Up Time
500RAU-50
Max
1.003
0.995
95
10
Unit
1.000
1.005
95
7
20
-0.08
-0.08
10
10
10
V
dB
15
-0.08
50
ppm/C°
ppm/
1000hrs
Note 7
min.
Note 7
Positive Supply
Operating Voltage Range
V+
4.5
5.5
4.5
5.5
4.5
5.5
V
Negative Supply
Operating Voltage Range
V-
-5.5
-4.5
-5.5
-4.5
-5.5
-4.5
V
Power Down Supply
Current
IPD
25
25
Test Conditions
500RA-50
500R-50
Min
Typ
Max
µA
25
Note 7
NOTES:
1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., VINT = 4V, VIN = 2.0V Full Scale
Resolution = VINT /integrate time/clock period
2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on CINT, CREF , CAZ characteristics.
~
4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27µsec, 0.54µsec, or 1.09µsec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
6. RREF is 100K Ω 1% metal film, 50 ppm/C.
7. Sample tested parameter.
6
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
PIN DESCRIPTION
Pin No.
Symbol
Description
1
IB
Bias circuit pin. Connect a 0.1µF capacitor from this pin to V- to minimize noise.
2
CINT
Integrator capacitor connection.
3
V-
Negative power supply.
4
CAZ
The Auto-zero capacitor connection.
5
BUF
The Integrator resistor buffer connection.
6
AGND
This pin is analog ground.
7
C-REF
Negative reference capacitor connection.
8
C+REF
Positive reference capacitor connection.
9
N/C
Internally connected. Connect to V- for normal operation.
10
N/C
Internally connected. Connect to V- for normal operation.
11
V-REF
External voltage reference (-) connection. High impedance load (≥100MΩ) only.
12
V+ REF
External voltage reference (+) connection. High impedance load (≥100MΩ) only.
13
V-IN
Negative analog input.
14
V+ IN
Positive analog input.
15
A
Converter phase control MSB Input.
16
B
Converter phase control LSB Input.
17
COUT
Comparator output. COUT is HIGH during the Integration phase when a positive input voltage is being integrated and
is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on COUT signals the processor
that the Deintegrate phase is completed. COUT is undefined during the Auto-Zero phase. It should be monitored to
time the Integrator Zero phase.
18
DGND
Digital ground.
19
V+
Positive power supply.
20
CS
Chip select - power down pin. Logic 1 = power on. Logic 0 = power down.
Table 1. Conversion Phase and Control Logic Internal Analog Switch Functions
Switch Functions
Conversion
Phase
Input
Connect
Reference Input
Polarity
SWIN
SW+R or SW- R
Auto Zero
Reference
Sample
VIN=AGND
System
Offset
SWAZ
SWR
SWG
SWS
Control
Logic
Auto Zero
A = 0, B = 1
Open
Open
Closed
Closed
Closed
Open
Input Signal
Integration
A = 1, B = 0
Closed
Open
Open
Open
Open
Open
Reference Voltage
Deintegration
A = 1, B = 1
Open
Closed*
Open
Open
Closed
Open
Integrator
Output Zero
A = 0, B = 0
Open
Open
Open
Closed
Closed
Closed
*SW+R would be closed for a positive input signal. SW-R would be closed for a negative input signal.
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
7
ALD500RAU/ALD500RA/ALD500R CONVERSION CYCLE
The ALD500RAU/ALD500RA/ALD500R conversion cycle
takes place in four distinct phases, the Auto Zero Phase, the
Input Signal Integration Phase, the Reference Voltage
Deintegration Phase, and the Integrator Zero Phase. A typical
measurement cycle uses all four phases in an order sequence
as mentioned above. The internal analog switch status for
each of these phases is summarized in Table 1.
time and depends on system parameters and component
value selections. The total number of clock pulses or clock
counts, during integration phase determine the resolution of
the conversion. For high resolution applications, this total
number of clock pulses should be maximized. The basic unit
of resolution is in µV/count. Before the end of this phase,
comparator output is sampled by the microcontroller. This
phase is terminated by changing logic inputs AB from 10 to 11.
Reference Voltage Deintegration Phase (DINT Phase)
The following is a detailed description of each one of the four
phases of the conversion cycle.
Auto Zero Phase (AZ Phase)
The analog-to-digital conversion cycle begins with the Auto
Zero Phase, when the digital controller applies low logic level
to input A and high logic level to input B of the analog
processor. During this phase, the reference voltage is stored
on reference capacitor CREF, comparator offset voltage and
the sum of the buffer and integrator offset voltages are stored
on auto zero capacitor CAZ. During the Auto Zero Phase, the
comparator output is characterized by an indeterminate
waveform.
During the Auto Zero Phase, the external input signal is
disconnected from the internal circuitry of the ALD500RAU/
ALD500RA/ALD500R by opening the two SW IN analog
switches and connecting the internal input nodes internally to
analog ground. A feedback loop, closed around the integrator
and comparator, charges the C AZ capacitor with a voltage to
compensate for buffer amplifier, integrator and comparator
offset voltages.
This is the system initialization phase, when a conversion is
ready to be initiated at system turn-on. In practice the
converter can be operated in continuous conversion mode,
where AZ phase must be long enough for the circuit conditions
to settle out any system errors. Typically this phase is set to
be equal to tINT.
Input Signal Integration Phase (INT Phase)
During the Input Signal Integration Phase (INT), the
ALD500RAU/ALD500RA/ALD500R integrates the differential
voltage across the (V +IN) and (V-IN) inputs. The differential
voltage must be within the device's common-mode voltage
range CMVR. The integrator charges CINT for a fixed period
of time, or counts a fixed number of clock pulses, at a rate
determined by the magnitude of the input voltage. During this
phase, the analog inputs see only the high impedance of the
noninverting operational amplifier input of the buffer. The
integrator responds only to the voltage difference between the
analog input terminals, thus providing true differential analog
inputs.
The input signal polarity is determined by software control at
the end of this phase: COUT = 1 for positive input polarity;
COUT = 0 for negative input polarity. The value is, in effect, the
sign bit for the overall conversion result.
At the end of the Input Signal Integration Phase, Reference
Voltage Deintegration Phase begins. The previously charged
reference capacitor is connected with the proper polarity to
ramp the integrator output back to zero. The ALD500RAU/
ALD500RA/ALD500R analog processors automatically selects
the proper logic state to cause the integrator to ramp back
toward zero at a rate proportional to the reference voltage
stored on the reference capacitor. The time required to return
to zero is measured by the counter in the digital processor
using the same crystal oscillator. The phase is terminated by
the comparator output after the comparator senses when the
integrator output crosses zero. The counter contents are then
transferred to the register. The resulting time measurement
is proportional to the magnitude of the applied input voltage.
The duration of this phase is precisely measured from the
transition of AB from 10 to 11 to the falling edge of the
comparator output, usually with a crystal controlled digital
counter chain. The comparator delay contributes some error
in this phase. The typical comparator delay is 1µsec . The
comparator delay and overshoot will result in error timing,
which translates into error voltages. This error can be zeroed
and minimized during Integrator Output Zero Phase and
corrected in software, to within ±1 count of the crystal clock
(which is equivalent to within ± 1 LSB, when 1 clock pulse = 1
LSB).
Integrator Zero Phase ( INTZ Phase)
This phase guarantees the integrator output is at 0V when the
Auto Zero phase is entered, and that only system offset
voltages are compensated. This phase is used at the end of
the reference voltage deintegration and is used for applications
with high resolutions. If this phase is not used, the value of the
Auto-Zero capacitor (CAZ) must be much greater than the
value of the integration capacitor (CINT) to reduce the effects
of charge-sharing. The Integrator Zero phase should be
programmed to operate until the Output of the Comparator
returns "HIGH". A typical Integrator Zero Phase lasts 1msec.
The comparator delay and the controller's response latency
may result in Overshoot causing charge buildup on the
integrator at the end of a conversion. This charge must be
removed or performance will degrade. The Integrator Output
Zero phase should be activated (AB = 00) until COUT goes
high. At this point, the integrator output is near zero. Auto Zero
Phase should be entered (AB = 01) and the ALD500RAU/
ALD500RA/ALD500R is held in this state until the next
conversion cycle.
The duration of this phase is selected by design to be a fixed
8
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
Differential Inputs (V+IN ,V-IN)
The ALD500RAU/ALD500RA/ALD500R operates with
differential voltages within the input amplifier common-mode
voltage range. The amplifier common-mode range extends
from 1.5V below positive supply to 1.5V above negative
supply. Within this common-mode voltage range, commonmode rejection is typically 95dB.
The integrator output also follows the common-mode voltage.
When large common-mode voltages with near full-scale
differential input voltages are applied, the input signal drives
the integrator output to near the supply rails where the
integrator output is near saturation. Under such conditions,
linearity of the converter may be adversely affected as the
integrator swing can be reduced. The integrator output must
not be allowed to saturate. Typically, the integrator output can
swing to within 0.9V of either supply rails without loss of
linearity.
Analog Ground
Analog Ground is V-IN during Auto Zero Phase and Reference
Voltage Deintegration Phase. If V-IN is different from analog
ground, a common-mode voltage exists at the inputs. This
common mode signal is rejected by the high common mode
rejection ratio of the converter. In most applications, V-IN is
set at a fixed known voltage (i.e., power supply ground). All
other ground connections should be connected to digital
ground in order to minimize noise at the inputs.
Differential Reference (V+REF, V-REF)
The reference voltage can be anywhere from 1V of the power
supply voltage rails of the converter. Roll-over error is caused
by the reference capacitor losing or gaining charge due to the
stray capacitance on its nodes. The difference in reference for
(+) or (-) input voltages will cause a roll-over error. This error
can be minimized by using a large reference capacitor in
comparison to the stray capacitance.
Phase Control Inputs (A, B)
The A and B logic inputs select the ALD500RAU/ALD500RA/
ALD500R operating phase. The A and B inputs are normally
driven by a microprocessor I/O port or external logic, using
CMOS logic levels. For logic control functions of A and B logic
inputs, see Table 1.
Comparator Output (COUT)
By monitoring the comparator output during the Input Signal
Integration Phase, which is a fixed signal integrate time
period, the input signal polarity can be determined by the
microcontroller controlling the conversion. The comparator
output is HIGH for positive signals and LOW for negative
signals during the Input Signal Integration Phase. The state of
the comparator should be checked by the microcontroller at
the end of the Input Signal Integration Phase, just before
transition to the Reference Voltage Deintegration Phase. For
very low level input signals noise may cause the comparator
output state to toggle between positive and negative states.
For the ALD500RAU/ALD500RA/ALD500R, this noise has
been minimized to typically within one count.
At the start of the Reference Voltage Deintegration Phase,
comparator output is set to HIGH state. During the Reference
Voltage Deintegration Phase, the microcontroller must monitor
the comparator output to make a HIGH-to-LOW transition as
the integrator output ramp crosses zero relative to analog
ground. This transition indicates that the conversion is
complete. The microcontroller then stops and records the
pulse count. The internal comparator delay is 1µsec, typically.
The comparator output is undefined during the Auto Zero
Phase.
Positive Input Signal (VIN)
0V
Negative Input Signal (VIN)
ANALOG INPUT
INTEGRATE
ANALOG INPUT
INTEGRATE
INTEGRATOR
OUTPUT
(VINT)
EXTERNAL INPUT
POLARITY DETECTION
COMPARATOR
OUTPUT
(COUT)
REFERENCE
DEINTEGRATE
REFERENCE
DEINTEGRATE
INTEGRATOR
OUTPUT
(VINT)
ZERO
CROSSING
ZERO
CROSSING
EXTERNAL INPUT
POLARITY DETECTION
COMPARATOR
OUTPUT
(COUT)
Figure 4. Comparator Output
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
9
where:
APPLICATIONS AND DESIGN NOTES
Determination and Selection of System Variables
The procedure outlined below allows the user to determine the
values for the following ALD500RAU/ALD500RA/ALD500R
system design variables:
(1)
(2)
(3)
(4)
(5)
(6)
Determine Input Voltage Range
Clock Frequency and Resolution Selection
Input Integration Phase Timing
Integrator Timing Components (RINT, CINT)
Auto Zero and Reference Capacitors
Voltage Reference
System Timing
Figure 3 and Figure 4 show the overall timing for a typical
system in which ALD500RAU/ALD500RA/ALD500R is
interfaced to a microcontroller. The microcontroller drives the
A, B inputs with I/O lines and monitors the comparator output,
COUT , using an I/O line or dedicated timer-capture control pin.
It may be necessary to monitor the state of the comparator
output in addition to having it control a timer directly during the
Reference Deintegration Phase.
There are four critical timing events: sampling the input
polarity; capturing the deintegration time; minimizing overshoot
and properly executing the Integrator Output Zero Phase.
VIN MAX = Maximum input voltage desired
(full count voltage)
RINT
= Integrating Resistor value
For minimum noise and maximum linearity, RINT should be in
the range of between 50kΩ to 150kΩ .
Integrating Capacitor (CINT)
The integrating capacitor should be selected to maximize
integrator output voltage swing VINT, for a given integration
time, without output level saturation. For +/-5V supplies,
recommended VINT range is between +/- 3 Volt to +/-4 Volt.
Using the 20µA buffer maximum output current, the value of
the integrating capacitor is calculated as follows:
CINT = (tINT ) . (20 x 10-6) / VINT
where: tINT =
VINT =
Input Integration Phase Period
Maximum integrator output
voltage swing
It is critical that the integrating capacitor must have a very low
dielectric absorption, as charge loss or gain during conversion
directly converts into an error voltage. Polypropylene capacitors
are recommended while Polyester and Polybicarbonate
capacitors may also be used in less critical applications.
Reference (CREF) and Auto Zero (CAZ) Capacitors
Selecting Input Integration Time
For maximum 50/60 cycle noise rejection, Input Integration
Time must be picked as a multiple of the period of line
frequency. For example, tINT times of 33msec, 66msec and
100 msec maximize 60Hz line rejection, and 20msec, 40
msec, 80msec, and 100 msec maximize 50Hz line rejection.
Note that tINT of 100 msec maximizes both 60 Hz and 50Hz
line rejection.
The duration of the Reference Deintegrate Phase (DINT) is a
function of the amount of voltage charge stored on the
integrator capacitor during INT phase, and the value of VREF.
The D INT phase must be initiated immediately following INT
phase and terminated when an integrator output zero-crossing
is detected. In general, the maximum number of counts
chosen for DINT phase is twice to three times that of INT phase
with V REF chosen as a maximum voltage relative to VIN . For
example, VREF = VIN(max)/2 would be a good reference
voltage.
Integrating Resistor (RINT )
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The buffer and
integrator amplifiers each have a full-scale current of 20µA.
The value of RINT is therefore directly calculated as follows:
= VIN MAX / 20 µA
Calculate VREF
The reference deintegration voltage is calculated using:
VREF = (VINT) . (CINT ) . (RINT) / 2(tINT)
INT and DINT Phase Timing
RINT
C REF and CAZ must be low leakage capacitors (e.g.
polypropylene types). The slower the conversion rate, the
larger the value CREF must be. Recommended capacitor
values for CREF and C AZ are equal to CINT. Larger values for
CAZ and CREF may also be used to limit roll-over errors.
The ALD500RAU/ALD500RA/ALD500R requires an external
RREF in order to operate properly. This R REF should be a 1%
metal film 100KΩ resistor, 50 ppm/C. Any other loading must
be high impedance (≥100MΩ).
Converter Noise
The converter noise is the total algebraic sum of the integrator
noise and the comparator noise. This value is typically 14 µV
peak to peak. The higher the value of the reference voltage,
the lower the converter noise. Such sources of noise errors
can be reduced by increased integration times, which effectively
filter out any such noise. If the integration time periods are
selected as multiples of 50/60Hz frequencies, then 50/60Hz
noise is also rejected, or averaged out. The signal-to-noise
ratio is related to the integration time (tINT ) and the integration
time constant (RINT) (CINT) as follows:
S/N (dB) = 20 Log ((VINT / 14 x 10-6) . tINT /(RINT . CINT))
This converter noise can also be reduced by using multiple
samples and mathematically averaged. For example, taking
16 samples and averaging the readings result in a mathematical
(by software) filtering of noise to less than 4µV.
10
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
EQUATIONS AND DERIVATIONS
Dual Slope Analog Processor equations and derivations
are as follows:
tINT
.t
1
V
(1)
VIN(t)dt = REF DINT
.
RINT CINT 0
RINT . CINT
For VIN(t) = VIN (constant):
∫
CINT =
(2)
(2a)
tINT . IB
VINT
VIN
IB
=
(3)
VINMAX
IBMAX
(4)
= 4 x 16.6667 msec.
2. Pick tINT = 4x
60Hz
= 66.6667ms
3. Pick clock period = 1.08507 µs and number of counts
over tINT =
0.0666667 = 61440
1.08507x10-6
4. Pick VINMAX value, e.g., VINMAX = 2.0 V
I BMAX = 20µA
(5a)
6. Pick CREF and CAZ ≥ CINT: CREF ~=CAZ ~= 0.33 µF
7. Pick tDINT = 2 x tINT = 133.3333 msec
VIN MAX . tINT
tDINT MAX
(5b)
8. Calculate VREF =
CINT . VINT
IBMAX =
VINMAX
RINT
VINTMAX . CINT . RINT
tDINT MAX
V
(6)
-6
3
= 4 x 0.33 x 10 x 100 x 10
133.3333 x 10-3
(7)
~ 1.00V
=
IB
and
2.0
= 100 kΩ
20x10-6
5. Applying equation (3) to calculate CINT:
Rearranging equations (3) and (4):
tINT =
RINT =
CINT = (0.0666667)(20x10-6)/4 where VINT = 4.0V
~= 0.33 µF
From equation (2a),
VIN . tINT
VREF =
tDINT
OR
VREF =
1. Pick resolution = 16 bit.
= 0.0666667 sec.
tDINT
tINT
At VINMAX, the current IB is also at a maximum level,
for a given RINT value:
RINT =
Design Example 1:
1
.t
V
tINT . VIN = REF DINT
RINT . CINT
RINT . CINT
1
... VIN = VREF .
DESIGN EXAMPLES
We now apply these equations in the following
design examples.
V
At VINT = VINT MAX, equation (6) becomes:
.
tINT = CINT VINTMAX
IBMAX
(6a)
1. Select resolution of 17 bit. Total number of
counts during tINT is131,072.
Combining (6a) and (7):
.
.
... tINT = CINT VINTMAX RINT
VINMAX
(8)
In equation (5b), substituting equation (8) for tINT:
CINT . VINTMAX . RINT
VREF =
=
VIN MAX .
VIN MAX
tDINT MAX
Design Example 2:
(9)
2. We can pick tINT of 16.6667 msec. x 5 = 83.3333 msec.
or alternately, pick t INT equal
16.6667 msec. x 6 = 100.00 msec.
(for 60 Hz rejection)
which is t INT = 20.00 msec. x 5
= 100.00 msec. (for 50 Hz rejection)
CINT . VINTMAX . RINT
Therefore, using t INT = 100 msec. would achieve
both 50 Hz and 60 Hz cycle noise rejection. For this
example, the following calculations would assume
t INT of 100 msec. Now select period equal to
0.5425 µsec. (clock frequency of 1.8432 MHz)
tDINT MAX
For tDINT MAX = 2 x tINT,
equation (9) becomes:
VREF =
CINT . VINTMAX . RINT
(10)
2tINT
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
11
3. Pick VINMAX = ±2V
Design Example 4:
Objective: 5 1/2 digit + sign +over-range measurement.
For I BMAX = 20µA, applying equation (4),
RINT =
1. Pick tINT = 133.333 msec. for 60Hz noise rejection.
(16.6667 msec. x 8 cycles)
Frequency = 1.8432 MHz
clock period = 0.5425 µsec.
2
= 100 K Ω
20x10-6
4. Calculate, using equation (3) for CINT:
CINT = (0.1) x (20 x 10-6/4)
~ = 0.5 µF
(assume V
INTMAX = 4V)
During Input Integrate Phase,
total count = 133.333 x 10-3
0.5425 x 10-6
Use CINT 0.47µF as the closest practical value.
= 245776
5. Pick CREF and CAZ = 0.47 µF
For VINT = 4.0V, the basic resolution is
6. Pick tDINT = 2 x tINT = 200 msec.
4
or 16.276 µV/count
245776
7. Calculate the value for VREF, from equation (10):
For VINMAX = 2.00V, the input resolution is
16.276 x VINMAX = 8.138 µV/count
VINTMAX
VREF = CINT . VINTMAX . RINT
tDINT MAX
=
0.5 x 10-6 x 4 x 100 x 103
2. Pick VIN range = ± 2V
200 x 10-3
2
= 100 KΩ
For IB = 20 µA, RINT =
20 x 10-6
= 1.00V
3. Calculate CINT = (0.133333) x (20 x 10-6)/4 ~= 0.67 µF
Design Example 3:
4. Pick CREF = CAZ = 0.67 µF
1. Pick resolution of 18 bit. Total number of counts during
tINT is 262,144.
2. Pick tINT = 16.66667 msec. x 10 cycles
5. Select tDINT = 2 x tINT = 266.667 msec.
6. Calculate VREF as shown in Design Example 1,
substituting the appropriate values:
= 0.1666667 sec.
This t INT allows clock period of 0.5425 µsec.
and still achieve 18 bits resolution.
VREF =
CINT . VINTMAX . RINT
tDINT MAX
~
= 1.005V
3. Again, as shown from previous example, pick VINMAX = ±2V
For I BMAX = 20 µA, RINT =
2
= 100 KΩ
20x10-6
4. Next, we calculate CINT:
C INT = (0.1666667) x (20 x 10-6)/4
~ 0.83 µF
(VINTMAX = 4.0V)
=
In this case, use CINT = 1.0 µF to keep
V INT < 4.0V
5. Pick CREF and CAZ = 1.0 µF
6. Select tDINT = 2 x tINT = 333.333 msec.
7. Calculate VREF as shown in the previous examples
and VREF = 1.00V
12
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
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