Product Folder Order Now Support & Community Tools & Software Technical Documents OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 OPA164x-Q1 SoundPlus™ JFET-Input, Automotive-Grade, Audio Operational Amplifiers 1 Features 3 Description • • The OPA1641-Q1 (single) and OPA1642-Q1 (dual) series are JFET-input, ultra-low distortion, low-noise operational amplifiers (op amps) fully specified for audio applications. 1 • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 Low Noise: 5.1 nV/√Hz at 1 kHz Ultra-low Distortion: 0.00005% at 1 kHz High Slew Rate: 20 V/μs Unity Gain Stable No Phase Reversal Low Quiescent Current: 1.8 mA per Channel Rail-to-Rail Output Wide Supply Range: ±2.25 V to ±18 V Single, Dual, and Quad Versions Available The rail-to-rail output swing allows increased headroom, making these devices ideal for use in any audio circuit. Features include 5.1-nV/√Hz noise, low total harmonic distortion + noise (THD+N) (0.00005%), a low input bias current of 2 pA, and low quiescent current of 1.8 mA per channel. These devices operate over a very wide supply voltage range of ±2.25 V to ±18 V. The OPA164x-Q1 series of operational amplifiers are unity-gain stable and provide excellent dynamic behavior over a wide range of load conditions. The dual version features completely independent circuitry for lowest crosstalk and freedom from interactions between channels, even when overdriven or overloaded. 2 Applications • • • • • Device Information(1) PART NUMBER Automotive HEV and EV Power Train Advanced Driver Assist (ADAS) Infotainment Systems In-Cabin Microphones PACKAGE OPA1641-Q1 OPA1642-Q1 BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.90 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.90 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space Simplified Internal Schematic Extremely Stable Input Capacitance 7.5 Pre-Output Driver IN– OUT IN+ V– Copyright © 2017 Texas Instruments Inc. Common-Mode Capacitance (pF) V+ 7 Traditional JFET-Input Amplifier 6.5 OPA164x Family 6 5.5 5 4.5 4 –10 –8 –6 –4 –2 0 2 4 6 8 10 Common-Mode Voltage (V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8 8.1 Application Information............................................ 16 8.2 Typical Application ................................................. 21 9 Power Supply Recommendations...................... 23 10 Layout................................................................... 24 10.1 Layout Guidelines ................................................. 24 10.2 Layout Example .................................................... 24 11 Device and Documentation Support ................. 25 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Application and Implementation ........................ 16 12 12 13 15 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 26 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History 2 DATE REVISION NOTES June 2017 * Initial release Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 5 Pin Configuration and Functions OPA1641-Q1: D and DGK Packages 8-Pin SOIC and VSSOP Top View NC (1) (1) 1 8 NC (1) –IN 2 – 7 V+ +IN 3 + 6 OUT V– 4 5 NC (1) NC - no internal connection Pin Functions: OPA1641-Q1 PIN NAME NO. I/O DESCRIPTION –IN 2 I Inverting input +IN 3 I Noninverting input NC 1, 5, 8 — No connection OUT 6 O Output V– 4 — Negative (lowest) power supply V+ 7 — Positive (highest) power supply OPA1642-Q1: D and DGK Packages 8-Pin SOIC and VSSOP Top View +IN A 3 V– 4 B – 2 + A – –IN A 1 + OUT A 8 V+ 7 OUT B 6 –IN B 5 +IN B Pin Functions: OPA1642-Q1 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) power supply V+ 8 — Positive (highest) power supply Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 3 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VS MAX UNIT 40 V Supply voltage (2) VIN Input voltage IIN Input current (2) (V–) – 0.5 (V+) + 0.5 V ±10 mA ±VS V VIN(DIFF) Differential input voltage (3) IO Output short-circuit TA Operating temperature –55 125 °C TJ Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) Continuous Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current-limited to 10 mA or less. The input voltage and output negative-voltage ratings can be exceeded if the input and output current ratings are followed. Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±3000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage (V+, V–) Single supply Dual supply NOM MAX 4.5 36 ±2.25 ±18 –40 125 Specified temperature UNIT V °C 6.4 Thermal Information OPA1641-Q1, OPA1642-Q1 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) 8 PINS 8 PINS UNIT 180 °C/W RθJA Junction-to-ambient thermal resistance 160 RθJC(top) Junction-to-case (top) thermal resistance 75 55 °C/W RθJB Junction-to-board thermal resistance 60 130 °C/W ψJT Junction-to-top characterization parameter 9 n/a °C/W ψJB Junction-to-board characterization parameter 50 120 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 6.5 Electrical Characteristics at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO PERFORMANCE THD+N IMD Total harmonic distortion + noise Intermodulation distortion 0.00005% G = 1, f = 1 kHz, VO = 3 VRMS –126 SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz), G = 1, VO = 3 VRMS 0.00004% DIM 30 (3-kHz square wave and 15-kHz sine wave), G = 1, VO = 3 VRMS 0.00008% CCIF twin-tone (19 kHz and 20 kHz), G = 1, VO = 3 VRMS 0.00007% dB –128 dB –122 dB –123 dB FREQUENCY RESPONSE GBW Gain-bandwidth product G=1 11 SR Slew rate G=1 20 V/μs Full-power bandwidth (1) VO = 1 VP 3.2 MHz Overload recovery time (2) G = –10 Channel separation (dual and quad) f = 1 kHz MHz 600 ns –126 dB NOISE Input voltage noise f = 20 Hz to 20 kHz 4.3 f = 10 Hz en Input voltage noise density In Input current noise density μVPP 8 f = 100 Hz 5.8 f = 1 kHz 5.1 f = 1 kHz 0.8 nV/√Hz fA/√Hz OFFSET VOLTAGE VOS Input offset voltage VS = ±18 V PSRR VOS vs power supply VS = ±2.25 V to ±18 V 1 3.5 0.14 2 mV μV/V INPUT BIAS CURRENT IB Input bias current VCM = 0 V ±2 ±20 pA IOS Input offset current VCM = 0 V ±2 ±20 pA (V+) – 3.5 V INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio (V–) – 0.1 VCM = (V–) – 0.1 V to (V+) – 3.5 V, VS = ±18 V 120 126 dB INPUT IMPEDANCE 1013 || 8 Differential Common-mode 13 VCM = (V–) – 0.1 V to (V+) – 3.5 V 10 || 6 Ω || pF Ω || pF OPEN-LOOP GAIN AOL (1) (2) Open-loop voltage gain (V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V, RL = 10 kΩ 120 134 (V–) + 0.35 V ≤ VO ≤ (V+) – 0.35 V, RL = 2 kΩ 114 126 dB Full power bandwidth = SR / (2π × VP), where SR = slew rate. See Figure 19 and Figure 20. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 5 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Electrical Characteristics (continued) at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing from rail IOUT Output current ZO Open-loop output impedance ISC Short-circuit current CLOAD Capacitive load drive RL = 10 kΩ, AOL ≥ 120 dB (V–) + 0.2 (V+ )– 0.2 RL = 2 kΩ, AOL ≥ 114 dB (V–) + 0.35 (V+) – 0.35 V See Typical Characteristics See Typical Characteristics Source 36 Sink mA –30 See Typical Characteristics POWER SUPPLY VS Specified voltage ±2.25 IQ Quiescent current (per amplifier) IOUT = 0 A 1.8 ±18 V 2.3 mA TEMPERATURE RANGE 6 Specified range –40 125 °C Operating range –55 125 °C Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 6.6 Typical Characteristics at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 100 nV/div Voltage Noise Density (nV/ÖHz) 100 10 1 0.1 1 10 100 1k 10k 100k Time (1 s/div) Frequency (Hz) Figure 2. 0.1-Hz to 10-Hz Noise Figure 1. Input Voltage Noise Density vs Frequency 35 160 25 Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) Output Voltage (VPP) Maximum Output Voltage Range Without Slew-Rate Induced Distortion VS = ±15 V 30 20 15 VS = ±5 V 10 VS = ±2.25 V 5 0 140 CMRR 120 100 –PSRR 80 +PSRR 60 40 20 0 10k 100k 1M 10M 1 10 100 1k Frequency (Hz) 10k 100k 1M 10M 100M Frequency (Hz) Figure 3. Maximum Output Voltage vs Frequency 140 Figure 4. CMRR and PSRR vs Frequency (Referred to Input) 30 180 120 Gain 20 135 90 60 40 Gain (dB) 80 G = +10 Phase (°) Gain (dB) 100 10 G = +1 0 Phase 45 20 –10 G = –1 0 -20 50 100 1k 10k 100k 1M 10M 0 100M –20 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure 5. Gain and Phase vs Frequency Figure 6. Closed-Loop Gain vs Frequency Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 7 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Typical Characteristics (continued) G = –1 RL = 600 Ω 0.0001% –120 G = +1 RL = 2 kΩ 10 100 1k 10k 0.001% G = +1 RL = 600 Ω –120 0.0001% G = +1 RL = 2 kΩ 10 20k 100 1k VOUT = 3 VRMS BW = 80 kHz –120 0.0001% G = –1, RL = 2 kΩ G = +1, RL = 2 kΩ –140 1 10 0.01% Intermodulation Distortion –100 0.001% Total Harmonic Distortion + Noise (dB) Total Harmonic Distortion + Noise –80 0.1 BW > 500 kHz Figure 8. THD+N Ratio vs Frequency Figure 7. THD+N Ratio vs Frequency 0.01% 0.00001% -80 SMPTE/DIN Two-Tone 4:1 (60 Hz and 7 kHz) 0.001% -100 DIM30 (3 kHz Square Wave and 15 kHz Sine Wave) -120 0.0001% CCIF Twin-Tone (19 kHz and 20 kHz) -140 0.00001% 20 0.1 1 Output Amplitude (VRMS) BW = 80 kHz –140 100k 10k Frequency (Hz) Frequency (Hz) VOUT = 3 VRMS –100 G = –1 RL = 2 kΩ 0.00001% –140 0.00001% G = –1 RL = 600 Ω Total Harmonic Distortion + Noise (dB) G = +1 RL = 600 Ω –80 0.01% Intermodulation Distortion (dB) Total Harmonic Distortion + Noise G = –1 RL = 2 kΩ Total Harmonic Distortion + Noise –100 0.001% Total Harmonic Distortion + Noise (dB) at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 10 20 Output Amplitude (VRMS) 1 kHz Signal RSOURCE = 0 Ω G=1 Figure 9. THD+N Ratio vs Output Amplitude Figure 10. Intermodulation Distortion vs Output Amplitude –90 Output –100 RL = 600 Ω 5 V/div Channel Separation (dB) –80 –110 –120 +18 V RL = 2 kΩ OPA1641-Q1 Output –130 -18 V 37 VPP Sine Wave (±18.5 V) RL = 5 kΩ –140 10 100 1k 10k 100k Frequency (Hz) VS = ±15 V VOUT = 3 VRMS Time (0.4 ms/div) G=1 Figure 11. Channel Separation vs Frequency 8 Figure 12. No Phase Reversal Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 Typical Characteristics (continued) 20 mV/div 20 mV/div at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) +15 V OPA1641-Q1 -15 V RL RI = 2 kW RF = 2 kW +15 V OPA1641-Q1 CL CL -15 V Time (100 ns/div) Time (100 ns/div) G=1 G = –1 CL = 100 pF CL = 100 pF Figure 14. Small-Signal Step Response (100 mV) 2 V/div 2 V/div Figure 13. Small-Signal Step Response (100 mV) Time (400 ns/div) Time (400 ns/div) G=1 CL = 100 pF G = –1 Figure 15. Large-Signal Step Response CL = 100 pF Figure 16. Large-Signal Step Response VOUT 5 V/div 5 V/div VIN 20 kW 20 kW 2 kW VIN 2 kW OPA1641-Q1 VOUT OPA1641-Q1 VIN VOUT VIN VOUT Time (0.4 ms/div) Time (0.4 ms/div) G = –10 G = –10 Figure 17. Positive Overload Recovery Figure 18. Negative Overload Recovery Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 9 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Typical Characteristics (continued) at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 40% 45% ROUT = 0 W 35% RI = 2 kW +15 V 40% ROUT +15 V OPA1641-Q1 RL -15 V ROUT 35% CL OPA1641-Q1 CL 30% 25% Overshoot Overshoot 30% ROUT = 24 W 20% ROUT = 0 W RF = 2 kW 15% ROUT = 24 W -15 V 25% 20% ROUT = 51 W 15% ROUT = 51 W 10% 10% 5% 5% 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) G=1 G = –1 Figure 19. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 20. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) 0 80 70 10 kΩ –0.2 60 IB and IOS (pA) AOL (μV/V) –0.4 2 kΩ –0.6 –0.8 +IB 50 40 30 20 –IB 10 0 –1 –10 –1.2 –IOS –20 -40 -15 35 10 60 85 –40 –15 10 35 60 85 Temperature (°C) Temperature (°C) Figure 21. Open-Loop Gain vs Temperature Figure 22. IB and IOS vs Temperature 2.5 10 8 2 +IB 4 –IB 2 0 IQ (mA) IB and IOS (pA) 6 IOS –2 1.5 1 –4 0.5 –6 –8 Common-Mode Range –10 –18 –12 –6 0 6 12 18 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 Temperature (°C) Common-Mode Voltage (V) VS = ±18 V Figure 23. IB and IOS vs Common-Mode Voltage 10 Figure 24. Quiescent Current vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 Typical Characteristics (continued) at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted) 60 2 1.75 50 ISC-SOURCE 1.5 40 ISC (mA) IQ (mA) 1.25 1 0.75 30 ISC-SINK 20 0.5 10 0.25 Specified Supply-Voltage Range 0 0 0 4 8 12 16 20 24 28 32 36 –50 –25 0 25 50 75 100 125 Temperature (°C) Supply Voltage (V) VOUT = Midsupply (includes self-heating) Figure 26. Short-Circuit Current vs Temperature Figure 25. Quiescent Current vs Supply Voltage 18 1k 17.5 100 16 ZO (W) Output Voltage (V) 17 16.5 +85°C -40°C +125°C +25°C -16 10 -16.5 -17 -17.5 1 -18 0 10 20 30 40 50 10 100 10k 100k 1M 10M 100M Frequency (Hz) Output Current (mA) Figure 27. Output Voltage vs Output Current 1k Figure 28. Open-Loop Output Impedance vs Frequency Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 11 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com 7 Detailed Description 7.1 Overview The OPA164x-Q1 family of operational amplifiers combine an ultra-low noise JFET input stage with a rail-to-rail output stage to provide high overall performance in audio applications. The internal topology is selected specifically to deliver extremely low distortion, consume limited power, and accommodate small packages. These amplifiers are well-suited for analog signal processing applications such as active filter circuits, pre-amplifiers, and tone controls. The unique input stage design and semiconductor processes used in this device deliver extremely high performance even in applications with high source impedance and wide common-mode voltage swings. 7.2 Functional Block Diagram V+ Pre-Output Driver IN– OUT IN+ V– 12 Submit Documentation Feedback Copyright © 2017 Texas Instruments Inc. Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 7.3 Feature Description 7.3.1 Phase Reversal Protection The OPA164x-Q1 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPA164x-Q1 prevents phase reversal with excessive commonmode voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 29. 5 V/div Output +18 V OPA1641-Q1 Output -18 V 37 VPP Sine Wave (±18.5 V) Time (0.4 ms/div) Figure 29. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition 7.3.2 Output Current Limit The output current of the OPA164x-Q1 series is limited by internal circuitry to 36 mA and –30 mA (sourcing and sinking), to protect the device if the output is accidentally shorted. This short-circuit current depends on temperature; see Figure 26. Although uncommon for most modern audio applications to require 600-Ω load drive capability, many audio operational amplifier applications continue to specify the total harmonic distortion (THD+N) at 600-Ω load for comparative purposes. Figure 7 and Figure 8 provide typical THD+N measurement curves for the OPA164x-Q1 series, where the output drives a 3-VRMS signal into a 600-Ω load. However, correct device operation cannot be ensured when driving 600-Ω loads at full supply. Depending on supply voltage and temperature, this operating condition can possibly trigger the output current limit circuitry of the device. 7.3.3 EMI Rejection Ratio (EMIRR) The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting input is tested for EMIRR for the following three reasons: • Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the supply or output pins. • The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit nearly matching EMIRR performance. • EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the noninverting input pin with no complex interactions from other components or connecting PCB traces. A more formal discussion of the EMIRR IN+ definition and test method is provided in application report EMI Rejection Ratio of Operational Amplifiers, available for download at www.ti.com. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 13 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Feature Description (continued) The EMIRR IN+ of the OPA164x-Q1 is plotted versus frequency in Figure 30. If available, any dual and quad operational amplifier device versions have nearly identical EMIRR IN+ performance. The OPA164x-Q1 unity-gain bandwidth is 11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the operational amplifier bandwidth. 140 120 EMIRR (dB) 100 80 60 40 20 0 10M 100M 1G 10G Frequency (Hz) C003 Figure 30. OPA164x-Q1 EMIRR vs Frequency Table 1 lists the EMIRR IN+ values for the OPA164x-Q1 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 can be centered on or operated near the particular frequency shown. This information can be of special interest to designers working with these types of applications, or working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, and medical (ISM) radio band. Table 1. OPA164x-Q1 EMIRR IN+ for Frequencies of Interest 14 FREQUENCY APPLICATION AND ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, UHF 53.1 dB 900 MHz GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM, aeronautical mobile, UHF 72.2 dB 1.8 GHz GSM, mobile personal comm. broadband, satellite, L-band 80.7 dB 2.4 GHz 802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band 86.8 dB 3.6 GHz Radiolocation, aero comm./nav., satellite, mobile, S-band 91.7 dB 5 GHz 802.11a/n, aero communication and navigation, mobile communication, space and satellite operation, C-band 96.6 dB Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 7.3.3.1 EMIRR IN+ Test Configuration Figure 31 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with multimeter accuracy. See EMI Rejection Ratio of Operational Amplifiers for more details. Ambient temperature: 25Û& +VS ± 50 Low-Pass Filter + RF source DC Bias: 0 V Modulation: None (CW) Frequency Sweep: 201 pt. Log -VS Not shown: 0.1 µF and 10 µF supply decoupling Sample / Averaging Digital Multimeter Figure 31. EMIRR IN+ Test Configuration Schematic 7.4 Device Functional Modes 7.4.1 Operating Voltage The OPA164x-Q1 series of operational amplifiers can be used with single or dual supplies from an operating range of VS = 4.5 V (±2.25 V) and up to VS = 36 V (±18 V). These devices do not require symmetrical supplies; only a minimum supply voltage of 4.5 V (±2.25 V) is required. For VS less than ±3.5 V, the common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently damage the device; see Absolute Maximum Ratings for more information. Key parameters are specified over the operating temperature range, TA = –40°C to +85°C. Key parameters that vary over the supply voltage or temperature range are shown in Typical Characteristics. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 15 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPA164x-Q1 amplifiers are unity-gain stable, audio operational amplifiers with very low noise, input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Figure 32 shows a simplified schematic of the OPA1641-Q1. V+ Pre-Output Driver IN– OUT IN+ V– Copyright © 2017 Texas Instruments Inc. Figure 32. Simplified Internal Schematic 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 Application Information (continued) 8.1.1 Total Harmonic Distortion Measurements The OPA164x-Q1 series operational amplifiers have excellent distortion characteristics. THD + noise is below 0.00005% (G = 1, VO = 3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load (see Figure 7). The distortion produced by the OPA164x-Q1 series op amps is below the measurement limit of many commercially available distortion analyzers. However, a special test circuit (such as shown in Figure 33) can be used to extend the measurement capabilities. Operational amplifier distortion can be considered an internal error source that can be referred to the input. Figure 33 shows a circuit that causes the operational amplifier distortion to be 101 times (or approximately 40 dB) greater than that normally produced by the op amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for error correction is reduced by a factor of 101, extending the resolution by 101. The input signal and load applied to the op amp are the same as with conventional feedback without R3. Keep the value of R3 small to minimize any effect on distortion measurements. The validity of this technique can be verified by duplicating measurements at high gain or high frequency where the distortion is within the measurement capability of the test equipment. Measurements for this document were made with an audio precision system two distortion and noise analyzer that greatly simplifies repetitive measurements. However, the measurement technique can be performed with manual distortion measurement instruments. space R1 R2 SIGNAL DISTORTION GAIN GAIN VO = 3 VRMS R3 Signal Gain = 1+ OPA1641-Q1 R2 R1 Distortion Gain = 1+ R2 R1 II R3 Generator Output R1 R2 R3 1 101 ¥ 1 kW 10 W 11 101 100 W 1 kW 11 W Analyzer Input Audio Precision System Two(1) with PC Controller Load Copyright © 2016, Texas Instruments Incorporated (1) For measurement bandwidth, see Figure 7 through Figure 10. Figure 33. Distortion Test Circuit 8.1.2 Source Impedance and Distortion In traditional JFET-input op amps, the impedance applied to the positive and negative inputs in noninverting applications must be matched for lowest distortion. Legacy methods for fabricating the JFETs in the FET input stage exhibit a varying input capacitance with applied common-mode input voltage. In inverting configurations, the input does not vary with input voltage because the inverting input is held at virtual ground. However, in noninverting applications, the inputs do vary, and the gate-to-source voltage is not constant. This effect produces increased distortion resulting from the varying capacitance for unmatched source impedances. However, the OPA164x-Q1 family of amplifiers is designed to maintain a constant input capacitance with varying commonmode voltage to prevent this mechanism of distortion. The variation of input capacitance with common-mode voltage for a traditional amplifier is compared to the OPA164x-Q1 family in Figure 34. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 17 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Common-Mode Capacitance (pF) 7.5 7 Traditional JFET-Input Amplifier 6.5 OPA164x Family 6 5.5 5 4.5 4 –10 –8 –6 –4 –2 0 2 4 6 8 10 Common-Mode Voltage (V) Figure 34. Input Capacitance of the OPA164x-Q1 Family of Amplifiers Compared to Traditional JFETinput Amplifiers Total Harmonic Distortion + Noise 1% –40 10 kΩ + –50 – 5 VRMS 0.1% –60 –70 Traditional JFET-Input Amplifier 0.01% –80 –90 OPA164x Amplifier 0.001% –100 –110 0.0001% –120 10 100 1k Total Harmonic Distortion + Noise (dB) By stabilizing the input capacitance, the distortion performance of the amplifier is greatly improved for noninverting configurations with high source impedances. The measured performance of an OPA164x-Q1 amplifier is compared to a traditional JFET-input amplifier in Figure 35. The unity-gain configuration, high source impedance, and large-signal amplitude produce additional distortion in the traditional amplifier. 10k 20k Frequency (Hz) Figure 35. Measured THD+N of the OPA164x-Q1 Family of Amplifiers Compared to Traditional JFETinput Amplifiers 8.1.3 Capacitive Load and Stability The dynamic characteristics of the OPA164x-Q1 are optimized for commonly encountered gains, loads, and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω, for example) in series with the output. Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of ROUT. For details of analysis techniques and application circuits, see see Feedback Plots Define Op Amp AC Performance available for download at www.ti.com 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 8.1.4 Power Dissipation and Thermal Protection The OPA164x-Q1 op amps are capable of driving 2-kΩ loads with power-supply voltages of up to ±18 V over the specified temperature range. In a single-supply configuration, where the load is connected to the negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply voltages (either single-supply or symmetrical supplies), a lower load resistance can be used, as long as the output current does not exceed 13 mA; otherwise, the device short-circuit current-protection circuit can activate. Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction used in the OPA164x-Q1 series of devices improves heat dissipation compared to conventional materials. PCB layout can help reduce a possible increase in junction temperature. Wide copper traces help dissipate the heat by functioning as an additional heat sink. Temperature rise can be further minimized by soldering the devices directly to the PCB rather than using a socket. Although the output current is limited by internal protection circuitry, accidental shorting one or more output channels of a device can result in excessive heating. For instance, when an output is shorted to midsupply, the typical short-circuit current of 36 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V. In case of a dual OPA1642-Q1 in an VSSOP-8 package (thermal resistance RθJA = 180°C/W), such a power dissipation results in the die temperature to be 220°C above ambient temperature, when both channels are shorted. This temperature increase destroys the device. To prevent such excessive heating that can destroy the device, the OPA164x-Q1 series has an internal thermal shutdown circuit that shuts down the device if the die temperature exceeds approximately 180°C. When this thermal shutdown circuit activates, a built-in hysteresis of 15°C ensures that the die temperature must drop to approximately 165°C before the device switches on again. 8.1.5 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. Figure 36 illustrates the ESD circuits contained in the OPA164x-Q1 series (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines where an internal absorption device is connected. This protection circuitry is intended to remain inactive during normal circuit operation. An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption device has a trigger (or threshold voltage) that is above the normal operating voltage of the OPA164x-Q1 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit as shown in Figure 36, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, some of the internal ESD protection circuits can be biased on and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device. Figure 36 depicts a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 19 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input when the power supplies +VS and –VS are at 0 V. The amplifier behavior depends on the supply characteristic when at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current can be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier most likely does not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current and any resistance in the input path. If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes can be added to the supply pins, as shown in Figure 36. The Zener voltage must be selected so the diode does not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. (2) TVS RF +VS +V OPA1641-Q1 RI ESD CurrentSteering Diodes -In RS (3) +In Op-Amp Core Edge-Triggered ESD Absorption Circuit ID VIN Out RL (1) -V -VS (2) TVS Copyright © 2016, Texas Instruments Incorporated (1) VIN = +VS + 500 mV. (2) TVS: +VS(max) > VTVSBR (Min) > +VS (3) Suggested value is approximately 1 kΩ. Figure 36. Equivalent Internal ESD Circuitry and the Relation to a Typical Circuit Application 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 8.2 Typical Application 8.2.1 Single-Supply Electret Microphone Preamplifier for Speech Electret microphones are commonly used in automotive hands-free phone systems because of their small size, low cost, and relatively good signal-to-noise ratio (SNR). The low noise and distortion of the OPA1641-Q1 makes the device a good choice for preamplifier circuits for electret microphones. The circuit shown in Figure 37 is a single-supply preamplifier circuit for electret microphones with a bandwidth from 100 Hz to 3 kHz for capturing speech. CFB +9 V 1 nF RFB RBIAS 14 k 61.9 k CIN +9 V 0.1 F 0.1 F Electret Microphone +9 V RDIV 100 k ± Output + RDIV 100 k VS+ OPA1641-Q1 VS± CDIV 160 nF Copyright © 2016, Texas Instruments Incorporated Figure 37. Preamplifier Circuit for Electret Microphones Using a Single Power Supply Voltage 8.2.1.1 Design Requirements • 9-V single supply • 1-VRMS output for 100-dBSPL input • Approximately 100-Hz to 3-kHz, –3-dB Bandwidth • Microphone sensitivity: 8 µA / Pa • Microphone operating voltage: 2 V to 10 V • Microphone bias current: 500 µA 8.2.1.2 Detailed Design Procedure In this circuit, the op amp is configured as a transimpedance amplifier which converts the signal current of the microphone into an output voltage. The bandwidth of this circuit is limited to the vocal range as is common in telephony systems. The gain of the circuit is determined by the feedback resistor (RFB), which must be calculated according to the microphone sensitivity. For this design, a microphone output current of 8 µA per Pascal (Pa) of air pressure was selected. Using this value, the output current for a sound pressure level of 100 dBSPL, or 2 Pa air pressure, is calculated in Equation 1. 8 PA imic u 2 Pa = 16 PA 1 Pa (1) RFB is then calculated from this current to produce 1-VRMS output for a 100-dBSPL input signal in Equation 2. VO 1 VRMS RFB 62500 o 61.9 k: imic 16 PA (2) The feedback capacitor (CFB) is calculated to limit the bandwidth of the amplifier to 3 kHz in Equation 3. 1 1 CFB 857 u 10 12 o 1 nF 2 ˜ S ˜ RFB ˜ fH 2 ˜ S ˜ (61.9 k:) ˜ (3 kHz) (3) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 21 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com Typical Application (continued) RBIAS is necessary to divert the microphone signal current through capacitor CIN rather than flowing from the power supply (VCC). Larger values of RBIAS allow for a smaller capacitor to be used for CIN and reduces the overall noise of the circuit. However, the maximum value for RBIAS is limited by the microphone bias current and minimum operating voltage. The value of RBIAS is calculated in Equation 4. VCC VMIC 9 V 2 V RBIAS 14 k: IBIAS 500 PA (4) Input capacitor CIN forms a high-pass filter in combination with resistor RBIAS. The filter corner frequency calculation is shown in Equation 5 to place the high-pass corner frequency at 100 Hz. 1 1 CIN 113.7 u 10 9 o 100 nF 2 ˜ S ˜ RBIAS ˜ fL 2 ˜ S ˜ (14 k:) ˜ (100 Hz) (5) The voltage divider network at the op amp noninverting input is used to bias the op amp output to the midsupply point (VCC / 2) to maximize the output voltage range of the circuit. This result is easily achieved by selecting the same value for both resistors in the divider. The absolute value of those resistors is limited by the acceptable power-supply current drawn by the voltage divider. Choosing 50 µA as an acceptable limit of supply current gives a value of 100 kΩ for the resistors in the divider, as Equation 6 shows. V 9V RDIV t CC t t 90 k: o 100 k: 2 ˜ IDIV 2 ˜ 50 PA (6) Finally, to minimize the additional noise contribution from the voltage divider, a capacitor is placed at the op amp noninverting input. This capacitor forms a low-pass filter with the parallel combination of the voltage divider resistors. Selecting a filter corner frequency of 20 Hz minimizes the noise contribution of the voltage divider inside the amplifier passband; see Equation 7. 1 1 CDIV 1.592 u 10 7 o 160 nF § RDIV · § 100 k: · 2˜S˜¨ ¸ ˜ (20 Hz) ¸ ˜ fL 2 ˜ S ˜ ¨ 2 © ¹ © 2 ¹ (7) 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 Typical Application (continued) 8.2.1.3 Application Curve The transfer function of the microphone preamplifier circuit is shown in Figure 38. The nominal gain of the circuit is 95.46 dB, or 59,292.5 V per amp of input current. The –3-dB bandwidth limits of the circuit are 105.7 Hz and 2.77 kHz. 98 96 94 Gain (dB, V/A) 92 90 88 86 84 82 80 10 100 1k 10k 20k Frequency (Hz) Figure 38. Microphone Preamplifier Transfer Function 9 Power Supply Recommendations The OPA164x-Q1 devices are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Typical Characteristics. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 23 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. • To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close as possible to the device. As shown in Figure 39, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • TI recommends cleaning the PCB following board assembly for best performance. • Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND ±IN V+ VIN +IN OUTPUT V± N/C RG Use low-ESR, ceramic bypass capacitor GND VS± GND Use low-ESR, ceramic bypass capacitor VOUT Ground (GND) plane on another layer Figure 39. OPA1641-Q1 Layout Example 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 OPA1641-Q1, OPA1642-Q1 www.ti.com SBOS791 – JUNE 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 TI Precision Designs TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 11.1.1.3 WEBENCH® Filter Designer WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets optimized filter designs to be created using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web based tool from the WEBENCH® Design Center, the WEBENCH® Filter Designer allows complete multistage active filter solutions to be designed, optimized, and simulated within minutes. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Operational amplifier gain stability, Part 3: AC gain-error analysis • Operational amplifier gain stability, Part 2: DC gain-error analysis • Using infinite-gain, MFB filter topology in fully differential active filters • Op Amp Performance Analysis • Single-Supply Operation of Operational Amplifiers • Tuning in Amplifiers • Shelf-Life Evaluation of Lead-Free Component Finishes Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 25 OPA1641-Q1, OPA1642-Q1 SBOS791 – JUNE 2017 www.ti.com 11.3 Related Links Table 2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA1641-Q1 Click here Click here Click here Click here Click here OPA1642-Q1 Click here Click here Click here Click here Click here 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks E2E is a trademark of Texas Instruments. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. 11.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: OPA1641-Q1 OPA1642-Q1 PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA1641AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPA1642AQDGKRQ1 PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 1641 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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