CXP82940/82948/82952/82960
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82940/82948/82952/82960 is a CMOS 8-bit
single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, fluorescent display panel
controller/driver, I2C bus interface, remote control
transmission circuit, remote control reception circuit,
and 32kHz timer/counter besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.
80 pin QFP (Plastic)
Structure
Features1
Silicon gate CMOS IC
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
(122µs at 32kHz operation)
• Incorporated ROM capacity
40K bytes (CXP82940)
48K bytes (CXP82948)
52K bytes (CXP82952)
60K bytes (CXP82960)
• Incorporated RAM capacity
2048 bytes (including fluorescent display area)
• Periphera; functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)
— Serial interface
Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
— Timers
8-bit timer, 8-bit timer/counter, 19-bit time base timer
32kHz timer/counter
— Fluorescent display panel controller/driver Maximum of 196 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
Hardware key scan function
Maximum of 12 × 8 key matrix supportable
2
— I C bus interface
— Remote control transmission circuit
Auto transmission for 1 to 32 bytes,
restart function, carrier output function
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
• Interruption
16 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
80-pin plastic QFP
• Piggyback/evaluation chip
CXP82900 80-pin ceramic QFP
Perchase of Sony’s I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95130-PK
–2–
12
8
S0 to S11
VFDP
KR0 to KR7
RAM
RAM
ADJ
I2C BUS
INTERFACE UNIT
8 BIT TIMER 1
TO
SCL0
SCL1
SDA0
SDA1
8 BIT TIMER/COUNTER 0
FIFO
SERIAL
INTERFACE
UNIT (CH1)
SI1
SO1
SCK1
EC
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH0)
CS0
SI0
SO0
SCK0
FIFO
REMOCON IN
RMC
RMCO
KEY SCAN
8
BUFFER
REMOCON OUT
RAM
FDP
CONTROLLER/
DRIVER
8
T0 to T7
AVSS
T8/S19 to T15/S12
AVDD
A/D CONVERTER
2
INT0
INT1
INT2
INT3/NMI
INTERRUPT CONTROLLER
AVREF
8
2
PRESCALER/
TIME BASE TIMER
ROM
40K/48K/52K/60K
BYTES
SPC 700
CPU CORE
RST
VDD
VSS
TEX
TX
EXTAL
XTAL
32KHz
TIMER/COUNTER
RAM
2048 BYTES
CLOCK
GENERATOR
SYSTEM CONTROL
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE5
PE6 to PE7
PF0 to PF3
8
8
8
6
2
4
4
PG0 to PG3
PA0 to PA7
8
PORT B
PORT E
AN0 to AN7
2
PORT A
PORT C
PORT D
PORT F
PORT G
Block Diagram
CXP82940/82948/82952/82960
CXP82940/82948/82952/82960
T6
T5
T4
T2
T3
T1
T0
TX
VDD
TEX
NC
PG1
PG0
PG2
PG3
PE0/EC/INT0
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PE1/INT1
1
64
T7
PE2/INT2
2
63
T8/S19
PE3/INT3/NMI
3
62
T9/S18
PE4/RMC
4
61
T10/S17
PE5
5
60
T11/S16
PE6/RMCO
6
59
T12/S15
PE7/TO/ADJ
7
58
T13/S14
PB0
8
57
T14/S13
PB1/CS0
9
56
T15/S12
S11
PB2/SCK0
10
55
PB3/SI0
11
54
S10
PB4/SO0
12
53
S9
PB5/SCK1
13
52
S8
51
PD7/S7
PB6/SI1
14
PB7/SO1
15
50
PD6/S6
PA0/AN0
16
49
PD5/S5
PA1/AN1
17
48
PD4/S4
PA2/AN2
18
47
PD3/S3
PA3/AN3
19
46
PD2/S2
PA4/AN4
20
45
PD1/S1
PA5/AN5
21
44
PD0/S0
PA6/AN6
22
43
VFDP
PA7/AN7
23
42
PC7/KR7
AVDD
24
41
PC6/KR6
Note) NC (Pin 75) must be connected to VDD.
–3–
PC5/KR5
PC4/KR4
PC3/KR3
PC1/KR1
PC2/KR2
PC0/KR0
RST
VSS
XTAL
EXTAL
AVSS
PF3/SDA1
PF2/SDA0
PF1/SCL1
PF0/SCL0
AVREF
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP82940/82948/82952/82960
Pin Description
Pin code
Functions
I/O
PA0/AN0
to
PA7/AN7
I/O/
Analog input
PB0
I/O
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
(Port A)
8-bit I/O port. I/O can
be set in a unit of
single bits.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
(Port B)
8-bit I/O port. I/O can
be set in a unit of
single bits.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter. (8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can
be set in a unit of single
bits. Capable of driving
Serves as key return inputs when operating
12mA sync current.
key scan with fluorescent display panel (FDP)
Incorporation of pull-up
segment signal (8 pins).
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
PC0/KR0
to
PC7/KR7
I/O/Input
PE0/INT0/EC
Input/Input/Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/Input
PE4/RMC
Input/Input
PE5
Input
PE6/RMCO
Output/Output
Carrier output of remote control transmission
circuit.
PE7/TO/ADJ
Output/Output/
Output
Output for the timer/counter rectangular waves,
and 32kHz oscillation dividing frequency.
PF0/SCL0
PF1/SCL1
Output/I/O
PF2/SDA0
PF3/SDA1
Output/I/O
(Port E)
8-bit port. Lower 6 bits
are for inputs; upper
2 bits are for outputs.
(8 pins)
Inputs for
external
interruption
request.
(4 pins)
External event inputs for
timer/counter.
Non-maskable interruption
request input.
Remote control reception circuit input.
(Port F)
Transfer clock I/Os for I2C bus interface.
4-bit output port,
operating as N-ch open
drain output for large
current (12mA).
Transfer data I/Os for I2C bus interface.
(4 pins)
–4–
CXP82940/82948/82952/82960
Pin code
I/O
Functions
PG0 to PG3
I/O
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits.
(4 pins)
PD0/S0
to
PD7/S7
Output/Output
(Port D)
8-bit output ports.
(8 pins)
S8 to S11
Output
FDP segment signal outputs. (4 pins)
T8/S12
to
T15/S19
Output/Output
Outputs for FDP timing signals/segment signals.
(8 pins)
T0 to T7
Output
FDP timing signal outputs.
VFDP
FDP segment signal outputs.
(8 pins)
FDP voltage supply when incorporated resistor is set by mask option.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
RST
Input
Low-level active, system reset.
NC
NC. Under normal operation, connect to VDD.
AVDD
Positive power supply for A/D converter.
AVREF
Input
Reference voltage input for A/D converter.
AVSS
A/D converter GND.
VDD
Positive power supply.
VSS
GND.
–5–
CXP82940/82948/82952/82960
I/O Circuit Format for Pins
Circuit format
Pin
Port A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
∗
Pull-up resistor
AA
AAAA
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
Input
protection
circuit
IP
"0" when reset
Data bus
Hi-Z
RD (Port A)
Port A input
selection
"0" when reset
8 pins
Port B
Input multiplexer
A/D converter
∗ Pull-up transistor approx. 100kΩ
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
AA
AAAA
"0" when reset
Port B data
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Hi-Z
Schmitt input
Data bus
RD (Port B)
CS0
SI0
SI1
3 pins
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistor approx. 100kΩ
Not Schmitt input for SI0 and SI1.
Port B
∗
Pull-up resistor
"0" when reset
SCK OUT
Output enable
Port B output
selection
PB2/SCK0
PB5/SCK1
AA
AAAA
"0" when reset
IP
Port B data
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
2 pins
∗ Pull-up transistor approx. 100kΩ
SCK in
–6–
Hi-Z
CXP82940/82948/82952/82960
Circuit format
Pin
Port B
When reset
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
SO
Output enable
AA
AAAA
Port B output
selection
"0" when reset
PB4/SO0
PB7/SO1
IP
Port B data
Hi-Z
Port B direction
“0” when reset
Data bus
RD (Port B)
2 pins
∗ Pull-up transistor approx. 100kΩ
AAAA
AAAA
AAAA
AAAA
Port C
∗2
Pull-up resistor
AA
AAAA
"0" when reset
Port C data
PC0/KR0
to
PC7/KR7
∗1
Port C direction
"0" when reset
Data bus
IP
Hi-Z
RD (Port C)
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Port E
∗2 Pull-up transistor approx. 100kΩ
AA
AA
AAAA
AA
AA
AAAA
EC/INT0
INT1
INT2
INT3/NMI
RMC
Schmitt input
IP
5 pins
PE5
∗1 Large current 12mA
Key input signal
8 pins
Port E
Data bus
RD (Port E)
Data bus
IP
1 pin
Port E
Hi-Z
Hi-Z
RD (Port E)
Remote control
transmission circuit
Port E output selection
"0" when reset
PE6/RMCO
Reset E data
Output enable
"1" when reset
Data bus
1 pin
RD (Port E)
–7–
High level
CXP82940/82948/82952/82960
Circuit format
Pin
When reset
Port E
AAAA
AAAAA
AAAAA
Internal reset signal
00
Port E data
"1" when reset TO
ADJ16K∗1
PE7/TO/ADJ
01
10
ADJ2K∗1
AA
AA
MPX
∗2
11
Port E output selection (upper)
Port E output selection (lower)
∗1 ADJ signal is a frequency dividing output for
32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.
∗2 Pull-up transistor approx. 150k Ω.
"00" when reset
TO output enable
1 pin
AA
AA
Port F
SCL, SDA
PF0/SCL0
PF1/SCL1
PF2/SDA0
PF3/SDA1
AAA
AAA
I2C output enable
("0" when reset)
Port F data
"1" when reset
Schmitt input
SCL, SDA
(I2C circuit)
4 pins
Port B
Port G
AAAA
AAAAA
AAAAA
AAAAA
AAAAA
AA
AA
Large current
12mA
Hi-Z
IP
BUS SW
To internal I2C pin
(to SCL1 for SCL0)
∗
Pull-up resistor
"0" when reset
Port B data or
Port G data
PB0
PG0 to PG3
High level
(with approx.
150kΩ
resistor when
reset)
Port B direction or
Port G direction
"0" when reset
Data bus
RD (Port B or Port G)
AA
AA
AA
AA
IP
∗ Pull-up transistor approx. 100kΩ
5 pins
–8–
Hi-Z
CXP82940/82948/82952/82960
Circuit format
Pin
When reset
Port D
AA
AA
AA
AA
∗ High voltage drive transistor
Segment output data
PD0/S0
to
PD7/S7
∗
AAAAA
AAAAA
Output selection
control signal
("0" when reset)
OP Mask option
Port D data
Pull-down
transistor
VFDP
Data bus
RD (Port D)
8 pins
Hi-Z or
Low level
(when PD
resistor is
connected)
∗ High voltage drive transistor
S8 to S11
T15/S12
to
T8/S19
T0 to T7
Segment output data
Timing output data
∗
Output selection
control signal
("0" when reset)
OP
Pull-down
resistor
20 pins
EXTAL
XTAL
AA AA A
AA
AA AA A
AA
2 pins
XTAL
TEX
TX
TEX
2 pins
RST
1 pin
IP
EXTAL
IP
IP
IP
AA
AA
AA
AA
Mask option
VFDP
• Diagram shows circuit
composition during oscillation.
• Feedback resistor is removed
during stop, and XTAL
becomes High.
AA
AA
Oscillation
•Diagram shows circuit
composition during oscillation.
•When the operation of the oscillation
circuit is stopped by the software,
the feedback resistor is removed,
and TEX becomes Low level and TX
becomes High level.
TX
Hi-Z or
Low level
(when PD
resistor is
connected)
Oscillation
Pull-up resistor
OP
AA
Mask option
Low level
IP
–9–
Schmitt input
CXP82940/82948/82952/82960
Absolute Maximum Ratings
Item
Symbol
(Vss = 0V reference)
Rating
Unit
V
Remarks
Supply voltage
VDD
Input voltage
VIN
–0.3 to +7.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD – 40 to VDD + 0.3
V
IOH
–5
mA
As P channel transistor is open drain,
VDD is reference.
All pins excluding outputs∗2 (value per pin)
IODH1
–15
mA
Display outputs S0 to S11 (value per pin)
IODH2
–35
mA
Display outputs T0 to T7, and T8/S19 to
T15/S12 (value per pin)
∑IOH
–40
mA
Total for all pins excluding display outputs
∑IODH
–100
mA
Total for all display outputs
IOL
15
mA
Port (value per pin)
IOLC
20
mA
Large current Port (value per pin)∗3
Low level total output current ∑IOL
100
mA
Total for all output pins
High level output current
High level total output
current
Low level output current
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
Allowable power dissipation PD
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 Specifies output current of general-purpose I/O ports.
∗3 The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP82940/82948/82952/82960
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
Unit
Remarks
4.5
5.5
V
Guaranteed operation range for high-speed
mode (1/2, 1/4 frequency dividing clock)
3.5
5.5
V
Guaranteed operation range for low-speed
mode (1/16 frequency dividing clock) or
SLEEP mode
2.7
5.5
V
Guaranteed operation range with TEX
clock
2.5
5.5
V
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VDD
VIHEX
Low level input
voltage
Operating temperature
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
Guaranteed data hold range during STOP
∗1
V
Hysteresis input∗2
EXTAL∗3
VIL
0
0.3VDD
V
∗1
VILS
0
0.2VDD
V
Hysteresis input∗2
VILEX
–0.3
0.4
V
EXTAL∗3
Topr
–20
+75
°C
∗1 Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG).
∗2 Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1,
SDA0, SDA1.
∗3 Specifies only during external clock input.
– 11 –
CXP82940/82948/82952/82960
Electrical Characteristics
DC Characteristics
Item
High level
output current
Low level
output current
Symbol
VOH
VOL
Pins
PA, PB,
PC, PE6,
PE7, PG
PC, PF
Conditions
IILE
IIHT
Typ.
IILT
EXTAL
TEX
IILR
RST∗1
IIL
PA to PC∗2,
PG∗2
IOH
Open drain output
ILOL
leakage current
(P-CH Tr off state)
S12/T15 to
S19/T8,
T0 to T7
S0 to S11,
S12/T15 to
S19/T8,
T0 to T7
S0 to S11,
S12/T15 to
S19/T8,
T0 to T7
PA to PC∗2,
PG∗2,
RST∗1
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
0.4
V
0.6
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–50
µA
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
S0 to S11
Display output
current
Min.
PF
VDD = 4.5V, IOL = 3.0mA
(SCL0, SCL1,
SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA
IIHE
Input current
(Ta = –20 to +75°C, Vss = 0V reference)
VDD = 4.5V
VOH = VDD – 2.5V
–3.3
µA
–8
mA
–20
mA
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
–20
µA
270
kΩ
VDD = 5.5V
VI = 0, 5.5V
±10
µA
Pull-down
resistance∗3
RL
I/O
leakage current
IIZ
Open drain
output leakage
current (N-ch Tr
off state)
ILOH
PF
VDD = 5.5V, VOH = 5.5V
10
µA
I2C bus switch
connection
impedance
(Output Tr off
state)
RBS
SCL0: SCL1
SDA0: SDA1
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
120
Ω
VDD = 5V
VOD – VFDP = 30V
– 12 –
60
100
CXP82940/82948/82952/82960
Item
Symbol
Pins
High speed mode operation
(1/2 frequency dividing clock)
IDD1
Input
capacity
IDDS1
VDD = 3V, 32MHz crystal
oscillation (C1 = C2 = 47pF)
VDD
Typ.
Max.
Unit
31
50
mA
40
100
µA
2.5
10
mA
8
30
µA
10
µA
20
pF
SLEEP mode
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
IDDS2
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS3
STOP mode
VDD = 5.5V, termination of 16MHz
and 32kHz crystal oscillation
CIN
Min.
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
IDD2
Power supply
current∗4
Conditions
PA to PC,
PE0 to PE5,
Clock 1MHz
PF, PG,
0V for all pins excluding
EXTAL,
measured pins
XTAL, TEX,
TX, RST
10
∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
∗2 PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current
when no resistance has been selected.
∗3 When incorporated pull-down resistance has been selected through mask option.
∗4 When all pins are open.
– 13 –
CXP82940/82948/82952/82960
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Item
System clock frequency
fC
Event count input clock
rise time, fall time
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
System clock frequency
fC
Event count input
pulse width
tTL
tTH
tTR
tTF
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input rise time,
fall time
Pin
Min.
Conditions
XTAL
EXTAL
Fig. 1, Fig. 2
1
EXTAL
Fig. 1, Fig. 2
External clock drive
28
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Typ.
Max.
Unit
16
MHz
ns
200
4tsys∗
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗ tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAAAAAA
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 3. Event count clock timing
0.8VDD
TEX
EC
0.2VDD
tEF
tTF
tEH
tTH
– 14 –
tEL
tTL
tER
tTR
CXP82940/82948/82952/82960
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
Min.
Max.
Unit
CS ↓ → SCK
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS ↑ → SCK
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS ↓ → SO
delay time
tDCSO
SO0
Chip select transfer mode
1.5tsys + 200
ns
CS ↑ → SO
float delay time
tDCSOF SO0
Chip select transfer mode
1.5tsys + 200
ns
CS High level width
tWHCS CS0
Chip select transfer mode
SCK cycle time
tKCY
SCK0
SCK
High, Low level width
tKH
tKL
SCK0
SI input setup time
(for SCK ↑)
tSIK
SI0
SI input hold time
(for SCK ↑)
tKSI
SCK ↓ → SO
delay time
tKSO
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
tsys + 200
2tsys + 200
ns
8000/fc
ns
tsys + 100
ns
8000/fc – 100
ns
–tsys + 100
ns
200
ns
2tsys + 100
ns
100
ns
ns
2tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) CS, SCK, SI and SO correspond to each pin of CS0, SCK0, SI0 and SO0.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
– 15 –
CXP82940/82948/82952/82960
Fig. 4. Serial transfer CH0 timing (CH0)
tWHCS
CSO
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 16 –
CXP82940/82948/82952/82960
Serial transfer (CH1) (SIO mode)
Item
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Pin
tKCY
SCK1
SCK1
High, Low level width
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Condition
Min.
Max.
Unit
Input mode
2tsys + 200
ns
Ouput mode
16000/fc
ns
Input mode
tsys + 100
ns
Ouput mode
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 ouput mode
200
ns
SCK1 input mode
tsys + 200
ns
SCK1 ouput mode
100
ns
SCK1 input mode
tsys + 200
ns
SCK1 ouput mode
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
0.2VDD
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 17 –
CXP82940/82948/82952/82960
Serial transfer (CH1) (Special mode)
Item
SO1 cycle time
SI1 data setup time
SI1 data hold time
Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Pin
Condition
Min.
Typ.
Max.
Unit
tLCY∗
SO1
SI1
tLSU
tLHD
SI1
2
µs
SI1
2
µs
104
µs
∗ tLCY is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1) (SIOM1:
address 01E2H) is set to 104µs.
Note) The load condition for SO1 is 50pF + 1TTL.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
SO1
tLCY
Start bit
Output data bit
0.5VDD
tLCY/2
tLSU
tLHD
0.8VDD
Input
data bit
SI1
0.2VDD
– 18 –
CXP82940/82948/82952/82960
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Linearity error
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Zero transition
voltage
VZT∗1
Full-scale
transition voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
IREF
AVREF current
VDD = AVDD = 4.5 to 5.5V
AVREF
Unit
8
Bits
±3
LSB
–10
10
70
mV
4910
4970
5030
mV
160/fADC∗3
µs
12/fADC∗3
µs
AVDD – 0.5
AVDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
Operation mode
IREFS
Max.
SLEEP mode
STOP mode
32kHz operation mode
Fig. 7. Definition of A/D converter terms
∗1 VZT: Value at which the digital conversion value change
from 00H to 01H and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control register (address: 00F9H) and bits 7
(PCK1) and 6 (PCK0) of the clock control register (address:
00FEH).
Digital conversion value
FFH
FEH
Linearity error
01H
CKS
00H
VFT
VZT
Analog input
PCK1, PCK0
0 (φ /2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
– 19 –
CXP82940/82948/82952/82960
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input Low level width
tRSL
RST
Min.
Condition
Max.
Unit
1
µs
32/fc
µs
Fig. 8. Interruption input timing
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI specifies only the
falling edge.)
0.2VDD
tIH
tIL
Fig. 9. RST input timing
tRSL
RST
0.2VDD
– 20 –
CXP82940/82948/82952/82960
(5) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
0
100
kHz
SCL clock frequency
fSLC
SCL
Bus-free time before starting transfer
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
SDA, SCL
4.7
µs
SDA, SCL
4.0
µs
SCL
4.7
µs
SCL
4.0
µs
SDA, SCL
µs
SDA, SCL
4.7
0∗
SDA, SCL
250
ns
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repetitive transfers
Data hold time
Data setup time
SDA, SCL rise time
SDA, SCL fall time
Setup time for transfer completion
µs
SDA, SCL
1
µs
SDA, SCL
300
ns
SDA, SCL
µs
4.7
∗ The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.
Fig.10. I2C bus transfer timing
SDA
tBUF
tR
tF
tHD ; STA
SCL
tHD ; STA
tSU ; STA
P
S
tLOW
tHD ; DAT
tHIGH
St
tSU ; DAT
tSU ; STO
P
Fig.11. Recommended circuit example for I2C device
I2C
device
RS
I2C
device
RS RS
R S RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by
CRT flash-over.
– 21 –
CXP82940/82948/82952/82960
Appendix
Fig. 12. Recommended oscillation circuit
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
(i)
EXTAL
(ii)
TEX
XTAL
Rd
C1
RIVER
ELETEC
CO., LTD.
Rd
C2
Model
Manufacturer
HC-49/U03
TX
C2
C1
Rd (Ω)
Circuit
example
0
(i)
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
8.00
16 (12)
16 (12)
10.00
16 (12)
16 (12)
12.00
12
12
0
16.00
12
12
0
32.768kHz
30
18
470k
10.00
12.00
16.00
KINSEKI
LTD.
HC-49/U (-S)
P3
0
(i)
(ii)
Mask Option Table
Content
Item
Reset pin pull-up resistance
Non-existent
Existent
High voltage drive output port pull-down resistance
Non-existent
Existent (Selectable for each pin)
– 22 –
CXP82940/82948/82952/82960
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5V, Ta = 25°C, Typical)
50
1/2 dividing mode
1/4 dividing mode
30
20
30
1/2 dividing mode
10
IDD – Supply current [mA]
1
0.5
(500µA)
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
1/16 dividing mode
SLEEP mode
5
20
1/4 dividing mode
10
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
0
1
2
3
4
5
6
7
0
VDD – Supply voltage [ V ]
5
10
Frequency [MHz]
– 23 –
15
CXP82940/82948/82952/82960
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.12
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
∗QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
– 24 –
0.8 ± 0.2
80