Freescale MC68HC912D60 M68hc12 microcontroller Datasheet

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MC68HC(9)12D60
Advance Information
M68HC12
Microcontrollers
MC68HC912D60/D
Rev. 4, 11/2003
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68HC912D60
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Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2003
68HC(9)12D60 — Rev 4.0
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List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23
Section 2. Central Processing Unit . . . . . . . . . . . . . . . . . 31
Section 3. Pinout and Signal Descriptions . . . . . . . . . . . 37
Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 5. Operating Modes and Resource Mapping . . 73
Section 6. Bus Control and Input/Output . . . . . . . . . . . . 87
Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . . 115
Section 9. Resets and Interrupts . . . . . . . . . . . . . . . . . . 123
Section 10. ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Section 11. I/O Ports with Key Wake-up . . . . . . . . . . . . 135
Section 12. Clock Functions . . . . . . . . . . . . . . . . . . . . . 143
Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . 181
Section 14. Enhanced Capture Timer. . . . . . . . . . . . . . 197
Section 15. Multiple Serial Interface. . . . . . . . . . . . . . . 237
Section 16. Motorola Interconnect Bus . . . . . . . . . . . . 263
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Section 17. MSCAN Controller . . . . . . . . . . . . . . . . . . . 277
Section 18. Analog-to-Digital Converter . . . . . . . . . . . 323
Section 19. Development Support . . . . . . . . . . . . . . . . 337
Section 20. Electrical Specifications . . . . . . . . . . . . . . 365
Section 21. Appendix: CGM Practical Aspects . . . . . . 387
Section 22. Appendix: 68HC912D60A Flash EEPROM399
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Section 23. Appendix: 68HC912D60A EEPROM . . . . . 407
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
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Table of Contents
List of Paragraphs
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Table of Contents
List of Tables
List of Figures
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5
68HC(9)12D60 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . .29
Section 2. Central Processing Unit
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.6
Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Section 3. Pinout and Signal Descriptions
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2
68HC(9)12D60 Pin Assignments in 112-pin QFP. . . . . . . . . . . 38
3.3
68HC(9)12D60 Pin Assignments in 80-pin QFP. . . . . . . . . . . . 40
3.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 4. Registers
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2
Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Operating Modes and Resource Mapping
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.4
Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.5
Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.6
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 6. Bus Control and Input/Output
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3
Detecting Access Type from External Signals . . . . . . . . . . . . .87
6.4
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Section 7. Flash Memory
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
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7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.4
Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .100
7.5
Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6
Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.8
Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 108
7.9
Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.10
Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .113
7.11
Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Section 8. EEPROM Memory
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3
Future EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.4
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .117
8.5
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Section 9. Resets and Interrupts
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.3
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.4
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.5
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .127
9.6
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.7
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.8
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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9.9
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Section 10. ROM
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.3
ROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
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Section 11. I/O Ports with Key Wake-up
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
11.3
Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .136
11.4
Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Section 12. Clock Functions
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.3
Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4
Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.5
Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .147
12.6
Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . 149
12.7
System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . .167
12.8
Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.9
Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .172
12.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Section 13. Pulse Width Modulator
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13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.3
PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.4
PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
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Section 14. Enhanced Capture Timer
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.3
Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . 203
14.4
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.5
Timer and Modulus Counter Operation in Different Modes . . 235
Section 15. Multiple Serial Interface
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4
Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .238
15.5
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . .250
15.6
Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Section 16. Motorola Interconnect Bus
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3
Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16.4
Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
16.5
Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
16.6
Interfacing to MI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
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16.7
MI Bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.8
SCI0/MI Bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
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Section 17. MSCAN Controller
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
17.3
External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
17.4
Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.5
Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .284
17.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
17.7
Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 289
17.8
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
17.9
Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
17.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .298
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . 303
Section 18. Analog-to-Digital Converter
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
18.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
18.4
ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.5
ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
Section 19. Development Support
19.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
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19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
19.3
Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
19.4
Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
19.5
Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
19.6
Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
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Section 20. Electrical Specifications
20.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
20.3
Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Section 21. Appendix: CGM Practical Aspects
21.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
21.3
A Few Hints For The CGM Crystal Oscillator Application. . . . 387
21.4
Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .390
21.5
Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .395
Section 22. Appendix: 68HC912D60A Flash EEPROM
22.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
22.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
22.4
Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .400
22.5
Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
22.6
Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
22.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
22.8
Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 404
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22.9
Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 405
22.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
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Section 23. Appendix: 68HC912D60A EEPROM
23.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
23.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
23.3
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .408
23.4
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 409
23.5
Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .415
23.6
Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
23.7
Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 416
Glossary
Revision History
23.8
Changes from Rev 3.0 to Rev 4.0 . . . . . . . . . . . . . . . . . . . . . 429
23.9
Changes from Rev 2.0 to Rev 3.0 . . . . . . . . . . . . . . . . . . . . . 429
23.10 Changes from Rev 1.0 to Rev 2.0 . . . . . . . . . . . . . . . . . . . . . 430
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List of Tables
Table
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8-1
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9-1
9-2
12-1
12-2
12-3
12-4
12-5
13-1
13-2
13-3
14-1
14-2
14-3
Title
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
68HC(9)12D60 Development Tools Ordering Information . . . .28
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34
Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . . 35
68HC(9)12D60 Power and Ground Connection Summary. . . . 44
68HC(9)12D60 Signal Description Summary . . . . . . . . . . . . . . 51
68HC(9)12D60 Port Description Summary. . . . . . . . . . . . . . . .60
Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . .61
68HC(9)12D60 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .85
EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . .85
Effects of ENPE, LAT and ERAS on Array Reads . . . . . . . . . 105
1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . 120
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Interrupt Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . . 132
Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . .161
Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . .161
Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . .175
COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . . 186
PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 196
PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 196
Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 212
Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .212
Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
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17-6
17-7
17-8
17-9
17-10
18-1
18-2
18-3
18-4
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
20-1
20-2
20-3
20-4
20-5
20-6
20-7
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Loop Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
SS Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
MI Bus Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
msCAN12 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . .289
msCAN12 vsCPU operating modes . . . . . . . . . . . . . . . . . . . .291
CAN Standard Compliant Bit Time Segment Settings . . . . . . 297
Data length codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
Synchronization jump width . . . . . . . . . . . . . . . . . . . . . . . . . .307
Baud rate prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
Time segment values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .315
Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . . 316
ATD Response to Background Debug Enable . . . . . . . . . . . . 327
Final Sample Time Selection . . . . . . . . . . . . . . . . . . . . . . . . .328
Clock Prescaler Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Multichannel Mode Result Register Assignment . . . . . . . . . .331
IPIPE Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Hardware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . .345
BDM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
TTAGO Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
REGN Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . . 359
Breakpoint Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . 361
Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .368
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 369
Analog Converter Characteristics (Operating) . . . . . . . . . . . .370
ATD AC Characteristics (Operating). . . . . . . . . . . . . . . . . . . .371
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20-9
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20-14
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21-1
21-2
23-1
23-2
23-3
23-4
ATD Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
Flash EEPROM Characteristics (68HC912D60 only). . . . . . .372
Pulse Width Modulator Characteristics. . . . . . . . . . . . . . . . . . 374
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Multiplexed Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . .381
SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
CGM Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Key Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
msCAN12 Wake-up Time from Sleep Mode. . . . . . . . . . . . . .386
Suggested 8MHz Synthesis PLL Filter Elements
(Tracking Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Suggested 8MHz Synthesis PLL Filter Elements
(Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . 412
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
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12-4
12-5
12-6
12-7
12-8
12-9
13-1
13-2
13-3
14-1
14-2
Title
68HC(9)12D60 112-pin QFP Block Diagram . . . . . . . . . . . . . . 29
68HC(9)12D60 80-pin QFP Block Diagram . . . . . . . . . . . . . . . 30
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Assignments in 112-pin TQFP for 68HC(9)12D60 . . . . . . . 38
112-pin TQFP Mechanical Dimensions (case no987) . . . . . . . 39
Pin Assignments in 80-pin QFP for 68HC(9)12D60 . . . . . . . . .40
80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . . 41
PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .43
Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . .45
External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45
68HC(9)12D60 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .86
Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . . 88
Program Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Erase Sequence Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
STOP Key Wake-up Filter (falling edge trigger) timing. . . . . . 141
Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .150
No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .152
STOP Exit and Fast STOP Recovery . . . . . . . . . . . . . . . . . . . 155
Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . . 170
Clock Chain for ECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM . . . . . . 172
Block Diagram of PWM Left-Aligned Output Channel . . . . . . 182
Block Diagram of PWM Center-Aligned Output Channel . . . . 183
PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .199
Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . . 200
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14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .201
14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .202
14-5 Block Diagram for Port7 with Output compare /
Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
14-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .203
15-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .238
15-2 Serial Communications Interface Block Diagram . . . . . . . . . . 239
15-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . 251
15-4 SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . .252
15-5 SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . .253
15-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . . 254
16-1 MI Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16-2 Biphase coding and error detection . . . . . . . . . . . . . . . . . . . . 266
16-3 MI BUS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
16-4 A typical MI Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
17-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17-2 User Model for Message Buffer Organization. . . . . . . . . . . . . 282
17-3 32-bit Maskable Identifier Acceptance Filters . . . . . . . . . . . . . 286
17-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . 286
17-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . . 287
17-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . . 293
17-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
17-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . 297
17-9 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
17-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . 299
17-11 Receive/Transmit Message Buffer Extended Identifier. . . . . . 300
17-12 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .301
18-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . 324
19-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . . 341
19-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .341
19-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .342
20-1 VFP Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20-2 VFP Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
20-3 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
20-4 POR and External Reset Timing Diagram . . . . . . . . . . . . . . . 376
20-5 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .377
20-6 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 378
20-7 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
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Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .380
Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 382
SPI Timing Diagram (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 384
SPI Timing Diagram (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 385
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Section 1. General Description
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5
68HC(9)12D60 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . .29
1.2 Introduction
The 68HC(9)12D60 microcontroller unit (MCU) is a 16-bit device
available in two package options, 80-pin QFP and 112-pin TQFP. Onchip peripherals include a 16-bit central processing unit (CPU12), 60K
bytes of flash EEPROM (68HC912D60) or ROM (68HC12D60), 2K
bytes of RAM, 1K bytes of EEPROM, two asynchronous serial
communication interfaces (SCI), a serial peripheral interface (SPI), an
enhanced capture timer (ECT), two (one on 80QFP) 8-channel,10-bit
analog-to-digital converters (ATD), a four-channel pulse-width
modulator (PWM), and a CAN 2.0 A, B software compatible module
(MSCAN12). System resource mapping, clock generation, interrupt
control and bus interfacing are managed by the lite integration module
(LIM). The 68HC(9)12D60 has full 16-bit data paths throughout,
however, the external bus can operate in an 8-bit narrow mode so single
8-bit wide memory can be interfaced for lower cost systems. The
inclusion of a PLL circuit allows power consumption and performance to
be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 16 (2 on 80QFP) I/O port pins are available
with Key-Wake-Up capability from STOP or WAIT mode.
68HC(9)12D60 — Rev 4.0
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1.3 Features
•
16-bit CPU12
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
Freescale Semiconductor, Inc...
– Instruction queue
– Enhanced indexed addressing
•
Multiplexed bus
– Single chip or expanded
– 16 address/16 data wide or 16 address/8 data narrow mode
•
Two 8-bit ports with key wake-up interrupt (2 pins only are
available on 80QFP) and one I2C start bit detector (112TQFP
only)
•
Memory
– 60K byte flash EEPROM, made of a 28K module and a 32K
module with 8K bytes protected BOOT section in each module
(68HC912D60)
– 60K byte ROM (68HC12D60)
– 1K byte EEPROM
– 2K byte RAM
•
Analog-to-digital converters
– 2 x 8-channels, 10-bit resolution in 112TQFP
– 1 x 8-channels, 8-bit resolution in 80QFP
•
1M bit per second, CAN 2.0 A, B software compatible module
– Two receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
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Features
– Low-pass filter wake-up function
– In 80QFP, only TxCAN and RxCAN pins are available
– Loop-back for self test operation
– Programmable link to a timer input capture channel, for timestamping and network synchronization.
•
Enhanced capture timer (ECT)
– 16-bit main counter with 7-bit prescaler
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– 8 programmable input capture or output compare channels; 4
of the 8 input captures with buffer
– Input capture filters and buffers, three successive captures on
four channels, or two captures on four channels with a
capture/compare selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators
– 16-bit modulus down-counter with 4-bit prescaler
– Four user-selectable delay counters for signal filtering
•
4 PWM channels with programmable period and duty cycle
– 8-bit 4-channel or 16-bit 2-channel
– Separate control for each pulse width and duty cycle
– Center- or left-aligned outputs
– Programmable clock select logic with a wide range of
frequencies
•
Serial interfaces
– Two asynchronous serial communications interfaces (SCI)
– MI-Bus implemented on final devices
– Synchronous serial peripheral interface (SPI)
•
LIM (light integration module)
– WCR (windowed COP watchdog, real time interrupt, clock
monitor)
– ROC (reset and clocks)
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– MEBI (multiplexed external bus interface)
– MBI (internal bus interface and map)
– INT (interrupt control)
•
Clock generation
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
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– Slow mode divider
– Low power 0.5 to 16 MHz crystal oscillator reference clock
•
112-Pin TQFP package or 80-pin QFP package
– Up to 68 general-purpose I/O lines, plus up to 18 input-only
lines in 112TQFP
or
Up to 48 general-purpose I/O lines, plus up to 10 input-only
lines in 80QFP
•
8MHz operation at 5V
•
Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
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General Description
Ordering Information
1.4 Ordering Information
Table 1-1. Device Ordering Information
Temperature
Package
Voltage
Range
Frequency
0 to +70°C
112-Pin TQFP
Single Tray
60 Pcs
XC68HC912D60PV8
–40 to +85°C
C
XC68HC912D60CPV8
4.5V–5.5V
8 MHz
–40 to +105°C
V
XC68HC912D60VPV8
–40 to +125°C
M*
XC68HC912D60MPV8
0 to +70°C
80-Pin QFP
Single Tray
84 Pcs
XC68HC912D60FU8
–40 to +85°C
C
XC68HC912D60CFU8
4.5V–5.5V
8 MHz
–40 to +105°C
V
XC68HC912D60VFU8
–40 to +125°C
M*
XC68HC912D60MFU8
0 to +70°C
112-Pin TQFP
Single Tray
60 Pcs
XC68HC12D60PV8
–40 to +85°C
C
XC68HC12D60CPV8
4.5V–5.5V
8 MHz
–40 to +105°C
V
XC68HC12D60VPV8
–40 to +125°C
M*
XC68HC12D60MPV8
0 to +70°C
80-Pin QFP
Single Tray
84 Pcs
Order Number
Designator
XC68HC12D60FU8
–40 to +85°C
C
XC68HC12D60CFU8
4.5V–5.5V
8 MHz
–40 to +105°C
V
XC68HC12D60VFU8
–40 to +125°C
M*
XC68HC12D60MFU8
* Important: M temperature operation is available only for single chip modes
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Table 1-2. 68HC(9)12D60 Development Tools Ordering Information
Description
Name
Freescale Semiconductor, Inc...
MCUez
Order Number
Free from World Wide Web
Serial Debug Interface
SDI
M68SDIL (3–5V), M68DIL12 (SDIL + MCUez +
SDBUG12)
Evaluation board
EVB
M68EVB912D60 (EVB only)
M68KIT912D60 (EVB + SDIL12)
NOTE:
SDBUG12 is a P & E Micro Product. It can be obtained from P & E from
their web site (http://www.pemicro.com) for approximately $100.
Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.html
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68HC(9)12D60 Block Diagrams
1.5 68HC(9)12D60 Block Diagrams
60K byte flash EEPROM *
60K byte ROM $
§
VFP*
VRH0
ATD0 VRL0
VRH0
VRL0
ATD1
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
VDDAD
VSSAD
VRH1
VRL1
VDDAD
VSSAD
VRH1
VRL1
VDDAD
VSSAD
SCI0 (MI BUS) RxD0
TxD0
SPI
PORT E
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1/CGMTST
DBE/CAL/ECLK
RxD1
TxD1
SCI1
SISO/MISO
MOMI/MOSI
SCK
SS
PW0
PW1
PW2
PW3
PWM
PORT S
Lite
integration
module
(LIM)
EXTAL
XTAL
RESET
Enhanced
capture
timer
PORT P
PLL
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
DDRS
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XFC
VDDPLL
VSSPLL
Periodic interrupt
COP watchdog
Clock monitor
Breakpoints
DDRP
Single-wire
background
debug module
BKGD
DDRT
I/O
Multiplexed Address/Data Bus
DDRG
PS4
PS5
PS6
PS7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PORTG
DDRH
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Narrow bus
PS0
PS1
PS2
PS3
TxCAN PCAN1
RxCAN PCAN0
CAN
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
PHPUD
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
I/O
PG7
KWG6
KWG5
KWG4
KWG3
KWG2
KWG1
KWG0
PGPUD
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PAD16
PAD17
PG7
PG6
PG5
PG4
VDD ×2
PG3
VSS ×2
PG2
PG1
PG0
Power for internal circuitry
PGPUD
PORTH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DDRB
PORT B
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Wide
bus
DDRA
PORT A
PORT AD1
CPU12
PORT T
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
1K byte EEPROM
PORT AD0
2K byte RAM
PH7
VDDX ×2
PH6
VSSX ×2
PH5
PH4
PH3
Power for I/O drivers
PH2
PH1
PH0
PHPUD
Notes: * 68HC912D60 only
$ 68HC12D60 only
§ On the 68HC12D60 this pin is not connected and can be tied to 5V or 12V without effect.
Figure 1-1. 68HC(9)12D60 112-pin QFP Block Diagram
68HC(9)12D60 — Rev 4.0
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Lite
integration
module
(LIM)
EXTAL
XTAL
RESET
PORT E
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1/CGMTST
DBE/CAL/ECLK
PORT AD0
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
SCI0 (MI BUS) RxD0
TxD0
RxD1
TxD1
SCI1
SPI
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
DDRT
PLL
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
PORT T
XFC
VDDPLL
VSSPLL
Enhanced
capture
timer
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
SISO/MISO
MOMI/MOSI
SCK
SS
PW0
PW1
PW2
PW3
PWM
DDRS
BKGD
Periodic interrupt
COP watchdog
Clock monitor
Breakpoints
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
PS0
PS1
PS2
PS3
PORT S
Single-wire
background
debug module
VRH0
VRL0
VDDAD
VSSAD
VRH0
VRL0
VDDAD
VSSAD
DDRP
CPU12
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
ATD0
PORT P
1K byte EEPROM
VRH1
VRL1
VDDAD
VSSAD
DDRCAN
2K byte RAM
ATD1
PORT CAN
60K byte flash EEPROM *
60K byte ROM $
§
PORT AD1
VFP*
PS4
PS5
PS6
PS7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
I/O
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
Multiplexed Address/Data Bus
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
PHPUD(VSS)
PORTG
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Narrow bus
PG7
KWG6
KWG5
KWG4
KWG3
KWG2
KWG1
KWG0
PGPUD(VDD)
DDRG
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Wide
bus
CAN
TxCAN PCAN1
RxCAN PCAN0
PG4
VDD ×2
VSS ×2
Power for internal circuitry
DDRH
PORT B
PORTH
PORT A
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRB
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
DDRA
PH4
VDDX ×2
VSSX ×2
Power for I/O drivers
Notes: * 68HC912D60 only
$ 68HC12D60 only
§ On the 68HC12D60 this pin is not connected and can be tied to 5V or 12V without effect.
Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. These internal pins should either be defined as outputs or have their pull-ups/downs enabled.
Figure 1-2. 68HC(9)12D60 80-pin QFP Block Diagram
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Section 2. Central Processing Unit
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.6
Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2 Introduction
The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data
paths and wider internal registers (up to 20 bits) for high-speed extended
math instructions. The instruction set is a proper superset of the
M68HC11instruction set. The CPU12 allows instructions with odd byte
counts, including many single-byte instructions. This provides efficient
use of ROM space. An instruction queue buffers program information so
the CPU always has immediate access to at least three bytes of machine
code at the start of every instruction. The CPU12 also offers an
extensive set of indexed addressing capabilities.
2.3 Programming Model
CPU12 registers are an integral part of the CPU and are not addressed
as if they were memory locations.
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Central Processing Unit
7
A
0 7
B
0
8-BIT ACCUMULATORS A & B
Freescale Semiconductor, Inc...
OR
15
D
0
16-BIT DOUBLE ACCUMULATOR D
15
IX
0
INDEX REGISTER X
15
IY
0
INDEX REGISTER Y
15
SP
0
STACK POINTER
15
PC
0
PROGRAM COUNTER
S X H I N Z V C
CONDITION CODE REGISTER
Figure 2-1. Programming Model
Accumulators A and B are general-purpose 8-bit accumulators used to
hold operands and results of arithmetic calculations or data
manipulations. Some instructions treat the combination of these two 8bit accumulators as a 16-bit double accumulator (accumulator D).
Index registers X and Y are used for indexed addressing mode. In the
indexed addressing mode, the contents of a 16-bit index register are
added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator
to form the effective address of the operand to be used in the instruction.
Stack pointer (SP) points to the last stack location used. The CPU12
supports an automatic program stack that is used to save system
context during subroutine calls and interrupts, and can also be used for
temporary storage of data. The stack pointer can also be used in all
indexed addressing modes.
Program counter is a 16-bit register that holds the address of the next
instruction to be executed. The program counter can be used in all
indexed addressing modes except autoincrement/decrement.
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Central Processing Unit
Data Types
Condition Code Register (CCR) contains five status indicators, two
interrupt masking bits, and a STOP disable bit. The five flags are half
carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The
half-carry flag is used only for BCD arithmetic operations. The N, Z, V,
and C status bits allow for branching based on the results of a previous
operation.
After a reset, the CPU fetches a vector from the appropriate address and
begins executing instructions. The X and I interrupt mask bits are set to
mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
2.4 Data Types
The CPU12 supports the following data types:
•
Bit data
•
8-bit and 16-bit signed and unsigned integers
•
16-bit unsigned fractions
•
16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. There are no special requirements for
alignment of instructions or operands.
2.5 Addressing Modes
Addressing modes determine how the CPU accesses memory locations
to be operated upon. The CPU12 includes all of the addressing modes
of the M68HC11 CPU as well as several new forms of indexed
addressing. Table 2-1 is a summary of the available addressing modes.
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Central Processing Unit
Table 2-1. M68HC12 Addressing Mode Summary
Addressing Mode
Source Format
Abbreviation
Description
Inherent
INST
(no externally
supplied operands)
INH
Operands (if any) are in CPU registers
Immediate
INST #opr8i
or
INST #opr16i
IMM
Operand is included in instruction stream
8- or 16-bit size implied by context
Direct
INST opr8a
DIR
Operand is the lower 8-bits of an address in
the range $0000 – $00FF
Extended
INST opr16a
EXT
Operand is a 16-bit address
Relative
INST rel8
or
INST rel16
REL
An 8-bit or 16-bit relative offset from the
current pc is supplied in the instruction
Indexed
(5-bit offset)
INST oprx5,xysp
IDX
5-bit signed constant offset from x, y, sp, or
pc
Indexed
(auto pre-decrement)
INST oprx3,–xys
IDX
Auto pre-decrement x, y, or sp by 1 ~ 8
Indexed
(auto pre-increment)
INST oprx3,+xys
IDX
Auto pre-increment x, y, or sp by 1 ~ 8
Indexed
(auto post-decrement)
INST oprx3,xys–
IDX
Auto post-decrement x, y, or sp by 1 ~ 8
Indexed
(auto post-increment)
INST oprx3,xys+
IDX
Auto post-increment x, y, or sp by 1 ~ 8
Indexed
(accumulator offset)
INST abd,xysp
IDX
Indexed with 8-bit (A or B) or 16-bit (D)
accumulator offset from x, y, sp, or pc
Indexed
(9-bit offset)
INST oprx9,xysp
IDX1
9-bit signed constant offset from x, y, sp, or
pc
(lower 8-bits of offset in one extension byte)
Indexed
(16-bit offset)
INST oprx16,xysp
IDX2
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(16-bit offset)
INST [oprx16,xysp]
[IDX2]
Pointer to operand is found at...
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Indexed-Indirect
(D accumulator offset)
INST [D,xysp]
[D,IDX]
Pointer to operand is found at...
x, y, sp, or pc plus the value in D
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Indexed Addressing Modes
2.6 Indexed Addressing Modes
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The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do the following tasks:
•
Specify which index register is used.
•
Determine whether a value in an accumulator is used as an offset.
•
Enable automatic pre- or post-increment or decrement
•
Specify use of 5-bit, 9-bit, or 16-bit signed offsets.
Table 2-2. Summary of Indexed Operations
Source
Code
Syntax
Postbyte
Code (xb)
,r
rr0nnnnn
n,r
–n,r
Comments
5-bit constant offset n = –16 to +15
rr can specify X, Y, SP, or PC
111rr0zs
n,r
–n,r
Constant offset (9- or 16-bit signed)
z-0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
111rr011
[n,r]
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
rr1pnnnn
n,–r n,+r
n,r– n,r+
Auto pre-decrement/increment or Auto postdecrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
111rr1aa
A,r
B,r
D,r
Accumulator offset (unsigned 8-bit or 16-bit)
aa-00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
111rr111
[D,r]
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
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2.7 Opcodes and Operands
The CPU12 uses 8-bit opcodes. Each opcode identifies a particular
instruction and associated addressing mode to the CPU. Several
opcodes are required to provide each instruction with a range of
addressing capabilities.
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Only 256 opcodes would be available if the range of values were
restricted to the number that can be represented by 8-bit binary
numbers. To expand the number of opcodes, a second page is added to
the opcode map. Opcodes on the second page are preceded by an
additional byte with the value $18.
To provide additional addressing flexibility, opcodes can also be
followed by a postbyte or extension bytes. Postbytes implement certain
forms of indexed addressing, transfers, exchanges, and loop primitives.
Extension bytes contain additional program information such as
addresses, offsets, and immediate data.
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68HC(9)12D60 — Rev 4.0
Central Processing Unit
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Section 3. Pinout and Signal Descriptions
Freescale Semiconductor, Inc...
3.1 Contents
3.2
68HC(9)12D60 Pin Assignments in 112-pin QFP. . . . . . . . . . . 38
3.3
68HC(9)12D60 Pin Assignments in 80-pin QFP. . . . . . . . . . . . 40
3.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.5
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
68HC(9)12D60 — Rev 4.0
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Pinout and Signal Descriptions
68HC(9)12D60
112TQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PAD17/AN17
PAD07/AN07
PAD16/AN16
PAD06/AN06
PAD15/AN15
PAD05/AN05
PAD14/AN14
PAD04/AN04
PAD13/AN13
PAD03/AN03
PAD12/AN12
PAD02/AN02
PAD11/AN11
PAD01/AN01
PAD10/AN10
PAD00/AN00
VRL0
VRH0
VSS
VDD
PA7/ADDR15/DATA15/DATA7
PA6/ADDR14/DATA14/DATA6
PA5/ADDR13/DATA13/DATA5
PA4/ADDR12/DATA12/DATA4
PA3/ADDR11/DATA11/DATA3
PA2/ADDR10/DATA10/DATA2
PA1/ADDR9/DATA9/DATA1
PA0/ADDR8/DATA8/DATA0
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
KWH7/PH7
KWH6/PH6
KWH5/PH5
KWH4/PH4
ECLK/DBE/CAL/PE7
CGMTST/MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSX
PHUPD
VDDX
VDDPLL
XFC
VSSPLL
RESET
EXTAL
XTAL
KWH3/PH3
KWH2/PH2
KWH1/PH1
KWH0/PH0
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
Freescale Semiconductor, Inc...
PW2/PP2
PW1/PP1
PW0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
PG7
KWG6/PG6
KWG5/PG5
KWG4/PG4
VDD
PGUPD
VSS
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
KWG3/PG3
KWG2/PG2
KWG1/PG1
KWG0/PG0
SMODN/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP3/PW3
PP4
PP5
PP6
PP7
VDDX
VSSX
PCAN0/RxCAN
PCAN1/TxCAN
PCAN2
PCAN3
PCAN4
PCAN5
PCAN6
PCAN7
VFP*
PS7/SS
PS6/SCK
PS5/SDO/MOSI
PS4/SDI/MISO
PS3/TxD1
PS2/RxD1
PS1/TxD0
PS0/RxD0
VSSA
VRL1
VRH1
VDDA
3.2 68HC(9)12D60 Pin Assignments in 112-pin QFP
Figure 3-1. Pin Assignments in 112-pin TQFP for 68HC(9)12D60
* Available on 68HC912D60 only. On the 68HC12D60 this pin is not
connected and can be tied to 5V or 12V without effect.
Advance Information
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68HC(9)12D60 — Rev 4.0
Pinout and Signal Descriptions
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Pinout and Signal Descriptions
68HC(9)12D60 Pin Assignments in 112-pin QFP
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
X
X=L, M OR N
G
VIEW Y
B
L
V
M
B1
28
AA
J
V1
57
29
F
D
56
0.13
N
M
T
BASE
METAL
L-M N
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
S1
A
S
C2
C
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
θ1
E
(Y)
(Z)
VIEW AB
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MAX
MIN
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--1.600
0.050
0.150
1.350
1.450
0.270
0.370
0.450
0.750
0.270
0.330
0.650 BSC
0.090
0.170
0.500 REF
0.325 BSC
0.100
0.200
0.100
0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090
0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure 3-2. 112-pin TQFP Mechanical Dimensions (case no. 987)
68HC(9)12D60 — Rev 4.0
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80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PP3/PW3
PP4
PP5
PP6
PP7
VDDX
VSSX
PCAN0/RxCAN
PCAN1/TxCAN
VFP*
PS7/SS
PS6/SCK
PS5/SDO/MOSI
PS4/SDI/MISO
PS3/TxD1
PS2/RxD1
PS1/TxD0
PS0/RxD0
VSSAD
VDDAD
3.3 68HC(9)12D60 Pin Assignments in 80-pin QFP
68HC(9)12D60
80 QFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VRL0
VRH0
VSS
VDD
PA7/ADDR15/DATA15/DATA7
PA6/ADDR14/DATA14/DATA6
PA5/ADDR13/DATA13/DATA5
PA4/ADDR12/DATA12/DATA4
PA3/ADDR11/DATA11/DATA3
PA2/ADDR10/DATA10/DATA2
PA1/ADDR9/DATA9/DATA1
PA0/ADDR8/DATA8/DATA0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
KWH4/PH4
ECLK/DBE/CAL/PE7
CGMTST/MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSX
VDDX
VDDPLL
XFC
VSSPLL
RESET
EXTAL
XTAL
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
Freescale Semiconductor, Inc...
PW2/PP2
PW1/PP1
PW0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
KWG4/PG4
VDD
VSS
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
SMODN/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Figure 3-3. Pin Assignments in 80-pin QFP for 68HC(9)12D60
* Available on 68HC912D60 only. On the 68HC12D60 this pin is not
connected and can be tied to 5V or 12V without effect.
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68HC(9)12D60 — Rev 4.0
Pinout and Signal Descriptions
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68HC(9)12D60 Pin Assignments in 80-pin QFP
L
60
41
61
D
S
M
V
P
B
C A-B
D
M
B
B
-A-,-B-,-D-
0.20
L
0.05 D
-B-
H A-B
-A-
S
S
S
40
0.20
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
DETAIL A
DETAIL A
21
80
1
0.20
A
H A-B
M
S
F
20
-DD
S
0.05 A-B
J
S
0.20
C A-B
M
S
D
S
D
M
E
DETAIL C
C
-H-
-C-
DATUM
PLANE
0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90 °
0.10
H
SEATING
PLANE
N
M
G
U
T
DATUM
PLANE
-H-
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
13.90
14.10
13.90
14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10 °
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95
17.45
0.13
--0°
--16.95
17.45
0.35
0.45
1.6 REF
Figure 3-4. 80-pin QFP Mechanical Dimensions (case no. 841B)
68HC(9)12D60 — Rev 4.0
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Pinout and Signal Descriptions
3.4 Power Supply Pins
68HC(9)12D60 power and ground pins are described below and
summarized in Table 3-1.
3.4.1 Internal Power (VDD) and Ground (VSS)
Power is supplied to the MCU through VDD and VSS. Because fast signal
transitions place high, short-duration current demands on the power
supply, use bypass capacitors with high-frequency characteristics and
place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
3.4.2 External Power (VDDX) and Ground (VSSX)
External power and ground for I/O drivers. Because fast signal
transitions place high, short-duration current demands on the power
supply, use bypass capacitors with high-frequency characteristics and
place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
3.4.3 VDDA, VSSA
Provides operating voltage and ground for the analog-to-digital
converter. This allows the supply voltage to the ATD to be bypassed
independently. Connecting VDDA to VDD if the ATD modules are not
used will not result in an increase of power consumption.
3.4.4 Analog to Digital Reference Voltages (VRH, VRL)
VRH0, VRL0: reference voltage high and low for ATD converter 0.
VRH1, VRL1: reference voltage high and low for ATD converter 1.
If the ATD modules are not used, leaving VRH connected to VDD will not
result in an increase of power consumption.
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68HC(9)12D60 — Rev 4.0
Pinout and Signal Descriptions
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Pinout and Signal Descriptions
Power Supply Pins
3.4.5 VDDPLL, VSSPLL
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed independently.
NOTE:
The VSSPLL pin should always be grounded even if the PLL is not used.
The VDDPLL pin should not be left floating. It is recommended to
connect the VDDPLL pin to ground if the PLL is not used.
3.4.6 XFC
PLL loop filter. Please see Appendix: CGM Practical Aspects for
information on how to calculate PLL loop filter elements. Any current
leakage on this pin must be avoided.
VDDPLL
C0
MCU
R0
Cp
XFC
Figure 3-5. PLL Loop FIlter Connections
If VDDPLL is connected to VSS (this is normal case), then the XFC pin
should either be left floating or connected to VSS (never to VDD). If
VDDPLL is tied to VDD but the PLL is switched off (PLLON bit cleared),
then the XFC pin should be connected preferably to VDDPLL (i.e. ready
for VCO minimum frequency).
3.4.7 VFP
Flash EEPROM programming voltage and supply voltage during normal
operation (68HC912D60 only – on the 68HC12D60 this pin is not
connected and can be tied to 5V or 12V without effect).
68HC(9)12D60 — Rev 4.0
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Pinout and Signal Descriptions
Table 3-1. 68HC(9)12D60 Power and Ground Connection Summary
Pin Number
Mnemonic
80-pin
QFP
112-pin
QFP
VDD
9, 49
12, 65
VSS
10, 50
14, 66
VDDX
30, 75
42, 107
VSSX
29, 74
40, 106
VDDA
61
85
VSSA
62
88
VRH1
—
86
VRL1
—
87
VRH0
51
67
VRL0
52
68
VDDPLL
31
43
VSSPLL
33
45
Description
Internal power and ground.
External power and ground, supply to pin drivers.
Operating voltage and ground for the analog-to-digital
converter, allows the supply voltage to the A/D to be
bypassed independently.
Reference voltages for the analog-to-digital converter 1
Reference voltages for the analog-to-digital converter 0.
VFP
71
97
Provides operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be
bypassed independently.
Programming voltage for the Flash EEPROM and required
supply for normal operation. (68HC912D60 only – on the
68HC12D60 this pin is not connected and can be tied to 5V
or 12V without effect)
3.5 Signal Descriptions
3.5.1 Crystal Driver and External Clock Input (XTAL, EXTAL)
These pins provide the interface for either a crystal or a CMOS
compatible clock to control the internal clock generator circuitry. Out of
reset the frequency applied to EXTAL is twice the desired E–clock rate.
All the device clocks are derived from the EXTAL input frequency.
NOTE:
CRYSTAL CIRCUIT IS CHANGED FROM STANDARD.
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Pinout and Signal Descriptions
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Pinout and Signal Descriptions
Signal Descriptions
NOTE:
The internal return path for the oscillator is the VSSPLL pin. Therefore it
is recommended to connect the common node of the resonator and the
capacitor directly to the VSSPLL pin.
2 x E crystal or ceramic resonator
EXTAL
MCU
C
C
Freescale Semiconductor, Inc...
XTAL
Figure 3-6. Common Crystal Connections
NOTE:
When selecting a crystal, it is recommended to use one with the lowest
possible frequency in order to minimise EMC emissions.
2 xE
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
EXTAL
MCU
XTAL
NC
Figure 3-7. External Oscillator Connections
XTAL is the crystal output.The XTAL pin must be left unterminated when
an external CMOS compatible clock input is connected to the EXTAL
pin. The XTAL output is normally intended to drive only a crystal. The
XTAL output can be buffered with a high-impedance buffer to drive the
EXTAL input of another device.
In all cases take extra care in the circuit board layout around the
oscillator pins. Load capacitances in the oscillator circuits include all
stray layout capacitances. Refer to Figure 3-6 and Figure 3-7 for
diagrams of oscillator circuits.
68HC(9)12D60 — Rev 4.0
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Pinout and Signal Descriptions
3.5.2 E-Clock Output (ECLK)
ECLK is the output connection for the internal bus clock and is used to
demultiplex the address and data and is used as a timing reference.
ECLK frequency is equal to 1/2 the crystal frequency out of reset. The Eclock output is turned off in single chip user mode to reduce the effects
of RFI. It can be turned on if necessary. In single-chip special mode, the
E-clock is turned ON at reset and can be turned OFF. In special
peripheral mode the E-clock is an input to the MCU. All clocks, including
the E clock, are halted when the MCU is in STOP mode. It is possible to
configure the MCU to interface to slow external memory. ECLK can be
stretched for such accesses.
3.5.3 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to
initialize the MCU to a known start-up state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the
clock monitor or COP watchdog circuit. The MCU goes into reset
asynchronously and comes out of reset synchronously. This allows the
part to reach a proper reset state even if the clocks have failed, while
allowing synchronized operation when starting out of reset.
It is important to use an external low-voltage reset circuit (such as
MC34064 or MC34164) to prevent corruption of RAM or EEPROM due
to power transitions.
The reset sequence is initiated by any of the following events:
•
Power-on-reset (POR)
•
COP watchdog enabled and watchdog timer times out
•
Clock monitor enabled and Clock monitor detects slow or stopped
clock
•
User applies a low level to the reset pin
External circuitry connected to the reset pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within nine bus cycles after the low drive is released.
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Pinout and Signal Descriptions
Signal Descriptions
Upon detection of any reset, an internal circuit drives the reset pin low
and a clocked reset sequence controls when the MCU can begin normal
processing. In the case of POR or a clock monitor error, a 4096 cycle
oscillator startup delay is imposed before the reset recovery sequence
starts (reset is driven low throughout this 4096 cycle delay). The internal
reset recovery sequence then drives reset low for 16 to 17 cycles and
releases the drive to allow reset to rise. Nine cycles later this circuit
samples the reset pin to see if it has risen to a logic one level. If reset is
low at this point, the reset is assumed to be coming from an external
request and the internally latched states of the COP timeout and clock
monitor failure are cleared so the normal reset vector ($FFFE:FFFF) is
taken when reset is finally released. If reset is high after this nine cycle
delay, the reset source is tentatively assumed to be either a COP failure
or a clock monitor fail. If the internally latched state of the clock monitor
fail circuit is true, processing begins by fetching the clock monitor vector
($FFFC:FFFD). If no clock monitor failure is indicated, and the latched
state of the COP timeout is true, processing begins by fetching the COP
vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are
pending, processing begins by fetching the normal reset vector
($FFFE:FFFF).
3.5.4 Maskable Interrupt Request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or levelsensitive triggering is program selectable (INTCR register). IRQ is
always enabled and configured to level-sensitive triggering at reset. It
can be disabled by clearing the IRQEN bit (INTCR register). When the
MCU is reset the IRQ function is masked in the condition code register.
This pin is always an input and can always be read. There is an active
pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPE in the PUCR register.
68HC(9)12D60 — Rev 4.0
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Pinout and Signal Descriptions
3.5.5 Nonmaskable Interrupt (XIRQ)
The XIRQ input provides a means of requesting a nonmaskable interrupt
after reset initialization. During reset, the X bit in the condition code
register (CCR) is set and any interrupt is masked until MCU software
enables it. Because the XIRQ input is level sensitive, it can be connected
to a multiple-source wired-OR network. This pin is always an input and
can always be read. There is an active pull-up on this pin while in reset
and immediately out of reset. The pull-up can be turned off by clearing
PUPE in the PUCR register. XIRQ is often used as a power loss detect
interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ
must be configured for level-sensitive operation if there is more than one
source of IRQ interrupt), each source must drive the interrupt input with
an open-drain type of driver to avoid contention between outputs. There
must also be an interlock mechanism at each interrupt source so that the
source holds the interrupt line low until the MCU recognizes and
acknowledges the interrupt request. If the interrupt line is held low, the
MCU will recognize another interrupt as soon as the interrupt mask bit in
the MCU is cleared (normally upon return from an interrupt).
3.5.6 Mode Select (SMODN, MODA, and MODB)
The state of these pins during reset determine the MCU operating mode.
After reset, MODA and MODB can be configured as instruction queue
tracking signals IPIPE0 and IPIPE1. MODA and MODB have active pulldowns during reset.
The SMODN pin has an active pull-up when configured as input. This pin
can be used as BKGD or TAGHI after reset.
3.5.7 Single-Wire Background Mode Pin (BKGD)
The BKGD pin receives and transmits serial background debugging
commands. A special self-timing protocol is used. The BKGD pin has an
active pull-up when configured as input; BKGD has no pull-up control.
Refer to Development Support.
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3.5.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])
External bus pins share function with general-purpose I/O ports A and B.
In single-chip operating modes, the pins can be used for I/O; in
expanded modes, the pins are used for the external buses.
In expanded wide mode, ports A and B are used for multiplexed 16-bit
data and address buses. PA[7:0] correspond to
ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].
In expanded narrow mode, ports A and B are used for the16-bit address
bus, and an 8-bit data bus is multiplexed with the most significant half of
the address bus on port A. In this mode, 16-bit data is handled as two
back-to-back bus cycles, one for the high byte followed by one for the
low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or
DATA[7:0], depending on the bus cycle. The state of the address pin
should be latched at the rising edge of E. To allow for maximum address
setup time at external devices, a transparent latch should be used.
3.5.9 Read/Write (R/W)
In all modes this pin can be used as general-purpose I/O and is an input
with an active pull-up out of reset. If the read/write function is required it
should be enabled by setting the RDWE bit in the PEAR register.
External writes will not be possible until enabled.
3.5.10 Low-Byte Strobe (LSTRB)
In all modes this pin can be used as general-purpose I/O and is an input
with an active pull-up out of reset. If the strobe function is required, it
should be enabled by setting the LSTRE bit in the PEAR register. This
signal is used in write operations and so external low byte writes will not
be possible until this function is enabled. This pin is also used as TAGLO
in Special Expanded modes and is multiplexed with the LSTRB function.
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3.5.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
These signals are used to track the state of the internal instruction
execution queue. Execution state is time-multiplexed on the two signals.
Refer to Development Support.
3.5.12 Data Bus Enable (DBE)
The DBE pin (PE7) is an active low signal that will be asserted low during
E-clock high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last E-clock cycle of stretch. In expanded modes this pin is used
to enable the drive control of external buses during external reads. Use
of the DBE is controlled by the NDBE bit in the PEAR register.DBE is
enabled out of reset in expanded modes. This pin has an active pull-up
during and after reset in single chip modes.
3.5.13 Inverted E clock (ECLK)
The ECLK pin (PE7) can be used to latch the address for demultiplexing. It has the same behavior as the ECLK, except is inverted.
In expanded modes this pin is used to enable the drive control of external
buses during external reads. Use of the ECLK is controlled by the NDBE
and DBENE bits in the PEAR register.
3.5.14 Calibration reference (CAL)
The CAL pin (PE7) is the output of the Slow Mode programmable clock
divider, SLWCLK, and is used as a calibration reference. The SLWCLK
frequency is equal to the crystal frequency out of reset and always has
a 50% duty. If the DBE function is enabled it will override the enabled
CAL output. The CAL pin output is disabled by clearing CALE bit in the
PEAR register.
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3.5.15 Clock generation module test (CGMTST)
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested.
Table 3-2. 68HC(9)12D60 Signal Description Summary
Pin Name
Pin Number
Description
80-pin
112-pin
EXTAL
35
47
XTAL
36
48
RESET
34
46
ADDR[7:0]
DATA[7:0]
23–16
31–24
ADDR[15:8]
DATA[15:8]
48–41
64–57
DBE
25
36
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
ECLK
25
36
Inverted E clock used to latch the address.
CAL
25
36
CAL is the output of the Slow Mode programmable clock divider, SLWCLK,
and is used as a calibration reference for functions such as time of day. It is
overridden when DBE function is enabled. It always has a 50% duty cycle.
CGMTST
26
37
Clock generation module test output.
MODB/
IPIPE1,
MODA/
IPIPE0
26, 27
37, 38
State of mode select pins during reset determine the initial operating mode of
the MCU. After reset, MODB and MODA can be configured as instruction
queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
ECLK
28
39
E Clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
Crystal driver and external clock input pins. On reset all the device clocks are
derived from the EXTAL input frequency. XTAL is the crystal output.
An active low bidirectional control signal, RESET acts as an input to initialize
the MCU to a known start-up state, and an output when COP or clock
monitor causes a reset.
External bus pins share function with general-purpose I/O ports A and B. In
single chip modes, the pins can be used for I/O. In expanded modes, the
pins are used for the external buses.
LSTRB/
TAGLO
37
53
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O.
The low strobe function is the exclusive-NOR of A0 and the internal SZ8
signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin function
TAGLO used in instruction tagging. See Development Support.
R/W
38
54
Indicates direction of data on expansion bus. Shares function with generalpurpose I/O. Read/write in expanded modes.
IRQ
39
55
Maskable interrupt request input provides a means of applying asynchronous
interrupt requests to the MCU. Either falling edge-sensitive triggering or
level-sensitive triggering is program selectable (INTCR register).
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Table 3-2. 68HC(9)12D60 Signal Description Summary
Pin Name
XIRQ
Pin Number
Description
80-pin
112-pin
40
56
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
Single-wire background interface pin is dedicated to the background debug
function. During reset, this pin determines special or normal operating
mode. Pin function TAGHI used in instruction tagging. See Development
Support.
SMODN/BK
GD/TAGHI
15
23
PW[3:0]
80, 1–3
112, 1–3
SS
70
96
Slave select output for SPI master mode, input for slave mode or master
mode.
SCK
69
95
Serial clock for SPI system.
SDO/MOSI
68
94
Master out/slave in pin for serial peripheral interface
SDI/MISO
67
93
Master in/slave out pin for serial peripheral interface
TxD1
66
92
SCI1 transmit pin
RxD1
65
91
SCI1 receive pin
TxD0
64
90
SCI0 transmit pin
RxD0
63
89
SCI0 receive pin
IOC[7:0]
14–11,
7–4
18–15, 7–4
AN1[7:0]
N/A
84/82/80/78/
Analog inputs for the analog-to-digital conversion module 1
76/74/72/70
AN0[7:0]
60–53
83/81/79/77/
Analog inputs for the analog-to-digital conversion module 0
75/73/71/69
TxCAN
72
104
MSCAN transmit pin
RxCAN
73
105
MSCAN receive pin
KWG[6:0]
Pulse Width Modulator channel outputs.
Pins used for input capture and output compare in the timer and pulse
accumulator subsystem.
8 (KWG4
Key wake-up and general purpose I/O; can cause an interrupt when an input
9–11, 19–22
only)
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.
PGUPD
(1)
13
KWH[7:0]
24 (KWH4
only)
32–35,
49–52
PHUPD
(2)
41
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
Key wake-up and general purpose I/O; can cause an interrupt when an input
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
1. In the 80-pin version PGUPD is connected internally to VDD
2. In the 80-pin version PHUPD is connected internally to VSS
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Port Signals
3.6 Port Signals
The 68HC(9)12D60 incorporates eight ports which are used to control
and access the various device subsystems. When not used for these
purposes, port pins may be used for general-purpose I/O. In addition to
the pins described below, each port consists of a data register which can
be read and written at any time, and, with the exception of port AD0, port
AD1 (available only in 112TQFP), PE[1:0], RxCAN and TxCAN, a data
direction register which controls the direction of each pin. After reset all
general purpose I/O pins are configured as input.
3.6.1 Port A
Port A pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as I/O. The port data register is not in
the address map during expanded and peripheral mode operation.
When it is in the map, port A can be read or written at anytime.
Register DDRA determines whether each port A pin is an input or output.
DDRA is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRA makes the corresponding bit in port A
an output; clearing a bit in DDRA makes the corresponding bit in port A
an input. The default reset state of DDRA is all zeros.
When the PUPA bit in the PUCR register is set, all port A input pins are
pulled-up internally by an active pull-up device. This bit has no effect if
the port is being used in expanded modes as the pull-ups are inactive.
Setting the RDPA bit in register RDRIV causes all port A outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
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3.6.2 Port B
Port B pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as I/O. The port data register is not in
the address map during expanded and peripheral mode operation.
When it is in the map, port B can be read or written at anytime.
Register DDRB determines whether each port B pin is an input or output.
DDRB is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRB makes the corresponding bit in port B
an output; clearing a bit in DDRB makes the corresponding bit in port B
an input. The default reset state of DDRB is all zeros.
When the PUPB bit in the PUCR register is set, all port B input pins are
pulled-up internally by an active pull-up device. This bit has no effect if
the port is being used in expanded modes as the pull-ups are inactive.
Setting the RDPB bit in register RDRIV causes all port B outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
3.6.3 Port E
Port E pins operate differently from port A and B pins. Port E pins are
used for bus control signals and interrupt service request signals. When
a pin is not used for one of these specific functions, it can be used as
general-purpose I/O. However, two of the pins (PE[1:0]) can only be
used for input, and the states of these pins can be read in the port data
register even when they are used for IRQ and XIRQ.
The PEAR register determines pin function, and register DDRE
determines whether each pin is an input or output when it is used for
general-purpose I/O. PEAR settings override DDRE settings. Because
PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in
the DDRE register makes the corresponding bit in port E an output;
clearing a bit in the DDRE register makes the corresponding bit in port E
an input. The default reset state of DDRE is all zeros.
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Port Signals
When the PUPE bit in the PUCR register is set, PE7 and PE[3:0] are
pulled up by active devices.
Neither port E nor DDRE is in the map in peripheral mode; neither is in
the internal map in expanded modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
3.6.4 Port G
Port G pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with a
falling edge signal (KWPG). An interrupt is generated if the
corresponding bit is enabled (KWIEG). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to I/O Ports with Key Wake-up.
Register DDRG determines pin direction of port G when used for
general-purpose I/O. When DDRG bits are set, the corresponding pin is
configured for output. On reset the DDRG bits are cleared and the
corresponding pin is configured for input.
Port PGUPD determines what type of resistive load is used for port G
input pins when PUPG bit is set in the PUCR register. When PGUPD pin
is low, it loads a pull-down in all port G input pins. When PGUPD pin is
high, it loads a pull-up in all port G input pins.
In 80-pin version, the PGUPD is connected internally to VDD. The PG4
will have a pull-up. All port G pins should either be defined as outputs or
have their pull-ups enabled.
Setting the RDPG bit in register RDRIV causes all port G outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
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3.6.5 Port H
Port H pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with a
falling edge signal (KWPH). An interrupt is generated if the
corresponding bit is enabled (KWIEH). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to I/O Ports with Key Wake-up.
Register DDRH determines pin direction of Port H when used for
general-purpose I/O. When DDRH bits are set, the corresponding pin is
configured for output. On reset the DDRH bits are cleared and the
corresponding pin is configured for input.
Port PHUPD determines what type of resistive load is used for Port H
input pins when PUPH bit is set in the PUCR register. When PHUPD pin
is low, it loads a pull-down in all Port H input pins. When PHUPD pin is
high, it loads a pull-up in all Port H input pins.
In 80-pin version, the PHUPD is connected internally to VSS. The PH4
will have a pull-down. All port H pins should either be defined as outputs
or have their pull-downs enabled.
Setting the RDPH bit in register RDRIV causes all Port H outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
3.6.6 Port CAN
The MSCAN12 uses two external pins, one input (RxCAN) and one
output (TxCAN). The TxCAN output pin represents the logic level on the
CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.
RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins
of Port CAN, available only in the 112-pin package, are controlled by
registers in the MSCAN12 address space.
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
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Port Signals
3.6.7 Port AD1
Input to the analog-to-digital subsystem and general-purpose input.
When analog-to-digital functions are not enabled, the port has eight
general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2
register enables the A/D function.
Port AD1 pins are inputs; no data direction register is associated with this
port. The port has no resistive input loads and no reduced drive controls.
Refer to Analog-to-Digital Converter.
Port AD1 is not available in the 80-pin package.
3.6.8 Port AD0
Input to the analog-to-digital subsystem and general-purpose input.
When analog-to-digital functions are not enabled, the port has eight
general-purpose input pins, PAD0[7:0]. The ADPU bit in the ATD0CTL2
register enables the A/D function.
Port AD0 pins are inputs; no data direction register is associated with this
port. The port has no resistive input loads and no reduced drive controls.
Refer to Analog-to-Digital Converter.
3.6.9 Port P
The four pulse-width modulation channel outputs share general-purpose
port P pins. The PWM function is enabled with the PWEN register.
Enabling PWM pins takes precedence over the general-purpose port.
When pulse-width modulation is not in use, the port pins may be used for
general-purpose I/O.
Register DDRP determines pin direction of port P when used for
general-purpose I/O. When DDRP bits are set, the corresponding pin is
configured for output. On reset the DDRP bits are cleared and the
corresponding pin is configured for input.
When the PUPP bit in the PWCTL register is set, all input pins are pulled
up internally by an active pull-up device. Pull-ups are disabled after
reset.
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Setting the RDPP bit in the PWCTL register configures all port P outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The PWCTL register can be read or written anytime after reset.
Refer to Pulse Width Modulator.
3.6.10 Port S
Port S is the 8-bit interface to the standard serial interface consisting of
the two serial communications interfaces (SCI1 and SCI0) and the serial
peripheral interface (SPI) subsystems. Port S pins are available for
general-purpose parallel I/O when standard serial functions are not
enabled.
Port S pins serve several functions depending on the various internal
control registers. If WOMS bit in the SC0CR1register is set, the Pchannel drivers of the output buffers are disabled for bits 0 through 1 for
the SCSI1 (2 through 3 for the SCI0). If SWOM bit in the SP0CR1
register is set, the P-channel drivers of the output buffers are disabled
for bits 4 through 7 (wire-ORed mode). The open drain control effects to
both the serial and the general-purpose outputs. If the RDPSx bits in the
PURDS register are set, the appropriate Port S pin drive capabilities are
reduced. If PUPSx bits in the PURDS register are set, the appropriate
pull-up device is connected to each port S pin which is programmed as
a general-purpose input. If the pin is programmed as a general-purpose
output, the pull-up is disconnected from the pin regardless of the state of
the individual PUPSx bits. See Multiple Serial Interface.
3.6.11 Port T
This port provides eight general-purpose I/O pins when not enabled for
input capture and output compare in the timer and pulse accumulator
subsystem. The TEN bit in the TSCR register enables the timer function.
The pulse accumulator subsystem is enabled with the PAEN bit in the
PACTL register.
Register DDRT determines pin direction of port T when used for generalpurpose I/O. When DDRT bits are set, the corresponding pin is
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configured for output. On reset the DDRT bits are cleared and the
corresponding pin is configured for input.
When the PUPT bit in the TMSK2 register is set, all input pins are pulled
up internally by an active pull-up device. Pull-ups are disabled after
reset.
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Setting the RDPT bit in the TMSK2 register configures all port T outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The TMSK2 register can be read or written anytime after reset
Refer to Enhanced Capture Timer.
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Table 3-3. 68HC(9)12D60 Port Description Summary
Pin Numbers
Port Name
80-pin
112-pin
Port A
PA[7:0]
48–41
64–57
Port B
PB[7:0]
23–16
31–24
Data Direction
Register
(Address)
In/Out
DDRA ($0002)
In/Out
DDRB ($0003)
Description
Port A and port B pins are used for address and data in
expanded modes. The port data registers are not in the
address map during expanded and peripheral mode
operation. When in the map, port A and port B can be
read or written any time.
DDRA and DDRB are not in the address map in expanded
or peripheral modes.
Port AD1
PAD1[7:0]
Port AD0
PAD0[7:0]
Port CAN
PCAN[7:0]
84/82/80
/78/76/7
4/72/70
83/81/79
60–53 /77/75/7
3/71/69
N/A
72, 73(1) 98–105
In
Analog-to-digital converter 1 and general-purpose I/O.
In
Analog-to-digital converter 0 and general-purpose I/O.
In/Out
General purpose I/O. PCAN[1:0] are used with the
MSCAN12 module and cannot be used as I/O.
Port E
PE[7:0]
25–28,
37–40
36–39,
53–56
PE[1:0] In
PE[7:2] In/Out
DDRE ($0009)
Mode selection, bus control signals and interrupt service
request signals; or general-purpose I/O.
Port P
PP[7:0]
76–80,
1–3
108–112
,
1–3
In/Out
DDRP ($0057)
General-purpose I/O. PP[3:0] are used with the pulse-width
modulator when enabled.
Port S
PS[7:0]
70–63
96–89
In/Out
DDRS ($00D7)
Port T
PT[7:0]
14–11,
7–4
18–15,
7–4
In/Out
DDRT ($00AF)
Serial communications interfaces 1 and 0 and serial
peripheral interface subsystems and general-purpose I/O.
General-purpose I/O when not enabled for input capture
and output compare in the timer and pulse accumulator
subsystem.
1. In 80-pin QFP package only TxCAN and RxCAN are available. PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
3.6.12 Port Pull-Up Pull-Down and Reduced Drive
MCU ports can be configured for internal pull-up. To reduce power
consumption and RFI, the pin output drivers can be configured to
operate at a reduced drive level. Reduced drive causes a slight increase
in transition time depending on loading and should be used only for ports
which have a light loading. Table 3-4 summarizes the port pull-up/pulldown default status and controls.
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Table 3-4. Port Pull-Up, Pull-Down and Reduced Drive Summary
Enable Bit
Port
Name
Port A
Port B
Port E:
PE7,
PE[3:2]
PE[1:0]
PE[6:4]
Port G
Port H
Port P
PS[1:0]
PS[3:2]
PS[7:4]
Port T
PortCAN[1]:
TxCAN
PortCAN[0]:
RxCAN
Port
CAN[7:2]
Port AD0
Port AD1
PUPA
PUPB
Reset
State
Disabled
Disabled
Reduced Drive Control Bit
Register
Reset
Bit Name
(Address)
State
RDRIV ($000D)
RDPA
Full drive
RDRIV ($000D)
RDPB
Full drive
PUCR ($000C)
PUPE
Enabled
RDRIV ($000D)
RDPE
Full drive
PUCR ($000C)
—
PUPE
Enabled
—
RDRIV ($000D)
RDPE
Full drive
PUCR ($000C)
PUPG
Enabled
RDRIV ($000D)
RDPG
Full drive
PUCR ($000C)
PUPH
Enabled
RDRIV ($000D)
RDPH
Full drive
PWCONT ($0054)
PURDS ($00D9)
PURDS ($00D9)
PURDS ($00D9)
TMSK2 ($008D)
PUPP
PUPS0
PUPS1
PUPS2
PUPT
Disabled
Disabled
Disabled
Disabled
Disabled
PWCONT ($0054) RDPP
PURDS ($00DB)
RDPS0
PURDS ($00DB)
RDPS1
PURDS ($00DB)
RDPS2
TMSK2 ($008D)
TDRB
Resistive
Register
Input Loads
(Address)
Pull-up
PUCR ($000C)
Pull-up
PUCR ($000C)
Pull-up
Pull-up
None
Pull-up or
Pulldown(1)
Pull-up or
Pulldown(2)
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
None
—
—
Pull-up
Always enabled
—
Pull-up
None
None
PCTLCAN
($013D)
—
—
Bit Name
PUPCAN Disabled
Full drive
Full drive
Full drive
Full drive
Full drive
PCTLCAN ($013D) RDPCAN Full drive
—
—
1. Pull-Up when PGUPD input pin is high, Pull-down when PGUPD input pin is low.
In the 80-pin version, PGUPD is internally tied to VDD, hence PG4 is pulled up.
2. Pull-Up when PHUPD input pin is high, Pull-down when PHUPD input pin is low.
In the 80-pin version, PHUPD is internally tied to VSS, hence PH4 is pulled down.
Advance Information
61
68HC(9)12D60 — Rev 4.0
Pinout and Signal Descriptions
For More Information On This Product,
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Pinout and Signal Descriptions
Advance Information
62
68HC(9)12D60 — Rev 4.0
Pinout and Signal Descriptions
For More Information On This Product,
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Advance Information — 68HC(9)12D60
Section 4. Registers
4.1 Contents
4.2
Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Register Block
The register block can be mapped to any 2K byte boundary within the
standard 64K byte address space by manipulating bits REG[15:11] in
the INITRG register. INITRG establishes the upper five bits of the
register block’s 16-bit address. The register block occupies the first 512
bytes of the 2K byte block. Default addressing (after reset) is indicated
in Table 4-1. For additional information refer to Operating Modes and
Resource Mapping.
68HC(9)12D60 — Rev 4.0
MOTOROLA
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Registers
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Registers
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTA(1)
$0001
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTB(1)
$0002
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
DDRA(1)
$0003
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
DDRB(1)
$0004
0
0
0
0
0
0
0
0
Reserved(3)
$0005
0
0
0
0
0
0
0
0
Reserved(3)
$0006
0
0
0
0
0
0
0
0
Reserved(3)
$0007
0
0
0
0
0
0
0
0
Reserved(3)
$0008
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORTE(2)
$0009
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
0
0
DDRE(2)
$000A
NDBE
CGMTE
PIPOE
NECLK
LSTRE
RDWE
CALE
DBENE
PEAR(3)
$000B
SMODN
MODB
MODA
ESTR
IVIS
EBSWAI
0
EME
MODE(3)
$000C
PUPH
PUPG
0
PUPE
0
0
PUPB
PUPA
PUCR(3)
$000D
0
RDPH
RDPG
0
RDPE
0
RDPB
RDPA
RDRIV(3)
$000E
0
0
0
0
0
0
0
0
Reserved(3)
$000F
0
0
0
0
0
0
0
0
Reserved(3)
$0010
RAM15
RAM14
RAM13
RAM12
RAM11
0
0
0
INITRM
$0011
REG15
REG14
REG13
REG12
REG11
0
0
MMSWAI
INITRG
$0012
EE15
EE14
EE13
EE12
0
0
0
EEON
INITEE
$0013
MAPROM
NDRF
RFSTR1
RFSTR0
EXSTR1
EXSTR0 ROMON28ROMON32
MISC
$0014
RTIE
RSWAI
RSBCK
Reserved
RTBYP
RTR2
RTR1
RTR0
RTICTL
$0015
RTIF
0
0
0
0
0
0
0
RTIFLG
$0016
CME
FCME
FCMCOP
WCOP
DISR
CR2
CR1
CR0
COPCTL
$0017
Bit 7
6
5
4
3
2
1
Bit 0
COPRST
$0018
0
0
0
0
0
0
0
0
Reserved
$0019
0
0
0
0
0
0
0
0
Reserved
$001A
0
0
0
0
0
0
0
0
Reserved
$001B
0
0
0
0
0
0
0
0
Reserved
$001C
0
0
0
0
0
0
0
0
Reserved
$001D
0
0
0
0
0
0
0
0
Reserved
$001E
IRQE
IRQEN
DLY
0
0
0
0
0
INTCR
$001F
1
1
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
0
HPRIO
$0020
BKEN1
BKEN0
BKPM
0
BK1ALE
BK0ALE
0
0
BRKCT0
$0021
0
BKDBE
BKMBH
BKMBL
BK1RWE
BK1RW
BK0RWE
BK0RW
BRKCT1
$0022
Bit 15
14
13
12
11
10
9
Bit 8
BRKAH
Table 4-1. 68HC(9)12D60 Register Map (Sheet 1 of 8)
Advance Information
64
68HC(9)12D60 — Rev 4.0
Registers
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Freescale Semiconductor, Inc.
Registers
Register Block
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$0023
Bit 7
6
5
4
3
2
1
Bit 0
BRKAL
$0024
Bit 15
14
13
12
11
10
9
Bit 8
BRKDH
$0025
Bit 7
6
5
4
3
2
1
Bit 0
BRKDL
$0026
0
0
0
0
0
0
0
0
reserved
$0027
0
0
0
0
0
0
0
0
reserved
$0028
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PORTG
$0029
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PORTH
$002A
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
DDRG
$002B
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
DDRH
$002C
WI2CE
KWIEG6
KWIEG5
KWIEG4
KWIEG3
KWIEG2
KWIEG1
KWIEG0
KWIEG
$002D
KWIEH7
KWIEH6
KWIEH5
KWIEH4
KWIEH3
KWIEH2
KWIEH1
KWIEH0
KWIEH
$002E
0
KWIFG6
KWIFG5
KWIFG4
KWIFG3
KWIFG2
KWIFG1
KWIFG0
KWIFG
$002F
KWIFH7
KWIFH6
KWIFH5
KWIFH4
KWIFH3
KWIFH2
KWIFH1
KWIFH0
KWIFH
$0030–$
0037
Unimplemented(4)
$0038
0
0
SYN5
SYN4
Reserved
SYN3
SYN2
SYN1
SYN0
SYNR
$0039
0
0
0
0
0
REFDV2
REFDV1
REFDV0
REFDV
$003A
0
0
0
0
0
0
0
0
Reserved
$003B
LOCKIF
LOCK
0
0
0
0
LHIF
LHOME
PLLFLG
$003C
LOCKIE
PLLON
AUTO
ACQ
0
PSTP
LHIE
NOLHM
PLLCR
$003D
0
BCSP
BCSS
0
0
MCS
0
0
CLKSEL
$003E
0
0
SLDV5
SLDV4
SLDV3
SLDV2
SLDV1
SLDV0
SLOW
$003F
0
0
0
0
0
0
0
0
Reserved
$0040
CON23
CON01
PCKA2
PCKA1
PCKA0
PCKB2
PCKB1
PCKB0
PWCLK
$0041
PCLK3
PCLK2
PCLK1
PCLK0
PPOL3
PPOL2
PPOL1
PPOL0
PWPOL
$0042
0
0
0
0
PWEN3
PWEN2
PWEN1
PWEN0
PWEN
$0043
0
Bit 6
5
4
3
2
1
Bit 0
PWPRES
$0044
Bit 7
6
5
4
3
2
1
Bit 0
PWSCAL0
$0045
Bit 7
6
5
4
3
2
1
Bit 0
PWSCNT0
$0046
Bit 7
6
5
4
3
2
1
Bit 0
PWSCAL1
$0047
Bit 7
6
5
4
3
2
1
Bit 0
PWSCNT1
$0048
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT0
$0049
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT1
$004A
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT2
$004B
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT3
$004C
Bit 7
6
5
4
3
2
1
Bit 0
PWPER0
$004D
Bit 7
6
5
4
3
2
1
Bit 0
PWPER1
$004E
Bit 7
6
5
4
3
2
1
Bit 0
PWPER2
Table 4-1. 68HC(9)12D60 Register Map (Sheet 2 of 8)
68HC(9)12D60 — Rev 4.0
MOTOROLA
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Registers
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65
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Registers
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$004F
Bit 7
6
5
4
3
2
1
Bit 0
PWPER3
$0050
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY0
$0051
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY1
$0052
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY2
$0053
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY3
$0054
0
0
0
PSWAI
CENTR
RDPP
PUPP
PSBCK
PWCTL
$0055
DISCR
DISCP
DISCAL
0
0
0
0
0
PWTST
$0056
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PORTP
$0057
DDP7
DDP6
DDP5
DDP4
DDP3
DDP2
DDP1
DDP0
DDRP
$0058
0
0
0
0
0
0
0
0
Reserved
$0059
0
0
0
0
0
0
0
0
Reserved
$005A
0
0
0
0
0
0
0
0
Reserved
$005B
0
0
0
0
0
0
0
0
Reserved
$005C
0
0
0
0
0
0
0
0
Reserved
$005D
0
0
0
0
0
0
0
0
Reserved
$005E
0
0
0
0
0
0
0
0
Reserved
$005F
0
0
0
0
0
0
0
0
Reserved
$0060
ATD0CTL0
Reserved
$0061
ATD0CTL1
$0062
ADPU
AFFC
AWAI
0
0
0
ASCIE
ASCIF
ATD0CTL2
$0063
0
0
0
0
0
0
FRZ1
FRZ0
ATD0CTL3
$0064
S10BM
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
ATD0CTL4
$0065
0
S8CM
SCAN
MULT
CD
CC
CB
CA
ATD0CTL5
$0066
SCF
0
0
0
0
CC2
CC1
CC0
ATD0STAT0
$0067
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
ATD0STAT1
$0068
SAR9
SAR8
SAR7
SAR6
SAR5
SAR4
SAR3
SAR2
ATD0TEST
H
$0069
SAR1
SAR0
RST
TSTOUT
TST3
TST2
TST1
TST0
ATD0TESTL
$006A–$
006E
0
0
0
0
0
0
0
0
Reserved
$006F
PAD07
PAD06
PAD05
PAD04
PAD03
PAD02
PAD01
PAD00
PORTAD0
$0070
Bit 15
14
13
12
11
10
9
Bit 8
ADR00H
$0071
Bit 7
Bit 6
0
0
0
0
0
0
ADR00L
$0072
Bit 15
14
13
12
11
10
9
Bit 8
ADR01H
$0073
Bit 7
Bit 6
0
0
0
0
0
0
ADR01L
$0074
Bit 15
14
13
12
11
10
9
Bit 8
ADR02H
$0075
Bit 7
Bit 6
0
0
0
0
0
0
ADR02L
$0076
Bit 15
14
13
12
11
10
9
Bit 8
ADR03H
$0077
Bit 7
Bit 6
0
0
0
0
0
0
ADR03L
Table 4-1. 68HC(9)12D60 Register Map (Sheet 3 of 8)
Advance Information
66
68HC(9)12D60 — Rev 4.0
Registers
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MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Registers
Register Block
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$0078
Bit 15
14
13
12
11
10
9
Bit 8
ADR04H
$0079
Bit 7
Bit 6
0
0
0
0
0
0
ADR04L
$007A
Bit 15
14
13
12
11
10
9
Bit 8
ADR05H
$007B
Bit 7
Bit 6
0
0
0
0
0
0
ADR05L
$007C
Bit 15
14
13
12
11
10
9
Bit 8
ADR06H
$007D
Bit 7
Bit 6
0
0
0
0
0
0
ADR06L
$007E
Bit 15
14
13
12
11
10
9
Bit 8
ADR07H
$007F
Bit 7
Bit 6
0
0
0
0
0
0
ADR07L
$0080
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
TIOS
$0081
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
CFORC
$0082
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7M
$0083
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
OC7D
$0084
Bit 15
14
13
12
11
10
9
Bit 8
TCNT
3
2
1
Bit 0
$0085
Bit 7
6
5
4
$0086
TEN
TSWAI
TSBCK
TFFCA
$0087
Reserved
Reserved
$0088
OM7
OL7
OM6
OL6
TCNT
TSCR
TQCR
OM5
OL5
OM4
OL4
TCTL1
$0089
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
TCTL2
$008A
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
TCTL3
$008B
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
TCTL4
$008C
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
TMSK1
$008D
TOI
0
PUPT
RDPT
TCRE
PR2
PR1
PR0
TMSK2
$008E
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
TFLG1
$008F
TOF
0
0
0
0
0
0
0
TFLG2
$0090
Bit 15
14
13
12
11
10
9
Bit 8
TC0
$0091
Bit 7
6
5
4
3
2
1
Bit 0
TC0
$0092
Bit 15
14
13
12
11
10
9
Bit 8
TC1
$0093
Bit 7
6
5
4
3
2
1
Bit 0
TC1
$0094
Bit 15
14
13
12
11
10
9
Bit 8
TC2
$0095
Bit 7
6
5
4
3
2
1
Bit 0
TC2
$0096
Bit 15
14
13
12
11
10
9
Bit 8
TC3
$0097
Bit 7
6
5
4
3
2
1
Bit 0
TC3
$0098
Bit 15
14
13
12
11
10
9
Bit 8
TC4
$0099
Bit 7
6
5
4
3
2
1
Bit 0
TC4
$009A
Bit 15
14
13
12
11
10
9
Bit 8
TC5
$009B
Bit 7
6
5
4
3
2
1
Bit 0
TC5
$009C
Bit 15
14
13
12
11
10
9
Bit 8
TC6
$009D
Bit 7
6
5
4
3
2
1
Bit 0
TC6
Table 4-1. 68HC(9)12D60 Register Map (Sheet 4 of 8)
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Registers
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Registers
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$009E
Bit 15
14
13
12
11
10
9
Bit 8
TC7
$009F
Bit 7
6
5
4
3
2
1
Bit 0
TC7
$00A0
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
PACTL
$00A1
0
0
0
0
0
0
PAOVF
PAIF
PAFLG
$00A2
Bit 7
6
5
4
3
2
1
Bit 0
PACN3
$00A3
Bit 7
6
5
4
3
2
1
Bit 0
PACN2
$00A4
Bit 7
6
5
4
3
2
1
Bit 0
PACN1
$00A5
Bit 7
6
5
4
3
2
1
Bit 0
PACN0
$00A6
MCZI
MODMC
RDMCL
ICLAT
FLMC
MCEN
MCPR1
MCPR0
MCCTL
$00A7
MCZF
0
0
0
POLF3
POLF2
POLF1
POLF0
MCFLG
$00A8
0
0
0
0
PA3EN
PA2EN
PA1EN
PA0EN
ICPACR
$00A9
0
0
0
0
0
0
DLY1
DLY0
DLYCT
$00AA
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
ICOVW
$00AB
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
ICSYS
$00AC
0
0
0
0
0
0
0
0
Reserved
$00AD
0
0
0
0
0
0
TCBYP
0
TIMTST
$00AE
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
PORTT
$00AF
DDT7
DDT6
DDT5
DDT4
DDT3
DDT2
DDT1
DDT0
DDRT
$00B0
0
PBEN
0
0
0
0
PBOVI
0
PBCTL
$00B1
0
0
0
0
0
0
PBOVF
0
PBFLG
$00B2
Bit 7
6
5
4
3
2
1
Bit 0
PA3H
$00B3
Bit 7
6
5
4
3
2
1
Bit 0
PA2H
$00B4
Bit 7
6
5
4
3
2
1
Bit 0
PA1H
$00B5
Bit 7
6
5
4
3
2
1
Bit 0
PA0H
$00B6
Bit 15
14
13
12
11
10
9
Bit 8
MCCNTH
$00B7
Bit 7
6
5
4
3
2
1
Bit 0
MCCNTL
$00B8
Bit 15
14
13
12
11
10
9
Bit 8
TC0H
$00B9
Bit 7
6
5
4
3
2
1
Bit 0
TC0H
$00BA
Bit 15
14
13
12
11
10
9
Bit 8
TC1H
$00BB
Bit 7
6
5
4
3
2
1
Bit 0
TC1H
$00BC
Bit 15
14
13
12
11
10
9
Bit 8
TC2H
$00BD
Bit 7
6
5
4
3
2
1
Bit 0
TC2H
$00BE
Bit 15
14
13
12
11
10
9
Bit 8
TC3H
$00BF
Bit 7
6
5
4
3
2
1
Bit 0
TC3H
$00C0
BTST
BSPL
BRLD
SBR12
SBR11
SBR10
SBR9
SBR8
SC0BDH
$00C1
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
SC0BDL
$00C2
LOOPS
WOMS
RSRC
M
WAKE
ILT
PE
PT
SC0CR1
$00C3
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SC0CR2
Table 4-1. 68HC(9)12D60 Register Map (Sheet 5 of 8)
Advance Information
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68HC(9)12D60 — Rev 4.0
Registers
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Registers
Register Block
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$00C4
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
SC0SR1
$00C5
SCSWAI
MIE
MDL1
MDL0
0
0
0
RAF
SC0SR2
$00C6
R8
T8
0
0
0
0
0
0
SC0DRH
$00C7
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
SC0DRL
$00C8
BTST
BSPL
BRLD
SBR12
SBR11
SBR10
SBR9
SBR8
SC1BDH
$00C9
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
SC1BDL
$00CA
LOOPS
WOMS
RSRC
M
WAKE
ILT
PE
PT
SC1CR1
$00CB
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SC1CR2
$00CC
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
SC1SR1
$00CD
SCSWAI
0
0
0
0
0
0
RAF
SC1SR2
$00CE
R8
T8
0
0
0
0
0
0
SC1DRH
$00CF
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
SC1DRL
$00D0
SPIE
SPE
SWOM
MSTR
CPOL
CPHA
SSOE
LSBF
SP0CR1
$00D1
0
0
0
0
0
0
SPSWAI
SPC0
SP0CR2
$00D2
0
0
0
0
0
SPR2
SPR1
SPR0
SP0BR
$00D3
SPIF
WCOL
0
MODF
0
0
0
0
SP0SR
$00D4
0
0
0
0
0
0
0
0
Reserved
$00D5
Bit 7
6
5
4
3
2
1
Bit 0
SP0DR
$00D6
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PORTS
$00D7
DDS7
DDS6
DDS5
DDS4
DDS3
DDS2
DDS1
DDS0
DDRS
$00D8
0
0
0
0
0
0
0
0
Reserved
$00D9
0
RDPS2
RDPS1
RDPS0
0
PUPS2
PUPS1
PUPS0
PURDS
$00DA–
$00DF
0
0
0
0
0
0
0
0
Reserved
$00E0–
$00EF
Unimplemented(4)
Reserved
$00F0
NOBDML
NOSHB
$00F1
SHPROT
1
1
BPROT4
BPROT3
BPROT2
$00F2
0
0
0
0
0
$00F3
Reserved
1
EESWAI PROTLCK
EERC
EEMCR
BPROT1
BPROT0
EEPROT
0
0
0
Reserved
BULKP
0
0
BYTE
ROW
ERASE
EELAT
EEPGM
EEPROG
(5)
0
0
0
0
0
0
0
LOCK
FEE32LCK
(5)
0
0
0
0
0
0
0
BOOTP
FEE32MCR
$00F4
$00F5
$00F6(5)
FSTE
GADR
HVT
FENLV
FDISVFP
VTCK
STRE
MWPR
FEETST
(5)
$00F7
0
0
0
FEESWAI
SVFP
ERAS
LAT
ENPE
FEE32CTL
$00F8(5)
0
0
0
0
0
0
0
LOCK
FEE28LCK
$00F9(5)
0
0
0
0
0
0
0
BOOTP
FEE28MCR
$00FA(5)
FSTE
GADR
HVT
FENLV
FDISVFP
VTCK
STRE
MWPR
FEETST
Table 4-1. 68HC(9)12D60 Register Map (Sheet 6 of 8)
68HC(9)12D60 — Rev 4.0
MOTOROLA
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Registers
Address
(5)
$00FB
Bit 7
6
5
4
3
2
1
Bit 0
Name
0
0
0
FEESWAI
SVFP
ERAS
LAT
ENPE
FEE28CTL
$00FC–
$00FF
Unimplemented(4)
Reserved
$0100
0
0
CSWAI
SYNCH
TLNKEN
SLPAK
SLPRQ
SFTRES
CMCR0
$0101
0
0
0
0
0
LOOPB
WUPM
CLKSRC
CMCR1
$0102
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
CBTR0
$0103
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
CBTR1
$0104
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
CRFLG
$0105
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
CRIER
$0106
0
ABTAK2
ABTAK1
ABTAK0
0
TXE2
TXE1
TXE0
CTFLG
$0107
0
ABTRQ2
ABTRQ1
ABTRQ0
0
TXEIE2
TXEIE1
TXEIE0
CTCR
$0108
0
0
IDAM1
IDAM0
0
IDHIT2
IDHIT1
IDHIT0
CIDAC
$0109–
$010D
Unimplemented(4)
Reserved
$010E
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CRXERR
$010F
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
CTXERR
$0110
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR0
$0111
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR1
$0112
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR2
$0113
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR3
$0114
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR0
$0115
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR1
$0116
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR2
$0117
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR3
$0118
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR4
$0119
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR5
$011A
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR6
$011B
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CIDAR7
$011C
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR4
$011D
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR5
$011E
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR6
$011F
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CIDMR7
$0120–
$013C
Unimplemented(4)
Reserved
$013D
0
0
0
0
0
0
$013E
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
$013F
PUPCAN RDPCAN
TxCAN
RxCAN
PORTCAN
0
0
DDRCAN
DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2
$0140–
$014F
PCTLCAN
RECEIVE BUFFER
RxFG
Table 4-1. 68HC(9)12D60 Register Map (Sheet 7 of 8)
Advance Information
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68HC(9)12D60 — Rev 4.0
Registers
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Registers
Register Block
Address
Bit 7
6
5
4
3
2
1
Bit 0
Name
$0150–
$015F
TRANSMIT BUFFER 0
Tx0
$0160–
$016F
TRANSMIT BUFFER 1
Tx1
$0170–
$017F
TRANSMIT BUFFER 2
Tx2
$0180–
$01DF
Unimplemented(4)
Reserved
$01E0
Reserved
ATD1CTL0
$01E1
Reserved
ATD1CTL1
$01E2
ADPU
AFFC
AWAI
0
0
0
ASCIE
ASCIF
ATD1CTL2
$01E3
0
0
0
0
0
0
FRZ1
FRZ0
ATD1CTL3
$01E4
S10BM
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
ATD1CTL4
$01E5
0
S8CM
SCAN
MULT
CD
CC
CB
CA
ATD1CTL5
$01E6
SCF
0
0
0
0
CC2
CC1
CC0
ATD1STAT0
$01E7
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
ATD1STAT1
$01E8
SAR9
SAR8
SAR7
SAR6
SAR5
SAR4
SAR3
SAR2
ATD1TESTH
$01E9
SAR1
SAR0
RST
TSTOUT
TST3
TST2
TST1
TST0
ATD1TESTL
$01EA–$
01EE
0
0
0
0
0
0
0
0
Reserved
$01EF
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PORTAD1
$01F0
Bit 15
14
13
12
11
10
9
Bit 8
ADR10H
$01F1
Bit 7
Bit 6
0
0
0
0
0
0
ADR10L
$01F2
Bit 15
14
13
12
11
10
9
Bit 8
ADR11H
$01F3
Bit 7
Bit 6
0
0
0
0
0
0
ADR11L
$01F4
Bit 15
14
13
12
11
10
9
Bit 8
ADR12H
$01F5
Bit 7
Bit 6
0
0
0
0
0
0
ADR12L
$01F6
Bit 15
14
13
12
11
10
9
Bit 8
ADR13H
$01F7
Bit 7
Bit 6
0
0
0
0
0
0
ADR13L
$01F8
Bit 15
14
13
12
11
10
9
Bit 8
ADR14H
$01F9
Bit 7
Bit 6
0
0
0
0
0
0
ADR14L
$01FA
Bit 15
14
13
12
11
10
9
Bit 8
ADR15H
$01FB
Bit 7
Bit 6
0
0
0
0
0
0
ADR15L
$01FC
Bit 15
14
13
12
11
10
9
Bit 8
ADR16H
$01FD
Bit 7
Bit 6
0
0
0
0
0
0
ADR16L
$01FE
Bit 15
14
13
12
11
10
9
Bit 8
ADR17H
$01FF
Bit 7
Bit 6
0
0
0
0
0
0
ADR17L
= Reserved or unimplemented bits.
Table 4-1. 68HC(9)12D60 Register Map (Sheet 8 of 8)
68HC(9)12D60 — Rev 4.0
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Registers
1. Port A, port B and data direction registers DDRA, DDRB are not in map in expanded and peripheral modes.
2. Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set.
3. Registers also not in map in peripheral mode.
4. Data read at these locations is undefined.
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5. Available on 68HC912D60 only. Registers are unimplemented on 68HC12D60 - data read at these locations is undefined.
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68HC(9)12D60 — Rev 4.0
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Advance Information — 68HC(9)12D60
Section 5. Operating Modes and Resource Mapping
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.4
Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.5
Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.6
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5.2 Introduction
Eight possible operating modes determine the operating configuration of
the 68HC(9)12D60. Each mode has an associated default memory map
and external bus configuration. After reset, most system resources can
be mapped to other addresses by writing to the appropriate control
registers.
5.3 Operating Modes
The operating mode out of reset is determined by the states of the
BKGD, MODB, and MODA pins during reset.
The SMODN, MODB, and MODA bits in the MODE register show current
operating mode and provide limited mode switching during operation.
68HC(9)12D60 — Rev 4.0
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Operating Modes and Resource Mapping
The states of the BKGD, MODB, and MODA pins are latched into these
bits on the rising edge of the reset signal.
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Table 5-1. Mode Selection
BKGD
MODB
MODA
Mode
Port A
Port B
1
0
0
Normal Single Chip
G.P. I/O
G.P. I/O
1
0
1
Normal Expanded Narrow
ADDR/DATA
ADDR
1
1
0
Reserved (Forced to
Peripheral)
—
—
1
1
1
Normal Expanded Wide
ADDR/DATA
ADDR/DATA
0
0
0
Special Single Chip
G.P. I/O
G.P. I/O
0
0
1
Special Expanded Narrow
ADDR/DATA
ADDR
0
1
0
Special Peripheral
ADDR/DATA
ADDR/DATA
0
1
1
Special Expanded Wide
ADDR/DATA
ADDR/DATA
There are two basic types of operating modes:
Normal modes — some registers and bits are protected
against accidental changes.
Special modes — allow greater access to protected control
registers and bits for special purposes such as testing and
emulation.
For operation above 105°C, the 68HC(9)12D60 (M temperature range
product only) is limited to single chip modes of operation.
A system development and debug feature, background debug mode
(BDM), is available in all modes. In special single-chip mode, BDM is
active immediately after reset.
5.3.1 Normal Operating Modes
These modes provide three operating configurations. Background
debugging is available in all three modes, but must first be enabled for
some operations by means of a BDM background command, then
activated.
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Operating Modes and Resource Mapping
Operating Modes
Normal Single-Chip Mode — There are no external address
and data buses in this mode. The MCU operates as a standalone device and all program and data resources are on-chip.
External port pins normally associated with address and data
buses can be used for general-purpose I/O.
Normal Expanded Wide Mode — This is a normal mode of
operation in which the expanded bus is present with a 16-bit
data bus. Ports A and B are used for the 16-bit multiplexed
address/data bus.
Normal Expanded Narrow Mode — This is a normal mode of
operation in which the expanded bus is present with an 8-bit
data bus. Ports A and B are used for the16-bit address bus.
Port A is used as the data bus, multiplexed with addresses. In
this mode, 16-bit data is presented one byte at a time, the high
byte followed by the low byte. The address is automatically
incremented on the second cycle.
5.3.2 Special Operating Modes
There are three special operating modes that correspond to normal
operating modes. These operating modes are commonly used in factory
testing and system development. In addition, there is a special
peripheral mode, in which an external master, such as an I.C. tester, can
control the on-chip peripherals.
Special Single-Chip Mode — This mode can be used to force
the MCU to active BDM mode to allow system debug through
the BKGD pin. There are no external address and data buses
in this mode. The MCU operates as a stand-alone device and
all program and data space are on-chip. External port pins can
be used for general-purpose I/O.
Special Expanded Wide Mode — This mode can be used for
emulation of normal expanded wide mode and emulation of
normal single-chip mode. Ports A and B are used for the 16-bit
multiplexed address/data bus.
68HC(9)12D60 — Rev 4.0
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Operating Modes and Resource Mapping
Special Expanded Narrow Mode — This mode can be used
for emulation of normal expanded narrow mode. Ports A and B
are used for the16-bit address bus. Port A is used as the data
bus, multiplexed with addresses. In this mode, 16-bit data is
presented one byte at a time, the high byte followed by the low
byte. The address is automatically incremented on the second
cycle.
Special Peripheral Mode — The CPU is not active in this
mode. An external master can control on-chip peripherals for
testing purposes. It is not possible to change to or from this
mode without going through reset. Background debugging
should not be used while the MCU is in special peripheral
mode as internal bus conflicts between BDM and the external
master can cause improper operation of both modes.
5.4 Background Debug Mode
Background debug mode (BDM) is an auxiliary operating mode that is
used for system development. BDM is implemented in on-chip hardware
and provides a full set of debug operations. Some BDM commands can
be executed while the CPU is operating normally. Other BDM
commands are firmware based, and require the BDM firmware to be
enabled and active for execution.
In special single-chip mode, BDM is enabled and active immediately out
of reset. BDM is available in all other operating modes, but must be
enabled before it can be activated. BDM should not be used in special
peripheral mode because of potential bus conflicts.
Once enabled, background mode can be made active by a serial
command sent via the BKGD pin or execution of a CPU12 BGND
instruction. While background mode is active, the CPU can interpret
special debugging commands, and read and write CPU registers,
peripheral registers, and locations in memory.
While BDM is active, the CPU executes code located in a small on-chip
ROM mapped to addresses $FF20 to $FFFF, and BDM control registers
are accessible at addresses $FF00 to $FF06. The BDM ROM replaces
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Operating Modes and Resource Mapping
Background Debug Mode
the regular system vectors while BDM is active. While BDM is active, the
user memory from $FF00 to $FFFF is not in the map except through
serial BDM commands.
Bit 7
6
5
4
3
2
1
Bit 0
SMODN
MODB
MODA
ESTR
IVIS
EBSWAI
0
EME
RESET:
0
0
0
1
1
0
0
1
Special Single Chip
RESET:
0
0
1
1
1
0
0
1
Special Exp Nar
RESET:
0
1
0
1
1
0
0
1
Peripheral
RESET:
0
1
1
1
1
0
0
1
Special Exp Wide
RESET:
1
0
0
1
0
0
0
0
Normal Single Chip
RESET:
1
0
1
1
0
0
0
0
Normal Exp Nar
RESET:
1
1
1
1
0
0
0
0
Normal Exp Wide
MODE — Mode Register
$000B
MODE controls the MCU operating mode and various configuration
options. This register is not in the map in peripheral mode
SMODN, MODB, MODA — Mode Select Special, B and A
These bits show the current operating mode and reflect the status of
the BKGD, MODB and MODA input pins at the rising edge of reset.
SMODN is Read anytime. May only be written in special modes
(SMODN = 0). The first write is ignored;
MODB, MODA may be written once in Normal modes (SMODN = 1).
Write anytime in special modes (first write is ignored) – special
peripheral and reserved modes cannot be selected.
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ESTR — E Clock Stretch Enable
Determines if the E Clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
ESTR is always 1 in expanded modes since it is required for address
and data bus de-multiplexing and must follow stretched cycles.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during
non-visible internal accesses (IVIS=0).
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Normal modes: write once; Special modes: write anytime. Read
anytime.
IVIS — Internal Visibility
This bit determines whether internal ADDR, DATA, R/W and LSTRB
signals can be seen on the external bus during accesses to internal
locations. In Special Narrow Mode if this bit is set and an internal
access occurs the data will appear wide on Ports A and B. This serves
the same function as the EMD bit of the non-multiplexed versions of
the HC12 and allows for emulation. Visibility is not available when the
part is operating in a single-chip mode.
0 = No visibility of internal bus operations on external bus.
1 = Internal bus operations are visible on external bus.
Normal modes: write once; Special modes: write anytime EXCEPT
the first time. Read anytime.
EBSWAI — External Bus Module Stop in Wait Control
This bit controls access to the external bus interface when in wait
mode. The module will delay before shutting down in wait mode to
allow for final bus activity to complete.
0 = External bus and registers continue functioning during wait mode.
1 = External bus is shut down during wait mode.
Normal modes: write anytime; Special modes: write never. Read
anytime.
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Internal Resource Mapping
EME — Emulate Port E
In single-chip mode PORTE and DDRE are always in the map
regardless of the state of this bit.
0 = PORTE and DDRE are in the memory map.
1 = If in an expanded mode, PORTE and DDRE are removed from the
internal memory map. Removing the registers from the map allows
the user to emulate the function of these registers externally.
Normal modes: write once; special modes: write anytime EXCEPT
the first time. Read anytime.
5.5 Internal Resource Mapping
The internal register block, RAM, and EEPROM have default locations
within the 64K byte standard address space but may be reassigned to
other locations during program execution by setting bits in mapping
registers INITRG, INITRM, and INITEE. During normal operating modes
these registers can be written once. It is advisable to explicitly establish
these resource locations during the initialization phase of program
execution, even if default values are chosen, in order to protect the
registers from inadvertent modification later.
Writes to the mapping registers go into effect between the cycle that
follows the write and the cycle after that. To assure that there are no
unintended operations, a write to one of these registers should be
followed with a NOP instruction.
If conflicts occur when mapping resources, the register block will take
precedence over the other resources; RAM or EEPROM addresses
occupied by the register block will not be available for storage. When
active, BDM ROM takes precedence over other resources, although a
conflict between BDM ROM and register space is not possible. The
following table shows resource mapping precedence.
In expanded modes, all address space not used by internal resources is
by default external memory.
The 68HC912D60 contains 60K bytes of Flash EEPROM nonvolatile
memory which can be used to store program code or static data. It is
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made of the 28K byte FEE28 array mapped from $1000 to $7FFF at
reset and of the 32 K byte FEE32 array mapped from $8000 to $FFFF at
reset. MAPROM bit in the MISC register allows the swapping of the two
flash arrays.
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The 68HC12D60 contains 60K bytes of ROM memory. It is made of a
28K byte array mapped from $1000 to $7FFF and a 32 K byte array
mapped from $8000 to $FFFF at reset. The MAPROM bit in the MISC
register allows the swapping of the two arrays.
Table 5-2. Mapping Precedence
Precedence
Resource
1
BDM ROM (if active)
2
Register Space
3
RAM
4
EEPROM
5
On-Chip Flash EEPROM (68HC912D60)
ROM (68HC12D60)
6
External Memory
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Internal Resource Mapping
5.5.1 Register Block Mapping
After reset the 512 byte register block resides at location $0000 but can
be reassigned to any 2K byte boundary within the standard 64K byte
address space. Mapping of internal registers is controlled by five bits in
the INITRG register. The register block occupies the first 512 bytes of the
2K byte block.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
REG15
REG14
REG13
REG12
REG11
0
0
MMSWAI
0
0
0
0
0
0
0
0
INITRG — Initialization of Internal Register Position Register
$0011
REG[15:11] — Internal register map position
These bits specify the upper five bits of the 16-bit registers address.
Normal modes: write once; special modes: write anytime. Read
anytime.
MMSWAI — Memory Mapping Interface Stop in Wait Control
This bit controls access to the memory mapping interface when in
Wait mode.
Normal modes: write anytime; special modes: write never. Read
anytime.
0 = Memory mapping interface continues to function during Wait
mode.
1 = Memory mapping interface access is shut down during Wait
mode.
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5.5.2 RAM Mapping
The 68HC(9)12D60 has 2K byte of fully static RAM that is used for
storing instructions, variables, and temporary data during program
execution. After reset, RAM addressing begins at location $0000 but can
be assigned to any 2K byte boundary within the standard 64K byte
address space. Mapping of internal RAM is controlled by five bits in the
INITRM register.
After reset, the first 512 bytes of RAM have their access inhibited by the
presence of the register address space. After initial MCU configuration,
it is recommended to map the register space at location $0800.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
RAM15
RAM14
RAM13
RAM12
RAM11
0
0
0
0
0
0
0
0
0
0
0
INITRM — Initialization of Internal RAM Position Register
$0010
RAM[15:11] — Internal RAM map position
These bits specify the upper five bits of the 16-bit RAM address.
Normal modes: write once; special modes: write anytime. Read
anytime.
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Internal Resource Mapping
5.5.3 EEPROM Mapping
The 68HC(9)12D60 has 1K bytes of EEPROM which is activated by the
EEON bit in the INITEE register. Mapping of internal EEPROM is
controlled by four bits in the INITEE register. After reset EEPROM
address space begins at location $0C00 but can be mapped to any 4K
byte boundary within the standard 64K byte address space.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
EE15
EE14
EE13
EE12
0
0
0
EEON
0
0
0
0
0
0
0
1
INITEE— Initialization of Internal EEPROM Position Register
$0012
EE[15:12] — Internal EEPROM map position
These bits specify the upper four bits of the 16-bit EEPROM address.
Normal modes: write once; special modes: write anytime. Read
anytime.
EEON — internal EEPROM On (Enabled)
This bit is forced to one in single-chip modes.
Read or write anytime.
0 = Removes the EEPROM from the map.
1 = Places the on-chip EEPROM in the memory map at the address
selected by EE[15:12].
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5.5.4 Miscellaneous System Control Register
Additional mapping and external resource controls are available. To use
external resources the part must be operated in one of the expanded
modes.
Bit 7
6
5
4
3
2
1
Bit 0
MAPROM
NDRF
RFSTR1
RFSTR0
EXSTR1
EXSTR0
RESET:
0
0
0
0
1
1
0
0
Exp Modes
RESET:
0
0
0
0
1
1
1
1
SC Modes
ROMON28 ROMON32
MISC — Miscellaneous Mapping Control Register
$0013
Normal modes: write once; Special modes: write anytime. Read
anytime.
MAPROM — Map Location of ROM
This bit is used to swap the location of the on-chip Flash EEPROM
(68HC912D60) or ROM (68HC12D60) arrays.
0 = 28K byte array is mapped from $1000 to $7FFF, 32K byte array
is mapped from $8000 to $FFFF.
1 = 28K byte is mapped from $9000 to $FFFF, 32K byte array is
mapped from $0000 to $7FFF.
NDRF — Narrow Data Bus for Register-Following Map Space
This bit enables a narrow bus feature for the 512 byte RegisterFollowing Map. This is useful for accessing 8-bit peripherals and
allows 8-bit and 16-bit external memory devices to be mixed in a
system. In Expanded Narrow (eight bit) modes, Single Chip Modes,
and Peripheral mode, this bit has no effect.
0 = Makes Register-Following MAP space act as a full 16 bit data bus.
1 = Makes the Register-Following MAP space act the same as an 8
bit only external data bus (data only goes through port A externally).
The Register-Following space is mapped from $0200 to $03FF after
reset, which is next to the register map. If the registers are moved this
space follows.
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Internal Resource Mapping
RFSTR1, RFSTR0 — Register Following Stretch
This two bit field determines the amount of clock stretch on accesses
to the 512 byte Register Following Map. It is valid regardless of the
state of the NDRF bit. In Single Chip and Peripheral Modes this bit
has no meaning or effect.
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Table 5-3. RFSTR Stretch Bit Definition
RFSTR1
RFSTR0
Number of E Clocks
Stretched
0
0
0
0
1
1
1
0
2
1
1
3
EXSTR1, EXSTR0 — External Access Stretch
This two bit field determines the amount of clock stretch on accesses
to the External Address Space. In Single Chip and Peripheral Modes
this bit has no meaning or effect.
Table 5-4. EXSTR Stretch Bit Definition
EXSTR1
EXSTR0
Number of E Clocks
Stretched
0
0
0
0
1
1
1
0
2
1
1
3
ROMON28, ROMON32 — Enable bits for ROM
These bits are used to enable the Flash EEPROM arrays FEE28 and
FEE32 (68HC912D60) or ROM arrays ROM28 and ROM32
(68HC12D60) respectively.
0 = Corresponding Flash EEPROM/ROM array disabled from the
memory map.
1 = Corresponding Flash EEPROM/ROM array enabled in the
memory map.
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5.6 Memory Maps
The following diagrams illustrate the memory map for each mode of
operation immediately after reset.
$0000
$01FF
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$0000
$0200
$0800
$0C00
$1000
$0000
$07FF
$0C00
$0FFF
REGISTERS
(MAPPABLE TO ANY 2K SPACE)
2K bytes RAM
(MAPPABLE TO ANY 2K SPACE)
1K bytes EEPROM
(MAPPABLE TO ANY 4K SPACE)
$1000
28K Flash EEPROM (FEE28) *
or 28K ROM (ROM28)$
$8000
EXT
$7FFF
$6000 - $7FFF Protected BOOT
$8000
32K Flash EEPROM (FEE32) *
or 32K ROM (ROM32)$
$FFFF
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
$FFFF
$E000 - $FFFF Protected BOOT
BDM
(if active)
* 68HC912D60
$ 68HC12D60
Figure 5-1. 68HC(9)12D60 Memory Map
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Section 6. Bus Control and Input/Output
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3
Detecting Access Type from External Signals . . . . . . . . . . . . .87
6.4
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.2 Introduction
Internally the 68HC(9)12D60 has full 16-bit data paths, but depending
upon the operating mode and control registers, the external multiplexed
bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit
accesses can appear on adjacent cycles using the LSTRB signal to
indicate 8- or 16-bit data.
It is possible to have a mix of 8 and 16 bit peripherals attached to the
external multiplexed bus, using the NDRF bit in the MISC register while
in expanded wide modes.
6.3 Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 can be used to determine the
type of bus access that is taking place. Accesses to the internal RAM
module are the only type of access that produce LSTRB = A0 = 1,
because the internal RAM is specifically designed to allow misaligned
16-bit accesses in a single cycle. In these cases the data for the address
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Bus Control and Input/Output
that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus.
Figure 6-1. Access Type vs. Bus Control Pins
LSTRB
1
0
1
0
0
A0
0
1
0
1
0
R/W
1
1
0
0
1
1
1
1
0
0
0
1
1
0
Type of Access
8-bit read of an even address
8-bit read of an odd address
8-bit write of an even address
8-bit write of an odd address
16-bit read of an even address
16-bit read of an odd address
(low/high data swapped)
16-bit write to an even address
16-bit write to an even address
(low/high data swapped)
6.4 Registers
Not all registers are visible in the 68HC(9)12D60 memory map under
certain conditions. In special peripheral mode the first 16 registers
associated with bus expansion are removed from the memory map.
In expanded modes, some or all of port A, port B, and port E are used
for expansion buses and control signals. In order to allow emulation of
the single-chip functions of these ports, some of these registers must be
rebuilt in an external port replacement unit. In any expanded mode, port
A, and port B, are used for address and data lines so registers for these
ports, as well as the data direction registers for these ports, are removed
from the on-chip memory map and become external accesses.
In any expanded mode, port E pins may be needed for bus control (e.g.,
ECLK, R/W). To regain the single-chip functions of port E, the emulate
port E (EME) control bit in the MODE register may be set. In this special
case of expanded mode and EME set, PORTE and DDRE registers are
removed from the on-chip memory map and become external accesses
so port E may be rebuilt externally.
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Bus Control and Input/Output
Registers
Bit 7
6
5
4
3
2
1
Bit 0
Single Chip
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
—
—
—
—
—
—
—
—
Expanded
& Periph:
ADDR15/
DATA15
ADDR14/
DATA14
ADDR13/
DATA13
ADDR12/
DATA12
ADDR11/
DATA11
ADDR10/
DATA10
ADDR9/
DATA9
ADDR8/
DATA8
Expanded
narrow
ADDR15/
DATA15/
DATA7
ADDR14/
DATA14/
DATA6
ADDR13/
DATA13/
DATA5
ADDR12/
DATA12/
DATA4
ADDR11/
DATA11/
DATA3
ADDR10/
DATA10/
DATA2
ADDR9/
DATA9/
DATA1
ADDR8/
DATA8/
DATA0
PORTA — Port A Register
$0000
Bits PA[7:0] are associated respectively with addresses ADDR[15:8],
DATA[15:8] and DATA[7:0], in narrow mode. When this port is not used
for external addresses such as in single-chip mode, these pins can be
used as general-purpose I/O. DDRA determines the primary direction of
each pin. This register is not in the on-chip map in expanded and
peripheral modes. Read and write anytime.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
DDRA — Port A Data Direction Register
$0002
This register determines the primary direction for each port A pin when
functioning as a general-purpose I/O port. DDRA is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
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Bit 7
6
5
4
3
2
1
Bit 0
Single Chip
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
—
—
—
—
—
—
—
—
Expanded
& Periph:
ADDR7/
DATA7
ADDR6/
DATA6
ADDR5/
DATA5
ADDR4/
DATA4
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
ADDR0/
DATA0
Expanded
narrow
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
PORTB — Port B Register
$0001
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]
(except in narrow mode) respectively. When this port is not used for
external addresses such as in single-chip mode, these pins can be used
as general-purpose I/O. DDRB determines the primary direction of each
pin. This register is not in the on-chip map in expanded and peripheral
modes. Read and write anytime.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
0
0
0
0
0
0
0
0
DDRB — Port B Data Direction Register
$0003
This register determines the primary direction for each port B pin when
functioning as a general-purpose I/O port. DDRB is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
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Registers
BIT 7
6
5
4
3
2
1
BIT 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
—
—
—
—
—
—
—
—
Alt. Pin
Function
DBE or
ECLK or
CAL
MODB or
IPIPE1 or
CGMTST
MODA or
IPIPE0
ECLK
LSTRB or
BDTAGL or
TAGLO
R/W
IRQ
XIRQ
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PORTE — Port E Register
$0008
This register is associated with external bus control signals and interrupt
inputs, including data bus enable (DBE), mode select (MODB/IPIPE1,
MODA/IPIPE0), E clock, size (LSTRB), read/write (R/W), IRQ, and
XIRQ. When the associated pin is not used for one of these specific
functions, the pin can be used as general-purpose I/O. The port E
assignment register (PEAR) selects the function of each pin. DDRE
determines the primary direction of each port E pin when configured to
be general-purpose I/O.
Some of these pins have software selectable pull-ups (DBE, LSTRB,
R/W, IRQ, and XIRQ). A single control bit enables the pull-ups for all
these pins which are configured as inputs.
This register is not in the map in peripheral mode or expanded modes
when the EME bit is set.
Read and write anytime.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
0
0
0
0
0
0
0
0
0
0
DDRE — Port E Data Direction Register
$0009
This register determines the primary direction for each port E pin
configured as general-purpose I/O.
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0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as
outputs. These pins can be read regardless of whether the alternate
interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes
while the EME control bit is set.
Read and write anytime.
BIT 7
6
5
4
3
2
1
BIT 0
NDBE
CGMTE
PIPOE
NECLK
LSTRE
RDWE
CALE
DBENE
RESET:
0
0
0
0
0
0
0
0
Normal
Expanded
RESET:
0
0
1
0
1
1
0
0
Special
Expanded
RESET:
1
1
0
1
0
0
0
0
Peripheral
RESET:
1
0
0
1
0
0
0
0
Normal
single chip
RESET:
0
0
1
0
1
1
0
0
Special
single chip
PEAR — Port E Assignment Register
$000A
The PEAR register is used to choose between the general-purpose I/O
functions and the alternate bus control functions of port E. When an
alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation
because bus-control signals are needed immediately after reset in some
modes.
In normal single-chip mode, no external bus control signals are needed
so all of port E is configured for general-purpose I/O.
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Registers
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In normal expanded modes, the reset vector is located in external
memory. The DBE and E clock are required for de-multiplexing address
and data, but LSTRB and R/W are only needed by the system when
there are external writable resources. Therefore in normal expanded
modes, only the DBE and E clock are configured for their alternate bus
control functions and the other bits of port E are configured for generalpurpose I/O. If the normal expanded system needs any other bus-control
signals, PEAR would need to be written before any access that needed
the additional signals.
In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and R/W
are configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or
writes. However, the CGMTE control bit is reset to one to configure PE6
as a test output from the PLL module.
NDBE — No Data Bus Enable
Normal: write once; Special: write anytime EXCEPT the first. Read
anytime.
0 = PE7 is used for DBE, external control of data enable on
memories, or inverted E clock.
1 = PE7 is the CAL function if CALE bit is set in PEAR register or
general-purpose I/O.
NDBE controls the use of the DBE pin of Port E. The NDBE bit has no
effect in Single Chip or Peripheral Modes. The associated pin will
default to the CAL function if the CALE bit is set in PEAR register or
otherwise to an I/O.
CGMTE — Clock Generator Module Testing Enable
Normal: write never; Special: write anytime EXCEPT the first. Read
anytime.
0 = PE6 is general-purpose I/O or pipe output.
1 = PE6 is a test signal output from the CGM module (no effect in
single chip or normal expanded modes). PIPOE = 1 overrides
this function and forces PE6 to be a pipe status output signal.
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PIPOE — Pipe Status Signal Output Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime.
0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test
output signal from the CGM module).
1 = PE[6:5] are outputs and indicate the state of the instruction
queue (only effective in expanded modes).
NECLK — No External E Clock
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Normal single chip: write once; special single chip: write anytime; all
other modes: write never. Read anytime. In peripheral mode, E is an
input and in all other modes, E is an output.
0 = PE4 is the external E-clock pin subject to the following
limitation: In single-chip modes, to get an E clock output signal,
it is necessary to have ESTR = 0 in addition to NECLK = 0.
1 = PE4 is a general-purpose I/O pin.
LSTRE — Low Strobe (LSTRB) Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes or normal
expanded narrow mode.
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB bus-control output, provided
the MCU is not in single chip or normal expanded narrow
modes.
LSTRB is used during external writes. After reset in normal expanded
mode, LSTRB is disabled. If needed, it should be enabled before
external writes. External reads do not normally need LSTRB because
all 16 data bits can be driven even if the MCU only needs 8 bits of
data.
In normal expanded narrow mode this pin is reset to an output driving
high allowing the pin to be an output while in and immediately after
reset.
TAGLO is a shared function of the PE3/LSTRB pin. In special
expanded modes with LSTRE set and the BDM tagging on, a zero at
the falling edge of E tags the instruction word low byte being read into
the instruction queue.
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Bus Control and Input/Output
Registers
RDWE — Read/Write Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes.
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W pin. In single chip modes, RDWE
has no effect and PE2 is a general-purpose I/O pin.
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R/W is used for external writes. After reset in normal expanded mode,
it is disabled. If needed it should be enabled before any external
writes.
CALE — Calibration Reference Enable
Read and write anytime.
0 = Calibration reference is disabled and PE7 is general-purpose
I/O in single chip or peripheral modes or if the NDBE bit is set.
1 = Calibration reference is enabled on PE7 in single chip and
peripheral modes or if the NDBE bit is set.
DBENE — DBE or Inverted E Clock on Port E[7]
Normal modes: write once. Special modes: write anytime EXCEPT
the first; read anytime.
DBENE controls which signal is output on PE7 when NDBE control bit
is cleared. The inverted E clock output can be used to latch the
address for demultiplexing. It has the same behaviour as the E clock,
except it is inverted. Please note that in the case of idle expansion
bus, the ‘not E clock’ signal could stay high for many cycles.
The DBNE bit has no effect in single chip or peripheral modes and
PE7 is defaulted to the CAL function if the CALE bit is set in the PEAR
register or to an I/O otherwise.
0 = PE7 pin used for DBE external control of data enable on
memories in expanded modes when NDBE = 0
1 = PE7 pin used for inverted E clock output in expanded modes
when NDBE = 0
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
PUPH
PUPG
0
PUPE
0
0
PUPB
PUPA
1
1
0
1
0
0
0
0
PUCR — Pull-Up Control Register
$000C
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These bits select pull-up resistors for any pin in the corresponding port
that is currently configured as an input. This register is not in the map in
peripheral mode.
Read and write anytime.
PUPH — Pull-Up or Pull-Down Port H Enable
0 = Port H pull-ups are disabled.
1 = Enable pull-up/down devices for all port H input pins.
PUPG — Pull-Up or Pull-Down Port G Enable
0 = Port G pull-ups are disabled.
1 = Enable pull-up/down devices for all port G input pins.
PUPE — Pull-Up Port E Enable
0 = Port E pull-ups on PE7 and PE[3:0] are disabled.
1 = Enable pull-up devices for port E input pins PE7 and PE[3:0].
PUPB — Pull-Up Port B Enable
0 = Port B pull-ups are disabled.
1 = Enable pull-up devices for all port B input pins.
This bit has no effect if port B is being used as part of the address/data
bus (the pull-ups are inactive).
PUPA — Pull-Up Port A Enable
0 = Port A pull-ups are disabled.
1 = Enable pull-up devices for all port A input pins.
This bit has no effect if port A is being used as part of the address/data
bus (the pull-ups are inactive).
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Bus Control and Input/Output
Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
RDPH
RDPG
0
RDPE
0
RDPB
RDPA
0
0
0
0
0
0
0
0
RDRIV — Reduced Drive of I/O Lines
$000D
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These bits select reduced drive for the associated port pins. This gives
reduced power consumption and reduced RFI with a slight increase in
transition time (depending on loading). The reduced drive function is
independent of which function is being used on a particular port.
This register is not in the map in peripheral mode.
Normal: write once; Special: write anytime EXCEPT the first time. Read
anytime.
RDPH — Reduced Drive of Port H
0 = All port H output pins have full drive enabled.
1 = All port H output pins have reduced drive capability.
RDPG — Reduced Drive of Port G
0 = All port G output pins have full drive enabled.
1 = All port G output pins have reduced drive capability.
RDPE — Reduced Drive of Port E
0 = All port E output pins have full drive enabled.
1 = All port E output pins have reduced drive capability.
RDPB — Reduced Drive of Port B
0 = All port B output pins have full drive enabled.
1 = All port B output pins have reduced drive capability.
RDPA — Reduced Drive of Port A
0 = All port A output pins have full drive enabled.
1 = All port A output pins have reduced drive capability.
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Bus Control and Input/Output
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Section 7. Flash Memory
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.4
Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .100
7.5
Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6
Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.8
Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 108
7.9
Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.10
Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .113
7.11
Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
7.2 Introduction
The two Flash EEPROM modules (32-Kbyte and 28-Kbyte) for the
68HC912D60 serve as electrically erasable and programmable, nonvolatile ROM emulation memory. The modules can be used for program
code that must either execute at high speed or is frequently executed,
such as operating system kernels and standard subroutines, or they can
be used for static data which is read frequently. The Flash EEPROM is
ideal for program storage for single-chip applications allowing for field
reprogramming.
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7.3 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may
be read as either bytes, aligned words or misaligned words. Access time
is one bus cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
The Flash EEPROM module requires an external program/erase voltage
(VFP) to program or erase the Flash EEPROM array. The external
program/erase voltage is provided to the Flash EEPROM module via an
external VFP pin. To prevent damage to the flash array, VFP should
always be within the specification as defined in Table 20-10 in Electrical
Specifications. Programming is by byte or aligned word. The Flash
EEPROM module supports bulk erase only.
The Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and programprotected 8-Kbyte block for boot routines is located at $6000–$7FFF or
$E000–$FFFF depending upon the mapped location of the Flash
EEPROM arrays.
7.4 Flash EEPROM Control Block
A 4-byte register block for each module controls the Flash EEPROM
module operation. Configuration information is specified and
programmed independently from the contents of the Flash EEPROM
array. At reset, the 4-byte register section starts at address $00F4/$00F8.
7.5 Flash EEPROM Arrays
After reset, the 32K Flash EEPROM array is located from addresses
$8000 to $FFFF and the 28K Flash EEPROM array is from $1000 to
$7FFF. In expanded modes, the Flash EEPROM arrays are turned off.
The Flash EEPROM can be mapped to an alternate address range. See
Operating Modes and Resource Mapping.
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Flash Memory
Flash EEPROM Registers
7.6 Flash EEPROM Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LOCK
0
0
0
0
0
0
0
0
FEE32LCK/FEE28LCK — Flash EEPROM Lock Control Register
$00F4/$00F8
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEExxMCR register
1 = Disable write to FEExxMCR register
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
BOOTP
0
0
0
0
0
0
0
1
FEE32MCR/FEE28MCR — Flash EEPROM Module Configuration Register
$00F5/$00F9
This register controls the operation of the Flash EEPROM array. BOOTP
cannot be changed when the LOCK control bit in the FEExxLCK register
is set or if ENPE in the FEExxCTL register is set.
BOOTP — Boot Protect
The boot blocks are located at $6000–$7FFF and $E000–$FFFF for
each Flash EEPROM module.
0 = Enable erase and program of 8K byte boot block
1 = Disable erase and program of 8K byte boot block
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
FSTE
GADR
HVT
FENLV
FDISVFP
VTCK
STRE
MWPR
0
0
0
0
0
0
0
0
FEE32TST/FEE28TST — Flash EEPROM Module Test Register
$00F6/$00FA
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In normal mode, writes to FEETST control bits have no effect and always
read zero. The Flash EEPROM module cannot be placed in test mode
inadvertently during normal operation.
FSTE — Stress Test Enable
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
GADR — Gate/Drain Stress Test Select
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
HVT — Stress Test High Voltage Status
0 = High voltage not present during stress test
1 = High voltage present during stress test
FENLV — Enable Low Voltage
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
FDISVFP — Disable Status VFP Voltage Lock
When the VFP pin is below normal programming voltage the Flash
module will not allow writing to the LAT bit; the user cannot erase or
program the Flash module. The FDISVFP control bit enables writing
to the LAT bit regardless of the voltage on the VFP pin.
0 = Enable the automatic lock mechanism if VFP is low
1 = Disable the automatic lock mechanism if VFP is low
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Flash EEPROM Registers
VTCK — VT Check Test Enable
When VTCK is set, the Flash EEPROM module uses the VFP pin to
control the control gate voltage; the sense amp time-out path is
disabled. This allows for indirect measurements of the bit cells
program and erase threshold. If VFP < VZBRK (breakdown voltage) the
control gate will equal the VFP voltage.
If VFP > VZBRK the control gate will be regulated by the following
equation:
Vcontrol gate = VZBRK + 0.44 × (VFP − VZBRK)
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0 = VT test disable
1 = VT test enable
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The
reserved word at location 31 contains production test information
which must be maintained through several erase cycles. When STRE
is set, the decoding for the spare test row overrides the address lines
which normally select the other rows in the array.
0 = LIB accesses are to the Flash EEPROM array
1 = Spare test row in array enabled if SMOD is active
MWPR — Multiple Word Programming
Used primarily for testing, if MPWR = 1, the two least-significant
address lines ADDR[1:0] will be ignored when programming a Flash
EEPROM location. The word location addressed if ADDR[1:0] = 00,
along with the word location addressed if ADDR[1:0] = 10, will both be
programmed with the same word data from the programming latches.
This bit should not be changed during programming.
0 = Multiple word programming disabled
1 = Program 32 bits of data
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
FEESWAI
SVFP
ERAS
LAT
ENPE
0
0
0
0
0
0
0
0
FEE32CTL/FEE28CTL — Flash EEPROM Control Register
$00F7/$00FB
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This register controls the programming and erasure of the Flash
EEPROM.
FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
NOTE:
The FEESWAI bit cannot be asserted if the interrupt vector resides in the
Flash EEPROM array.
SVFP — Status VFP Voltage
SVFP is a read only bit.
0 = Voltage of VFP pin is below normal programming voltage levels
1 = Voltage of VFP pin is above normal programming voltage levels
ERAS — Erase Control
This bit can be read anytime or written when ENPE = 0. When set, all
locations in the array will be erased at the same time. The boot block
will be erased only if BOOTP = 0. This bit also affects the result of
attempted array reads. See Table 7-1 for more information. Status of
ERAS cannot change if ENPE is set.
0 = Flash EEPROM configured for programming
1 = Flash EEPROM configured for erasure
LAT — Latch Control
This bit can be read anytime or written when ENPE = 0. When set, the
Flash EEPROM is configured for programming or erasure and, upon
the next valid write to the array, the address and data will be latched
for the programming sequence. See Table 7-1 for the effects of LAT
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Operation
on array reads. A high voltage detect circuit on the VFP pin will prevent
assertion of the LAT bit when the programming voltage is at normal
levels.
0 = Programming latches disabled
1 = Programming latches enabled
ENPE — Enable Programming/Erase
0 = Disables program/erase voltage to Flash EEPROM
1 = Applies program/erase voltage to Flash EEPROM
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ENPE can be asserted only after LAT has been asserted and a write
to the data and address latches has occurred. If an attempt is made
to assert ENPE when LAT is negated, or if the latches have not been
written to after LAT was asserted, ENPE will remain negated after the
write cycle is complete.
The LAT, ERAS and BOOTP bits cannot be changed when ENPE is
asserted. A write to FEExxCTL may only affect the state of ENPE.
Attempts to read a Flash EEPROM array location in the Flash
EEPROM module while ENPE is asserted will not return the data
addressed. See Table 7-1 for more information.
Flash EEPROM module control registers may be read or written while
ENPE is asserted. If ENPE is asserted and LAT is negated on the
same write access, no programming or erasure will be performed.
Table 7-1. Effects of ENPE, LAT and ERAS on Array Reads
ENPE
0
0
0
1
LAT
0
1
1
–
ERAS
–
0
1
–
Result of Read
Normal read of location addressed
Read of location being programmed
Normal read of location addressed
Read cycle is ignored
7.7 Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
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7.7.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
7.7.2 Normal Operation
The Flash EEPROM allows a byte or aligned word read/write in one bus
cycle. Misaligned word read/write require an additional bus cycle. The
Flash EEPROM array responds to read operations only. Write
operations are ignored.
7.7.3 Program/Erase Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes and a
write to a set of programming latches.
Programming is restricted to a single byte or aligned word at a time as
determined by internal signal SZ8 and ADDR[0]. The Flash EEPROM
must first be completely erased prior to programming final data values.
It is possible to program a location in the Flash EEPROM without erasing
the entire array if the new value does not require the changing of bit
values from zero to one.
Read/Write Accesses During Program/Erase — During program or
erase operations, read and write accesses may be different from those
during normal operation and are affected by the state of the control bits
in the Flash EEPROM control register (FEExxCTL). The next write to
any valid address to the array after LAT is set will cause the address and
data to be latched into the programming latches. Once the address and
data are latched, write accesses to the array will be ignored while LAT is
set. Writes to the control registers will occur normally.
Program/Erase Verification — When programming or erasing the
Flash EEPROM array, a special verification method is required to ensure
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Operation
that the program/erase process is reliable, and also to provide the
longest possible life expectancy. This method requires stopping the
program/erase sequence at periods of tPPULSE (tEPULSE for erasing) to
determine if the Flash EEPROM is programmed/erased. After the
location reaches the proper value, it must continue to be
programmed/erased with additional margin pulses to ensure that it will
remain programmed/erased. Failure to provide the margin pulses could
lead to corrupted or unreliable data.
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Program/Erase Sequence — To begin a program or erase sequence
the external VFP voltage must be applied and stabilized. The ERAS bit
must be set or cleared, depending on whether a program sequence or
an erase sequence is to occur. The LAT bit will be set to cause any
subsequent data written to a valid address within the Flash EEPROM to
be latched into the programming address and data latches. The next
Flash array write cycle must be either to the location that is to be
programmed if a programming sequence is being performed, or, if
erasing, to any valid Flash EEPROM array location. Writing the new
address and data information to the Flash EEPROM is followed by
assertion of ENPE to turn on the program/erase voltage to
program/erase the new location(s). The LAT bit must be asserted and
the address and data latched to allow the setting of the ENPE control bit.
If the data and address have not been latched, an attempt to assert
ENPE will be ignored and ENPE will remain negated after the write cycle
to FEExxCTL is completed. The LAT bit must remain asserted and the
ERAS bit must remain in its current state as long as ENPE is asserted.
A write to the LAT bit to clear it while ENPE is set will be ignored. That
is, after the write cycle, LAT will remain asserted. Likewise, an attempt
to change the state of ERAS will be ignored and the state of the ERAS
bit will remain unchanged.
The programming software is responsible for all timing during a program
sequence. This includes the total number of program pulses (nPP), the
length of the program pulse (tPPULSE), the program margin pulses (pm)
and the delay between turning off the high voltage and verifying the
operation (tVPROG).
The erase software is responsible for all timing during an erase
sequence. This includes the total number of erase pulses (em), the
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length of the erase pulse (tEPULSE), the erase margin pulse or pulses,
and the delay between turning off the high voltage and verifying the
operation (tVERASE).
Software also controls the supply of the proper program/erase voltage to
the VFP pin, and should be at the proper level before ENPE is set during
a program/erase sequence.
A program/erase cycle should not be in progress when starting another
program/erase, or while attempting to read from the array.
NOTE:
Although clearing ENPE disables the program/erase voltage (VFP) from
the VFP pin to the array, care must be taken to ensure that VFP is at VDD
whenever programming/erasing is not in progress. Not doing so could
damage the part. Ensuring that VFP is always greater or equal to VDD
can be accomplished by controlling the VFP power supply with the
programming software via an output pin. Alternatively, all programming
and erasing can be done prior to installing the device on an application
circuit board which can always connect VFP to VDD. Programming can
also be accomplished by plugging the board into a special programming
fixture which provides program/erase voltage to the VFP pin.
7.8 Programming the Flash EEPROM
Programming the Flash EEPROM is accomplished by the following
sequence. The VFP pin voltage must be at the proper level prior to
executing step 4 the first time.
1. Apply program/erase voltage to the VFP pin.
2. Clear ERAS and set the LAT bit in the FEExxCTL register to
establish program mode and enable programming address and
data latches.
3. Write data to a valid address. The address and data is latched. If
BOOTP is asserted, an attempt to program an address in the boot
block will be ignored.
4. Apply programming voltage by setting ENPE.
5. Delay for one programming pulse (tPPULSE).
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Programming the Flash EEPROM
6. Remove programming voltage by clearing ENPE.
7. Delay while high voltage is turning off (tVPROG).
8. Read the address location to verify that it has been programmed
•
If the location is not programmed, repeat steps 4 through 7 until
the location is programmed or until the specified maximum
number of program pulses has been reached (nPP)
If the location is programmed, repeat the same number of pulses
as required to program the location. This provides 100% program
margin.
9. Read the address location to verify that it remains programmed.
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•
10. Clear LAT.
11. If there are more locations to program, repeat steps 2 through 10.
12. Turn off VFP (reduce voltage on VFP pin to VDD).
The flowchart in Figure 7-1 demonstrates the recommended
programming sequence.
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START PROG
TURN ON VFP
CLEAR MARGIN FLAG
CLEAR PROGRAM PULSE COUNTER (nPP)
CLEAR ERAS
SET LAT
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WRITE DATA
TO ADDRESS
SET ENPE
DELAY FOR DURATION
OF PROGRAM PULSE
(tPPULSE)
CLEAR ENPE
SET
MARGIN FLAG
DELAY BEFORE VERIFY
(tVPROG)
IS
MARGIN FLAG
SET?
NO
YES
INCREMENT
nPP COUNTER
READ
LOCATION
DECREMENT
nPP COUNTER
DATA
CORRECT?
YES
NO
NO
nPP = 0?
nPP = 50?
YES
DATA
CORRECT?
NO
YES
NO
YES
CLEAR LAT
GET NEXT
ADDRESS/DATA
NO
LOCATION FAILED
TO PROGRAM
DONE?
YES
TURN OFF VFP
DONE PROG
Figure 7-1. Program Sequence Flow
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Erasing the Flash EEPROM
7.9 Erasing the Flash EEPROM
The following sequence demonstrates the recommended procedure for
erasing the Flash EEPROM. The VFP pin voltage must be at the proper
level prior to executing step 4 the first time.
1. Turn on VFP (apply program/erase voltage to the VFP pin).
2. Set the LAT bit and ERAS bit to configure the Flash EEPROM for
erasing.
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3. Write to any valid address in the Flash array. This allows the erase
voltage to be turned on; the data written and the address written
are not important. The boot block will be erased only if the control
bit BOOTP is negated.
4. Apply erase voltage by setting ENPE.
5. Delay for a single erase pulse (tEPULSE).
6. Remove erase voltage by clearing ENPE.
7. Delay while high voltage is turning off (tVERASE).
8. Read the entire array to ensure that the Flash EEPROM is erased.
•
If all of the Flash EEPROM locations are not erased, repeat steps
4 through 7 until either the remaining locations are erased, or until
the maximum erase pulses have been applied (nEP)
•
If all of the Flash EEPROM locations are erased, repeat the same
number of pulses as required to erase the array. This provides
100% erase margin.
9. Read the entire array to ensure that the Flash EEPROM is erased.
10. Clear LAT.
11. Turn off VFP (reduce voltage on VFP pin to VDD).
The flowchart in Figure 7-2 demonstrates the recommended erase
sequence.
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START ERASE
TURN ON VFP
CLEAR MARGIN FLAG
CLEAR ERASE PULSE COUNTER (nEP)
SET ERAS
SET LAT
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WRITE TO ARRAY
SET ENPE
DELAY FOR DURATION
OF ERASE PULSE
(tEPULSE)
CLEAR ENPE
SET
MARGIN FLAG
DELAY BEFORE VERIFY
(tVERASE)
IS
MARGIN FLAG
SET?
NO
YES
DECREMENT
nEP COUNTER
INCREMENT
nEP COUNTER
READ
ARRAY
ARRAY
ERASED?
YES
NO
NO
nEP = 0?
nEP = 5?
YES
YES
ARRAY
ERASED?
NO
NO
YES
CLEAR LAT
TURN OFF VFP
ARRAY ERASED
ARRAY FAILED TO ERASE
Figure 7-2. Erase Sequence Flow
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Program/Erase Protection Interlocks
7.10 Program/Erase Protection Interlocks
The Flash EEPROM program and erase mechanisms provide maximum
protection from accidental programming or erasure.
The voltage required to program/erase the Flash EEPROM (VFP) is
supplied via an external pin. If VFP is not present, no
programming/erasing will occur. Furthermore, the program/erase
voltage will not be applied to the Flash EEPROM unless turned on by
setting a control bit (ENPE). The ENPE bit may not be set unless the
programming address and data latches have been written previously
with a valid address. The latches may not be written unless enabled by
setting a control bit (LAT). The LAT and ENPE control bits must be
written on separate writes to the control register (FEExxCTL) and must
be separated by a write to the programming latches. The ERAS and LAT
bits are also protected when ENPE is set. This prevents inadvertent
switching between erase/program mode and also prevents the latched
data and address from being changed after a program cycle has been
initiated.
7.11 Stop or Wait Mode
When stop or wait commands are executed, the MCU puts the Flash
EEPROM in stop or wait mode. In these modes the Flash module will
cease erasure or programming immediately. It is advised not to enter
stop or wait modes when programming the Flash array.
CAUTION:
The Flash EEPROM module requires a 250nsec delay for wake-up from
STOP mode. If the operating bus frequency is greater than 4MHz, the
Flash cannot be used when recovering from STOP mode when the DLY
bit in the INTCR register is cleared.
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Section 8. EEPROM Memory
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3
Future EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
8.4
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .117
8.5
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.2 Introduction
The 68HC(9)12D60 EEPROM nonvolatile memory is arranged in a 16bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in all modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the
internal VDD supply with an internal charge pump.
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8.3 Future EEPROM Support
Design is underway to introduce an improved EEPROM module with
integrated state machine to simplify programming and erase. This will be
introduced on the 68HC912D60A together with 5V programming Flash
EEPROM.
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Appendix: 68HC912D60A EEPROM contains detailed information to
assist in software planning for future EEPROM compatibility and
transition to the 68HC912D60A. Read, write and erase algorithms are
fully compatible with the present EEPROM design. The key change
comes in the form of a self timed state machine for erasing & writing
data. This is implemented using a pre-scaler loaded from a new word
register EEDIV ($00EE) - located in a presently unused location this
register can be written without effect, reading the location will return
unpredictable data.
Adding 5 bytes of initialisation code to current software to load EEDIV
(with value appropriate for the application’s crystal frequency, EXTALi)
will help ensure compatibility.
Other new features for performance improvement are disabled at reset
providing a compatible algorithm for modifying the EEPROM.
CAUTION:
Other areas for consideration include:
Program/Erase is not guaranteed in Limp home mode. Clock monitor
CME bit must be enabled during program/erase.
Program/erase should not be performed with input clock frequency <250
KHz.
Resonator/crystal frequency tolerance should be better than 2% total for
< 2MHz, 3% total for >= 2MHz.
Successive writes to an EEPROM location must be preceded by an
erase cycle.
To ensure full compatibility it is recommended that all of Appendix:
68HC912D60A EEPROM be reviewed.
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EEPROM Programmer’s Model
8.4 EEPROM Programmer’s Model
The EEPROM module consists of two separately addressable sections.
The first is a four-byte memory mapped control register block used for
control, testing and configuration of the EEPROM array. The second
section is the EEPROM array itself.
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At reset, the four-byte register section starts at address $00F0 and the
EEPROM array is located from addresses $0C00 to $0FFF. For
information on re-mapping the register block and EEPROM address
space, refer to Operating Modes and Resource Mapping.
Read/write access to the memory array section can be enabled or
disabled by the EEON control bit in the INITEE register. This feature
allows the access to memory mapped resources with lower priority than
the EEPROM memory array. EEPROM control registers can be accessed
regardless of the state of EEON. Any EEPROM erase or program
operations already in progress will not be affected by modifying EEON.
Using the normal EEPROG control, it is possible to continue
program/erase operations during WAIT. For lowest power consumption
during WAIT, stop program/erase by turning off EEPGM.
If the STOP mode is entered during programming or erasing,
program/erase voltage will be automatically turned off and the RC clock
(if enabled) is stopped. However, the EEPGM control bit will remain set.
When STOP mode is terminated, the program/erase voltage will be
automatically turned back on if EEPGM is set.
At low bus frequencies, the RC clock must be turned on for
program/erase.
The EEPROM module contains an extra byte called SHADOW byte which
is loaded at reset into the EEMCR register. To program the SHADOW
byte, when in special modes (SMODN=0), the NOSHB bit in EEMCR
register must be cleared. Normal programming routines are used to
program the SHADOW byte which becomes accessible at address $0FC0
when NOSHB is cleared. At the next reset the SHADOW byte data is
loaded into the EEMCR. The SHADOW byte can be protected from being
programmed or erased by setting the SHPROT bit of EEPROT register.
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EEPROM Memory
8.5 EEPROM Control Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
NOBDML
NOSHB
1(1)
1(1)
1
EESWAI
PROTLCK
EERC
—(2)
—(2)
—(2)
—(2)
1
1
0
0
EEMCR — EEPROM Module Configuration
$00F0
1. Bits 4 and 5 have test functions and should not be cleared (set to ‘0’).
2. Loaded from SHADOW byte.
Bits[7:4] are loaded at reset from the EEPROM SHADOW byte.
NOTE:
Bits 5 and 4 are reserved for test purposes. These locations in the
SHADOW byte should not be programmed otherwise some locations in
the regular EEPROM array will no longer be visible.
NOBDML — Background Debug Mode Lockout Disable
0 = The BDM lockout is enabled.
1 = The BDM lockout is disabled.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
NOSHB — SHADOW Byte Disable
0 = SHADOW byte enabled and accessible at address $0FC0.
1 = Regular EEPROM array at address $0FC0.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
When NOSHB cleared, the regular EEPROM array byte at address
$0FC0 is no longer visible. The SHADOW byte is accessed instead
for both read and program/erase operations. BULK, ODD and EVEN
program/erase only apply if the SHADOW byte is enabled.
NOTE:
Bit 6 of the SHADOW byte should not be cleared (set to '0') in order to
have the full EEPROM array visible. If Bit 6 from the SHADOW byte is
cleared then the following thirty-one bytes $0FC1–$0FFF have no
meaning and are reserved by Motorola.
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EEPROM Memory
EEPROM Control Registers
EESWAI — EEPROM Stops in Wait Mode
0 = The module is not affected during WAIT mode
1 = The module ceases to be clocked during WAIT mode
Read and write anytime.
NOTE:
The EESWAI bit should be cleared if the WAIT mode vectors are
mapped in the EEPROM array.
PROTLCK — Block Protect Write Lock
0 = Block protect bits and bulk erase protection bit can be written
1 = Block protect bits are locked
Read anytime. Write once in normal modes (SMODN = 1), set and
clear any time in special modes (SMODN = 0).
EERC — EEPROM Charge Pump Clock
0 = System clock is used as clock source for the internal charge
pump. Internal RC oscillator is stopped.
1 = Internal RC oscillator drives the charge pump. The RC
oscillator is required when the system bus clock is lower than
fPROG.
Read and write anytime.
Bit 7
6
5
4
3
2
1
Bit 0
SHPROT
1
1
BPROT4
BPROT3
BPROT2
BPROT1
BPROT0
1
1
1
1
1
1
1
1
RESET:
EEPROT — EEPROM Block Protect
$00F1
Prevents accidental writes to EEPROM. Read anytime. Write anytime if
EEPGM = 0 and PROTLCK = 0.
SHPROT — SHADOW Byte Protection
0 = The SHADOW byte can be programmed and erased.
1 = The SHADOW byte is protected from being programmed and
erased.
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BPROT[4:0] — EEPROM Block Protection
0 = Associated EEPROM block can be programmed and erased.
1 = Associated EEPROM block is protected from being
programmed and erased.
Table 8-1. 1K byte EEPROM Block Protection
Bit Name
BPROT4
BPROT3
BPROT2
BPROT1
BPROT0
RESET:
Block Protected
$0C00 to $0DFF
$0E00 to $0EFF
$0F00 to $0F7F
$0F80 to $0FBF
$0FC0 to $0FFF
Block Size
512 Bytes
256 Bytes
128 Bytes
64 Bytes
64 Bytes
Bit 7
6
5
4
3
2
1
Bit 0
BULKP
0
0
BYTE
ROW
ERASE
EELAT
EEPGM
1
0
0
0
0
0
0
0
EEPROG — EEPROM Control
$00F3
BULKP — Bulk Erase Protection
0 = EEPROM can be bulk erased.
1 = EEPROM is protected from being bulk or row erased.
Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.
BYTE — Byte and Aligned Word Erase
0 = Bulk or row erase is enabled.
1 = One byte or one aligned word erase only.
Read anytime. Write anytime if EEPGM = 0.
ROW — Row or Bulk Erase (when BYTE = 0)
0 = Erase entire EEPROM array.
1 = Erase only one 32-byte row.
Read anytime. Write anytime if EEPGM = 0.
BYTE and ROW have no effect when ERASE = 0
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EEPROM Control Registers
Table 8-2. Erase Selection
BYTE
0
0
1
1
ROW
0
1
0
1
Block size
Bulk erase entire EEPROM array
Row erase 32 bytes
Byte or aligned word erase
Byte or aligned word erase
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ERASE — Erase Control
0 = EEPROM configuration for programming.
1 = EEPROM configuration for erasure.
Read anytime. Write anytime if EEPGM = 0.
Configures the EEPROM for erasure or programming.
EELAT — EEPROM Latch Control
0 = EEPROM set up for normal reads.
1 = EEPROM address and data bus latches set up for
programming or erasing.
Read anytime. Write anytime if EEPGM = 0.
BYTE, ROW, ERASE and EELAT bits can be written simultaneously
or in any sequence.
EEPGM — Program and Erase Enable
0 = Disables program/erase voltage to EEPROM.
1 = Applies program/erase voltage to EEPROM.
The EEPGM bit can be set only after EELAT has been set. When
EELAT and EEPGM are set simultaneously, EEPGM remains clear
but EELAT is set.
The BULKP, BYTE, ROW, ERASE and EELAT bits cannot be
changed when EEPGM is set. To complete a program or erase, two
successive writes to clear EEPGM and EELAT bits are required
before reading the programmed data. A write to an EEPROM location
has no effect when EEPGM is set. Latched address and data cannot
be modified during program or erase.
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A program or erase operation should follow the sequence below:
1. Write BYTE, ROW and ERASE to the desired value, write EELAT
=1
2. Write a byte or an aligned word to an EEPROM address
3. Write EEPGM = 1
4. Wait for programming (tPROG) or erase (terase) delay time
5. Write EEPGM = 0
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6. Write EELAT = 0
It is possible to program/erase more bytes or words without intermediate
EEPROM reads, by jumping from step 5 to step 2.
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Section 9. Resets and Interrupts
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.3
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.4
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.5
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . .127
9.6
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.7
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.8
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.9
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.2 Introduction
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
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Resets and Interrupts
9.2.1 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
maskable. The remaining sources are maskable, and any one of them
can be given priority over other maskable interrupts.
The priorities of the non-maskable sources are:
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. Unimplemented instruction trap
5. Software interrupt instruction (SWI)
6. XIRQ signal (if X bit in CCR = 0)
9.3 Maskable interrupts
Maskable interrupt sources include on-chip peripheral systems and
external interrupt service requests. Interrupts from these sources are
recognized when the global interrupt mask bit (I) in the CCR is cleared.
The default state of the I bit out of reset is one, but it can be written at
any time.
Interrupt sources are prioritized by default but any one maskable
interrupt source may be assigned the highest priority by means of the
HPRIO register. The relative priorities of the other sources remain the
same.
An interrupt that is assigned highest priority is still subject to global
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. HPRIO can only be
written while the I bit is set (interrupts inhibited). Table 9-1 lists interrupt
sources and vectors in default order of priority.
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Latching of Interrupts
9.4 Latching of Interrupts
XIRQ is always level triggered and IRQ can be selected as a level
triggered interrupt. These level triggered interrupt pins should only be
released during the appropriate interrupt service routine. Generally the
interrupt service routine will handshake with the interrupting logic to
release the pin. In this way, the MCU will start the interrupt service
sequence only to determine that there is no longer an interrupt source.
In the event that this does not occur, the trap vector will be taken.
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If IRQ is selected as an edge triggered interrupt, the hold time of the level
after the active edge is independent of when the interrupt is serviced. As
long as the minimum hold time is met, the interrupt will be latched inside
the MCU. In this case the IRQ edge interrupt latch is cleared
automatically when the interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit.
These interrupt flags should be cleared during an interrupt service
routine or when interrupts are masked by the I bit. By doing this, the
MCU will never get an unknown interrupt source and take the trap vector.
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Resets and Interrupts
Table 9-1. Interrupt Vector Map
Vector Address
Interrupt Source
CCR
Mask
None
None
None
None
None
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Reset
Clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time interrupt
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
$FFD6, $FFD7
SCI 0
I bit
$FFD4, $FFD5
SCI 1
I bit
$FFD2, $FFD3
$FFD0, $FFD1
ATD0 or ATD1
MSCAN wake-up
I bit
I bit
$FFCE, $FFCF
Key wake-up G or H
I bit
$FFCC, $FFCD
$FFCA, $FFCB
Modulus down counter underflow
Pulse Accumulator B Overflow
I bit
I bit
$FFC8, $FFC9
MSCAN errors
I bit
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FF80–$FFC1
MSCAN receive
MSCAN transmit
CGM lock and limp home
Reserved
I bit
I bit
I bit
I bit
Local Enable
None
COPCTL (CME, FCME)
COP rate selected
None
None
None
INTCR (IRQEN)
RTICTL (RTIE)
TMSK1 (C0I)
TMSK1 (C1I)
TMSK1 (C2I)
TMSK1 (C3I)
TMSK1 (C4I)
TMSK1 (C5I)
TMSK1 (C6I)
TMSK1 (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
SC1CR2
(TIE, TCIE, RIE, ILIE)
ATDxCTL2 (ASCIE)
CRIER (WUPIE)
KWIEG[6:0] and
KWIEH[7:0]
MCCTL (MCZI)
PBCTL (PBOVI)
CRIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
CRIER (RXFIE)
CTCR (TXEIE[2:0])
PLLCR (LOCKIE, LHIE)
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HPRIO Value to
Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$CC
$CA
$C8
$C6
$C4
$C2
$80–$C0
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Interrupt Control and Priority Registers
9.5 Interrupt Control and Priority Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
IRQE
IRQEN
DLY
0
0
0
0
0
0
1
1
0
0
0
0
0
INTCR — Interrupt Control Register
$001E
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin
PE1/IRQ).
IRQE can be read anytime and written once in normal modes. In
special modes, IRQE can be read anytime and written anytime,
except the first write is ignored.
IRQEN — External IRQ Enable
The IRQ pin has an active pull-up. See Table 3-4.
0 = External IRQ pin is disconnected from interrupt logic.
1 = External IRQ pin is connected to interrupt logic.
IRQEN can be read and written anytime in all modes.
DLY — Enable Oscillator Start-up Delay on Exit from STOP
The delay time of about 4096 cycles is based on the X clock rate
chosen.
0 = No stabilization delay imposed on exit from STOP mode. A
stable external oscillator must be supplied.
1 = Stabilization delay is imposed before processing resumes after
STOP.
DLY can be read anytime and written once in normal modes. In
special modes, DLY can be read and written anytime.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
1
1
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
0
1
1
1
1
0
0
1
0
HPRIO — Highest Priority I Interrupt
$001F
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
To give a maskable interrupt source highest priority, write the low byte of
the vector address to the HPRIO register. For example, writing $F0 to
HPRIO would assign highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an un-implemented vector address or a non-Imasked vector address (value higher than $F2) is written, then IRQ will
be the default highest priority interrupt.
9.6 Resets
There are four possible sources of reset. Power-on reset (POR), and
external reset on the RESET pin share the normal reset vector. The
computer operating properly (COP) reset and the clock monitor reset
each has a vector. Entry into reset is asynchronous and does not require
a clock but the MCU cannot sequence out of reset without a system
clock.
9.6.1 Power-On Reset
A positive transition on VDD causes a power-on reset (POR). An external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
It is important to use an external low voltage reset circuit (for example:
MC34064 or MC33464) to prevent power transitions or corruption of
RAM or EEPROM.
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Resets
9.6.2 External Reset
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than eight Eclock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for about 16 E-clock cycles, then released. Eight E-clock cycles later it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an
external reset, hold the reset pin low for at least 32 cycles. An external
RC power-up delay circuit on the reset pin is not recommended as circuit
charge time can cause the MCU to misinterpret the type of reset that has
occurred.
9.6.3 COP Reset
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When COP is enabled, software must
write $55 and $AA (in this order) to the COPRST register in order to keep
a watchdog timer from timing out. Other instructions may be executed
between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
9.6.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
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9.7 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
9.7.1 Operating Mode and Memory Map
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The SMODN,
MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
9.7.2 Clock and Watchdog Control Logic
The COP watchdog system is enabled, with the CR[2:0] bits set for the
longest duration time-out. The clock monitor is disabled. The RTIF flag
is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is
used. The DLY control bit is set to specify an oscillator start-up delay
upon recovery from STOP mode.
9.7.3 Interrupts
PSEL is initialized in the HPRIO register with the value $F2, causing the
external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin
is configured for level-sensitive operation (for wired-OR systems).
However, the interrupt mask bits in the CPU12 CCR are set to mask Xand I-related interrupt requests.
9.7.4 Parallel I/O
If the MCU comes out of reset in a single-chip mode, all ports are
configured as general-purpose high-impedance inputs.
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Register Stacking
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus (operation of port E pins can be affected by the
PEAR register). Out of reset, port G, port H, port P, port S, port T, port
CAN[7:2], port AD0 and port AD1 are all configured as general-purpose
inputs.
9.7.5 Central Processing Unit
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
9.7.6 Memory
After reset, the internal register block is located from $0000 to $01FF,
RAM is at $0000 to $07FF, and EEPROM is at $0C00 to $0FFF. In single
chip mode the two FLASH EEPROM(68HC912D60)/ROM(68HC12D60)
modules are located from $1000 to $7FFF and $8000 to $FFFF.
9.7.7 Other Resources
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), Motorola Scalable CAN (MSCAN) and
analog-to-digital converters (ATD0 and ATD1) are off after reset.
9.8 Register Stacking
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
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required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in Table 9-2.
Table 9-2. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
CPU Registers
RTNH : RTNL
SP – 4
YH : YL
SP – 6
XH : XL
SP – 8
SP – 9
B:A
CCR
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
If another interrupt is pending at the end of an interrupt service routine,
the register unstacking and restacking is bypassed and the vector of the
interrupt is fetched.
9.9 Customer Information
Before disabling an interrupt using a local interrupt control bit, set the I
mask bit in the CCR. Failing to do so may cause an SWI interrupt to be
fetched instead of the vector for the interrupt source that was disabled.
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Section 10. ROM
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.3
ROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.2 Introduction
The 68HC12D60 contains 60 Kbytes of read-only memory (ROM). The
ROM array is arranged in a 16-bit configuration and may be read as
either bytes, aligned words or misaligned words. Access time is one bus
cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
10.3 ROM Array
The ROM is made of a 28K byte array mapped from $1000 to $7FFF and
of a 32 K byte array mapped from $8000 to $FFFF at reset. The
MAPROM bit in the MISC register allows the swapping of the two arrays.
ROMON28 and ROMON32 enable or disable the ROM module.
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ROM
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Section 11. I/O Ports with Key Wake-up
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
11.3
Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . .136
11.4
Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.2 Introduction
The 112QFP 68HC(9)12D60 offers 16 additional I/O port pins with key
wake-up capability on 15 of them (KWG7 is used for I2C start detect).
Only two (KWG4 and KWH4) are available on the 80QFP package. All
Port G and Port H pins should either be defined as outputs or have their
pull-ups/downs enabled.
The key wake-up feature of the 68HC(9)12D60 issues an interrupt that
will wake up the CPU when it is in the STOP or WAIT mode. Two ports
are associated with the key wake-up function: port G and port H. Port G
and port H wake-ups are triggered with a falling signal edge. For each
pin which has an interrupt enabled, there is a path to the interrupt
request signal which has no clocked devices when the part is in stop
mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFG or KWIFH register and
its corresponding KWIEG or KWIEH bit are both set. All 15 bits/pins
share the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
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I/O Ports with Key Wake-up
Pull-up/down status is selected by PGUPD and PHUPD input pins: pullup when PxUPD pin is high, pull-down when PxUPD pin is low. On
80QFP these pins are tied internally so that KWG4 is pull-up and KWH4
is pull-down.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes and Resource Mapping.
11.3 Key Wake-up and Port Registers
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RESET:
—
—
—
—
—
—
—
—
Alt. Pin
Function
—
KWG6
KWG5
KWG4
KWG3
KWG2
KWG1
KWG0
PORTG — Port G Register
$0028
Read and write anytime.
Bit 7
6
5
4
3
2
1
Bit 0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
RESET:
—
—
—
—
—
—
—
—
Alt. Pin
Function
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
PORTH — Port H Register
$0029
Read and write anytime.
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Key Wake-up and Port Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
0
0
0
0
0
0
0
0
DDRG — Port G Data Direction Register
$002A
Data direction register G is associated with port G and designates each
pin as an input or output.
Read and write anytime
0 = Associated pin is an input
1 = Associated pin is an output
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
0
0
0
0
0
0
0
0
DDRH — Port H Data Direction Register
$002B
Data direction register H is associated with port H and designates each
pin as an input or output.
Read and write anytime.
0 = Associated pin is an input
1 = Associated pin is an output
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I/O Ports with Key Wake-up
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
WI2CE
KWIEG6
KWIEG5
KWIEG4
KWIEG3
KWIEG2
KWIEG1
KWIEG0
0
0
0
0
0
0
0
0
KWIEG — Key Wake-up Port G Interrupt Enable Register
$002C
Read and write anytime.
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WI2CE — Wake-up I2C Enable
0 = PG6 default key wake-up on falling edge
1 = I2C Start condition detection on PG7 and PG6
When WI2CE is set, PG6 and PG7 operate in wired-OR or open-drain
mode.
The I2C Start condition is defined as a high to low transition of the
SDA line when SCL is high. When WI2CE is set, a falling edge on
PG6 (SDA) is recognized only if PG7 (SCL) is high.
Depending on WI2CE bit, KWIEG6 enables either falling edge or I2C
Start condition interrupt.
KWIEG[6:0] — Key Wake-up Port G Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
KWIEH7
KWIEH6
KWIEH5
KWIEH4
KWIEH3
KWIEH2
KWIEH1
KWIEH0
0
0
0
0
0
0
0
0
KWIEH — Key Wake-up Port H Interrupt Enable Register
$002D
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
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Key Wake-up and Port Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
KWIFG6
KWIFG5
KWIFG4
KWIFG3
KWIFG2
KWIFG1
KWIFG0
0
0
0
0
0
0
0
0
KWIFG — Key Wake-up Port G Flag Register
$002E
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Each flag, except bit 6, is set by a falling edge on its associated input pin.
To clear the flag, write one to the corresponding bit in KWIFG.
Read and write anytime
Bit 7 always reads zero.
KWIFG6 — Key Wake-up Port G Flag 6
0 = Falling edge on the associated bit or I2C Start condition has not
occurred
1 = Falling edge on the associated bit or I2C Start condition has
occurred (an interrupt will occur if the associated enable bit is set)
Depending on WI2CE bit in KWIEG register, KWIFG6 flags either
falling edge or I2C Start condition.
KWIFG[5:0] — Key Wake-up Port G Flags
0 = Falling edge on the associated bit has not occurred
1 = Falling edge on the associated bit has occurred (an interrupt
will occur if the associated enable bit is set).
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
KWIFH7
KWIFH6
KWIFH5
KWIFH4
KWIFH3
KWIFH2
KWIFH1
KWIFH0
0
0
0
0
0
0
0
0
KWIFH — Key Wake-up Port H Flag Register
$002F
Read and write anytime.
Each flag is set by a falling edge on its associated input pin. To clear the
flag, write one to the corresponding bit in KWIFH.
KWIFH[7:0] — Key Wake-up Port H Flags
0 = Falling edge on the associated bit has not occurred
1 = Falling edge on the associated bit has occurred (an interrupt
will occur if the associated enable bit is set)
11.4 Key Wake-Up Input Filter
The KWU input signals are filtered by a digital filter which is active only
during STOP mode. The purpose of the filter is to prevent single pulses
shorter than a specified value from waking the part from STOP.
The filter is composed of an internal oscillator and a majority voting logic.
The filter oscillator starts the oscillation by detecting a triggering edge on
an input if the corresponding interrupt enable bit is set. The majority
voting logic takes three samples of an asserted input pin at each filter
oscillator period and if two samples are taken at the triggering level, the
filter recognizes a valid triggering level and sets the corresponding
interrupt flag. In this way the majority voting logic rejects the short nontriggering state between two incoming triggering pulses. As the filter is
shared with all KWU inputs, the filter considers any pulse coming from
any input pin for which the corresponding interrupt enable bit is set.
The timing specification is given for a single pulse. The time interval
between the triggering edges of two following pulses should be greater
than the tKWSP in order to be considered as a single pulse by the filter. If
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Key Wake-Up Input Filter
this time interval is shorter than tKWSP, the majority voting logic may treat
the two consecutive pulses as a single valid pulse.
The filter is shared by all the KWU pins. Hence any valid triggering level
on any KWU pin is seen by the filter. The timing specification applies to
the input of the filter.
Glitch, filtered out, no STOP wake-up
Valid STOP Wake-Up pulse
tKWSTP min.
tKWSTP max.
Minimum time interval between pulses to be recognized as single pulses
tKWSP
Figure 11-1. STOP Key Wake-up Filter (falling edge trigger) timing
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Section 12. Clock Functions
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.3
Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4
Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.5
Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .147
12.6
Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . 149
12.7
System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . .167
12.8
Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.9
Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .172
12.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.2 Introduction
Clock generation circuitry generates the internal and external E-clock
signals as well as internal clock signals used by the CPU and on-chip
peripherals. A clock monitor circuit, a computer operating properly
(COP) watchdog circuit, and a periodic interrupt circuit are also
incorporated into the 68HC(9)12D60.
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Clock Functions
12.3 Clock Sources
A compatible external clock signal can be applied to the EXTAL pin or
the MCU can generate a clock signal using an on-chip oscillator circuit
and an external crystal or ceramic resonator. The MCU uses several
types of internal clock signals derived from the primary clock signal:
TxCLK clocks are used by the CPU.
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ECLK and PCLK are used by the bus interfaces, SPI, PWM, ATD0 and
ATD1.
MCLK is either PCLK or XCLK, and drives on-chip modules such as
SCI0, SCI1 and ECT.
XCLK drives on-chip modules such as RTI, COP and restart-from-stop
delay time.
SLWCLK is used as a calibration output signal.
The MSCAN module is clocked by EXTALi or SYSCLK, under control of
an MSCAN bit.
The clock monitor is clocked by EXTALi.
The BDM system is clocked by BCLK or ECLK, under control of a BDM
bit.
A slow mode clock divider is included to deliver a lower clock frequency
for the SCI baud rate generators, the ECT timer module, and the RTI and
COP clocks. The slow clock bus frequencies divide the crystal frequency
in a programmable range of 4 to 252, with steps of 4.
Figure 12-1 shows some of the timing relationships. See the Clock
Divider Chains section for further details.
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Phase-Locked Loop (PLL)
T1CLK
T2CLK
T3CLK
T4CLK
INT ECLK
PCLK
XCLK
CANCLK
Figure 12-1. Internal Clock Relationships
12.4 Phase-Locked Loop (PLL)
The phase-locked loop (PLL) of the 68HC(9)12D60 is designed for
robust operation in an Automotive environment. The allowed PLL crystal
or ceramic resonator reference of 0.5 to 8MHz is selected for the wide
availability of components with good stability over the automotive
temperature range. Please refer to Figure 12-6 in section Clock Divider
Chains for an overview of system clocks.
NOTE:
When selecting a crystal, it is recommended to use one with the lowest
possible frequency in order to minimise EMC emissions.
An oscillator design with reduced power consumption allows for slow
wait operation with a typical power supply current less than a milliampere. The PLL circuitry can be bypassed when the VDDPLL supply is
at VSS level. In this case, the PLL module is powered down and the
oscillator output transistor has a stronger transconductance for improved
drive of higher frequency resonators (as the crystal frequency needs to
be twice the maximum bus frequency). Refer to Figure 3-5 in Pinout and
Signal Descriptions.
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EXTAL
REDUCED
CONSUMPTION
OSCILLATOR
REFERENCE
PROGRAMMABLE
DIVIDER
LOCK
LOCK
DETECTOR
REFDV <2:0>
REFCLK
XTAL
EXTALi
DIVCLK
PDET
PHASE
DETECTOR
UP
DOWN
CPUMP
VCO
VDDPLL
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SLOW MODE
PROGRAMMABLE
CLOCK DIVIDER
SLWCLK
LOOP
PROGRAMMABLE
DIVIDER
LOOP
FILTER
÷2
SLDV <5:0>
EXTALi
SYN <5:0>
XCLK
XFC
PAD
×2
PLLCLK
Figure 12-2. PLL Functional Diagram
The PLL may be used to run the MCU from a different time base than the
incoming crystal value. It creates an integer multiple of a reference
frequency. For increased flexibility, the crystal clock can be divided by
values in a range of 1 – 8 (in unit steps) to generate the reference
frequency. The PLL can multiply this reference clock in a range of 1 to
64. Although it is possible to set the divider to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If the PLL is selected, it will continue to run when in WAIT mode resulting
in more power consumption than normal. To take full advantage of the
reduced power consumption of WAIT mode, turn off the PLL before
going into WAIT. Please note that in this case the PLL stabilization time
applies.
The PLL operation is suspended in STOP mode. After STOP exit
followed by the stabilization time, it resumes operation at the same
frequency, provided the AUTO bit is set.
A passive external loop filter must be placed on the control line (XFC
pad). The filter is a second-order, low-pass filter to eliminate the VCO
input ripple. Values of components in the diagram are dependent upon
the desired VCO operation. See XFC description.
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Acquisition and Tracking Modes
12.5 Acquisition and Tracking Modes
The lock detector compares the frequencies of the VCO feedback clock,
DIVCLK, and the final reference clock, REFCLK. Therefore, the speed
of the lock detector is directly proportional to the final reference
frequency. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
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The PLL filter is manually or automatically configurable into one of two
operating modes:
•
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO
frequency is far off the desired frequency. This mode can also be
desired in harsh environments when the leakage levels on the
filter pin (XFC) can overcome the tracking currents of the PLL
charge pump. When in acquisition mode, the ACQ bit in the PLL
control register is clear.
•
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. The PLL enters tracking
mode when the VCO frequency is nearly correct. The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. With an identical filtering time constant, the
PLL bandwidth is larger in acquisition mode than in tracking by a ratio of
about 3.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, PLLCLK, is safe to use as the source for the base clock,
SYSCLK. If PLL LOCK interrupt requests are enabled, the software can
wait for an interrupt request and then check the LOCK bit. If CPU
interrupts are disabled, software can poll the LOCK bit continuously
(during PLL start-up, usually) or at periodic intervals. In either case,
when the LOCK bit is set, the PLLCLK clock is safe to use as the source
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for the base clock. See Clock Divider Chains. If the VCO is selected as
the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate
action, depending on the application.
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The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit is a read-only indicator of the mode of the filter.
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆trk, and is cleared when the VCO frequency is out of a
certain tolerance, ∆unt. See 19 Electrical Characteristics.
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
•
The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆unl. See 19 Electrical Characteristics.
•
CPU interrupts can occur if enabled (LOCKIE = 1) when the lock
condition changes, toggling the LOCK bit.
The PLL also can operate in manual mode (AUTO = 0). All LOCK
features described above are active in this mode, only the bandwidth
control is disabled. Manual mode is used mainly for systems operating
under harsh conditions (e.g.uncoated PCBs in automotive
environments). When this is the case, the PLL is likely to remain in
acquisition mode. The following conditions apply when in manual mode:
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
•
In case tracking is desired (ACQ = 1), the software must wait a
given time, tacq, after turning on the PLL by setting PLLON in the
PLL control register. This is to avoid switching to tracking mode
too early while the XFC voltage level is still too far away from its
quiescent value corresponding to the target frequency. This
operation would be very detrimental to the stabilization time.
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Clock Functions
Limp-Home and Fast STOP Recovery modes
12.6 Limp-Home and Fast STOP Recovery modes
If the crystal frequency is not available due to a crystal failure or a long
crystal start-up time, the MCU system clock can be supplied by the VCO
at its minimum operating frequency, f VCOMIN. This mode of operation is
called Limp-Home Mode and is only available when the VDDPLL supply
voltage is at VDD level (i.e. power supply for the PLL module is present).
Upon power-up, the ability of the system to start in Limp-Home Mode is
restricted to normal MCU modes only.
The Clock Monitor circuit (see section Clock Monitor) can detect the loss
of EXTALi, the external clock input signal, regardless of whether this
signal is used as the source for MCU clocks or as the PLL reference
clock. The clock monitor control bits, CME and FCME, are used to
enable or disable external clock detection.
A missing external clock may occur in the three following instances:
•
During normal clock operation.
•
At Power-On Reset.
•
In the STOP exit sequence
12.6.1 Clock Loss during Normal Operation
The ‘no limp-home mode’ bit, NOLHM, determines how the MCU
responds to an external clock loss in this case.
With limp home mode disabled (NOLHM bit set) and the clock monitor
enabled (CME or FCME bits set), on a loss of clock the MCU is reset via
the clock monitor reset vector. A latch in the PLL control section prevents
the chip exiting reset in Limp Home Mode (this is required as the NOLHM
bit gets cleared by reset). Only external clock activity can bring the MCU
out from this reset state. Once reset has been exited, the latch is cleared
and another session, with or without Limp Home Mode enabled, can
take place. This is the same behavior as standard M68HC12 circuits
without PLL or operation with VDDPLL at VSS level.
With limp home mode enabled (NOLHM bit cleared) and the clock
monitor enabled (CME or FCME bits set), on a loss of clock, the PLL
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VCO clock at its minimum frequency, f VCOMIN, is provided as the system
clock, allowing the MCU to continue operating.
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The MCU is said to be operating in “limp-home” mode with the forced
VCO clock as the system clock. PLLON and BCSP (‘bus clock select
PLL’) signals are forced high and the MCS (‘module clock select’) signal
is forced low. The LHOME flag in the PLLFLG register is set to indicate
that the MCU is running in limp-home mode. A change of this flag sets
the limp-home interrupt flag, LHIF, and if enabled by the LHIE bit, the
limp-home mode interrupt is requested. The Clock Monitor is enabled
irrespective of CME and FCME bit settings. Module clocks to the RTI &
COP (XCLK), BDM (BCLK) and ECT & SCI (MCLK) are forced to be
PCLK (at f VCOMIN) and ECLK is also equal to f VCOMIN. MSCAN clock
select is unaffected.
EXTALi
A
B
Clock Monitor Fail
0 --> 4096
0 --> 4096
13-stage counter
(Clocked by XCLK)
Limp-Home
BCSP
SYSCLK
Restore BCSP
PLLCLK (Limp-Home)
Restore PLLCLK or EXTALi
Figure 12-3. Clock Loss during Normal Operation
The clock monitor is polled each time the 13-stage free running counter
reaches a count of 4096 XCLK cycles i.e. mid-count, hence the clock
status gets checked once every 8192 XCLK cycles. When the presence
of an external clock is detected, the MCU exits limp-home mode,
clearing the LHOME flag and setting the limp-home interrupt flag. Upon
leaving limp-home mode, BCSP and MCS signals are restored to their
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Limp-Home and Fast STOP Recovery modes
values before the clock loss. All clocks return to their normal settings and
Clock Monitor control is returned to the CME & FCME bits. If AUTO and
BCSP bits were set before the clock loss (selecting the PLL to provide a
system clock) the SYSCLK ramps-up and the PLL locks at the previously
selected frequency. To prevent PLL operation when the external clock
frequency comes back, software should clear the BCSP bit while running
in limp-home mode.
The two shaded regions A and B in Figure 12-3 present a of code run
away due to incorrect clocks on SYSCLK if the MCU is clocked by
EXTALi and the PLL is not used.
In region A, there is a delay between the loss of clock and its detection
by the clock monitor. When the EXTALi clock signal is disturbed, the
clock generation circuitry may receive an out of spec signal and drive the
CPU with irregular clocks. This may lead to code runaway.
In region B, as the 13-stage counter is free running, the count of 4096
may be reached when the amplitude of the EXTALi clock has not
stabilized. In this case, an improper EXTALi is sent to the clock
generation circuitry when limp-home mode is exited. This may also
cause code runaway.
If the MCU is clocked by the PLL, the risk of code runaway is very
low, but it can still occur under certain conditions due to irregular
clocks from the clock source appearing on the SYSCLK.
CAUTION:
NOTE:
The COP watch dog should always be enabled in order to reset the MCU
in case of a code runaway situation.
It is always advisable to take additional precautions within the
application software to trap such situations.
12.6.2 No Clock at Power-On Reset
The voltage level on VDDPLL determines how the MCU responds to an
external clock loss in this case.
With the VDDPLL supply voltage at VDD level, any reset sets the Clock
Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.
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Therefore, if the MCU is powered up without an external clock, limphome mode is entered provided the MCU is in a normal mode of
operation.
VDD
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Power-On Detector
EXTALi
(Slow EXTALi)
Clock Monitor Fail
Limp-Home
13-stage counter
(Clocked by XCLK)
0 --> 4096
0 --> 4096
BCSP
Reset: BCSP = 0
Internal reset
SYSCLK
SYSCLK
(Slow EXTALi)
PLLCLK (L.H.)
EXTALi
PLLCLK (Software check of Limp-Home Flag)
EXTALi
Figure 12-4. No Clock at Power-On Reset
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Limp-Home and Fast STOP Recovery modes
During this power up sequence, after the POR pulse falling edge, the
VCO supplies the limp-home clock frequency to the 13-stage counter, as
the BCSP output is forced high and MCS is forced low. XCLK, BCLK and
MCLK are forced to be PCLK, which is supplied by the VCO at fVCOMIN.
The initial period taken for the 13-stage counter to reach 4096 defines
the internal reset period.
If the clock monitor indicates the presence of an external clock during the
internal reset period, limp-home mode is de-asserted and the 13-stage
counter is then driven by EXTALi clock. After the 13-stage counter
reaches a count of 4096 XCLK cycles, the internal reset is released, the
13-stage counter is reset and the MCU exits reset normally using
EXTALi clock.
However, if the crystal start-up time is longer than the initial count of
4096 XCLK cycles, or in the absence of an external clock, the MCU will
leave the reset state in limp-home mode. The LHOME flag is set and
LHIF limp-home interrupt request is set, to indicate it is not operating at
the desired frequency. Then after yet another 4096 XCLK cycles
followed regularly by 8192 XCLK cycles (corresponding to the 13-stage
counter timing out), a check of the clock monitor status is performed.
When the presence of an external clock is detected limp-home mode is
exited generating a limp-home interrupt if enabled.
CAUTION:
The clock monitor circuit can be misled by the EXTALi clock into
reporting a good signal before it has fully stabilised. Under these
conditions improper EXTALi clock cycles can occur on SYSCLK. This
may lead to a code runaway. To ensure that this situation does not
occur, the external Reset period should be longer than the oscillator
stabilisation time - this is an application dependent parameter.
With the VDDPLL supply voltage at VSS level, the PLL module and
hence limp-home mode are disabled, the device will remain effectively
in a static state whilst there is no activity on EXTALi. The internal reset
period and MCU operation will execute only on EXTALi clock.
NOTE:
The external clock signal must stabilise within the initial 4096 reset
counter cycles.
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12.6.3 STOP Exit and Fast STOP Recovery
Stop mode is entered when a STOP instruction is executed. Recovery
from STOP depends primarily on the state of the three status bits
NOLHM, CME & DLY.
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The DLY bit controls the duration of the waiting period between the
actual exit for some key blocks (e.g. clock monitor, clock generators) and
the effective exit from stop for all the rest of the MCU. DLY=1 enables
the 13-stage counter to generate a 4096 count delay. DLY=0 selects no
delay. As the XCLK is derived from the slow mode divider, the value in
the SLOW register modifies the actual delay time.
NOTE:
DLY=0 is only recommended when there is a good signal available
at the EXTAL pin (e.g. an external square wave source).
STOP mode is exited with an external reset, an external interrupt from
IRQ or XIRQ, a Key Wake-Up interrupt from port J or port H, or an
MSCAN Wake-Up interrupt.
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Limp-Home and Fast STOP Recovery modes
EXTALi
Clock Monitor Fail
Limp-Home
13-stage counter
(Clocked by XCLK)
0 --> 4096
BCSP
Restore BCSP
STOP (DLY = 1)
STOP (DLY = 0)
SYSCLK
PLLCLK (L.H.)
Restore PLLCLK or EXTALi
Figure 12-5. STOP Exit and Fast STOP Recovery
12.6.4 STOP exit without Limp Home mode, clock monitor disabled
(NOLHM=1, CME=0, DLY=X)
If Limp home mode is disabled (VDDPLL=VSS or NOLHM bit set) and the
CME (or FCME) bit is cleared, the MCU goes into STOP mode when a
STOP instruction is executed.
If EXTALi clock is present then exit from STOP will occur normally using
this clock. Under this condition, DLY should always be set to allow the
crystal to stabilise and minimise the risk of code runaway. With DLY=1
execution resumes after a delay of 4096 XCLK cycles.
NOTE:
The external clock signal should stabilise within the 4096 reset counter
cycles. Use of DLY=0 is not recommended due to this requirement.
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12.6.5 Executing the STOP instruction without Limp Home mode, clock monitor enabled
(NOLHM=1, CME=1, DLY=X)
If the NOLHM bit and the CME (or FCME) bits are set, a clock monitor
failure is detected when a STOP instruction is executed and the MCU
resets via the clock monitor reset vector.
12.6.6 STOP exit in Limp Home mode with Delay
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(NOLHM=0, CME=X, DLY=1)
If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when
a STOP instruction is executed to prevent a clock monitor failure. When
coming out of STOP mode, the MCU goes into limp-home mode where
CME and FCME signals are asserted.
When using a crystal oscillator, a normal STOP exit sequence requires
the DLY bit to be set to allow for the crystal stabilization period.
With the 13-stage counter clocked by the VCO (at fVCOMIN), following a
delay of 4096 XCLK cycles at the limp-home frequency, if the clock
monitor indicates the presence of an external clock, the limp-home mode
is de-asserted and the MCU exits STOP normally using EXTALi clock.
Where the crystal start-up time is longer than the initial count of 4096
XCLK cycles, or in the absence of an external clock, the MCU recovers
from STOP following the 4096 count in limp-home mode with both the
LHOME flag set and the LHIF limp-home interrupt request set to indicate
it is not operating at the desired frequency. Each time the 13-stage
counter reaches a count of 4096 XCLK cycles, a check of the clock
monitor status is performed.
When the presence of an external clock is detected, limp-home mode is
exited and the LHOME flag is cleared. This sets the limp-home interrupt
flag and if enabled by the LHIE bit, the limp-home mode interrupt is
requested.
CAUTION:
The clock monitor circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised. Under these conditions,
improper EXTALi clock cycles can occur on SYSCLK. This may lead to
a code runaway.
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Limp-Home and Fast STOP Recovery modes
12.6.7 STOP exit in Limp Home mode without Delay (Fast Stop Recovery)
(NOLHM=0, CME=X, DLY=0)
Fast STOP recovery refers to any exit from STOP using DLY=0.
If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when
a STOP instruction is executed to prevent a clock monitor failure. When
coming out of STOP mode, the MCU goes into limp-home mode where
CME and FCME signals are asserted.
When using a crystal oscillator, it is possible to exit STOP with the DLY
bit cleared. In this case, STOP is de-asserted without delay and the MCU
will execute software in limp-home mode, giving the crystal oscillator
time to stablise.
CAUTION:
This mode is not recommended since the risk of the clock monitor
detecting incorrect clocks is high.
Each time the 13-stage counter reaches a count of 4096 XCLK cycles
(every 8192 cycles), a check of the clock monitor status is performed. If
the clock monitor indicates the presence of an external clock limp-home
mode is de-asserted, the LHOME flag is cleared and the limp-home
interrupt flag is set. Upon leaving limp-home mode, BCSP and MCS are
restored to their values before the loss of clock, and all clocks return to
their previous frequencies. If AUTO and BCSP were set before the clock
loss, the SYSCLK ramps-up and the PLL locks at the previously selected
frequency.
To prevent PLL operation when the external clock frequency comes
back, the software should clear the BCSP bit while running in limp-home
mode.
When using an external clock, i.e. a square wave source, it is possible
to exit STOP with the DLY bit cleared. In this case the LHOME flag is
never set and STOP is de-asserted without delay.
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12.6.8 Pseudo-STOP
Pseudo-STOP is a low power mode similar to STOP where the external
oscillator is allowed to run (at reduced amplitude) whilst the rest of the
part is in STOP. This increases the current consumption over STOP
mode by the amount of current in the oscillator, but reduces wear and
mechanical stress on the crystal.
If the PSTP bit in the PLLCR register is set, the MCU goes into PseudoSTOP mode when a STOP instruction is executed.
Pseudo-STOP mode is exited the same as STOP with an external reset,
an external interrupt from IRQ or XIRQ, a Key Wake-Up interrupt from
port J or port H, or an MSCAN Wake-Up interrupt.
The effect of the DLY bit is the same as noted above in STOP Exit and
Fast STOP Recovery.
12.6.9 Pseudo-STOP exit in Limp Home mode with Delay
(NOLHM=0, CME=X, DLY=1)
When coming out of Pseudo-STOP mode with the NOLHM bit cleared
and the DLY bit set, the MCU goes into limp-home mode (regardless of
the state of the CME or FCME bits).
The VCO supplies the limp-home clock frequency to the 13-stage
counter (XCLK). The BCSP output is forced high and MCS is forced low.
After the 13-stage counter reaches a count of 4096 XCLK cycles, a
check of the clock monitor is performed and as the crystal oscillator was
kept running due to the Pseudo-stop mode, the MCU exits STOP
normally, using the EXTALi clock. In the case where a crystal failure
occurred during pseudo-stop, then the MCU exits STOP using the limp
home clock (fVCOMIN) with both the LHOME flag set and the LHIF limphome interrupt request set to indicate it is not operating at the desired
frequency. Each time the 13-stage counter reaches a count of 4096
XCLK cycles, a check of the clock monitor is performed. If the clock
monitor indicates the presence of an external clock, limp-home mode is
de-asserted, the LHOME flag is cleared and the LHIF limp-home
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interrupt request is set to indicate a return to normal operation using
EXTALi clock.
12.6.10 Pseudo-STOP exit in Limp Home mode without Delay (Fast Stop Recovery)
(NOLHM=0, CME=X, DLY=0)
If Pseudo-STOP is exited with the NOLHM bit set to 0 and the DLY bit is
cleared then the exit from Pseudo-STOP is accomplished without delay
as in Fast STOP recovery.
CAUTION:
Where Pseudo-STOP recovers using the Limp Home Clock the VCO which has been held in STOP - must be restarted in order to supply the
limp home frequency. This restart, which occurs at a high frequency and
ramps toward the limp home frequency, is almost immediately supplied
to the CPU before it may have reached the steady state frequency. It is
possible that the initial clock frequency may be high enough to cause the
CPU to function incorrectly with a resultant risk of code runaway.
12.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled
(NOLHM=1, CME=1, DLY=X)
If the NOLHM bit is set and the CME (or FCME) bits are set, a clock
monitor failure is detected when a STOP instruction is executed and the
MCU resets via the clock monitor reset vector.
12.6.12 Pseudo-STOP exit without Limp Home mode, clock monitor disabled
(NOLHM=1, CME=0, DLY=1)
If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp
home clock is not used. In this mode, crystal activity is the only method
by which the device may recover from Pseudo-STOP. The device will
start execution with the EXTALi clock following 4096 XCLK cycles.
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(NOLHM=1, CME=0, DLY=0)
If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp
home clock is not used. In this mode, crystal activity is the only method
by which the device may recover from Pseudo-STOP. The device will
start execution with the EXTALi clock following 16 XCLK cycles.
CAUTION:
Due to switching of the clock this configuration is not recommended.
12.6.13 Summary of STOP and pseudo-STOP Mode Exit Conditions
Table 12-1 and Table 12-2 summarise the exit conditions from STOP
and pseudo-STOP modes using Interrupt, Key-interrupt and XIRQ.
A short RESET pulse should not be used to exit stop or pseudo-STOP
mode because Limp Home mode is automatically entered after RESET
(when VDDPLL=VDD). The RESET wakeup pulse must be longer than the
oscillator startup time (as in power on reset) in order to remove the risk
of code runaway.
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Clock Functions
Limp-Home and Fast STOP Recovery modes
. .
Table 12-1. Summary of STOP Mode Exit Conditions
Mode
Conditions
Summary
STOP exit without Limp Home
mode,
clock monitor disabled
NOLHM=1
CME=0
DLY=X
Oscillator must be stable within 4096 XCLK cycles. XCLK
can be modified by SLOW divider register.
Use of DLY=0 only recommended with external clock.
Executing the STOP instruction
without Limp Home mode,
clock monitor enabled
NOLHM=1
CME=1
DLY=X
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
STOP exit in Limp Home mode
with Delay
NOLHM=0
CME=X
DLY=1
Oscillator must be stable within 4096
fVCOMIN cycles or there is a possibility of code runaway as
the clock monitor circuit can be misled by EXTALi clock
into reporting a good signal before it has fully stabilised
STOP exit in Limp Home mode
without Delay (Fast Stop
Recovery)
NOLHM=0
CME=X
DLY=0
This mode is only recommended for use with an external
clock source.
Table 12-2. Summary of Pseudo STOP Mode Exit Conditions
Mode
Conditions
Summary
Pseudo-STOP exit in Limp Home
mode with Delay
NOLHM=0
CME=X
DLY=1
CPU exits stop in limp home mode and oscillator running. If
the oscillator fails during pseudo-STOP and then recovers
there is a possibility of code runaway as the clock monitor
circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised
Pseudo-STOP exit
in Limp Home mode without
Delay (Fast Stop Recovery)
NOLHM=0
CME=X
DLY=0
This mode is not recommended as it is possible that the
initial VCO clock frequency may be high enough to cause
code runaway.
Pseudo-STOP exit without Limp
Home mode, clock monitor
enabled
NOLHM=1
CME=1
DLY=X
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, with Delay
NOLHM=1
CME=0
DLY=1
Oscillator starts operation following 4096 XCLK cycles
(actual controlled by SLOW mode divider).
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, without Delay
NOLHM=1
CME=0
DLY=0
This mode is only recommended for use with an external
clock source.
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12.6.14 PLL Register Descriptions
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0
0
0
0
0
0
0
0
SYNR — Synthesizer Register
$0038
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
REFDV2
REFDV1
REFDV0
0
0
0
0
0
0
0
0
REFDV — Reference Divider Register
$0039
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
TSTOUT7
TSTOUT6
TSTOUT5
TSTOUT4
TSTOUT3
TSTOUT2
TSTOUT1
TSTOUT0
0
0
0
0
0
0
0
0
CGTFLG — Clock Generator Test Register
$003A
Always reads zero, except in test modes.
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Limp-Home and Fast STOP Recovery modes
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
LOCKIF
LOCK
0
0
0
0
LHIF
LHOME
0
0
0
0
0
0
0
0
PLLFLG — PLL Flags
$003B
Read anytime, refer to each bit for write conditions.
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LOCKIF — PLL Lock Interrupt Flag
0 = No change in LOCK bit.
1 = LOCK condition has changed, either from a locked state to an
unlocked state or vice versa.
To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home
mode.
LOCK — Locked Phase Lock Loop Circuit
Regardless of the bandwidth control mode (automatic or manual):
0 = PLL VCO is not within the desired tolerance of the target
frequency.
1 = After the phase lock loop circuit is turned on, indicates the PLL
VCO is within the desired tolerance of the target frequency.
Write has no effect on LOCK bit. This bit is cleared in limp-home mode as
the lock detector cannot operate without the reference frequency.
LHIF — Limp-Home Interrupt Flag
0 = No change in LHOME bit.
1 = LHOME condition has changed, either entered or exited limphome mode.
To clear the flag, write one to this bit in PLLFLG.
LHOME — Limp-Home Mode Status
0 = MCU is operating normally, with EXTALi clock available for
generating clocks or as PLL reference.
1 = Loss of reference clock. CGM delivers PLL VCO limp-home
frequency to the MCU.
For Limp-Home mode, see Limp-Home and Fast STOP Recovery modes.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
LOCKIE
PLLON
AUTO
ACQ
0
PSTP
LHIE
NOLHM
0
—(1)
1
0
0
0
0
—(2)
PLLCR — PLL Control Register
$003C
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.
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Read and write anytime. Exceptions are listed below for each bit.
LOCKIE — PLL LOCK Interrupt Enable
0 = PLL LOCK interrupt is disabled
1 = PLL LOCK interrupt is enabled
Forced to 0 when VDDPLL=0.
PLLON — Phase Lock Loop On
0 = Turns the PLL off.
1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will
lock automatically.
Cannot be cleared when BCSP = 1 (PLL selected as bus clock).
Forced to 0 when VDDPLL is at VSS level. In limp-home mode, the
output of PLLON is forced to 1, but the PLLON bit reads the latched
value.
AUTO — Automatic Bandwidth Control
0 = Automatic Mode Control is disabled and the PLL is under
software control, using ACQ bit.
1 = Automatic Mode Control is enabled. ACQ bit is read only.
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running. See
Electrical Specifications.
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Clock Functions
Limp-Home and Fast STOP Recovery modes
ACQ — Not in Acquisition
If AUTO = 1 (ACQ is Read Only)
0 = PLL VCO is not within the desired tolerance of the target
frequency. The loop filter is in high bandwidth, acquisition
mode.
1 = After the phase lock loop circuit is turned on, indicates the PLL
VCO is within the desired tolerance of the target frequency.
The loop filter is in low bandwidth, tracking mode.
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If AUTO = 0
0 = High bandwidth PLL loop selected
1 = Low bandwidth PLL loop selected
PSTP — Pseudo-STOP Enable
0 = Pseudo-STOP oscillator mode is disabled
1 = Pseudo-STOP oscillator mode is enabled
In Pseudo-STOP mode, the oscillator is still running while the MCU is
maintained in STOP mode. This allows for a faster STOP recovery
and reduces the mechanical stress and aging of the resonator in case
frequent STOP conditions at the expense of a slightly increased
power consumption.
LHIE — Limp-Home Interrupt Enable
0 = Limp-Home interrupt is disabled
1 = Limp-Home interrupt is enabled
Forced to 0 when VDDPLL is at VSS level.
NOLHM —No Limp-Home Mode
0 = Loss of reference clock forces the MCU in limp-home mode.
1 = Loss of reference clock causes standard Clock Monitor reset.
Read anytime; Normal modes: write once; Special modes: write
anytime. Forced to 1 when VDDPLL is at VSS level.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
BCSP
BCSS
0
0
MCS
0
0
0
0
0
0
0
0
0
0
CLKSEL — Clock Generator Clock select Register
$003D
Read and write anytime. Exceptions are listed below for each bit.
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BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
BCSP — Bus Clock Select PLL
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
BCSS — Bus Clock Select Slow
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
This bit has no effect when BCSP is set.
MCS — Module Clock Select
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
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Clock Functions
System Clock Frequency formulas
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
SLDV5
SLDV4
SLDV3
SLDV2
SLDV1
SLDV0
0
0
0
0
0
0
0
0
SLOW — Slow mode Divider Register
$003E
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tuneup of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
12.7 System Clock Frequency formulas
See Figure 12-6:
SLWCLK = EXTALi / ( 2 x SLOW )
SLOW = 1,2,..63
SLWCLK = EXTALi
SLOW = 0
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)
ECLK = SYSCLK / 2
XCLK = SLWCLK / 2
PCLK = SYSCLK / 2
BCLK(1) = EXTALi / 2
Boolean equations:
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.
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Clock Functions
SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP &
BCSS & SLWCLK)
MCLK = (PCLK & MCS) | (XCLK & MCS)
MSCAN system = (EXTALi & CLKSRC) | (SYSCLK & CLKSRC)
BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)
NOTE:
During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are
supplied by VCO (PLLCLK).
12.8 Clock Divider Chains
Figure 12-6, Figure 12-7, Figure 12-8, and Figure 12-9 summarize the
clock divider chains for the various peripherals on the 68HC(9)12D60.
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Clock Functions
Clock Divider Chains
BCSP BCSS
1:x
PHASE
LOCK
LOOP
SYSCLK
PLLCLK
÷2
EXTALi
EXTAL
BCSP BCSS
0:0
REDUCED
CONSUMPTION
OSCILLATOR
T CLOCK
GENERATOR
TCLKs
E AND P
CLOCK
GENERATOR
ECLK
PCLK
EXTALi
TO CPU
TO
BUSES,
SPI,
PWM,
ATD0, ATD1
CLKSRC = 1
BCSP BCSS
0:1
XTAL
EXTALi
TO
MSCAN
CLKSRC = 0
MCS = 0
MCLK
MCS = 1
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷2
TO
SCI0, SCI1,
ECT
SYNC
XCLK
TO
RTI, COP
TO CAL
CLKSW = 0
÷2
SYNC
BDMCLK
CLKSW = 1
TO BDM
TO CLOCK
MONITOR
Figure 12-6. Clock Generation Chain
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
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the transition, the clock select output will be held low and all CPU activity
will cease until the transition is complete.
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The Module Clock Select bit MCS determines the clock used by the ECT
module and the baud rate generators of the SCIs. In limp-home mode,
the output of MCS is forced to 0, but the MCS bit reads the latched value.
It allows normal operation of the serial and timer subsystems at a fixed
reference frequency while allowing the CPU to operate at a higher,
variable frequency.
XCLK
÷ 2048
÷4
REGISTER: RTICTL
BITS: RTR2, RTR1, RTR0
REGISTER: RTICTL
BIT:RTBYP
0:0:0
REGISTER: COPCTL
BITS: CR2, CR1, CR0
0:0:1
MCLK
SC0BD
MODULUS DIVIDER:
÷ 1, 2, 3, 4, 5, 6,...,8190, 8191
SCI0
RECEIVE
BAUD RATE (16x)
÷ 16
SCI0
TRANSMIT
BAUD RATE (1x)
SC1BD
MODULUS DIVIDER:
÷ 1, 2, 3, 4, 5, 6,...,8190, 8191
SCI1
RECEIVE
BAUD RATE (16x)
÷ 16
SCI1
TRANSMIT
BAUD RATE (1x)
0:0:0
0:0:1
÷2
0:1:0
÷4
0:1:0
÷2
0:1:1
÷4
0:1:1
÷2
1:0:0
÷4
1:0:0
÷2
1:0:1
÷4
1:0:1
÷2
1:1:0
÷2
1:1:0
÷2
1:1:1
÷2
1:1:1
TO RTI
TO COP
Figure 12-7. Clock Chain for SCI0, SCI1, RTI, COP
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Clock Functions
Clock Divider Chains
MCLK
REGISTER: TMSK2
BITS: PR2, PR1, PR0
0:0:0
TEN
REGISTER: MCCTL
BITS: MCPR1, MCPR0
0:0
MCEN
÷2
0:0:1
÷4
0:1
÷2
0:1:0
÷2
1:0
÷2
0:1:1
÷2
1:1
MODULUS
DOWN
COUNTER
REGISTER: PACTL
BITS: PAEN, CLK1, CLK0
0:x:x
1:0:0
÷2
1:0:0
Prescaled MCLK
1:0:1
÷2
1:0:1
÷2
1:1:0
1:1:0
÷2
PULSE ACC
LOW BYTE
PACLK/256
1:1:1
PACLK/65536
(PAOV)
1:1:1
PACLK
GATE
LOGIC
PORT T7
PULSE ACC
HIGH BYTE
PAMOD
TO TIMER
MAIN
COUNTER
(TCNT)
PAEN
Figure 12-8. Clock Chain for ECT
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Clock Functions
PCLK
5-BIT MODULUS
COUNTER (PR0-PR4)
÷2
÷2
TO ATD0
and ATD1
÷2
REGISTER: SP0BR
BITS: SPR2, SPR1, SPR0
0:0:0
SPI
BIT RATE
0:0:1
MSCAN
CLOCK
EXTALi
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
÷2
÷2
CLKSRC
SYSCLK
ECLK
CLKSW
1:1:0
BDM BIT CLOCK:
BCLK
BKGD IN
Receive: Detect falling edge,
count 12 ECLKs, Sample input
SYNCHRONIZER
1:1:1
BKGD DIRECTION
BKGD
PIN
LOGIC
BKGD OUT
Transmit 1: Detect falling edge,
count 6 ECLKs while output is
high impedance, Drive out 1 E
cycle pulse high, high impedance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 ECLKs,
Drive out 1 E cycle pulse high,
high impedance output
Figure 12-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
12.9 Computer Operating Properly (COP)
The COP or watchdog timer is an added check that a program is running
and sequencing properly. When the COP is being used, software is
responsible for keeping a free running watchdog timer from timing out. If
the watchdog timer times out it is an indication that the software is no
longer being executed in the intended sequence; thus a system reset is
initiated. Three control bits allow selection of seven COP time-out
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this the part will reset. If any value other than
$55 or $AA is written, the part is reset.
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Real-Time Interrupt
In addition, windowed COP operation can be selected. In this mode,
writes to the COPRST register must occur in the last 25% of the selected
period. A premature write will also reset the part.
12.10 Real-Time Interrupt
There is a real time (periodic) interrupt available to the user. This
interrupt will occur at one of seven selected rates. An interrupt flag and
an interrupt enable bit are associated with this function. There are three
bits for the rate select.
12.11 Clock Monitor
The clock monitor circuit is based on an internal resistor-capacitor (RC)
time delay. If no EXTALi clock edges are detected within this RC time
delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled/disabled by the CME control bit in the
COPCTL register. This time-out is based on an RC delay so that the
clock monitor can operate without any EXTALi clock.
Clock monitor time-outs are shown in Table 12-3. The corresponding
EXTALi clock period with an ideal 50% duty cycle is twice this time-out
value.
Table 12-3. Clock Monitor Time-Outs
Supply
5 V +/– 10%
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Range
2–20 µS
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12.12 Clock Function Registers
All register addresses shown reflect the reset state. Registers may be
mapped to any 2K byte space.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
RTIE
RSWAI
RSBCK
Reserved
RTBYP
RTR2
RTR1
RTR0
0
0
0
0
0
0
0
0
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RTICTL — Real-Time Interrupt Control Register
$0014
RTIE — Real Time Interrupt Enable
Read and write anytime.
0 = Interrupt requests from RTI are disabled.
1 = Interrupt will be requested whenever RTIF is set.
RSWAI — RTI and COP Stop While in Wait
Write once in normal modes, anytime in special modes. Read
anytime.
0 = Allows the RTI and COP to continue running in wait.
1 = Disables both the RTI and COP whenever the part goes into
Wait.
RSBCK — RTI and COP Stop While in Background Debug Mode
Write once in normal modes, anytime in special modes. Read
anytime.
0 = Allows the RTI and COP to continue running while in
background mode.
1 = Disables both the RTI and COP when the part is in background
mode. This is useful for emulation.
RTBYP — Real Time Interrupt Divider Chain Bypass
Write not allowed in normal modes, anytime in special modes. Read
anytime.
0 = Divider chain functions normally.
1 = Divider chain is bypassed, allows faster testing (the divider
chain is normally XCLK divided by 213, when bypassed
becomes XCLK divided by 4).
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Clock Function Registers
RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select
Read and write anytime.
Rate select for real-time interrupt. The clock used for this module is
the XCLK.
Table 12-4. Real Time Interrupt Rates
RTR2 RTR1 RTR0 Divide X By:
Time-Out Period Time-Out Period Time-Out Period Time-Out Period
X = 125 KHz
X = 500 KHz
X = 2.0 MHz
X = 8.0 MHz
OFF
OFF
OFF
OFF
0
0
0
OFF
0
0
1
213
65.536 ms
16.384 ms
4.096 ms
1.024 ms
131.72 ms
32.768 ms
8.196 ms
2.048 ms
0
1
0
214
0
1
1
215
263.44 ms
65.536 ms
16.384 ms
4.096 ms
1
0
0
216
526.88 ms
131.72 ms
32.768 ms
8.196 ms
1
0
1
217
1.05 s
263.44 ms
65.536 ms
16.384 ms
0
2
18
2.11 s
526.88 ms
131.72 ms
32.768 ms
1
219
4.22 s
1.05 s
263.44 ms
65.536 ms
1
1
1
1
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
RTIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RTIFLG — Real Time Interrupt Flag Register
$0015
RTIF — Real Time Interrupt Flag
This bit is cleared automatically by a write to this register with this bit
set.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
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Bit 7
6
5
4
3
2
1
Bit 0
CME
FCME
FCMCOP
WCOP
DISR
CR2
CR1
CR0
RESET:
0/1
0
0
0
0
1
1
1
Normal
RESET:
0/1
0
0
0
1
1
1
1
Special
COPCTL — COP Control Register
$0016
CME — Clock Monitor Enable
Read and write anytime.
Freescale Semiconductor, Inc...
If FCME is set, this bit has no meaning nor effect.
0 = Clock monitor is disabled. Slow clocks and stop instruction may
be used.
1 = Slow or stopped clocks (including the stop instruction) will
cause a clock reset sequence or limp-home mode. See LimpHome and Fast STOP Recovery modes.
On reset
CME is 1 if VDDPLL is high
CME is 0 if VDDPLL is low.
NOTE:
The VDDPLL-dependent reset operation is not implemented on first
pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or
limp-home mode.
See Limp-Home and Fast STOP Recovery modes.
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Clock Functions
Clock Function Registers
FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
Freescale Semiconductor, Inc...
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = A clock monitor failure reset or a COP failure reset is forced
depending on the state of CME and if COP is enabled.
CME
COP enabled
Forced reset
0
0
none
0
1
COP failure
1
0
Clock monitor failure
1
1
Both(1)
1. Highest priority interrupt vector is serviced.
WCOP — Window COP mode
Write once in normal modes, anytime in special modes. Read
anytime.
0 = Normal COP operation
1 = Window COP operation
When set, a write to the COPRST register must occur in the last 25%
of the selected period. A premature write will also reset the part. As
long as all writes occur during this window, $55 can be written as often
as desired. Once $AA is written the time-out logic restarts and the
user must wait until the next window before writing to COPRST.
Please note, there is a fixed time uncertainty about the exact COP
counter state when reset, as the initial prescale clock divider in the
RTI section is not cleared when the COP counter is cleared. This
means the effective window is reduced by this uncertainty. Table 125 below shows the exact duration of this window for the seven
available COP rates.
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Clock Functions
Table 12-5. COP Watchdog Rates
CR2
CR1
CR0
Window COP enabled:
Divide
X clock
by
8.0 MHz X clock.
Time-out
Window start
(1)
Window end
Effective
Window (2)
0
0
0
OFF
OFF
OFF
OFF
OFF
0
0
1
2 13
1.024 ms -0/+0.256 ms
0.768 ms
0.768 ms
0 % (3)
0
1
0
2 15
4.096 ms -0/+0.256 ms
3.072 ms
3.840 ms
18.8 %
0
1
1
2 17
16.384 ms -0/+0.256 ms
12.288 ms
16.128 ms
23.4 %
1
0
0
2 19
65.536 ms -0/+1.024 ms
49.152 ms
64.512 ms
23.4 %
1
0
1
2 21
262.144 ms -0/+1.024 ms
196.608 ms
261.120 ms
24.6 %
1
1
0
2 22
524.288 ms -0/+1.024 ms
393.216 ms
523.264 ms
24.8 %
1
1
1
2 23
1.048576 ms -0/+1.024 ms
786.432 ms
1.047552 ms
24.9 %
1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.
2. Please refer to WCOP bit description above.
3. Window COP cannot be used at this rate.
DISR — Disable Resets from COP Watchdog and Clock Monitor
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor
will not generate a system reset.
CR2, CR1, CR0 — COP Watchdog Timer Rate select bits
These bits select the COP time-out rate. The clock used for this
module is the XCLK.
Write once in normal modes, anytime in special modes. Read
anytime.
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Clock Functions
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
COPRST — Arm/Reset COP Timer Register
$0017
Always reads $00.
Freescale Semiconductor, Inc...
Writing $55 to this address is the first step of the COP watchdog
sequence.
Writing $AA to this address is the second step of the COP watchdog
sequence. Other instructions may be executed between these writes
but both must be completed in the correct order prior to time-out to
avoid a watchdog reset. Writing anything other than $55 or $AA
causes a COP reset to occur.
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Clock Functions
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Advance Information — 68HC(9)12D60
Section 13. Pulse Width Modulator
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.3
PWM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.4
PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
13.2 Introduction
The pulse-width modulator (PWM) subsystem provides four
independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a
combination of one 16-bit and two 8-bit PWM waveforms. Each
waveform channel has a programmable period and a programmable
duty-cycle as well as a dedicated counter. A flexible clock select scheme
allows four different clock sources to be used with the counters. Each of
the modulators can create independent, continuous waveforms with
software-selectable duty rates from 0 percent to 100 percent. The PWM
outputs can be programmed as left-aligned outputs or center-aligned
outputs.
The period and duty registers are double buffered so that if they change
while the channel is enabled, the change will not take effect until the
counter rolls over or the channel is disabled. If the channel is not
enabled, then writes to the period and/or duty register will go directly to
the latches as well as the buffer, thus ensuring that the PWM output will
always be either the old waveform or the new waveform, not some
variation in between.
A change in duty or period can be forced into immediate effect by writing
the new value to the duty and/or period registers and then writing to the
counter. This causes the counter to reset and the new duty and/or period
values to be latched. In addition, since the counter is readable it is
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Pulse Width Modulator
possible to know where the count is with respect to the duty value and
software can be used to make adjustments by turning the enable bit off
and on.
The four PWM channel outputs share general-purpose port P pins.
Enabling PWM pins takes precedence over the general-purpose port.
When PWM channels are not in use, the port pins may be used for
discrete input/output.
Freescale Semiconductor, Inc...
CLOCK SOURCE
(ECLK or Scaled ECLK)
CENTR = 0
FROM PORT P
DATA REGISTER
UP/DOWN
PWCNTx
GATE
(CLOCK EDGE SYNC)
RESET
8-BIT COMPARE =
PWDTYx
S
Q
MUX
MUX
Q
8-BIT COMPARE =
PWPERx
PWENx
TO PIN
DRIVER
R
PPOLx
SYNC
PPOL = 0
PPOL = 1
PWDTY
PWPER
Figure 13-1. Block Diagram of PWM Left-Aligned Output Channel
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Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
CENTR = 1
FROM PORT P
DATA REGISTER
RESET
PWCNTx
GATE
(CLOCK EDGE SYNC)
UP/DOWN
(DUTY CYCLE)
8-BIT COMPARE =
PWDTYx
T
Q
(PERIOD)
MUX
MUX
Q
TO PIN
DRIVER
8-BIT COMPARE =
PWPERx
PPOLx
PWENx
SYNC
PPOL = 1
PPOL = 0
PWDTY
(PWPER − PWDTY) × 2
PWPER × 2
PWDTY
Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel
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Pulse Width Modulator
PSBCK
PSBCK IS BIT 0 OF PWCTL REGISTER.
INTERNAL SIGNAL LIMBDM IS ‘1’ IF THE MCU IS IN BACKGROUND DEBUG MODE.
LIMBDM
CLOCK A
CLOCK TO PWM
CHANNEL 0
MUX
ECLK
0:0:0
0:0:0
8-BIT DOWN COUNTER
0:0:1
÷2
0:1:0
PCLK0
8-BIT SCALE REGISTER
0:1:1
÷2
0:1:1
1:0:0
÷2
1:0:0
CLOCK TO PWM
CHANNEL 1
MUX
0:1:0
PWSCNT0
CLOCK S0*
÷2
0:0:1
=0
÷2
PWSCAL0
PCLK1
CLOCK B
÷2
1:0:1
1:1:0
÷2
1:1:0
1:1:1
÷2
1:1:1
8-BIT DOWN COUNTER
=0
PWSCNT1
BITS:
PCKA2,
PCKA1,
PCKA0
REGISTER:
PWPRES
PCLK2
CLOCK TO PWM
CHANNEL 3
MUX
BITS:
PCKB2,
PCKB1,
PCKB0
CLOCK TO PWM
CHANNEL 2
MUX
1:0:1
CLOCK S1**
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8-BIT SCALE REGISTER
÷2
PWSCAL1
PCLK3
*CLOCK S0 = A/2 * (PWSCAL0 + 1)
**CLOCK S1 = B/2 * (PWSCAL1 + 1)
Figure 13-3. PWM Clock Sources
13.3 PWM Register Description
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
CON23
CON01
PCKA2
PCKA1
PCKA0
PCKB2
PCKB1
PCKB0
0
0
0
0
0
0
0
0
PWCLK — PWM Clocks and Concatenate
$0040
Read and write anytime.
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PWM Register Description
CON23 — Concatenate PWM Channels 2 and 3
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When concatenated, channel 2 becomes the high-order byte and
channel 3 becomes the low-order byte. Channel 2 output pin is used
as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clockselect control bits determines the clock source. Channel 3 output pin
becomes a general purpose I/O.
0 = Channels 2 and 3 are separate 8-bit PWMs.
1 = Channels 2 and 3 are concatenated to create one 16-bit PWM
channel.
CON01 — Concatenate PWM Channels 0 and 1
When concatenated, channel 0 becomes the high-order byte and
channel 1 becomes the low-order byte. Channel 0 output pin is used
as the output for this 16-bit PWM (bit 0 of port P). Channel 1 clockselect control bits determine the clock source. Channel 1 output pin
becomes a general purpose I/O.
0 = Channels 0 and 1 are separate 8-bit PWMs.
1 = Channels 0 and 1 are concatenated to create one 16-bit PWM
channel.
PCKA2 – PCKA0 — Prescaler for Clock A
Clock A is one of two clock sources which may be used for channels
0 and 1. These three bits determine the rate of clock A, as shown in
Table 13-1.
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Pulse Width Modulator
PCKB2 – PCKB0 — Prescaler for Clock B
Clock B is one of two clock sources which may be used for channels
2 and 3. These three bits determine the rate of clock B, as shown in
Table 13-1.
Table 13-1. Clock A and Clock B Prescaler
PCKA2 PCKA1 PCKA0
(PCKB2) (PCKB1) (PCKB0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
RESET:
Value of
Clock A (B)
P
P÷2
P÷4
P÷8
P ÷ 16
P ÷ 32
P ÷ 64
P ÷ 128
Bit 7
6
5
4
3
2
1
Bit 0
PCLK3
PCLK2
PCLK1
PCLK0
PPOL3
PPOL2
PPOL1
PPOL0
0
0
0
0
0
0
0
0
PWPOL — PWM Clock Select and Polarity
$0041
Read and write anytime.
PCLK3 — PWM Channel 3 Clock Select
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
PCLK2 — PWM Channel 2 Clock Select
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
PCLK1 — PWM Channel 1 Clock Select
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
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Pulse Width Modulator
PWM Register Description
PCLK0 — PWM Channel 0 Clock Select
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a
truncated or stretched pulse may occur during the transition.
The following four bits apply in left-aligned mode only:
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PPOL3 — PWM Channel 3 Polarity
0 = Channel 3 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 3 output is high at the beginning of the period; low
when the duty count is reached.
PPOL2 — PWM Channel 2 Polarity
0 = Channel 2 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 2 output is high at the beginning of the period; low
when the duty count is reached.
PPOL1 — PWM Channel 1 Polarity
0 = Channel 1 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 1 output is high at the beginning of the period; low
when the duty count is reached.
PPOL0 — PWM Channel 0 Polarity
0 = Channel 0 output is low at the beginning of the period; high
when the duty count is reached.
1 = Channel 0 output is high at the beginning of the period; low
when the duty count is reached.
Depending on the polarity bit, the duty registers may contain the count
of either the high time or the low time. If the polarity bit is zero and left
alignment is selected, the duty registers contain a count of the low time.
If the polarity bit is one, the duty registers contain a count of the high
time.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
PWEN3
PWEN2
PWEN1
PWEN0
0
0
0
0
0
0
0
0
PWEN — PWM Enable
$0042
Freescale Semiconductor, Inc...
Setting any of the PWENx bits causes the associated port P line to
become an output regardless of the state of the associated data
direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to zero, the data direction bit controls
I/O direction. On the front end of the PWM channel, the scaler clock is
enabled to the PWM circuit by the PWENx enable bit being high. When
all four PWM channels are disabled, the prescaler counter shuts off to
save power. There is an edge-synchronizing gate circuit to guarantee
that the clock will only be enabled or disabled at an edge.
Read and write anytime.
PWEN3 — PWM Channel 3 Enable
The pulse modulated signal will be available at port P, bit 3 when its
clock source begins its next cycle.
0 = Channel 3 is disabled.
1 = Channel 3 is enabled.
PWEN2 — PWM Channel 2 Enable
The pulse modulated signal will be available at port P, bit 2 when its
clock source begins its next cycle.
0 = Channel 2 is disabled.
1 = Channel 2 is enabled.
PWEN1 — PWM Channel 1 Enable
The pulse modulated signal will be available at port P, bit 1 when its
clock source begins its next cycle.
0 = Channel 1 is disabled.
1 = Channel 1 is enabled.
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PWM Register Description
PWEN0 — PWM Channel 0 Enable
The pulse modulated signal will be available at port P, bit 0 when its
clock source begins its next cycle.
0 = Channel 0 is disabled.
1 = Channel 0 is enabled.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
Bit 6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
PWPRES — PWM Prescale Counter
$0043
PWPRES is a free-running 7-bit counter. Read anytime. Write only in
special mode (SMOD = 1).
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
PWSCAL0 — PWM Scale Register 0
$0044
Read and write anytime. A write will cause the scaler counter PWSCNT0
to load the PWSCAL0 value unless in special mode with DISCAL = 1 in
the PWTST register.
PWM channels 0 and 1 can select clock S0 (scaled) as its input clock by
setting the control bit PCLK0 and PCLK1 respectively. Clock S0 is
generated by dividing clock A by the value in the PWSCAL0 register + 1
and dividing again by two. When PWSCAL0 = $FF, clock A is divided by
256 then divided by two to generate clock S0.
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Pulse Width Modulator
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
PWSCNT0 — PWM Scale Counter 0 Value
$0045
PWSCNT0 is a down-counter that, upon reaching $00, loads the value
of PWSCAL0. Read any time.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
PWSCAL1 — PWM Scale Register 1
$0046
Read and write anytime. A write will cause the scaler counter PWSCNT1
to load the PWSCAL1 value unless in special mode with DISCAL = 1 in
the PWTST register.
PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by
setting the control bit PCLK2 and PCLK3 respectively. Clock S1 is
generated by dividing clock B by the value in the PWSCAL1 register + 1
and dividing again by two. When PWSCAL1 = $FF, clock B is divided by
256 then divided by two to generate clock S1.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
PWSCNT1 — PWM Scale Counter 1 Value
$0047
PWSCNT1 is a down-counter that, upon reaching $00, loads the value
of PWSCAL1. Read any time.
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PWM Register Description
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT0
Bit 7
6
5
4
3
2
1
Bit 0
$0048
PWCNT1
Bit 7
6
5
4
3
2
1
Bit 0
$0049
PWCNT2
Bit 7
6
5
4
3
2
1
Bit 0
$004A
PWCNT3
Bit 7
6
5
4
3
2
1
Bit 0
$004B
RESET:
0
0
0
0
0
0
0
0
PWCNTx — PWM Channel Counters
Read and write anytime. A write will cause the PWM counter to reset to
$00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
The PWM counters are not reset when PWM channels are disabled. The
counters must be reset prior to a new enable.
Each counter may be read any time without affecting the count or the
operation of the corresponding PWM channel. Writes to a counter cause
the counter to be reset to $00 and force an immediate load of both duty
and period registers with new values. To avoid a truncated PWM period,
write to a counter while the counter is disabled. In left-aligned output
mode, resetting the counter and starting the waveform output is
controlled by a match between the period register and the value in the
counter. In center-aligned output mode the counters operate as up/down
counters, where a match in period changes the counter direction. The
duty register changes the state of the output during the period to
determine the duty.
When a channel is enabled, the associated PWM counter starts at the
count in the PWCNTx register using the clock selected for that channel.
In special mode, when DISCP = 1 and configured for left-aligned output,
a match of period does not reset the associated PWM counter.
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Bit 7
6
5
4
3
2
1
Bit 0
PWPER0
Bit 7
6
5
4
3
2
1
Bit 0
$004C
PWPER1
Bit 7
6
5
4
3
2
1
Bit 0
$004D
PWPER2
Bit 7
6
5
4
3
2
1
Bit 0
$004E
PWPER3
Bit 7
6
5
4
3
2
1
Bit 0
$004F
RESET:
1
1
1
1
1
1
1
1
PWPERx — PWM Channel Period Registers
Read and write anytime.
The value in the period register determines the period of the associated
PWM channel. If written while the channel is enabled, the new value will
not take effect until the existing period terminates, forcing the counter to
reset. The new period is then latched and is used until a new period
value is written. Reading this register returns the most recent value
written. To start a new period immediately, write the new period value
and then write the counter forcing a new period to start with the new
period value.
Period = Channel-Clock-Period × (PWPER + 1)
Period = Channel-Clock-Period × (2 × PWPER)
(CENTR = 0)
(CENTR = 1)
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY0
Bit 7
6
5
4
3
2
1
Bit 0
$0050
PWDTY1
Bit 7
6
5
4
3
2
1
Bit 0
$0051
PWDTY2
Bit 7
6
5
4
3
2
1
Bit 0
$0052
PWDTY3
Bit 7
6
5
4
3
2
1
Bit 0
$0053
RESET:
1
1
1
1
1
1
1
1
PWDTYx — PWM Channel Duty Registers
Read and write anytime.
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Pulse Width Modulator
PWM Register Description
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or
the channel is disabled. Reading this register returns the most recent
value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be the
state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%
(PPOLx = 1)
Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)]×100% (PPOLx = 0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx−PWDTYx)/PWPERx]×100%
Duty cycle = [PWDTYx / PWPERx] × 100%
RESET:
(PPOLx = 0)
(PPOLx = 1)
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
PSWAI
CENTR
RDPP
PUPP
PSBCK
0
0
0
0
0
0
0
0
PWCTL — PWM Control Register
$0054
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
0 = Allows PWM main clock generator to continue while in wait
mode.
1 = Halt PWM main clock generator when the part is in wait mode.
CENTR — Center-Aligned Output Mode
To avoid irregularities in the PWM output mode, write the CENTR bit
only when PWM channels are disabled.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
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RDPP — Reduced Drive of Port P
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
PUPP — Pull-Up Port P Enable
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DISCR
DISCP
DISCAL
0
0
0
0
0
0
0
0
0
0
0
0
0
PWTST — PWM Special Mode Register (“Test”)
$0055
Read anytime but write only in special mode (SMODN = 0). These bits
are available only in special mode and are reset in normal mode.
DISCR — Disable Reset of Channel Counter on Write to Channel
Counter
0 = Normal operation. Write to PWM channel counter will reset
channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal operation
1 = In left-aligned output mode, match of period does not reset the
associated PWM counter register.
DISCAL — Disable Load of Scale-Counters on Write to the Associated
Scale-Registers
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale
counters
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Pulse Width Modulator
PWM Register Description
Bit 7
6
5
4
3
2
1
Bit 0
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PWM
–
–
–
–
PWM3
PWM2
PWM1
PWM0
RESET:
–
–
–
–
–
–
–
–
PORTP — Port P Data Register
$0056
PORTP can be read anytime.
PWM functions share port P pins 3 to 0 and take precedence over the
general-purpose port when enabled.
When configured as input, a read will return the pin level.
When configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the
corresponding PWM channel is not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDP7
DDP6
DDP5
DDP4
DDP3
DDP2
DDP1
DDP0
0
0
0
0
0
0
0
0
DDRP — Port P Data Direction Register
$0057
DDRP determines pin direction of port P when used for general-purpose
I/O.
Read and write anytime.
DDRP[7:0] — Data Direction Port P pin 7-0
0 = I/O pin configured as high impedance input
1 = I/O pin configured for output.
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13.4 PWM Boundary Cases
The boundary conditions for the PWM channel duty registers and the
PWM channel period registers cause these results:
Table 13-2. PWM Left-Aligned Boundary Conditions
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PWDTYx
$FF
$FF
≥PWPERx
≥PWPERx
–
–
PWPERx
>$00
>$00
–
–
$00
$00
PPOLx
1
0
1
0
1
0
Output
Low
High
High
Low
High
Low
Table 13-3. PWM Center-Aligned Boundary Conditions
PWDTYx
$00
$00
≥PWPERx
≥PWPERx
–
–
PWPERx
>$00
>$00
–
–
$00
$00
PPOLx
1
0
1
0
1
0
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Output
Low
High
High
Low
High
Low
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Section 14. Enhanced Capture Timer
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
14.3
Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . 203
14.4
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.5
Timer and Modulus Counter Operation in Different Modes . . 235
14.2 Introduction
The HC12 Enhanced Capture Timer module has the features of the
HC12 Standard Timer module enhanced by additional features in order
to enlarge the field of applications, in particular for automotive ABS
applications.
The additional features permit the operation of this timer module in a
mode similar to the Input Control Timer implemented on
MC68HC11NB4.
These additional features are:
•
16-Bit Buffer Register for four Input Capture (IC) channels.
•
Four 8-Bit Pulse Accumulators with 8-bit buffer registers
associated with the four buffered IC channels. Configurable also
as two 16-Bit Pulse Accumulators.
•
16-Bit Modulus Down-Counter with 4-bit Prescaler.
•
Four user selectable Delay Counters for input noise immunity
increase.
•
Main Timer Prescaler extended to 7-bit.
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Enhanced Capture Timer
This design specification describes the standard timer as well as the
additional features.
The basic timer consists of a 16-bit, software-programmable counter
driven by a prescaler. This timer can be used for many purposes,
including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from
microseconds to many seconds.
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A full access for the counter registers or the input capture/output
compare registers should take place in one clock cycle. Accessing high
byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
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Enhanced Capture Timer
Introduction
÷ 1, 2, ..., 128
M clock
16-bit Free-running
16 BIT MAIN
TIMER
main
timer
Prescaler
16-bit load register
÷ 1, 4, 8, 16
M clock
16-bit modulus
down counter
Prescaler
RESET
0
Pin logic
Delay counter
EDG0
Underflow
PT0
Comparator
TC0 capture/compare register
PAC0
TC0H hold register
PA0H hold register
RESET
0
PT1
Comparator
Pin logic
Delay counter
EDG1
TC1 capture/compare register
TC1H hold register
PAC1
PA1H hold register
RESET
0
PT2
Comparator
Pin logic
Delay counter
EDG2
TC2 capture/compare register
TC2H hold register
PAC2
PA2H hold register
RESET
0
PT3
Comparator
Pin logic
Delay counter
EDG3
TC3 capture/compare register
TC3H hold register
PT4
Pin logic
Pin logic
Pin logic
Pin logic
ICLAT, LATQ, BUFEN
(force latch)
Comparator
EDG5
TC5 capture/compare register
MUX
Write $0000
to modulus counter
Comparator
EDG6
LATQ
(MDC latch enable)
TC6 capture/compare register
MUX
EDG2
PT7
TC4 capture/compare register
MUX
EDG1
PT6
PA3H hold register
Comparator
EDG4
EDG0
PT5
PAC3
LATCH
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Comparator
EDG7
EDG3
TC7 capture/compare register
MUX
Figure 14-1. Timer Block Diagram in Latch Mode
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÷1, 2, ..., 128
16-bit Free-running
16 BIT MAIN
TIMER
main
timer
Prescaler
16-bit load register
÷ 1, 4, 8, 16
M clock
16-bit modulus
down counter
Prescaler
0
Delay counter
EDG0
TC0 capture/compare register
PAC0
TC0H hold register
PA0H hold register
PT1
Pin logic
Delay counter
EDG1
TC1 capture/compare register
TC1H hold register
PAC1
PA1H hold register
0
PT2
Pin logic
EDG2
TC2 capture/compare register
TC2H hold register
PAC2
PA2H hold register
0
Pin logic
EDG3
TC3 capture/compare register
TC3H hold register
Pin logic
Comparator
EDG4
Pin logic
TC4 capture/compare register
PAC3
PA3H hold register
LATQ, BUFEN
(queue mode)
MUX
EDG0
PT5
RESET
Comparator
Delay counter
PT4
RESET
Comparator
Delay counter
PT3
RESET
Comparator
LATCH1
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0
LATCH0
Pin logic
LATCH2
PT0
RESET
Comparator
LATCH3
M clock
Comparator
EDG5
Read TC3H
hold register
TC5 capture/compare register
MUX
EDG1
Read TC2H
hold register
PT6
Pin logic
Comparator
EDG6
MUX
EDG2
PT7
Pin logic
TC6 capture/compare register
Read TC1H
hold register
Comparator
EDG7
EDG3
TC7 capture/compare register
Read TC0H
hold register
MUX
Figure 14-2. Timer Block Diagram in Queue Mode
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Introduction
Load holding register and reset pulse accumulator
0
EDG0
PT0
Edge detector
8-bit PAC0 (PACN0)
Delay counter
PA0H holding register
Interrupt
0
EDG1
PT1
Edge detector
8-bit PAC1 (PACN1)
Delay counter
PA1H holding register
Host CPU data bus
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0
EDG2
PT2
Edge detector
8-bit PAC2 (PACN2)
Delay counter
PA2H holding register
Interrupt
0
EDG3
PT3
Edge detector
8-bit PAC3 (PACN3)
Delay counter
PA3H holding register
Figure 14-3. 8-Bit Pulse Accumulators Block Diagram
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TIMCLK (Timer clock)
CLK1
CLK0
Clock select
(PAMOD)
Edge detector
PT7
PACLK
PACLK / 256
PACLK / 65536
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Prescaled clock
from timer
4:1 MUX
Interrupt
8-bit PAC3 (PACN3)
8-bit PAC2 (PACN2)
MUX
PACA
M clock
Intermodule Bus
Divide by 64
Interrupt
8-bit PAC1 (PACN1)
8-bit PAC0 (PACN0)
Delay counter
PACB
Edge detector
PT0
Figure 14-4. 16-Bit Pulse Accumulators Block Diagram
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Enhanced Capture Timer
Enhanced Capture Timer Modes of Operation
Pulse accumulator A
PAD
OC7
(OM7=1 or OL7=1) or (OC7M7 = 1)
Figure 14-5. Block Diagram for Port7 with Output compare / Pulse Accumulator A
16-bit Main Timer
PTn
Edge detector
Delay counter
Set CnF Interrupt
TCn Input Capture Reg.
TCnH I.C. Holding Reg.
BUFEN • LATQ • TFMOD
Figure 14-6. C3F-C0F Interrupt Flag Setting
14.3 Enhanced Capture Timer Modes of Operation
The Enhanced Capture Timer has 8 Input Capture, Output Compare
(IC/OC) channels same as on the HC12 standard timer (timer channels
TC0 to TC7). When channels are selected as input capture by selecting
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the IOSx bit in TIOS register, they are called Input Capture (IC)
channels.
Four IC channels are the same as on the standard timer with one capture
register which memorizes the timer value captured by an action on the
associated input pin.
Four other IC channels, in addition to the capture register, have also one
buffer called holding register. This permits to memorize two different
timer values without generation of any interrupt.
Four 8-bit pulse accumulators are associated with the four buffered IC
channels. Each pulse accumulator has a holding register to memorize
their value by an action on its external input. Each pair of pulse
accumulators can be used as a 16-bit pulse accumulator.
The 16-bit modulus down-counter can control the transfer of the IC
registers contents and the pulse accumulators to the respective holding
registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base
with periodic interrupt capability.
14.3.1 IC Channels
The IC channels are composed of four standard IC registers and four
buffered IC channels.
An IC register is empty when it has been read or latched into the
holding register.
A holding register is empty when it has been read.
14.3.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin
transition. If the corresponding NOVWx bit of the ICOVW register is
cleared, with a new occurrence of a capture, the contents of IC register
are overwritten by the new value.
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Enhanced Capture Timer Modes of Operation
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register cannot be written unless it is empty.
This will prevent the captured value to be overwritten until it is read.
14.3.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels.
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•
IC Latch Mode:
When enabled (LATQ=1), the main timer value is memorized in the IC
register by a valid input pin transition.
The value of the buffered IC register is latched to its holding register by
the Modulus counter for a given period when the count reaches zero, by
a write $0000 to the modulus counter or by a write to ICLAT in the
MCCTL register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a
new occurrence of a capture, the contents of IC register are overwritten
by the new value. In case of latching, the contents of its holding register
are overwritten.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they
are empty (see IC Channels). This will prevent the captured value to be
overwritten until it is read or latched in the holding register.
•
IC Queue Mode:
When enabled (LATQ=0), the main timer value is memorized in the IC
register by a valid input pin transition.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a
new occurrence of a capture, the value of the IC register will be
transferred to its holding register and the IC register memorizes the new
timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register or its holding register cannot be written by an event unless they
are empty (see IC Channels).
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In queue mode, reads of holding register will latch the corresponding
pulse accumulator value to its holding register.
14.3.2 Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers
associated with the four IC buffered channels. A pulse accumulator
counts the number of active edges at the input of its channel.
The user can prevent 8-bit pulse accumulators counting further than $FF
by PACMX control bit in ICSYS ($AB). In this case a value of $FF means
that 255 counts or more have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse
accumulator.
There are two modes of operation for the pulse accumulators.
14.3.2.1 Pulse Accumulator latch mode
The value of the pulse accumulator is transferred to its holding register
when the modulus down-counter reaches zero, a write $0000 to the
modulus counter or when the force latch control bit ICLAT is written.
At the same time the pulse accumulator is cleared.
14.3.2.2 Pulse Accumulator queue mode
When queue mode is enabled, reads of an input capture holding register
will transfer the contents of the associated pulse accumulator to its
holding register.
At the same time the pulse accumulator is cleared.
14.3.3 Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a
periodic interrupt. It can also be used to latch the values of the IC
registers and the pulse accumulators to their holding registers.
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Timer Registers
The action of latching can be programmed to be periodic or only once.
14.4 Timer Registers
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTT bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTT bit.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
0
TIOS — Timer Input Capture/Output Compare Select
$0080
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
0
0
0
0
0
0
0
0
CFORC — Timer Compare Force Register
$0081
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
0
0
0
0
0
0
0
0
OC7M — Output Compare 7 Mask Register
$0082
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding IOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for each bit that
is set in OC7M, the corresponding data bit OC7D is stored to the
corresponding bit of the timer port.
NOTE:
OC7M has priority over output action on the timer port enabled by OMn
and OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
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Timer Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0
0
0
0
0
0
0
0
OC7D — Output Compare 7 Data Register
$0083
Read or write anytime.
The bits of OC7D correspond bit-for-bit with the bits of timer port
(PORTT). When a successful OC7 compare occurs, for each bit that is
set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
When the OC7Mn bit is set, a successful OC7 action will override a
successful OC[6:0] compare action during the same cycle; therefore, the
OCn action taken will depend on the corresponding OC7D bit.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
TCNT — Timer Count Register
$0084–$0085
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in
special modes (SMODN = 0).
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The period of the first count after a write to the TCNT registers may be a
different size because the write is not synchronized with the prescaler
clock.
RESET:
Bit 7
6
5
4
TEN
TSWAI
TSBCK
TFFCA
0
0
0
0
3
2
1
Bit 0
0
0
0
0
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TSCR — Timer System Control Register
$0086
Read or write anytime.
TEN — Timer Enable
0 = Disables the main timer, including the counter. Can be used for
reducing power consumption.
1 = Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the
pulse accumulator since the E÷64 is generated by the timer prescaler.
TSWAI — Timer Module Stops While in Wait
0 = Allows the timer module to continue running during wait.
1 = Disables the timer module when the MCU is in the wait mode.
Timer interrupts cannot be used to get the MCU out of wait.
TSWAI also affects pulse accumulators and modulus down counters.
TSBCK — Timer and Modulus Counter Stop While in Background Mode
0 = Allows the timer and modulus counter to continue running while
in background mode.
1 = Disables the timer and modulus counter whenever the MCU is
in background mode. This is useful for emulation.
TBSCK does not stop the pulse accumulator.
TFFCA — Timer Fast Flag Clear All
0 = Allows the timer flag clearing to function normally.
1 = For TFLG1($8E), a read from an input capture or a write to the
output compare channel ($90–$9F) causes the corresponding
channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any
access to the PACN3 and PACN2 registers ($A2, $A3) clears
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Timer Registers
the PAOVF and PAIF flags in the PAFLG register ($A1). Any
access to the PACN1 and PACN0 registers ($A4, $A5) clears
the PBOVF flag in the PBFLG register ($B1). Any access to the
MCCNT register ($B6, $B7) clears the MCZF flag in the
MCFLG register ($A7). This has the advantage of eliminating
software overhead in a separate clear sequence. Extra care is
required to avoid accidental flag clearing due to unintended
accesses.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
TQCR — Reserved
RESET:
$0087
Bit 7
6
5
4
3
2
1
Bit 0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0
0
0
0
0
0
0
0
TCTL1 — Timer Control Register 1
RESET:
$0088
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0
0
0
0
0
0
0
0
TCTL2 — Timer Control Register 2
$0089
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
NOTE:
To enable output action by OMn and OLn bits on the timer port, the
corresponding bit in OC7M should be cleared.
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Table 14-1. Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
0
0
0
0
0
0
0
0
TCTL3 — Timer Control Register 3
RESET:
$008A
Bit 7
6
5
4
3
2
1
Bit 0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
0
0
0
0
0
0
0
0
TCTL4 — Timer Control Register 4
$008B
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Table 14-2. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
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Timer Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
0
0
0
0
0
TMSK1 — Timer Interrupt Mask 1
$008C
Read or write anytime.
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status
register. If cleared, the corresponding flag is disabled from causing a
hardware interrupt. If set, the corresponding flag is enabled to cause a
hardware interrupt.
Read or write anytime.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
TOI
0
PUPT
RDPT
TCRE
PR2
PR1
PR0
0
0
0
0
0
0
0
0
TMSK2 — Timer Interrupt Mask 2
$008D
Read or write anytime.
TOI — Timer Overflow Interrupt Enable
0 = Interrupt inhibited
1 = Hardware interrupt requested when TOF flag set
PUPT — Timer Port Pull-Up Resistor Enable
This enable bit controls pull-up resistors on the timer port pins when
the pins are configured as inputs.
0 = Disable pull-up resistor function
1 = Enable pull-up resistor function
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RDPT — Timer Port Drive Reduction
This bit reduces the effective output driver size which can reduce
power supply current and generated noise depending upon pin
loading.
0 = Normal output drive capability
1 = Enable output drive reduction function
TCRE — Timer Counter Reset Enable
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This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is
reset from $FFFF to $0000.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of ÷2 stages that are to be
inserted between the module clock and the main timer counter.
Table 14-3. Prescaler Selection
PR2
PR1
PR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Prescale
Factor
1
2
4
8
16
32
64
128
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
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Timer Registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
0
TFLG1 — Main Timer Interrupt Flag 1
$008E
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the
use of the ICOVW register ($AA) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
TOF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TFLG2 — Main Timer Interrupt Flag 2
$008F
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, set the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
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TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC0 — Timer Input Capture/Output Compare Register 0
$0090–$0091
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC1 — Timer Input Capture/Output Compare Register 1
$0092–$0093
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC2 — Timer Input Capture/Output Compare Register 2
$0094–$0095
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC3 — Timer Input Capture/Output Compare Register 3
$0096–$0097
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC4 — Timer Input Capture/Output Compare Register 4
$0098–$0099
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC5 — Timer Input Capture/Output Compare Register 5
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Timer Registers
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC6 — Timer Input Capture/Output Compare Register 6
$009C–$009D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC7 — Timer Input Capture/Output Compare Register 7
$009E–$009F
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
0
0
0
PACTL — 16-Bit Pulse Accumulator A Control Register
$00A0
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
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PAEN — Pulse Accumulator A System Enable
0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and
PAC2 can be enabled when their related enable bits in
ICPACR ($A8) are set.
Pulse Accumulator Input Edge Flag (PAIF) function is
disabled.
1 = Pulse Accumulator A system enabled. The two 8-bit pulse
accumulators PAC3 and PAC2 are cascaded to form the
PACA 16-bit pulse accumulator. When PACA in enabled, the
PACN3 and PACN2 registers contents are respectively the
high and low byte of the PACA.
PA3EN and PA2EN control bits in ICPACR ($A8) have no
effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled.
PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PAMOD — Pulse Accumulator Mode
0 = event counter mode
1 = gated time accumulation mode
PEDGE — Pulse Accumulator Edge Control
For PAMOD bit = 0 (event counter mode).
0 = falling edges on PT7 pin cause the count to be incremented
1 = rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 = PT7 input pin high enables M divided by 64 clock to Pulse
Accumulator and the trailing falling edge on PT7 sets the PAIF
flag.
1 = PT7 input pin low enables M divided by 64 clock to Pulse
Accumulator and the trailing rising edge on PT7 sets the PAIF
flag.
PAMOD
PEDGE
0
0
Falling edge
Pin Action
0
1
Rising edge
1
0
Div. by 64 clock enabled with pin high level
1
1
Div. by 64 clock enabled with pin low level
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Timer Registers
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
CLK1
CLK0
Clock Source
0
0
Use timer prescaler clock as timer counter clock
0
1
Use PACLK as input to timer counter clock
1
0
Use PACLK/256 as timer counter clock frequency
1
1
Use PACLK/65536 as timer counter clock
frequency
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator A Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
PAOVF
PAIF
0
0
0
0
0
0
0
0
PAFLG — Pulse Accumulator A Flag Register
$00A1
Read or write anytime. When the TFFCA bit in the TSCR register is set, any
access to the PACNT register will clear all the flags in the PAFLG register.
PAOVF — Pulse Accumulator A Overflow Flag
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
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This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
PAIF — Pulse Accumulator Input edge Flag
Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation
mode the trailing edge of the gate signal at the PT7 input pin triggers
PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACN3, PACN2 registers will clear all the flags in
this register when TFFCA bit in register TSCR($86) is set.
BIT 7
6
5
4
3
2
1
BIT 0
$00A2
BIt 7
6
5
4
3
2
1
Bit 0
PACN3 (hi)
$00A3
Bit 7
6
5
4
3
2
1
Bit 0
PACN2 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN3, PACN2 — Pulse Accumulators Count Registers
$00A2, $00A3
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form
the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1
in PACTL, $A0) the PACN3 and PACN2 registers contents are
respectively the high and low byte of the PACA.
When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in
PAFLG ($A1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
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Timer Registers
BIT 7
6
5
4
3
2
1
BIT 0
$00A4
BIt 7
6
5
4
3
2
1
Bit 0
PACN1 (hi)
$00A5
Bit 7
6
5
4
3
2
1
Bit 0
PACN0 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN1, PACN0 — Pulse Accumulators Count Registers
$00A4, $00A5
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
MCZI
MODMC
RDMCL
ICLAT
FLMC
MCEN
MCPR1
MCPR0
0
0
0
0
0
0
0
0
MCCTL — 16-Bit Modulus Down-Counter Control Register
$00A6
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
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MODMC — Modulus Mode Enable
0 = The counter counts once from the value written to it and will
stop at $0000.
1 = Modulus mode is enabled. When the counter reaches $0000,
the counter is loaded with the latest value written to the
modulus count register.
NOTE:
For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FF.
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RDMCL — Read Modulus Down-Counter Load
0 = Reads of the modulus count register will return the present
value of the count register.
1 = Reads of the modulus count register will return the contents of
the load register.
ICLAT — Input Capture Force Latch Action
When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS ($AB) are set), a write one to this bit immediately forces the
contents of the input capture registers TC0 to TC3 and their
corresponding 8-bit pulse accumulators to be latched into the
associated holding registers. The pulse accumulators will be
automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will return always
zero.
FLMC — Force Load Register into the Modulus Counter Count Register
This bit is active only when the modulus down-counter is enabled
(MCEN=1).
A write one into this bit loads the load register into the modulus
counter count register. This also resets the modulus counter
prescaler.
Write zero to this bit has no effect.
When MODMC=0, counter starts counting and stops at $0000.
Read of this bit will return always zero.
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Timer Registers
MCEN — Modulus Down-Counter Enable
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
MCPR1, MCPR0 — Modulus Counter Prescaler select
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
RESET:
MCPR1
MCPR0
Prescaler division
rate
0
0
1
0
1
4
1
0
8
1
1
16
BIT 7
6
5
4
3
2
1
BIT 0
MCZF
0
0
0
POLF3
POLF2
POLF1
POLF0
0
0
0
0
0
0
0
0
MCFLG — 16-Bit Modulus Down-Counter FLAG Register
$00A7
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
The flag is set when the modulus down-counter reaches $0000.
Writing a1 to this bit clears the flag (if TFFCA=0). Writing zero has no
effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
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POLF3 – POLF0 — First Input Capture Polarity Status
These are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
PA3EN
PA2EN
PA1EN
PA0EN
0
0
0
0
0
0
0
0
ICPACR — Input Control Pulse Accumulators Control Register
$00A8
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
Read: any time
Write: any time
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
0 = 8-Bit Pulse Accumulator is disabled.
1 = 8-Bit Pulse Accumulator is enabled.
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Timer Registers
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
DLY1
DLY0
0
0
0
0
0
0
0
0
DLYCT — Delay Counter Control Register
$00A9
Read: any time
Write: any time
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If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
DLY1
DLY0
Delay
0
0
Disabled (bypassed)
0
1
256 M clock cycles
1
0
512 M clock cycles
1
1
1024 M clock cycles
BIT 7
6
5
4
3
2
1
BIT 0
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
0
0
0
0
0
0
0
0
RESET:
ICOVW — Input Control Overwrite Register
$00AA
Read: any time
Write: any time
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An IC register is empty when it has been read or latched into the holding
register.
A holding register is empty when it has been read.
NOVWx — No Input Capture Overwrite
0 = The contents of the related capture register or holding register
can be overwritten when a new input capture or latch occurs.
1 = The related capture register or holding register cannot be
written by an event unless they are empty (see IC Channels).
This will prevent the captured value to be overwritten until it is
read or latched in the holding register.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
0
0
0
0
0
0
0
0
ICSYS — Input Control System Control Register
$00AB
Read: any time
Write: May be written once (SMODN=1). Writes are always permitted
when SMODN=0.
SHxy — Share Input action of Input Capture Channels x and y
0 = Normal operation
1 = The channel input ‘x’ causes the same action on the channel
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
TFMOD — Timer Flag-setting Mode
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with
the use of the ICOVW register ($AA) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
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Timer Registers
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See Figure 14-6.
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In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid
input capture transition on the corresponding port pin occurs.
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
C3F–C0F in TFLG1 ($8E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD=0.
PACMX — 8-Bit Pulse Accumulators Maximum Count
0 = Normal operation. When the 8-bit pulse accumulator has
reached the value $FF, with the next active edge, it will be
incremented to $00.
1 = When the 8-bit pulse accumulator has reached the value $FF,
it will not be incremented further. The value $FF indicates a
count of 255 or more.
BUFEN — IC Buffer Enable
0 = Input Capture and pulse accumulator holding registers are
disabled.
1 = Input Capture and pulse accumulator holding registers are
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL ($A6), when LATQ is set
will produce latching of input capture and pulse accumulators
registers into their holding registers.
LATQ — Input Control Latch or Queue Mode Enable
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
Write one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN
are set will produce latching of input capture and pulse accumulators
registers into their holding registers.
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0 = Queue Mode of Input Capture is enabled.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
1 = Latch Mode is enabled. Latching function occurs when
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see Buffered IC Channels).
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
TCBYP
0
0
0
0
0
0
0
0
0
TIMTST — Timer Test Register
$00AD
Read: any time
Write: only in special mode (SMOD = 1).
TCBYP — Main Timer Divider Chain Bypass
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided
into two 8-bit halves and the prescaler is bypassed. The clock
drives both halves directly.
When the high byte of timer counter TCNT ($84) overflows
from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.
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Timer Registers
BIT 7
6
5
4
3
2
1
BIT 0
PORT
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
TIMER
I/OC7
I/OC6
I/OC5
I/OC4
I/OC3
I/OC2
I/OC1
I/OC0
RESET:
0
0
0
0
0
0
0
0
PORTT — Timer Port Data Register
$00AE
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Read: any time (inputs return pin level; outputs return data register
contents)
Write: data stored in an internal latch (drives pins only if configured for
output)
Since the Output Compare 7 shares the pin with Pulse Accumulator
input, the only way for Pulse accumulator to receive an independent
input from Output Compare 7 is setting both OM7 & OL7 to be zero, and
also OC7M7 in OC7M register to be zero.
OC7 is still able to reset the counter if enabled while PT7 is used as input
to Pulse Accumulator.
PORTT can be read anytime. When configured as an input, a read will
return the pin level. When configured as an output, a read will return the
latched output data.
NOTE:
Writes do not change pin state when the pin is configured for timer
output. The minimum pulse width for pulse accumulator input should
always be greater than the width of two module clocks due to input
synchronizer circuitry. The minimum pulse width for the input capture
should always be greater than the width of two module clocks due to
input synchronizer circuitry.
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RESET:
BIT 7
6
5
4
3
2
1
BIT 0
DDT7
DDT6
DDT5
DDT4
DDT3
DDT2
DDT1
DDT0
0
0
0
0
0
0
0
0
DDRT — Data Direction Register for Timer Port
$00AF
Read or write any time.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output.
The timer forces the I/O state to be an output for each timer port line
associated with an enabled output compare. In these cases the data
direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of
a pin when the associated timer output compare is disabled. Input
captures do not override the DDRT settings.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
PBEN
0
0
0
0
PBOVI
0
0
0
0
0
0
0
0
0
PBCTL — 16-Bit Pulse Accumulator B Control Register
$00B0
Read: any time
Write: any time
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input
pin with IC0.
PBEN — Pulse Accumulator B System Enable
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
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Timer Registers
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPACR ($A8) have no
effect.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PBOVI — Pulse Accumulator B Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PBOVF is set
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
PBOVF
0
0
0
0
0
0
0
0
0
PBFLG — Pulse Accumulator B Flag Register
$00B1
Read: any time
Write: any time
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
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BIT 7
6
5
4
3
2
1
BIT 0
$00B2
BIt 7
6
5
4
3
2
1
Bit 0
PA3H
$00B3
Bit 7
6
5
4
3
2
1
Bit 0
PA2H
$00B4
BIt 7
6
5
4
3
2
1
Bit 0
PA1H
$00B5
Bit 7
6
5
4
3
2
1
Bit 0
PA0H
RESET:
0
0
0
0
0
0
0
0
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
$00B2–$00B5
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see Pulse Accumulators).
BIT 7
6
5
4
3
2
1
BIT 0
$00B6
BIt 15
14
13
12
11
10
9
Bit 8
MCCNTH
$00B7
Bit 7
6
5
4
3
2
1
Bit 0
MCCNTL
RESET:
1
1
1
1
1
1
1
1
MCCNTH/L — Modulus Down-Counter Count Register
$00B6, $00B7
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
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Timer Registers
If a $0000 is written into MCCNT and modulus counter while LATQ and
BUFEN in ICSYS ($AB) register are set, the input capture and pulse
accumulator registers will be latched.
With a $0000 write to the MCCNT, the modulus counter will stay at zero
and does not set the MCZF flag in MCFLG register.
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If modulus mode is enabled (MODMC=1), a write to this address will
update the load register with the value written to it. The count register will
not be updated with the new value until the next counter underflow.
The FLMC bit in MCCTL ($A6) can be used to immediately update the
count register with the new value if an immediate load is desired.
If modulus mode is not enabled (MODMC=0), a write to this address will
clear the prescaler and will immediately update the counter register with
the value written to it and down-counts once to $0000.
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Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC0H — Timer Input Capture Holding Register 0
$00B8–$00B9
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC1H — Timer Input Capture Holding Register 1
$00BA–$00BB
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC2H — Timer Input Capture Holding Register 2
$00BC–$00BD
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TC3H — Timer Input Capture Holding Register 3
$00BE–$00BF
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be
cleared (see IC Channels).
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Timer and Modulus Counter Operation in Different Modes
14.5 Timer and Modulus Counter Operation in Different Modes
STOP:
Timer and modulus counter are off since clocks are stopped.
BGDM:
Timer and modulus counter keep on running, unless TSBCK
(REG$86, bit5) is set to one.
WAIT:
Counters keep on running, unless TSWAI in TSCR ($86) is
set to one.
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NORMAL: Timer and modulus counter keep on running, unless TEN in
TSCR($86) respectively MCEN in MCCTL ($A6) are
cleared.
TEN=0:
All 16-bit timer operations are stopped, can only access the
registers.
MCEN=0: Modulus counter is stopped.
PAEN=1:
16-bit Pulse Accumulator A is active.
PAEN=0:
8-Bit Pulse Accumulators 3 and 2 can be enabled. (see
ICPACR)
PBEN=1:
16-bit Pulse Accumulator B is active.
PBEN=0:
8-Bit Pulse Accumulators 1 and 0 can be enabled. (see
ICPACR)
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Section 15. Multiple Serial Interface
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4
Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .238
15.5
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . .250
15.6
Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
15.2 Introduction
The multiple serial interface (MSI) module consists of three independent
serial I/O sub-systems: two serial communication interfaces (SCI0 and
SCI1) and the serial peripheral interface (SPI). Each serial pin shares
function with the general-purpose port pins of port S. The SCI
subsystems are NRZ type systems that are compatible with standard
RS-232 systems. These SCI systems have a new single wire operation
mode which allows the unused pin to be available as general-purpose
I/O. The SPI subsystem, which is compatible with the M68HC11 SPI,
includes new features such as SS output and bidirectional mode.
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Multiple Serial Interface
15.3 Block diagram
SCI0
SCI1
RxD0
PS0
TxD0
PS1
RxD1
TxD1
MISO/SISO
SPI
MOSI/MOMI
DDRS/IOCTLR
MSI
PORT S I/O DRIVERS
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PS2
PS3
PS4
PS5
SCK
PS6
CS/SS
PS7
Figure 15-1. Multiple Serial Interface Block Diagram
15.4 Serial Communication Interface (SCI)
Two serial communication interfaces are available on the
68HC(9)12D60. These are NRZ format (one start, eight or nine data, and
one stop bit) asynchronous communication systems with independent
internal baud rate generation circuitry and SCI transmitters and
receivers. They can be configured for eight or nine data bits (one of
which may be designated as a parity bit, odd or even). If enabled, parity
is generated in hardware for transmitted and received data. Receiver
parity errors are flagged in hardware. The baud rate generator is based
on a modulus counter, allowing flexibility in choosing baud rates. There
is a receiver wake-up feature, an idle line detect feature, a loop-back
mode, and various error detection features. Two port pins for each SCI
provide the external interface for the transmitted data (TXD) and the
received data (RXD).
For a faster wake-up out of WAIT mode by a received SCI message,
both SCI have the capability of sending a receiver interrupt, if enabled,
when RAF (receiver active flag) is set. For compatibility with other
M68HC12 products, this feature is active only in WAIT mode and is
disabled when VDDPLL supply is at VSS level.
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Serial Communication Interface (SCI)
MCLK
BAUD RATE
CLOCK
SCI TRANSMITTER
MSB
DIVIDER
Rx Baud Rate
PARITY
GENERATOR
LSB
10-11 Bit SHIFT REG
TxD BUFFER/SCxDRL
SCxBD/SELECT
PIN CONTROL / DDRS / PORT S
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Tx Baud Rate
SCxCR1/SCI CTL 1
DATA BUS
TxMTR CONTROL
SCxCR2/SCI CTL 2
TxD
SCxSR1/INT STATUS
RxD
INT REQUEST LOGIC
TO
INTERNAL
LOGIC
PARITY
DETECT
DATA RECOVERY
SCI RECEIVER
MSB
LSB
10-11 BIT SHIFT REG
TxD BUFFER/SCxDRL
SCxCR1/SCI CTL 1
WAKE-UP LOGIC
SCxSR1/INT STATUS
SCxCR2/SCI CTL 2
INT REQUEST LOGIC
Figure 15-2. Serial Communications Interface Block Diagram
15.4.1 Data Format
The serial data format requires the following conditions:
•
An idle-line in the high state before transmission or reception of a
message.
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Multiple Serial Interface
•
A start bit (logic zero), transmitted or received, that indicates the
start of each character.
•
Data that is transmitted or received least significant bit (LSB) first.
•
A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
•
A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
•
This SCI supports hardware parity for transmit and receive.
15.4.2 SCI Baud Rate Generation
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
Table 15-1. Baud Rate Generation
Desired
SCI Baud Rate
110
300
600
1200
2400
4800
9600
14400
19200
38400
BR Divisor for
M = 4.0 MHz
2273
833
417
208
104
52
26
17
13
—
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BR Divisor for
M = 8.0 MHz
4545
2273
833
417
208
104
52
35
26
13
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Multiple Serial Interface
Serial Communication Interface (SCI)
15.4.3 SCI Register Descriptions
Control and data registers for the SCI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. Both SCI have identical control registers
mapped in two blocks of eight bytes.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
BTST
BSPL
BRLD
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
0
0
SC0BDH/SC1BDH — SCI Baud Rate Control Register
RESET:
High
$00C0/$00C8
Bit 7
6
5
4
3
2
1
Bit 0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
SC0BDL/SC1BDL — SCI Baud Rate Control Register
Low
$00C1/$00C9
SCxBDH and SCxBDL are considered together as a 16-bit baud rate
control register.
Read any time. Write SBR[12:0] anytime. Low order byte must be written
for change to take effect. Write SBR[15:13] only in special modes. The
value in SBR[12:0] determines the baud rate of the SCI. The desired
baud rate is determined by the following formula:
MCLKSCI Baud Rate = ------------------16 × BR
which is equivalent to:
MCLK
BR = ----------------------------------------------16 × SCI Baud Rate
BR is the value written to bits SBR[12:0] to establish baud rate.
NOTE:
The baud rate generator is disabled until TE or RE bit in SCxCR2
register is set for the first time after reset, and/or the baud rate generator
is disabled when SBR[12:0] = 0.
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BTST — Reserved for test function
BSPL — Reserved for test function
BRLD — Reserved for test function
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
WOMS
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
0
0
0
0
SC0CR1/SC1CR1 — SCI Control Register 1
$00C2/$00CA
Read or write anytime.
LOOPS — SCI LOOP Mode/Single Wire Mode Enable
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the
RXD pin is available as general purpose I/O. The receiver input is
determined by the RSRC bit. The transmitter output is controlled
by the associated DDRS bit. Both the transmitter and the receiver
must be enabled to use the LOOP or the single wire mode.
If the DDRS bit associated with the TXD pin is set during the LOOPS
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit
associated with the TXD pin is clear during the LOOPS = 1, the TXD
pin becomes high (IDLE line state) for RSRC = 0 and high impedance
for RSRC = 1. Refer to Table 15-2.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TXD and RXD) associated with the SCIx
section.
0 = Pins operate in a normal mode with both high and low drive
capability. To affect the RXD bit, that bit would have to be
configured as an output (via DDS0/2) which is the single wire
case when using the SCI. WOMS bit still affects general purpose
output on TXD and RXD pins when SCIx is not using these pins.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
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Serial Communication Interface (SCI)
RSRC — Receiver Source
When LOOPS = 1, the RSRC bit determines the internal feedback
path for the receiver.
0 = Receiver input is connected to the transmitter internally (not
TXD pin)
1 = Receiver input is connected to the TXD pin
Table 15-2. Loop Mode Functions
LOOPS RSRC
0
x
1
0
1
0
1
0
DDSI(3)
x
0
1
1
1
1
0
1
1
1
1
1
1
WOMS
Function of Port S Bit 1/3
x
Normal Operations
0/1
LOOP mode without TXD output(TXD = High Impedance)
1
LOOP mode with TXD output (CMOS)
1
LOOP mode with TXD output (open-drain)
Single wire mode without TXD output
x
(the pin is used as receiver input only, TXD = High Impedance)
Single wire mode with TXD output
0
(the output is also fed back to receiver input, CMOS)
1
Single wire mode for the receiving and transmitting(open-drain)
M — Mode (select character format)
0 = One start, eight data, one stop bit
1 = One start, eight data, ninth data, one stop bit
WAKE — Wake-up by Address Mark/Idle
0 = Wake up by IDLE line recognition
1 = Wake up by address mark (last data bit set)
ILT — Idle Line Type
Determines which of two types of idle line detection will be used by
the SCI receiver.
0 = Short idle line mode is enabled.
1 = Long idle line mode is detected.
In the short mode, the SCI circuitry begins counting ones in the search
for the idle line condition immediately after the start bit. This means
that the stop bit and any bits that were ones before the stop bit could
be counted in that string of ones, resulting in earlier recognition of an
idle line.
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In the long mode, the SCI circuitry does not begin counting ones in the
search for the idle line condition until a stop bit is received. Therefore,
the last byte’s stop bit and preceding “1” bits do not affect how quickly
an idle line condition can be detected.
PE — Parity Enable
0 = Parity is disabled.
1 = Parity is enabled.
PT — Parity Type
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = Even parity is selected. An even number of ones in the data
character causes the parity bit to be zero and an odd number
of ones causes the parity bit to be one.
1 = Odd parity is selected. An odd number of ones in the data
character causes the parity bit to be zero and an even number
of ones causes the parity bit to be one.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
SC0CR2/SC1CR2 — SCI Control Register 2
$00C3/$00CB
Read or write anytime.
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt will be requested whenever the TDRE status flag
is set.
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt will be requested whenever the TC status flag is
set.
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Serial Communication Interface (SCI)
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode
disabled
1 = SCI interrupt will be requested whenever the RDRF or OR
status flag is set, or when RAF is set while in WAIT mode with
VDDPLL high.
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ILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt will be requested whenever the IDLE status flag
is set.
TE — Transmitter Enable
0 = Transmitter disabled
1 = SCI transmit logic is enabled and the TXD pin (Port S bit 1/bit
3) is dedicated to the transmitter. The TE bit can be used to
queue an idle preamble.
RE — Receiver Enable
0 = Receiver disabled
1 = Enables the SCI receive circuitry.
RWU — Receiver Wake-Up Control
0 = Normal SCI Receiver
1 = Enables the wake-up function and inhibits further receiver
interrupts. Normally hardware wakes the receiver by
automatically clearing this bit.
SBK — Send Break
0 = Break generator off
1 = Generate a break code (at least 10 or 11 contiguous zeros).
As long as SBK remains set the transmitter will send zeros. When
SBK is changed to zero, the current frame of all zeros is finished
before the TxD line goes to the idle state. If SBK is toggled on and off,
the transmitter will send only 10 (or 11) zeros and then revert to mark
idle or sending data.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
SC0SR1/SC1SR1 — SCI Status Register 1
$00C4/$00CC
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The bits in these registers are set by various conditions in the SCI
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SCxSR1 (RDRF, IDLE, OR,
NF, FE, and PF) are all cleared by a read of the SCxSR1 register
followed by a read of the transmit/receive data register low byte.
However, only those bits which were set when SCxSR1 was read will be
cleared by the subsequent read of the transmit/receive data register low
byte. The transmit related bits in SCxSR1 (TDRE and TC) are cleared by
a read of the SCxSR1 register followed by a write to the transmit/receive
data registerl low byte.
Read anytime (used in auto clearing mechanism). Write has no meaning
or effect.
TDRE — Transmit Data Register Empty Flag
New data will not be transmitted unless SCxSR1 is read before writing
to the transmit data register. Reset sets this bit.
0 = SCxDR busy
1 = Any byte in the transmit data register is transferred to the serial
shift register so new data may now be written to the transmit
data register.
TC — Transmit Complete Flag
Flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear by reading SCxSR1 with TC set and
then writing to SCxDR.
0 = Transmitter busy
1 = Transmitter is idle
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Serial Communication Interface (SCI)
RDRF — Receive Data Register Full Flag
Once cleared, IDLE is not set again until the RxD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with
RDRF set and then reading SCxDR.
0 = SCxDR empty
1 = SCxDR full
IDLE — Idle Line Detected Flag
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Receiver idle line is detected (the receipt of a minimum of 10/11
consecutive ones). This bit will not be set by the idle line condition
when the RWU bit is set. Once cleared, IDLE will not be set again until
after RDRF has been set (after the line has been active and becomes
idle again).
0 = RxD line is idle
1 = RxD line is active
OR — Overrun Error Flag
New byte is ready to be transferred from the receive shift register to
the receive data register and the receive data register is already full
(RDRF bit is set). Data transfer is inhibited until this bit is cleared.
0 = No overrun
1 = Overrun detected
NF — Noise Error Flag
Set during the same cycle as the RDRF bit but not set in the case of
an overrun (OR).
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
FE — Framing Error Flag
Set when a zero is detected where a stop bit was expected. Clear the
FE flag by reading SCxSR1 with FE set and then reading SCxDR.
0 = Stop bit detected
1 = Zero detected rather than a stop bit
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PF — Parity Error Flag
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
0 = Parity correct
1 = Incorrect parity detected
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
SCSWAI
MIE(1)
MDL1(1)
MDL0(1)
0
0
0
RAF
0
0
0
0
0
0
0
0
SC0SR2 — SCI Status Register 2
$00C5/$00CD
1. See Motorola Interconnect Bus for descriptions of these bits.
Read anytime. Write has no meaning or effect.
SCSWAI — Serial Communications Interface Stop in WAIT Mode
0 = SCI clock operates normally.
1 = Halt SCI clock generation when in WAIT mode.
RAF — Receiver Active Flag
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
0 = A character is not being received
1 = A character is being received
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high.
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Serial Communication Interface (SCI)
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
—
—
—
—
—
—
—
—
SC0DRH/SC1DRH — SCI Data Register High
RESET:
$00C6/$00CE
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
—
—
—
—
—
—
—
—
SC0DRL/SC1DRL — SCI Data Register Low
$00C7/$00CF
R8 — Receive Bit 8
Read anytime. Write has no meaning or affect.
This bit is the ninth serial data bit received when the SCI system is
configured for nine-data-bit operation.
T8 — Transmit Bit 8
Read or write anytime.
This bit is the ninth serial data bit transmitted when the SCI system is
configured for nine-data-bit operation. When using 9-bit data format
this bit does not have to be written for each data word. The same
value will be transmitted as the ninth bit until this bit is rewritten.
R7/T7–R0/T0 — Receive/Transmit Data Bits 7 to 0
Reads access the eight bits of the read-only SCI receive data register
(RDR). Writes access the eight bits of the write-only SCI transmit data
register (TDR). SCxDRL:SCxDRH form the 9-bit data word for the
SCI. If the SCI is being used with a 7- or 8-bit data word, only SCxDRL
needs to be accessed. If a 9-bit format is used, the upper register
should be written first to ensure that it is transferred to the transmitter
shift register with the lower register.
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15.5 Serial Peripheral Interface (SPI)
The serial peripheral interface allows the 68HC(9)12D60 to
communicate synchronously with peripheral devices and other
microprocessors. The SPI system in the 68HC(9)12D60 can operate as
a master or as a slave. The SPI is also capable of interprocessor
communications in a multiple master system.
When the SPI is enabled, all pins that are defined by the configuration
as inputs will be inputs regardless of the state of the DDRS bits for those
pins. All pins that are defined as SPI outputs will be outputs only if the
DDRS bits for those pins are set. Any SPI output whose corresponding
DDRS bit is cleared can be used as a general-purpose input.
A bidirectional serial pin is possible using the DDRS as the direction
control.
15.5.1 SPI Baud Rate Generation
The E Clock is input to a divider series and the resulting SPI clock rate
may be selected to be E divided by 2, 4, 8, 16, 32, 64, 128 or 256. Three
bits in the SP0BR register control the SPI clock rate. This baud rate
generator is activated only when SPI is in the master mode and serial
transfer is taking place. Otherwise this divider is disabled to save power.
15.5.2 SPI Operation
In the SPI system the 8-bit data register in the master and the 8-bit data
register in the slave are linked to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially
shifted eight bit positions by the SCK clock from the master so the data
is effectively exchanged between the master and the slave. Data written
to the SP0DR register of the master becomes the output data for the
slave and data read from the SP0DR register of the master after a
transfer operation is the input data from the slave.
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Serial Peripheral Interface (SPI)
MCU P CLOCK
(SAME AS E RATE)
DIVIDER
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256
8-BIT SHIFT REGISTER
S
M
MISO
PS4
M
S
MOSI
PS5
READ DATA BUFFER
SP0DR SPI DATA REGISTER
SELECT
LSBF
PIN
CONTROL
LOGIC
SPR0
SPR1
SPR2
SHIFT CONTROL LOGIC
CLOCK
SCK
PS6
S
CLOCK
LOGIC
SP0BR SPI BAUD RATE REGISTER
M
SS
PS7
MSTR
SPE
SPI CONTROL
SPI
INTERRUPT
REQUEST
SP0SR SPI STATUS REGISTER
SP0CR1 SPI CONTROL REGISTER 1
SPC0
RDS
PUPS
LSBF
SSOE
CPHA
CPOL
SWOM
MSTR
SPE
SPIE
MODF
WCOL
SWOM
SPIF
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SP0CR2 SPI CONTROL REGISTER 2
INTERNAL BUS
Figure 15-3. Serial Peripheral Interface Block Diagram
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)
in the SP0CR1 register select one of four possible clock formats to be
used by the SPI system. The CPOL bit simply selects non-inverted or
inverted clock. The CPHA bit is used to accommodate two
fundamentally different protocols by shifting the clock by one half cycle
or no phase shift.
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Transfer
Begin
End
SCK (CPOL=0)
SCK (CPOL=1)
If next transfer begins here
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SAMPLE I
(MOSI/MISO)
CHANGE O
(MOSI pin)
CHANGE O
(MISO pin)
SEL SS (O)
(Master only)
SEL SS (I)
MSB first (LSBF=0):
LSB first (LSBF=1):
tL
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
tT
tL
tI
Minimum 1/2 SCK
for tT, tl, tL
Figure 15-4. SPI Clock Format 0 (CPHA = 0)
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Serial Peripheral Interface (SPI)
Transfer
Begin
End
SCK (CPOL=0)
SCK (CPOL=1)
SAMPLE I
(MOSI/MISO)
If next transfer begins here
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CHANGE O
(MOSI pin)
CHANGE O
(MISO pin)
SEL SS (O)
(Master only)
SEL SS (I)
tL
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
tT
tL
tI
LSB Minimum 1/2 SCK
for tT, tl, tL
MSB
Figure 15-5. SPI Clock Format 1 (CPHA = 1)
15.5.3 SS Output
Available in master mode only, SS output is enabled with the SSOE bit
in the SP0CR1 register if the corresponding DDRS is set. The SS output
pin will be connected to the SS input pin of the external slave device. The
SS output automatically goes low for each transmission to select the
external device and it goes high during each idling state to deselect
external devices.
Table 15-3. SS Output Selection
DDS7
0
0
1
1
SSOE
0
1
0
1
Master Mode
SS Input with MODF Feature
Reserved
General-Purpose Output
SS Output
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SS Input
SS Input
SS Input
SS Input
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15.5.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
When SPE=1
Master Mode
MSTR=1
Slave Mode
MSTR=0
MO
Serial Out
Normal
Mode
SPC0=0
SPI
SPI
DDS5
MI
Serial In
SWOM enables open drain output.
SPI
Serial In
DDS4
SO
Serial Out
SWOM enables open drain output.
MOMI
Serial Out
Bidirectional
Mode
SPC0=1
SI
Serial In
SPI
DDS5
PS4
SWOM enables open drain output. PS4 becomes GPIO.
PS5
Serial In
DDS4
Serial Out
SISO
SWOM enables open drain output. PS5 becomes GPIO.
Figure 15-6. Normal Mode and Bidirectional Mode
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Serial Peripheral Interface (SPI)
15.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes
and Resource Mapping.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
SWOM
MSTR
CPOL
CPHA
SSOE
LSBF
0
0
0
0
0
1
0
0
SP0CR1 — SPI Control Register 1
$00D0
Read or write anytime.
SPIE — SPI Interrupt Enable
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
or MODF status flag is set
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a lowpower disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
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CPOL, CPHA — SPI Clock Polarity, Clock Phase
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See Figure 15-4 and Figure 15-5.
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
LSBF — SPI LSB First enable
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
SPSWAI
SPC0
0
0
0
0
0
0
0
0
SP0CR2 — SPI Control Register 2
$00D1
Read or write anytime.
SPSWAI — Serial Interface Stop in WAIT mode
0 = Serial interface clock operates normally
1 = Halt serial interface clock generation in WAIT mode
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Serial Peripheral Interface (SPI)
SPC0 — Serial Pin Control 0
This bit decides serial pin configurations with MSTR control bit.
SPC0(1)
Pin Mode
#1
Normal
MSTR
MISO(2)
MOSI(3)
SCK(4)
SS(5)
0
Slave Out
Slave In
SCK In
SS In
1
Master In Master Out SCK Out
SS I/O
0
Slave I/O
SS In
1
GPI/O
0
#2
#3
Bidirectional
GPI/O
SCK In
1
#4
Master I/O SCK Out
SS I/O
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
SPR2
SPR1
SPR0
0
0
0
0
0
0
0
0
SP0BR — SPI Baud Rate Register
$00D2
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Table 15-4. SPI Clock Rate Selection
SPR2
SPR1
SPR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at
Frequency at
E Clock = 4 MHz E Clock = 8 MHz
2.0 MHz
4.0 MHz
1.0 MHz
2.0 MHz
500 kHz
1.0 MHz
250 kHz
500 KHz
125 kHz
250 KHz
62.5 kHz
125 KHz
31.3 kHz
62.5 KHz
15.6 kHz
31.3 KHz
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
SP0SR — SPI Status Register
$00D3
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Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
WCOL — Write Collision Status Flag
The MCU write is disabled to avoid writing over the data being
transferred. No interrupt is generated because the error status flag
can be read upon completion of the transfer that was in progress at
the time of the error. Automatically cleared by a read of the SP0SR
(with WCOL set) followed by an access (read or write) to the SP0DR
register.
0 = No write collision
1 = Indicates that a serial transfer was in progress when the MCU
tried to write new data into the SP0DR data register.
MODF — SPI Mode Error Interrupt Status Flag
This bit is set automatically by SPI hardware if the MSTR control bit is
set and the slave select input pin becomes zero. This condition is not
permitted in normal operation. In the case where DDRS bit 7 is set,
the PS7 pin is a general-purpose output pin or SS output pin rather
than being dedicated as the SS input for the SPI system. In this
special case the mode fault function is inhibited and MODF remains
cleared. This flag is automatically cleared by a read of the SP0SR
(with MODF set) followed by a write to the SP0CR1 register.
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Serial Peripheral Interface (SPI)
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
SP0DR — SPI Data Register
$00D5
Read anytime (normally only after SPIF flag set). Write anytime (see
WCOL write collision flag).
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Reset does not affect this address.
This 8-bit register is both the input and output register for SPI data.
Reads of this register are double buffered but writes cause data to be
written directly into the serial shifter. In the SPI system the 8-bit data
register in the master and the 8-bit data register in the slave are linked
by the MOSI and MISO wires to form a distributed 16-bit register. When
a data transfer operation is performed, this 16-bit register is serially
shifted eight bit positions by the SCK clock from the master so the data
is effectively exchanged between the master and the slave. Note that
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
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15.6 Port S
In all modes, port S bits PS[7:0] can be used for either general-purpose
I/O, or with the SCI and SPI subsystems. During reset, port S pins are
configured as high-impedance inputs (DDRS is cleared).
PORTS — Port S Data Register
Bit 7
Pin
Function
6
$00D6
5
4
3
2
1
Bit 0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
SS
CS
SCK
MOSI
MOMI
MISO
SISO
TXD1
RXD1
TXD0
RXD0
Read anytime (inputs return pin level; outputs return pin driver input
level). Write data stored in internal latch (drives pins only if configured for
output). Writes do not change pin state when pin configured for SPI or
SCI output.
After reset all bits are configured as general-purpose inputs.
Port S shares function with the on-chip serial systems (SPI and SCI0/1).
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
DDS7
DDS6
DDS5
DDS4
DDS3
DDS2
DDS1
DDS0
0
0
0
0
0
0
0
0
DDRS — Data Direction Register for Port S
$00D7
Read or write anytime.
After reset, all general-purpose I/O are configured for input only.
0 = Configure the corresponding I/O pin for input only
1 = Configure the corresponding I/O pin for output
DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0
If the SCI receiver is configured for two-wire SCI operation,
corresponding port S pins will be input regardless of the state of these
bits.
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Port S
DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1
If the SCI transmitter is configured for two-wire SCI operation,
corresponding port S pins will be output regardless of the state of
these bits.
DDS[6:4] — Data Direction for Port S Bits 6 through 4
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If the SPI is enabled and expects the corresponding port S pin to be
an input, it will be an input regardless of the state of the DDRS bit. If
the SPI is enabled and expects the bit to be an output, it will be an
output ONLY if the DDRS bit is set.
DDS7 — Data Direction for Port S Bit 7
In SPI slave mode, DDRS7 has no meaning or effect; the PS7 pin is
dedicated as the SS input. In SPI master mode, DDRS7 determines
whether PS7 is an error detect input to the SPI or a general-purpose
or slave select output line.
NOTE:
If mode fault error occurs, bits 5, 6 and 7 are forced to zero.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
RDPS2
RDPS1
RDPS0
0
PUPS2
PUPS1
PUPS0
0
0
0
0
0
0
0
0
PURDS — Pull-Up Register for Port S
$00D9
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RDPS2 — Reduce Drive of Port S[7:4]
0 = Port S[7:4] output drivers operate normally
1 = Port S[7:4] output pins have reduced drive capability for lower
power and less noise
RDPS1 — Reduce Drive of Port S[3:2]
0 = Port S[3:2] output drivers operate normally
1 = Port S[3:2] output pins have reduced drive capability for lower
power and less noise
RDPS0 — Reduce Drive of Port S[1:0]
0 = Port S[1:0] output drivers operate normally
1 = Port S[1:0] output pins have reduced drive capability for lower
power and less noise
PUPS2 — Pull-up Port S[7:4] Enable
0 = No internal pull-ups on port S[7:4]
1 = Port S[7:4] input pins have an active pull-up device. If a pin is
programmed as output, the pull-up device becomes inactive.
PUPS1 — Pull-up Port S[3:2] Enable
0 = No internal pull-ups on port S[3:2]
1 = Port S[3:2] input pins have an active pull-up device. If a pin is
programmed as output, the pull-up device becomes inactive.
PUPS0 — Pull-up Port S[1:0] Enable
0 = No internal pull-ups on port S[1:0]
1 = Port S[1:0] input pins have an active pull-up device. If a pin is
programmed as output, the pull-up device becomes inactive.
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Section 16. Motorola Interconnect Bus
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
16.3
Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
16.4
Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
16.5
Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
16.6
Interfacing to MI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.7
MI Bus clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.8
SCI0/MI Bus registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.2 Introduction
The Motorola Interconnect Bus (MI Bus) is a serial communications
protocol which supports distributed real-time control efficiently and with
a high degree of noise immunity, at a typical data transfer bit rate of
20kHz. The MI Bus is suitable for medium speed networks requiring very
low cost multiplex wiring; only one wire is required to connect to slave
devices.(1)
The MI Bus uses a push-pull sequence to transfer data. The master
device, which in this case is the 68HC(9)12D60, sends a push field to the
slave devices connected to the bus. The push field contains data plus an
address that is recognized by one of the slaves. The slave addressed
returns data which the master pulls from the MI Bus over the same wire.
Specific details of the message format are covered later in this section.
1. Related information on Motorola’s MI Bus is contained in the following Motorola publications:
EB409/D — The MI Bus and Product family for Multiplexing Systems
AN475/D — Single Wire MI Bus Controlling Stepper Motors
BR477/D — Smart Mover – Stepper Motors with Integrated Serial Bus Controller
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The MCU (master) can take the bus at any time, with a start bit that
violates the rules of Manchester biphase encoding. Up to eight slave
devices may be addressed by the MI Bus. Other features of MI Bus
include message validation, error detection, and default value setting.
On the 68HC(9)12D60 the MI Bus module shares the same pins on port
S as the SCI0 module. Data is transmitted (or ‘pushed’) via the TxD0 pin,
and received (‘pulled’) via the RxD0 pin. While data is being pushed,
RxD0 will be disconnected from the receiver circuitry. The message
frame is handled automatically in hardware. The MCU register interface
is similar to that for the SCI.
16.3 Push-pull sequence
Communication between the MCU and the slave device always utilizes
the same frame organization. First, the MCU sends serial data to the
selected device. This data field is called the ‘push field’. At the end of the
push field, the selected device automatically sends back to the MCU the
data held during the push sequence. The MCU reads the serial data sent
by the selected device. This data is called the ‘pull field’ and contains
status information followed by the end-of-frame information from the
selected device.
Time slots
Push (biphase coded)
Push-pull function
Pull (NRZ coded)
TxD0 pin (true data)
1 0
0 1
MI Bus wire
0 1 2 3 4 5 6 7
Start
Push
Start sync D0 D1 D2 D3 D4
A0
Data
A1
Pull
A2 sync
Address
NRZ
Data
Push field
(driven by MCU)
End of frame
Pull field
(driven by slave)
New frame
Bit fields
Stop
S3
S2
S1
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Message frame
Figure 16-1. MI Bus timing
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Biphase coding
16.3.1 The push field
The push field consists of a start bit, a push synchronization bit, a push
data field and a push address field. The start consists of three time slots
having the dominant logical state ‘0’. The start marks the beginning of
the message frame by violation of the rule of the Manchester code. The
push synchronization bit consists of a biphase coded ‘0’. Biphase coding
will be discussed later. The push data field consists of five bits of biphase
coded data. The push address consists of three bits of biphase coded
data. Data and address are written to the lower byte of the SCI data
register (SC0DRL). The push data occupies the lower five bits and the
push address occupies the upper three bits of the register.
16.3.2 The pull field
The pull field consists of a pull synchronization bit, a pull data field and
an end of frame. The pull synchronization bit is a biphase coded ‘1’ and
is initiated by the MCU during the time slot after the last address bit of
the push field. The pull data field consists of an NRZ coded transmission,
each bit taking one time slot. Once shifted in, the pull data is stored in
the lower byte of the SCI data register (SC0DRL). The end-of-frame field
is a square wave signal having a typical frequency of 20kHz ± 1%
tolerance (i.e. the bit rate of the push field) when the data sent to the
selected device is valid.
16.4 Biphase coding
Manchester biphase L coding is used for the push field bits. Each bit
requires two time slots to encode the logic value of the bit. This encoding
allows the detection of a single error at the time slot level. Bits are
encoded as follows:
0 = In the first time slot, the logic level is set to one, followed by a
logic level zero in the second time slot.
1 = In the first time slot, the logic level is set to zero, followed by a
logic level one in the second time slot.
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‘0’
‘1’
Biphase coded signal
0
1
2
3
4
5
a
6
7
0
1
b
2
3
4
5
a
6
t
7
b
Biphase detection
a’
a
b’
b
a’
a
b’
b
Noise detection
Figure 16-2. Biphase coding and error detection
16.5 Message validation
The communication between the MCU and the selected device is valid
when the MCU reads a pull data field having correct codes (excluding
the codes ‘111’ and ‘000’) followed by a square wave signal, having a
frequency of 20kHz, contained in the end-of-frame information.
An MI Bus error is detected when the pull field contains the code ‘111’
followed by the end-of-frame permanently tied to logical state ‘1’. This
means that the communication between the MCU and the selected
device was not accomplished.
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Message validation
Transmit buffer
T8
LOOPS
10/11-bit TX shift register
H 8 7
RSRC
M
TxD0
0 L
WAKE
MCLK
clock
ILT
PE
MIE
PT
PT
Transmitter
control
TE
Flag control
Rate generator
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SBK
TIE
TCIE
ILIE
MIE
RE
RE
SC0BDL
SC0CR2
RIE
TE
Receiver
RWU
WOMS
SC0BDH
SC0CR1
WOMS
control
SBK
WOMS
SCSWAI
MIE
SC0SR2
MDL1
10/11-bit RX shift register
MDL0
8 7
Data
recovery
0
STOP
RxD0
START
R8
Receive buffer
RAF
†
†
NF
†
OR
TC
RDRF
TDRE
SC0SR1
IDLE
ILIE
&
RDRF
RIE
&
+
SCI interrupt request
TC
TCIE
&
TDRE
TIE
&
Note: † = always reads as zero
= not used in MI Bus mode
Internal data bus
Figure 16-3. MI BUS Block Diagram
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16.5.1 Controller detected errors
There are three different MI Bus error types which are detected by the
selected slave device and are not mutually exclusive. The MCU cannot
determine which error occurred.
Noise error — Slave devices take two samples in each time slot of
the biphase encoded push field. An error occurs when the two
samples for each time slot are not the same logical level.
Biphase error — Slave devices receiving the push field detect the
biphase code. An error occurs when the two time slots of the biphase
code do not yield a logical exclusive-OR function.
Field error — A field error is detected when the fixed-form of the push
field is violated.
16.5.2 MCU detected errors
There is a fourth error that can be detected by the MCU. This error
causes the noise flag (NF) to be asserted in the SC0SR1 register during
the push field sequence.
Bit error — A bit error can be detected by the MCU during the push
field. The MI Bus serial system monitors the bus via on-chip hardware
at the RxD0 pin at the same time as sending data. A bit error is
detected at that bit time when the value monitored is different from the
bit value sent.
16.6 Interfacing to MI Bus
Physically the MI Bus consists of only a single wire. In the example
shown in Figure 16-4, only a single transistor and a few passive
components are required to connect up the 68HC(9)12D60 for full
MI Bus operation.
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Interfacing to MI Bus
VDD
+12V
4.7kΩ
1.2kΩ
18V
MI Bus
VDD
T1
TX
3.9kΩ
VDD
10kΩ
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MCU
22kΩ
10kΩ
RX
VSS
Figure 16-4. A typical MI Bus interface
The transistor serves both to drive the MI Bus during the push field and
to protect the MCU TX pin from voltage transients generated in the
wiring. Without the transistor, EMI could damage the TX pin. Similarly,
the input pin (RX) is protected from EMI by clamping it to the MCU supply
rails with two diodes. When a load dump occurs, the zener diode (18V)
is switched on and hence turns the transistor on; this generates the logic
‘0’ state on the MI Bus. After eight time slots (200ms) of continuous ‘0’
state, all devices on the MI Bus will have their outputs disabled.
The MI Bus line can take two states, recessive or dominant. The
dominant state (‘0’) is represented by a maximum 0.3V (VCESAT of the
transistor, T1). The recessive state (‘1’) is represented by 5V, through a
pull-up resistor of 10kΩ.
The bus load depends on the number of devices on the bus. Each device
has a pull-up resistor of 10kΩ. An external termination resistor is used
to stabilize the load resistance of the bus at 600Ω.
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16.7 MI Bus clock rate
The MI Bus clock rate is set via the SCI baud registers. To use the
MI Bus, the MCLK clock frequency that drives the SCI clock generator
must be selected to match the minimum resolution of the MI Bus logic.
This is expressed by the following formula:
MCLK = 16 • n • (2 • Push_field_bit_rate) = 16 • n • 40kHz = n • 640kHz
where ‘n’ is an integer and 20kHz is the minimum Push field bit rate for
the MI Bus. Values for MCLK could be 640kHz,1280kHz, 1920kHz, …,
n • 640kHz. The value ‘n’ is the modulus for the MI Bus baud register.
MCLK may be the output of the PLL circuit or it may be the EXTAL/2
input of the MCU. Refer to Clock Divider Chains.
16.8 SCI0/MI Bus registers
MI Bus operation is controlled by the same group of registers as is used
for the SCI. However the functions of some of the bits are modified when
in MI Bus mode. A description of the registers, as applicable to the
MI Bus function, is given here.
In MI Bus mode, bits that have no meaning are reserved by Motorola,
and are not described.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
BTST
BSPL
BRLD
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
0
0
SC0BDH — MI Bus Clock Rate Control Register
RESET:
$00C0
Bit 7
6
5
4
3
2
1
Bit 0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
SC0BDL — MI Bus Clock Rate Control Register
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High
Low
$00C1
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SCI0/MI Bus registers
SC0BDH and SC0BDL are considered together as a 16-bit baud rate
control register.
Read any time. Write SBR[12:0] anytime. Low order byte must be written
for change to take effect. Write SBR[15:13] only in special modes.
The value in SBR[12:0] determines the clock rate of the MI Bus. The
desired baud rate is determined by the following formula:
MCLKMI BUS Clock Rate = ------------------16 × BR
BR is the value written to bits SBR[12:0] to establish baud rate.
NOTE:
The baud rate generator is disabled until TE or RE bit in SC0CR2
register is set for the first time after reset, and/or the baud rate generator
is disabled when SBR[12:0] = 0.
BTST — Reserved for test function
BSPL — Reserved for test function
BRLD — Reserved for test function
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
—
WOMS
—
—
—
—
—
PT
0
0
0
0
0
0
0
0
SC0CR1 — MI Bus Control Register 1
$00C2
Read or write anytime.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TxD0 and RxD0) associated with the
SC0 section.
0 = Pins operate in a normal mode with both high and low drive
capability.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
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PT — MI Bus TxD0 polarity
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = MI Bus transmit pin functions normally.
1 = MI Bus transmit pin will send inverted data.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
—
—
RIE
—
TE
RE
—
SBK
0
0
0
0
0
0
0
0
SC0CR2 — MI Bus Control Register 2
$00C3
Read or write anytime.
RIE — Receiver Interrupt Enable
0 = RDRF interrupt disabled.
1 = MI Bus interrupt will be requested whenever the RDRF status
flag is set.
OR does not generate an interrupt request in MI Bus mode.
TE — Transmitter Enable
0 = Transmitter disabled.
1 = MI Bus transmit logic is enabled and the TxD0 pin (Port S bit 1)
is dedicated to the transmitter.
RE — Receiver Enable
0 = Receiver disabled.
1 = Port pin dedicated to the MI Bus; the receiver is enabled by a
pull sync and is inhibited during a push field.
SBK — Send Break
0 = No action.
1 = MI transmit line is set low for 20 time slots.
When an MI Bus wire is held low for eight or more time slots an
internal circuit on any slave device connected to the bus may reset or
preset the device with default values.
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SCI0/MI Bus registers
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
—
—
RDRF
—
OR
NF
—
—
1
1
0
0
0
0
0
0
SC0SR1 — MI Bus Status Register 1
$00C4
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The bits in these registers are set by various conditions in the MI Bus
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SC0SR1 (RDRF, OR and
NF) are all cleared by a read of this register followed by a read of the
transmit/receive data register low byte. However, only those bits
which were set when SC0SR1 was read will be cleared by the
subsequent read of the transmit/receive data register low byte.
Read anytime (used in auto clearing mechanism). Write has no
meaning or effect.
RDRF — Receive Data Register Full Flag
0 = Contents of the receiver shift register have not been transferred
to the receiver data register.
1 = Contents of the receiver serial shift register have been
transferred to the receiver data register.
The EOF (end-of-frame) during an MI Bus pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
– By clearing the RIE mask, ignoring unneeded RDRFs, initiating
a push field, waiting for TDRE(1) and then clearing the RDRF
– By clearing the RE bit when a pull field is complete, followed by
setting the RE bit after the TDRE1 flag associated with the next
push field is asserted.
– By disabling the MI Bus.
1. Note that TDRE and TC will both behave in the same way as during normal SCI transmissions.
The MI Bus will still be receiving when the TC bit becomes set, hence any queued transmission
will not start until the current pull field has finished. See also Register Descriptions.
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OR — Bit Error Flag
0 = No bit error has been detected.
1 = A bit error has been detected.
This bit is set when a push field bit value on the MI Bus does not
match the bit value that was sent. This is known as an MI Bus bit
error. OR does not generate an interrupt request in MI Bus mode.
NF — Noise Error Flag
0 = No noise detected.
1 = Noise detected.
This bit is set when noise is detected on the receive line during an
MI Bus pull field.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
SCSWAI
MIE
MDL1
MDL0
0
0
0
RAF
0
0
0
0
0
0
0
0
SC0SR2 — MI Bus Status Register 2
$00C5
Read anytime. Write has no meaning or effect.
SCSWAI — Serial Communications Interface Stop in WAIT Mode
0 = SCI clock operates normally.
1 = Halt SCI clock generation when in WAIT mode.
MIE — Motorola Interface Bus (MI Bus) Enable
0 = The SCI functions normally.
1 = MI Bus is enabled for this subsystem.
When MIE is set, the SCI0 registers, bits and pins assume the
functionality required for MI Bus.
MDL1, MDL0 — MI Bus delay select
These bits are used to set up the delay for the start of the NRZ receive
for MI Bus operation as shown (for a 20kHz bit rate) in the following
table.
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SCI0/MI Bus registers
Table 16-1. MI Bus Delay
Delay factor Delay time(1)
MDL1
MDL0
0
0
1
0
1
1
1
0
1
2
3
4
1.5625 µs(2)
3.125 µs
4.6875 µs
6.25 µs
1. 20kHz bit rate requires 25µs (40kHz) time slots.
2. 25µs ÷ 16
RAF — Receiver Active Flag
0 = A character is not being received
1 = A character is being received
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Pull field
0
1
0
1
S1
S2
S3
1
Push field
A2
A1
A0
D4
D3
D2
D1
D0
RESET:
—
—
—
—
—
—
—
—
SC0DRL— MI Bus Data Register Low
$00C7
This register forms the 8-bit data/address word for the MI push field
and contains the 3-bit data word received as the MI pull field.
R7T7–R0T0 — Receive/Transmit Data Bits 7 to 0
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI Bus receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI Bus. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
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WRITE: Writes access the eight bits of the write-only MI Bus transmit
data register. MI Bus devices require a 5-bit data pattern followed by
a 3-bit address pattern to be sent during the push field. The data
pattern is mapped to the lowest five bits of the data register and the
address to the highest three bits, as shown in the above table. Thus
MI-data[4:0] is written to SC0DRL[4:0] and MI-address[2:0] is written
to SC0DRL[7:5].
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Section 17. MSCAN Controller
17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
17.3
External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
17.4
Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
17.5
Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .284
17.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
17.7
Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 289
17.8
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
17.9
Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
17.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .298
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . 303
17.2 Introduction
The msCAN12 is the specific implementation of the Motorola scalable
CAN (msCAN) concept targeted for the Motorola M68HC12
microcontroller family.
The module is a communication controller implementing the CAN 2.0 A/B
protocol as defined in the BOSCH specification dated September 1991.
The CAN protocol was primarily, but not only, designed to be used as a
vehicle serial data bus, meeting the specific requirements of this field:
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real-time processing, reliable operation in the EMI environment of a
vehicle, cost-effectiveness and required bandwidth.
msCAN12 utilises an advanced buffer arrangement resulting in a
predictable real-time behaviour and simplifies the application software.
17.3 External Pins
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The msCAN12 uses 2 external pins, 1 input (RxCAN) and 1 output
(TxCAN). The TxCAN output pin represents the logic level on the CAN:
0 is for a dominant state, and 1 is for a recessive state.
RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins
of Port CAN (112TQFP version only) are controlled by registers in the
msCAN12 address space (see msCAN12 Port CAN Control Register
(PCTLCAN) and msCAN12 Port CAN Data Direction Register
(DDRCAN)).
A typical CAN system with msCAN12 is shown in Figure 17-1.
Each CAN station is connected physically to the CAN bus lines through
a transceiver chip. The transceiver is capable of driving the large current
needed for the CAN and has current protection, against defective CAN
or defective stations.
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Message Storage
CAN station 1
CAN station 2
.....
CAN station n
CAN system
msCAN12
Controller
TxCAN RxCAN
Transceiver
CAN
Figure 17-1. The CAN System
17.4 Message Storage
msCAN12 facilitates a sophisticated message storage system which
addresses the requirements of a broad range of network applications.
17.4.1 Background
Modern application layer software is built upon two fundamental
assumptions:
1. Any CAN node is able to send out a stream of scheduled
messages without releasing the bus between two messages.
Such nodes will arbitrate for the bus right after sending the
previous message and will only release the bus when arbitration
is lost.
2. The internal message queue within any CAN node is organized
such that if more than one message is ready to be sent, the
highest priority message will be sent out first.
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The above behaviour cannot be achieved with a single transmit buffer.
That buffer must be reloaded right after the previous message has been
sent. This loading process lasts a definite amount of time and has to be
completed within the inter-frame sequence (IFS) in order to be able to
send an uninterrupted stream of messages. Even if this is feasible for
limited CAN bus speeds it requires that the CPU reacts with short
latencies to the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit
buffers from the actual message sending and as such reduces the
reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the
second buffer, no buffer would then be ready for transmission and the
bus would be released.
At least three transmit buffers are required to meet the first of above
requirements under all circumstances. The msCAN12 has three transmit
buffers.
The second requirement calls for some sort of internal prioritisation
which the msCAN12 implements with the local priority concept
described below.
17.4.2 Receive Structures
The received messages are stored in a two stage input FIFO. The two
message buffers are alternately mapped into a single memory area (see
Figure 17-2). While the background receive buffer (RxBG) is exclusively
associated to the msCAN12, the foreground receive buffer (RxFG) is
addressable by the CPU12. This scheme simplifies the handler software
as only one address area is applicable for the receive process.
Both buffers have a size of 13 bytes to store the CAN control bits, the
identifier (standard or extended) and the data contents (for details see
Programmer’s Model of Message Storage).
The receiver full flag (RXF) in the msCAN12 receiver flag register
(CRFLG) (see msCAN12 Receiver Flag Register (CRFLG)) signals the
status of the foreground receive buffer. When the buffer contains a
correctly received message with matching identifier this flag is set.
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Message Storage
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On reception, each message is checked to see if it passes the filter (for
details see Identifier Acceptance Filter) and in parallel is written into
RxBG. The msCAN12 copies the content of RxBG into RxFG(1), sets the
RXF flag, and generates a receive interrupt to the CPU(2). The user’s
receive handler has to read the received message from RxFG and then
reset the RXF flag in order to acknowledge the interrupt and to release
the foreground buffer. A new message, which can follow immediately
after the IFS field of the CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the identifier filter
function.
1. Only if the RXF flag is not set.
2. The receive interrupt is generated only if not masked. A polling scheme can be applied on RXF
also.
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msCAN12
CPU bus
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RxBG
RxFG
RXF
Tx0
TXE
PRIO
Tx1
TXE
PRIO
Tx2
TXE
PRIO
Figure 17-2. User Model for Message Buffer Organization
When the msCAN12 module is transmitting, the msCAN12 receives its
own messages into the background receive buffer, RxBG, but does NOT
overwrite RxFG, generate a receive interrupt or acknowledge its own
messages on the CAN bus. The exception to this rule is in loop-back
mode (see msCAN12 Module Control Register 1 (CMCR1).) where the
msCAN12 treats its own messages exactly like all other incoming
messages. The msCAN12 receives its own transmitted messages in the
event that it loses arbitration. If arbitration is lost, the msCAN12 must be
prepared to become receiver.
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Message Storage
An overrun condition occurs when both the foreground and the
background receive message buffers are filled with correctly received
messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message is
discarded and an error interrupt with overrun indication is generated if
enabled. The msCAN12 is still able to transmit messages with both
receive message buffers filled, but all incoming messages are
discarded.
17.4.3 Transmit Structures
The msCAN12 has a triple transmit buffer scheme in order to allow
multiple messages to be set up in advance and to achieve an optimized
real-time performance. The three buffers are arranged as shown in
Figure 17-2.
All three buffers have a 13 byte data structure similar to the outline of the
receive buffers (see Programmer’s Model of Message Storage). An
additional transmit buffer priority register (TBPR) contains an 8-bit so
called local priority field (PRIO) (see Transmit Buffer Priority Registers
(TBPR)).
In order to transmit a message, the CPU12 has to identify an available
transmit buffer which is indicated by a set transmit buffer empty (TXE)
flag in the msCAN12 transmitter flag register (CTFLG) (see msCAN12
Transmitter Flag Register (CTFLG)).
The CPU12 then stores the identifier, the control bits and the data
content into one of the transmit buffers. Finally, the buffer has to be
flagged as being ready for transmission by clearing the TXE flag.
The msCAN12 will then schedule the message for transmission and will
signal the successful transmission of the buffer by setting the TXE flag.
A transmit interrupt will be emitted(1) when TXE is set and this can be
used to drive the application software to re-load the buffer.
1. The transmit interrupt is generated only if not masked. A polling scheme can be applied on
TXE also.
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If more than one buffer is scheduled for transmission when the CAN bus
becomes available for arbitration, the msCAN12 uses the local priority
setting of the three buffers for prioritisation. For this purpose every
transmit buffer has an 8-bit local priority field (PRIO). The application
software sets this field when the message is set up. The local priority
reflects the priority of this particular message relative to the set of
messages being emitted from this node. The lowest binary value of the
PRIO field is defined to be the highest priority.
The internal scheduling process takes places whenever the msCAN12
arbitrates for the bus. This is also the case after the occurrence of a
transmission error.
When a high priority message is scheduled by the application software
it may become necessary to abort a lower priority message being set up
in one of the three transmit buffers. As messages that are already under
transmission cannot be aborted, the user has to request the abort by
setting the corresponding abort request flag (ABTRQ) in the
transmission control register (CTCR). The msCAN12 grants the request,
if possible, by setting the corresponding abort request acknowledge
(ABTAK) and the TXE flag in order to release the buffer and by
generating a transmit interrupt. The transmit interrupt handler software
can tell from the setting of the ABTAK flag whether the message was
aborted (ABTAK=1) or sent in the meantime (ABTAK=0).
17.5 Identifier Acceptance Filter
The identifier acceptance registers (CIDAR0–7) define the acceptable
patterns of the standard or extended identifier (ID10–ID0 or ID28–ID0).
Any of these bits can be marked don’t care in the identifier mask
registers (CIDMR0–7).
A filter hit is indicated to the application software by a set RXF (receive
buffer full flag, see msCAN12 Receiver Flag Register (CRFLG)) and
three bits in the identifier acceptance control register (see msCAN12
Identifier Acceptance Control Register (CIDAC)). These identifier hit
flags (IDHIT2–0) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the
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Identifier Acceptance Filter
cause of the receiver interrupt. When more than one hit occurs (two or
more filters match) the lower hit has priority.
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A very flexible programmable generic identifier acceptance filter has
been introduced in order to reduce the CPU interrupt loading. The filter
is programmable to operate in four different modes:
•
Two identifier acceptance filters, each to be applied to a) the full
29 bits of the extended identifier and to the following bits of the
CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard
identifier, the RTR and IDE bits of CAN 2.0A/B messages. This
mode implements two filters for a full length CAN 2.0B compliant
extended identifier. Figure 17-3 shows how the first 32-bit filter
bank (CIDAR0–3, CIDMR0–3) produces a filter 0 hit. Similarly, the
second filter bank (CIDAR4–7, CIDMR4–7) produces a filter 1 hit.
•
Four identifier acceptance filters, each to be applied to a) the 14
most significant bits of the extended identifier plus the SRR and
IDE bits of CAN 2.0B messages or b) the 11 bits of the standard
identifier, the RTR and IDE bits of CAN 2.0A/B mesages. Figure
17-4 shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)
produces filter 0 and 1 hits. Similarly, the second filter bank
(CIDAR4–7, CIDMR4–7) produces filter 2 and 3 hits.
•
Eight identifier acceptance filters, each to be applied to the first 8
bits of the identifier. This mode implements eight independent
filters for the first 8 bits of a CAN 2.0A/B compliant standard
identifier or of a CAN 2.0B compliant extended identifier. Figure
17-5 shows how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3)
produces filter 0 to 3 hits. Similarly, the second filter bank
(CIDAR4–7, CIDMR4–7) produces filter 4 to 7 hits.
•
Closed filter. No CAN message will be copied into the foreground
buffer RxFG, and the RXF flag will never be set.
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ID28 IDR0
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ID10 IDR0
ID21 ID20 IDR1
ID3 ID2
ID15
ID14 IDR2
ID7
ID6
IDR3 RTR
IDR1 IDE
AC7 CIDMRO AC0 AC7 CIDMR1 AC0
AC7 CIDMR2 AC0
AC7 CIDMR3 AC0
AC7 CIDARO AC0 AC7 CIDAR1 AC0
AC7 CIDAR2 AC0
AC7 CIDAR3 AC0
ID accepted (Filter 0 hit)
Figure 17-3. 32-bit Maskable Identifier Acceptance Filters
ID28 IDR0
ID10 IDR0
ID21 ID20 IDR1
ID3 ID2
ID15
ID14 IDR2
ID7
ID6
IDR3 RTR
IDR1 IDE
AC7 CIDMRO AC0 AC7 CIDMR1 AC0
AC7 CIDARO AC0 AC7 CIDAR1 AC0
ID accepted (Filter 0 hit)
AC7 CIDMR2 AC0 AC7 CIDMR3 AC0
AC7 CIDAR2 AC0 AC7 CIDAR3 AC0
ID accepted (Filter 1 hit)
Figure 17-4. 16-bit Maskable Acceptance Filters
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Interrupts
ID28
IDR0
ID21 ID20
ID10
IDR0
ID3 ID2
IDR1
ID15
ID14 IDR2
ID7
ID6
IDR3
RTR
IDR1 IDE
AC7 CIDMRO AC0
AC7 CIDARO AC0
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ID accepted (Filter 0 hit)
AC7 CIDMR1 AC0
AC7 CIDAR1 AC0
ID accepted (Filter 1 hit)
AC7 CIDMR2 AC0
AC7 CIDAR2 AC0
ID accepted (Filter 2 hit)
AC7 CIDMR3 AC0
AC7 CIDAR3 AC0
Figure 17-5. 8-bit Maskable Acceptance Filters
17.6 Interrupts
The msCAN12 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see msCAN12 Receiver Flag Register (CRFLG) to msCAN12
Transmitter Control Register (CTCR)):
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•
Transmit interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
•
Receive interrupt: A message has been successfully received and
loaded into the foreground receive buffer. This interrupt is
generated immediately after receiving the EOF symbol. The RXF
flag is set.
•
Wake-up interrupt: An activity on the CAN bus occurred during
msCAN12 internal SLEEP mode.
•
Error interrupt: An overrun, error or warning condition occurred.
The receiver flag register (CRFLG) indicates one of the following
conditions:
– Overrun: an overrun condition as described in Receive
Structures has occurred.
– Receiver warning: the receive error counter has reached the
CPU warning limit of 96.
– Transmitter warning: the transmit error counter has reached
the CPU warning limit of 96.
– Receiver error passive: the receive error counter has
exceeded the error passive limit of 127 and msCAN12 has
gone to error passive state.
– Transmitter error passive: the transmit error counter has
exceeded the error passive limit of 127 and msCAN12 has
gone to error passive state.
– Bus off: the transmit error counter has exceeded 255 and
msCAN12 has gone to BUSOFF state.
17.6.1 Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either
the msCAN12 receiver flag register (CRFLG) or the msCAN12
transmitter flag register (CTFLG). Interrupts are pending as long as one
of the corresponding flags is set. The flags in above registers must be
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Protocol Violation Protection
reset within the interrupt handler in order to handshake the interrupt. The
flags are reset through writing a 1 to the corresponding bit position. A flag
cannot be cleared if the respective condition still prevails.
NOTE:
Bit manipulation instructions (BSET) shall not be used to clear interrupt
flags.
17.6.2 Interrupt Vectors
The msCAN12 supports four interrupt vectors as shown in Table 17-1.
The vector addresses and the relative interrupt priority are dependent on
the chip integration and to be defined.
Table 17-1. msCAN12 Interrupt Vectors
Function
Wake-Up
Error
Interrupts
Receive
Transmit
Source
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
TXE0
TXE1
TXE2
Local Mask
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
TXEIE0
TXEIE1
TXEIE2
Global Mask
I Bit
17.7 Protocol Violation Protection
The msCAN12 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
•
The receive and transmit error counters cannot be written or
otherwise manipulated.
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•
All registers which control the configuration of the msCAN12
cannot be modified while the msCAN12 is on-line. The SFTRES
bit in CMCR0 (see msCAN12 Module Control Register 0
(CMCR0)) serves as a lock to protect the following registers:
– msCAN12 module control register 1 (CMCR1)
– msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)
– msCAN12 identifier acceptance control register (CIDAC)
– msCAN12 identifier acceptance registers (CIDAR0–7)
– msCAN12 identifier mask registers (CIDMR0–7)
•
The TxCAN pin is forced to recessive when the msCAN12 is in any
of the low power modes.
17.8 Low Power Modes
In addition to normal mode, the msCAN12 has three modes with
reduced power consumption: SLEEP, SOFT_RESET and
POWER_DOWN mode. In SLEEP and SOFT_RESET modes, power
consumption is reduced by stopping all clocks except those to access
the registers. In POWER_DOWN mode, all clocks are stopped and no
power is consumed.
The WAI and STOP instructions put the MCU in low power consumption
stand-by modes. Table 17-2 summarizes the combinations of msCAN12
and CPU modes. A particular combination of modes is entered for the
given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes,
an msCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While
the CPU is in Wait Mode, the msCAN12 can be operated in Normal
Mode and generate interrupts (registers can be accessed via
background debug mode).
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Low Power Modes
Table 17-2. msCAN12 vs. CPU operating modes
msCAN Mode
CPU Mode
WAIT
STOP
(1)
POWER_DOWN
CSWAI = X
SLPAK = X
SFTRES = X
SLEEP
SOFT_RESET
Normal
RUN
CSWAI = 1
SLPAK = X
SFTRES = X
CSWAI = 0
SLPAK = 1
SFTRES = 0
CSWAI = 0
SLPAK = 0
SFTRES = 1
CSWAI = 0
SLPAK = 0
SFTRES = 0
CSWAI = X
SLPAK = 1
SFTRES = 0
CSWAI = X
SLPAK = 0
SFTRES = 1
CSWAI = X
SLPAK = 0
SFTRES = 0
1. X means don’t care.
17.8.1 msCAN12 SLEEP Mode
The CPU can request the msCAN12 to enter this low-power mode by
asserting the SLPRQ bit in the Module Configuration Register (see
Figure 17-6). The time when the msCAN12 enters Sleep Mode depends
on its activity:
NOTE:
•
If there are one or more message buffers scheduled for
transmission (TXEx = 0), the msCAN will continue to transmit until
all transmit message buffers are empty (TXEx = 1, transmitted
successfully or aborted) and then goes into Sleep Mode.
•
If it is receiving, it continues to receive and goes into Sleep Mode
as soon as the CAN bus next becomes idle.
•
If it is neither transmitting nor receiving, it immediately goes into
Sleep Mode.
The application software must avoid setting up a transmission (by
clearing one or more TXE flag(s)) and immediately request Sleep Mode
(by setting SLPRQ). It then depends on the exact sequence of
operations whether the msCAN12 starts transmitting or goes into Sleep
Mode directly.
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During Sleep Mode, the SLPAK flag is set. The application software
should use SLPAK as a handshake indication for the request (SLPRQ)
to go into Sleep Mode. When in Sleep Mode, the msCAN12 stops its
internal clocks. However, clocks to allow register accesses still run. If the
msCAN12 is in bus-off state, it stops counting the 128*11 consecutive
recessive bits due to the stopped clocks. The TxCAN pin stays in
recessive state. If RXF=1, the message can be read and RXF can be
cleared. Copying of RxBG into RxFG doesn’t take place while in sleep
mode. It is possible to access the transmit buffers and to clear the TXE
flags. No message abort takes place while in sleep mode.
The msCAN12 leaves Sleep Mode (wake-up) when
NOTE:
•
bus activity occurs or
•
the MCU clears the SLPRQ bit or
•
the MCU sets SFTRES.
The MCU cannot clear the SLPRQ bit before the msCAN12 is in Sleep
Mode (SLPAK = 1).
After wake-up, the msCAN12 waits for 11 consecutive recessive bits to
synchronize to the bus. As a consequence, if the msCAN12 is woken-up
by a CAN frame, this frame is not received. The receive message buffers
(RxFG and RxBG) contain messages if they were received before sleep
mode was entered. All pending actions are executed upon wake-up:
copying of RxBG into RxFG, message aborts and message
transmissions. If the msCAN12 is still in bus-off state after sleep mode
was left, it continues counting the 128*11 consecutive recessive bits.
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Low Power Modes
msCAN12 Running
SLPRQ = 0
SLPAK = 0
MCU
MCU
or msCAN12
msCAN12 Sleeping
SLEEP Request
SLPRQ = 1
SLPAK = 1
SLPRQ = 1
SLPAK = 0
msCAN12
Figure 17-6. SLEEP Request / Acknowledge Cycle
17.8.2 msCAN12 SOFT_RESET Mode
In SOFT_RESET mode, the msCAN12 is stopped. Registers can still be
accessed. This mode is used to initialize the module configuration, bit
timing, and the CAN message filter. See msCAN12 Module Control
Register 0 (CMCR0) for a complete description of the SOFT_RESET
mode.
When setting the SFTRES bit, the msCAN12 immediately stops all
ongoing transmissions and receptions, potentially causing the CAN
protocol violations.
NOTE:
The user is responsible for ensuring that the msCAN12 is not active
when SOFT_RESET mode is entered. The recommended procedure is
to bring the msCAN12 into SLEEP mode before the SFTRES bit is set.
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17.8.3 msCAN12 POWER_DOWN Mode
The msCAN12 is in POWER_DOWN mode when
•
the CPU is in STOP mode or
•
the CPU is in WAIT mode and the CSWAI bit is set (see msCAN12
Module Control Register 0 (CMCR0)).
When entering the POWER_DOWN mode, the msCAN12 immediately
stops all ongoing transmissions and receptions, potentially causing CAN
protocol violations.
NOTE:
The user is responsible for ensuring that the msCAN12 is not active
when POWER_DOWN mode is entered. The recommended procedure
is to bring the msCAN12 into SLEEP mode before the STOP instruction
(or the WAI instruction, if CSWAI is set) is executed.
To protect the CAN bus system from fatal consequences of violations to
the above rule, the msCAN12 drives the TxCAN pin into recessive state.
In POWER_DOWN mode no registers can be accessed.
17.8.4 Programmable Wake-Up Function
The msCAN12 can be programmed to apply a low-pass filter function to
the RxCAN input line while in SLEEP mode (see control bit WUPM in the
module control register, msCAN12 Module Control Register 1
(CMCR1).). This feature can be used to protect the msCAN12 from
wake-up due to short glitches on the CAN bus lines. Such glitches can
result from electromagnetic interference within noisy environments.
17.9 Timer Link
The msCAN12 generates a timer signal whenever a valid frame has
been received. Because the CAN specification defines a frame to be
valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal is generated right after the EOF. A pulse of
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Clock System
one bit time is generated. As the msCAN12 receiver engine also
receives the frames being sent by itself, a timer signal is also generated
after a successful transmission.
The previously described timer signal can be routed into the on-chip
timer interface module (ECT). This signal is connected to the Timer n
Channel m input(1) under the control of the timer link enable (TLNKEN)
bit in the CMCR0.
After timer n has been programmed to capture rising edge events, it can
be used under software control to generate 16-bit time stamps which can
be stored with the received message.
17.10 Clock System
Figure 17-7 shows the structure of the msCAN12 clock generation
circuitry. With this flexible clocking scheme the msCAN12 is able to
handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
CGM
msCAN12
SYSCLK
CGMCANCLK
CLKSRC
EXTALi
Prescaler
(1...64)
Time quanta
clock
CLKSRC
Figure 17-7. Clocking Scheme
The clock source bit (CLKSRC) in the msCAN12 module control register
(CMCR1) (see msCAN12 Bus Timing Register 0 (CBTR0)) defines
whether the msCAN12 is connected to the output of the crystal oscillator
(EXTALi) or to a clock twice as fast as the system clock (ECLK).
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met. Additionally, for
high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.
1. The timer channel being used for the timer link is integration dependent.
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NOTE:
If the system clock is generated from a PLL, it is recommended to select
the crystal clock source rather than the system clock source due to jitter
considerations, especially at faster CAN bus rates.
For microcontrollers without the CGM module, CGMCANCLK is driven
from the crystal oscillator (EXTALi).
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A programmable prescaler is used to generate out of msCANCLK the
time quanta (Tq) clock. A time quantum is the atomic unit of time handled
by the msCAN12.
A bit time is subdivided
f CGMCANCLK
f Tq = ------------------------------------------Presc ⋅ value
into three segments(1):
•
SYNC_SEG: This segment has a fixed length of one time
quantum. Signal edges are expected to happen within this section.
•
Time segment 1: This segment includes the PROP_SEG and the
PHASE_SEG1 of the CAN standard. It can be programmed by
setting the parameter TSEG1 to consist of 4 to 16 time quanta.
•
Time segment 2: This segment represents the PHASE_SEG2 of
the CAN standard. It can be programmed by setting the TSEG2
parameter to be 2 to 8 time quanta long.
f Tq
BitRate = -----------------------------------------------------------------------number ⋅ of ⋅ TimeQuanta
The synchronisation jump width can be programmed in a range of 1 to 4
time quanta by setting the SJW parameter.
Above parameters can be set by programming the bus timing registers
(CBTR0–1, see msCAN12 Bus Timing Register 0 (CBTR0) and
msCAN12 Bus Timing Register 1 (CBTR1).).
NOTE:
It is the user’s responsibility to make sure that his bit time settings are in
compliance with the CAN standard. Table 17-3 gives an overview on the
CAN conforming segment settings and the related parameter values.
1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section
10.3.
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Clock System
NRZ Signal
SYNC
_SEG
Time segment 1
(PROP_SEG + PHASE_SEG1)
Time Seg. 2
(PHASE_SEG2)
1
4 ... 16
2 ... 8
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8... 25 Time Quanta
= 1 Bit Time
Transmit point
Sample point
(single or triple sampling)
Figure 17-8. Segments within the Bit Time
Table 17-3. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1
TSEG1
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
4 .. 9
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
Time Segment 2 TSEG2
2
3
4
5
6
7
8
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1
2
3
4
5
6
7
Synchron.
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
SJW
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
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17.11 Memory Map
The msCAN12 occupies 128 bytes in the CPU12 memory space. The
background receive buffer can only be read in test mode.
Figure 17-9. msCAN12 Memory Map
$0100
$0108
$0109
$010D
$010E
$010F
$0110
$011F
$0120
$013C
$013D
$013F
$0140
$014F
$0150
$015F
$0160
$016F
$0170
$017F
Control registers
9 bytes
Reserved
5 bytes
Error counters
2 bytes
Identifier filter
16 bytes
Reserved
29 bytes
Port CAN registers
3 bytes
Receive buffer
Transmit buffer 0
Transmit buffer 1
Transmit buffer 2
17.12 Programmer’s Model of Message Storage
The following section details the organisation of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional
transmit buffer priority register (TBPR) is defined for the transmit buffers.
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Programmer’s Model of Message Storage
Figure 17-10. Message Buffer Organization
Address(1)
01x0
01x1
01x2
01x3
01x4
01x5
01x6
01x7
01x8
01x9
01xA
01xB
01xC
01xD
01xE
01xF
Register name
Identifier register 0
Identifier register 1
Identifier register 2
Identifier register 3
Data segment register 0
Data segment register 1
Data segment register 2
Data segment register 3
Data segment register 4
Data segment register 5
Data segment register 6
Data segment register 7
Data length register
Transmit buffer priority register(2)
Unused
Unused
1. x is 4, 5, 6, or 7 depending on which buffer RxFG,
Tx0, Tx1, or Tx2 respectively.
2. Not applicable for receive buffers
17.12.1 Message Buffer Outline
Figure 17-11 shows the common 13 byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 17-12. All bits of the
13 byte data structure are undefined out of reset.
NOTE:
The foreground receive buffer can be read anytime but cannot be
written.
The transmit buffers can be read or written anytime.
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Figure 17-11. Receive/Transmit Message Buffer Extended Identifier
ADDR(1)
REGISTER
$01x0
IDR0
R/W
BIT 7
6
5
4
3
2
1
BIT 0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
ID19
ID18
SRR
(1)
IDE (1)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
R
W
R
$01x1
IDR1
W
R
$01x2
IDR2
W
R
$01x3
IDR3
W
R
$01x4
DSR0
W
R
$01x5
DSR1
W
R
$01x6
DSR2
W
R
$01x7
DSR3
W
R
$01x8
DSR4
W
R
$01x9
DSR5
W
R
$01xA
DSR6
W
R
$01xB
DSR7
W
R
$01xC
DLR
W
1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.
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Programmer’s Model of Message Storage
Figure 17-12. Standard Identifier Mapping
ADDR(1)
REGISTER
$01x0
IDR0
R/W
BIT 7
6
5
4
3
2
1
BIT 0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
IDE(0)
R
W
R
$01x1
IDR1
W
R
$01x2
IDR2
W
R
$01x3
IDR3
W
1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.
17.12.2 Identifier Registers (IDRn)
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29
bits (ID28–ID0) for the extended format. ID10/28 is the most significant
bit and is transmitted first on the bus during the arbitration procedure.
The priority of an identifier is defined to be highest for the smallest binary
number.
SRR — Substitute Remote Request
This fixed recessive bit is used only in extended format. It must be set
to 1 by the user for transmission buffers and will be stored as received
on the CAN bus for receive buffers.
IDE — ID Extended
This flag indicates whether the extended or standard identifier format
is applied in this buffer. In the case of a receive buffer the flag is set
as being received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer the flag indicates to
the msCAN12 what type of identifier to send.
0 = Standard format (11-bit)
1 = Extended format (29-bit)
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RTR — Remote transmission request
This flag reflects the status of the Remote Transmission Request bit
in the CAN frame. In the case of a receive buffer it indicates the status
of the received frame and supports the transmission of an answering
frame in software. In the case of a transmit buffer this flag defines the
setting of the RTR bit to be sent.
0 = Data frame
1 = Remote frame
17.12.3 Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
DLC3 – DLC0 — Data length code bits
The data length code contains the number of bytes (data byte count)
of the respective message. At the transmission of a remote frame, the
data length code is transmitted as programmed while the number of
transmitted data bytes is always 0. The data byte count ranges from
0 to 8 for a data frame. Table 17-4 shows the effect of setting the DLC
bits.
Table 17-4. Data length codes
Data length code
DLC3
DLC2
DLC1
DLC0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
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Data
byte
count
0
1
2
3
4
5
6
7
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Programmer’s Model of Control Registers
17.12.4 Data Segment Registers (DSRn)
The eight data segment registers contain the data to be transmitted or
being received. The number of bytes to be transmitted or being received
is determined by the data length code in the corresponding DLR.
17.12.5 Transmit Buffer Priority Registers (TBPR)
TBPR(1)
R
$01xD
W
RESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
–
–
–
–
–
–
–
–
1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.
PRIO7 – PRIO0 — Local Priority
This field defines the local priority of the associated message buffer.
The local priority is used for the internal prioritisation process of the
msCAN12 and is defined to be highest for the smallest binary number.
The msCAN12 implements the following internal prioritisation
mechanism:
•
All transmission buffers with a cleared TXE flag participate in the
prioritisation immediately before the SOF (Start of Frame) is sent.
•
The transmission buffer with the lowest local priority field wins the
prioritisation.
•
In cases of more than one buffer having the same lowest priority,
the message buffer with the lower index number wins.
17.13 Programmer’s Model of Control Registers
17.13.1 Overview
The programmer’s model has been laid out for maximum simplicity and
efficiency.
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17.13.2 msCAN12 Module Control Register 0 (CMCR0)
CMCR0
R
Bit 7
6
0
0
5
4
SYNCH
CSWAI
$0100
RESET
3
2
1
Bit 0
SLPRQ
SFTRES
0
1
SLPAK
TLNKEN
W
0
0
1
0
0
0
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CSWAI — CAN Stops in Wait Mode
0 = The module is not affected during WAIT mode.
1 = The module ceases to be clocked during WAIT mode.
SYNCH — Synchronized Status
This bit indicates whether the msCAN12 is synchronized to the CAN
bus and as such can participate in the communication process.
0 = msCAN12 is not synchronized to the CAN bus
1 = msCAN12 is synchronized to the CAN bus
TLNKEN — Timer Enable
This flag is used to establish a link between the msCAN12 and the onchip timer (see Timer Link).
0 = The port is connected to the timer input.
1 = The msCAN12 timer signal output is connected to the timer
input.
SLPAK — SLEEP Mode Acknowledge
This flag indicates whether the msCAN12 is in module internal
SLEEP Mode. It shall be used as a handshake for the SLEEP Mode
request (see msCAN12 SLEEP Mode).
0 = Wake-up – The msCAN12 is not in SLEEP Mode.
1 = SLEEP – The msCAN12 is in SLEEP Mode.
SLPRQ — SLEEP request
This flag allows to request the msCAN12 to go into an internal powersaving mode (see msCAN12 SLEEP Mode).
0 = Wake-up – The msCAN12 will function normally.
1 = SLEEP request – The msCAN12 will go into SLEEP Mode
when the CAN bus is idle, i.e. the module is not receiving a
message and all transmit buffers are empty.
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Programmer’s Model of Control Registers
SFTRES— SOFT_RESET
When this bit is set by the CPU, the msCAN12 immediately enters the
SOFT_RESET state. Any ongoing transmission or reception is
aborted and synchronisation to the bus is lost.
The following registers will go into and stay in the same state as out
of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3,
CIDMR0–3 can only be written by the CPU when the msCAN12 is in
SOFT_RESET state. The values of the error counters are not affected
by SOFT_RESET.
When this bit is cleared by the CPU, the msCAN12 will try to
synchronize to the CAN bus: If the msCAN12 is not in BUSOFF state
it will be synchronized after 11 recessive bits on the bus; if the
msCAN12 is in BUSOFF state it continues to wait for 128 occurrences
of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in
separate instructions.
0 = Normal operation
1 = msCAN12 in SOFT_RESET state.
17.13.3 msCAN12 Module Control Register 1 (CMCR1).
CMCR1
R
$0101
W
RESET
Bit 7
6
5
4
3
0
0
0
0
0
0
0
0
0
2
1
Bit 0
LOOPB
WUPM
CLKSRC
0
0
0
0
LOOPB — Loop Back Self Test Mode
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it does normally when transmitting and treats
its own transmitted message as a message received from a remote
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node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
0 = Normal operation
1 = Activate loop back self test mode
WUPM — Wake-Up Mode
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This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see Programmable
Wake-Up Function).
0 = msCAN12 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in the case of dominant
pulse on the bus which has a length of at least approximately
Twup.
CLKSRC — msCAN12 Clock Source
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see Clock System, Figure
17-7).
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
ECLK.
NOTE:
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
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Programmer’s Model of Control Registers
17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
CBTR0
R
$0102
W
RESET
Bit 7
6
5
4
3
2
1
Bit 0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0
0
0
0
0
0
0
0
SJW1, SJW0 — Synchronization Jump Width
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The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 17-5).
Table 17-5. Synchronization jump width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization jump width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
BRP5 – BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to Table 17-6.
Table 17-6. Baud rate prescaler
NOTE:
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0
0
0
0
:
:
1
0
0
0
0
:
:
1
0
0
0
0
:
:
1
0
0
0
0
:
:
1
0
0
1
1
:
:
1
0
1
0
1
:
:
1
The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
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Prescaler value
(P)
1
2
3
4
:
:
64
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17.13.5 msCAN12 Bus Timing Register 1 (CBTR1).
CBTR1
R
$0103
W
Bit 7
6
5
4
3
2
1
Bit 0
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
0
0
0
0
0
0
0
0
RESET
SAMP — Sampling
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This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
0 = One sample per bit.
1 = Three samples per bit.(1)
TSEG22 – TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point. (See Figure 17-8)
Table 17-7. Time segment syntax
SYNC_SEG
Transmit point
Sample point
System expects transitions to occur on the
bus during this period.
A node in transmit mode will transfer a new
value to the CAN bus at this point.
A node in receive mode will sample the bus
at this point. If the three samples per bit
option is selected then this point marks the
position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in Table 17-8.
1. In this case, PHASE_SEG1 must be at least two time quanta.
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Programmer’s Model of Control Registers
Table 17-8. Time segment values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
0
0
0
0
1 Tq clock cycle
0
0
0
1
2 Tq clock cycles
0
0
1
0
3 Tq clock cycles
0
0
1
1
4 Tq clock cycles
.
.
.
.
.
.
.
.
.
.
1
1
1
1
16 Tq clock cycles
TSEG22 TSEG21 TSEG20
0
0
0
0
0
1
.
.
.
.
.
.
1
1
1
Time segment 2
1 Tq clock cycle
2 Tq clock cycles
.
.
8 Tq clock cycles
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit (as
shown above).
Presc ⋅ value
BitTime = ------------------------------------------- • number Þ of Þ TimeQuanta
f CGMCANCLK
NOTE:
The CBTR1 register can only be written if the SFTRES bit in CMCR0 is set
17.13.6 msCAN12 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset clears the register.
CRFLG
R
$0104
W
RESET
Bit 7
6
5
4
3
2
1
Bit 0
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
0
0
0
0
0
0
0
0
WUPIF — Wake-up Interrupt Flag
If the msCAN12 detects bus activity while in SLEEP Mode, it sets the
WUPIF flag. If not masked, a Wake-Up interrupt is pending while this
flag is set.
0 = No wake-up activity has been observed while in SLEEP Mode.
1 = msCAN12 has detected activity on the bus and requested
wake-up.
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RWRNIF — Receiver Warning Interrupt Flag
This flag is set when the msCAN12 goes into warning status due to
the Receive Error counter (REC) exceeding 96 and neither one of the
Error interrupt flags or the Bus-Off interrupt flag is set(1). If not
masked, an Error interrupt is pending while this flag is set.
0 = No receiver warning status has been reached.
1 = msCAN12 went into receiver warning status.
TWRNIF — Transmitter Warning Interrupt Flag
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This bit will be set when the msCAN12 goes into warning status due
to the Transmit Error counter (TEC) exceeding 96 and neither one of
the Error interrupt flags or the Bus-Off interrupt flag is set(2). If not
masked, an Error interrupt is pending while this flag is set.
0 = No transmitter warning status has been reached.
1 = msCAN12 went into transmitter warning status.
RERRIF — Receiver Error Passive Interrupt Flag
This flag is set when the msCAN12 goes into error passive status due
to the Receive Error counter (REC) exceeding 127 and the Bus-Off
interrupt flag is not set(3). If not masked, an Error interrupt is pending
while this flag is set.
0 = No receiver error passive status has been reached.
1 = msCAN12 went into receiver error passive status.
TERRIF — Transmitter Error Passive Interrupt Flag
This flag is set when the msCAN12 goes into error passive status due
to the Transmit Error counter (TEC) exceeding 127 and the Bus-Off
interrupt flag is not set(4). If not masked, an Error interrupt is pending
while this flag is set.
0 = No transmitter error passive status has been reached.
1 = msCAN12 went into transmitter error passive status.
1. Condition to set the flag: RWRNIF = (96 ≤ REC ≤ 127) & RERRIF & TERRIF & BOFFIF
2. Condition to set the flag: TWRNIF = (96 ≤ TEC ≤ 127) & RERRIF & TERRIF & BOFFIF
3. Condition to set the flag: RERRIF = (128 ≤ REC ≤ 255) & BOFFIF
4. Condition to set the flag: TERRIF = (128 ≤ TEC ≤ 255) & BOFFIF
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Programmer’s Model of Control Registers
BOFFIF — BUSOFF Interrupt Flag
This flag is set when the msCAN12 goes into BUSOFF status, due to
the Transmit Error counter exceeding 255. It cannot be cleared before
the msCAN12 has monitored 128 times 11 consecutive recessive bits
on the bus. If not masked, an Error interrupt is pending while this flag
is set.
0 = No BUSOFF status has been reached.
1 = msCAN12 went into BUSOFF status.
OVRIF — Overrun Interrupt Flag
This flag is set when a data overrun condition occurrs. If not masked,
an Error interrupt is pending while this flag is set.
0 = No data overrun has occurred.
1 = A data overrun has been detected.
RXF — Receive Buffer Full
The RXF flag is set by the msCAN12 when a new message is
available in the foreground receive buffer. This flag indicates whether
the buffer is loaded with a correctly received message. After the CPU
has read that message from the receive buffer, the RXF flag must be
handshaken (cleared) in order to release the buffer. A set RXF flag
prohibits the exchange of the background receive buffer into the
foreground buffer. If not masked, a Receive interrupt is pending while
this flag is set.
0 = The receive buffer is released (not full).
1 = The receive buffer is full. A new message is available.
WARNING:
NOTE:
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
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17.13.7 msCAN12 Receiver Interrupt Enable Register (CRIER)
CRIER
R
$0105
W
RESET
Bit 7
6
5
4
3
2
1
Bit 0
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
0
0
0
0
0
0
0
0
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WUPIE — Wake-up Interrupt Enable
0 = No interrupt is generated from this event.
1 = A wake-up event results in a wake-up interrupt.
RWRNIE — Receiver Warning Interrupt Enable
0 = No interrupt is generated from this event.
1 = A receiver warning status event results in an error interrupt.
TWRNIE — Transmitter Warning Interrupt Enable
0 = No interrupt is generated from this event.
1 = A transmitter warning status event results in an error interrupt.
RERRIE — Receiver Error Passive Interrupt Enable
0 = No interrupt is generated from this event.
1 = A receiver error passive status event results in an error
interrupt.
TERRIE — Transmitter Error Passive Interrupt Enable
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event results in an error
interrupt.
BOFFIE — BUSOFF Interrupt Enable
0 = No interrupt is generated from this event.
1 = A BUSOFF event results in an error interrupt.
OVRIE — Overrun Interrupt Enable
0 = No interrupt is generated from this event.
1 = An overrun event results in an error interrupt.
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Programmer’s Model of Control Registers
RXFIE — Receiver Full Interrupt Enable
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event
results in a receive interrupt.
NOTE:
The CRIER register is held in the reset state when the SFTRES bit in CMCR0
is set.
17.13.8 msCAN12 Transmitter Flag Register (CTFLG)
The Abort Acknowledge flags are read only. The Transmitter Buffer Empty
flags are read and clear only. A flag can be cleared by writing a 1 to the
corresponding bit position. Writing a zero has no effect on the flag setting.
The Transmitter Buffer Empty flags each have an associated interrupt
enable bit in the CTCR register. A hard or soft reset resets the register.
CTFLG
R
$0106
W
RESET
Bit 7
6
5
4
3
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
0
2
1
Bit 0
TXE2
TXE1
TXE0
1
1
1
0
ABTAK2 – ABTAK0 — Abort Acknowledge
This flag acknowledges that a message has been aborted due to a
pending abort request from the CPU. After a particular message
buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been
aborted successfully or has been sent in the meantime. The ABTAKx
flag is cleared implicitly whenever the corresponding TXE flag is
cleared.
0 = The massage has not been aborted, thus has been sent out.
1 = The message has been aborted.
TXE2 – TXE0 —Transmitter Buffer Empty
This flag indicates that the associated transmit message buffer is empty,
thus not scheduled for transmission. The CPU must handshake (clear)
the flag after a message has been set up in the transmit buffer and is due
for transmission. The msCAN12 sets the flag after the message has been
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sent successfully. The flag is also set by the msCAN12 when the
transmission request was successfully aborted due to a pending abort
request (msCAN12 Transmitter Control Register (CTCR)). If not masked,
a transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag (see
above). When a TXEx flag is set, the corresponding ABTRQx bit is
cleared (see msCAN12 Transmitter Control Register (CTCR)).
0 = The associated message buffer is full (loaded with a message
due for transmission).
1 = The associated message buffer is empty (not scheduled).
WARNING:
To ensure data integrity, no registers of the transmit buffers should be written
to while the associated TXE flag is cleared.
NOTE:
The CTFLG register is held in the reset state if the SFTRES bit CMCR0 is set.
17.13.9 msCAN12 Transmitter Control Register (CTCR)
Bit 7
CTCR
$0107
R
6
5
4
ABTRQ2
ABTRQ1
ABTRQ0
0
0
0
3
2
1
Bit 0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
0
W
RESET
0
0
ABTRQ2 – ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that a scheduled message
buffer (TXEx = 0) shall be aborted. The msCAN12 grants the request
if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a
message is aborted the associated TXE and the Abort Acknowledge
flag (ABTAK, see msCAN12 Transmitter Flag Register (CTFLG)) are
set and an TXE interrupt is generated if enabled. The CPU cannot
reset ABTRQx. ABTRQx is cleared implicitly whenever the
associated TXE flag is set.
0 = No abort request.
1 = Abort request pending.
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Programmer’s Model of Control Registers
NOTE:
The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
NOTE:
The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
CIDAC
$0108
R
Bit 7
6
0
0
5
4
IDAM1
IDAM0
0
0
3
2
1
Bit 0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
W
RESET
0
0
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see Identifier Acceptance Filter). Table 17-8
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
Table 17-9. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Four 16 bit Acceptance Filters
Eight 8 bit Acceptance Filters
Filter Closed
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IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator
The msCAN12 sets these flags to indicate an identifier acceptance hit
(see Identifier Acceptance Filter). Table 17-8 summarizes the
different settings.
Table 17-10I. dentifier Acceptance Hit Indication
IDHIT2
0
0
0
0
1
1
1
1
IDHIT1
0
0
1
1
0
0
1
1
IDHIT0
0
1
0
1
0
1
0
1
Identifier Acceptance Hit
Filter 0 Hit
Filter 1 Hit
Filter 2 Hit
Filter 3 Hit
Filter 4 Hit
Filter 5 Hit
Filter 6 Hit
Filter 7 Hit
The IDHIT indicators are always related to the message in the
foreground buffer. When a message gets copied from the background to
the foreground buffer the indicators are updated as well.
NOTE:
The CIDAC register can only be written if the SFTRES bit in CMCR0 is
set.
17.13.11 msCAN12 Receive Error Counter (CRXERR)
CRXERR
R
$010E
W
Bit 7
6
5
4
3
2
1
Bit 0
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
0
0
0
0
0
0
0
0
RESET
This register reflects the status of the msCAN12 receive error counter.
The register is read only.
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Programmer’s Model of Control Registers
17.13.12 msCAN12 Transmit Error Counter (CTXERR)
CTXERR
R
$010F
W
RESET
Bit 7
6
5
4
3
2
1
Bit 0
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
This register reflects the status of the msCAN12 transmit error counter.
The register is read only.
NOTE:
Both error counters must only be read when in SLEEP or SOFT_RESET
mode.
17.13.13 msCAN12 Identifier Acceptance Registers (CIDAR0–7)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message is overwritten by the next
message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied.
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CIDAR0
R
$0110
W
CIDAR1
R
$0111
W
CIDAR2
R
$0112
W
CIDAR3
R
$0113
W
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
–
–
–
–
–
–
–
–
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
–
–
–
–
–
–
–
–
RESET
CIDAR4
R
$0118
W
CIDAR5
R
$0119
W
CIDAR6
R
$011A
W
CIDAR7
R
$011B
W
RESET
AC7 – AC0 — Acceptance Code Bits
AC7 – AC0 comprise a user defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the
receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
NOTE:
The CIDAR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
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Programmer’s Model of Control Registers
17.13.14 msCAN12 Identifier Mask Registers (CIDMR0–7)
The identifier mask register specifies which of the corresponding bits in
the identifier acceptance register are relevant for acceptance filtering. To
receive standard identifiers in 32 bit filter mode it is required to program
the last three bits (AM2–AM0) in the mask registers CIDMR1 and
CIDMR5 to ‘don’t care’. To receive standard identifiers in 16 bit filter
mode it is required to program the last three bits (AM2–AM0) in the mask
registers CIDMR1, CIDMR3, CIDMR5 and CIDMR7 to ‘don’t care’.
CIDMR0
R
$0114
W
CIDMR1
R
$0115
W
CIDMR2
R
$0116
W
CIDMR3
R
$0117
W
RESET
CIDMR4
R
$011C
W
CIDMR5
R
$011D
W
CIDMR6
R
$011E
W
CIDMR7
R
$011F
W
RESET
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
–
–
–
–
–
–
–
–
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
–
–
–
–
–
–
–
–
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AM7 – AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the same
as its identifier bit, before a match is detected. The messageis accepted
if all such bits match. If a bit is set, it indicates that the state of the
corresponding bit in the identifier acceptance register does not affect
whether or not the message is accepted.
Bit description:
0 = Match corresponding acceptance code register and identifier
bits.
1 = Ignore corresponding acceptance code register bit.
NOTE:
The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
17.13.15 msCAN12 Port CAN Control Register (PCTLCAN)
PCTLCAN
R
$013D
W
RESET
Bit 7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit 0
PUPCAN
RDPCAN
0
0
The following bits control pins 7 through 2 of Port CAN. Pins 1 and 0 are
reserved for the RxCan (input only) and TxCan (output only) pins.
PUPCAN — Pull-Up Enable Port CAN
0 = Pull mode disabled for Port CAN.
1 = Pull mode enabled for Port CAN.
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
RDPCAN — Reduced Drive Port CAN
0 = Reduced drive disabled for Port CAN.
1 = Reduced drive enabled for Port CAN.
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MSCAN Controller
17.13.16 msCAN12 Port CAN Data Register (PORTCAN)
Bit 7
6
5
4
3
2
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
0
0
0
0
0
0
PORTCAN R
$013E
1
Bit 0
TxCAN
RxCAN
0
0
W
RESET
PCAN7 – PCAN2 — Port CAN Data Bits (not available in 80QFP)
Writing to PCANx stores the bit value in an internal bit memory. This
value is driven to the respective pin only if DDCANx = 1.
Reading PCANx returns
•
the value of the internal bit memory driven to the pin, if DDCANx = 1
•
the value of the respective pin, if DDCANx = 0
Reading bits 1 and 0 returns the value of the TxCAN and RxCAN pins,
respectively.
17.13.17 msCAN12 Port CAN Data Direction Register (DDRCAN)
DDRCAN register determines the primary direction for the Port CAN pins
which are available as general purpose I/O. The value in the DDRCAN
also affects the source of data for reads of the corresponding Port CAN
register. When the DDCANx = 0 (input), the pin is read. When the
DDCANx =1 (output), the internal bit memory is read.
DDRCAN
$013F
RESET
Bit 7
6
5
4
3
2
DDCAN7
DDCAN6
DDCAN5
DDCAN4
DDCAN3
DDCAN2
0
0
0
0
0
0
R
1
Bit 0
0
0
0
0
W
DDCAN7 – DDCAN2 — Data Direction Port CAN Bits
0 = Respective I/O pin is configured for input.
1 = Respective I/O pin is configured for output.
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68HC(9)12D60 — Rev 4.0
MSCAN Controller
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MSCAN Controller
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MSCAN Controller
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Advance Information — 68HC(9)12D60
Section 18. Analog-to-Digital Converter
18.1 Contents
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
18.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
18.4
ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.5
ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
18.2 Introduction
The 112TQFP version of the 68HC(9)12D60 has two identical ATD
modules identified as ATD0 and ATD1. Except for the VDDA and VSSA
Analog supply voltage, all pins are duplicated and indexed with ‘0’ or ‘1’
in the following description. An ‘x’ indicates either ‘0’ or ‘1’.
The 80QFP version has only one ATD available, ATD0. ATD1 is not
bonded out. As this module defaults to disabled on reset and it's I/O are
inputs by default it requires no configuration.
The ATD module is an 8-channel, 10-bit or 8-bit, multiplexed-input
successive-approximation analog-to-digital converter. It does not
require external sample and hold circuits because of the type of charge
redistribution technique used. The ATD converter timing can be
synchronized to the system P clock. The ATD module consists of a 16word (32-byte) memory-mapped control register block used for control,
testing and configuration.
68HC(9)12D60 — Rev 4.0
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Analog-to-Digital Converter
VRHx
RC DAC ARRAY
AND COMPARATOR
VRLx
REFERENCE
VDDA
SUPPLY
VSSA
MODE AND TIMING CONTROLS
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SAR
ATD 0
ANALOG MUX
AND
SAMPLE BUFFER AMP
ATD 1
ATD 2
ATD 3
ATD 4
ANx7/PADx7
ANx6/PADx6
ANx5/PADx5
ANx4/PADx4
ANx3/PADx3
ANx2/PADx2
ANx1/PADx1
ANx0/PADx0
PORT AD
DATA INPUT REGISTER
ATD 5
ATD 6
ATD 7
CLOCK
SELECT/PRESCALE
INTERNAL BUS
Figure 18-1. Analog-to-Digital Converter Block Diagram
18.3 Functional Description
A single conversion sequence consists of four or eight conversions,
depending on the state of the select 8 channel mode (S8CM) bit when
ATDxCTL5 is written. There are eight basic conversion modes. In the
non-scan modes, the SCF bit is set after the sequence of four or eight
conversions has been performed and the ATD module halts. In the scan
modes, the SCF bit is set after the first sequence of four or eight
conversions has been performed, and the ATD module continues to
restart the sequence. In both modes, the CCF bit associated with each
register is set when that register is loaded with the appropriate
conversion result. That flag is cleared automatically when that result
register is read. The conversions are started by writing to the control
registers.
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Analog-to-Digital Converter
ATD Registers
18.4 ATD Registers
Control and data registers for the ATD modules are described below.
Both ATDs have identical control registers mapped in two blocks of 16
bytes.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
ATD0CTL0/ATD1CTL0 — Reserved
$0060/$01E0
Writes to this register will abort current conversion sequence.
READ: any time WRITE: any time.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
ATD0CTL1/ATD1CTL1 — Reserved
$0061/$01E1
WRITE: Write to this register has no meaning
READ: Special Mode only
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
AFFC
AWAI
0
0
0
ASCIE
ASCIF
0
0
0
0
0
0
0
0
ATD0CTL2/ATD1CTL2 — ATD Control Register 2
$0062/$01E2
Freescale Semiconductor, Inc...
The ATD control register 2 and 3 are used to select the power up mode,
interrupt control, and freeze control. Writes to these registers abort any
current conversion sequence.
Read or write anytime except ASCIF bit, which cannot be written.
Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always
read as zeros.
ADPU — ATD Disable
0 = Disables the ATD, including the analog section for reduction in
power consumption.
1 = Allows the ATD to function normally.
Software can disable the clock signal to the A/D converter and power
down the analog circuits to reduce power consumption. When reset
to zero, the ADPU bit aborts any conversion sequence in progress.
Because the bias currents to the analog circuits are turned off, the
ATD requires a period of recovery time to stabilize the analog circuits
after setting the ADPU bit.
AFFC — ATD Fast Flag Clear All
0 = ATD flag clearing operates normally (read the status register
before reading the result register to clear the associated CCF
bit).
1 = Changes all ATD conversion complete flags to a fast clear
sequence. Any access to a result register (ATD0–7) will cause
the associated CCF flag to clear automatically if it was set at
the time.
AWAI — ATD Wait Mode
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
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Analog-to-Digital Converter
ATD Registers
When the AWAI bit is set and the module enters wait mode, most of
the clocks stop and the analog portion powers down. When the
module comes out of wait, it is recommended that a stabilisation delay
(stop and ATD power up recovery time, tSR) is allowed before new
conversions are started. Additionally, the ATD does not re-initialise
automatically on leaving wait mode.
ASCIE — ATD Sequence Complete Interrupt Enable
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
ASCIF — ATD Sequence Complete Interrupt Flag
Cannot be written in any mode.
0 = No ATD interrupt occurred
1 = ATD sequence complete
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
FRZ1
FRZ0
0
0
0
0
0
0
0
0
ATD0CTL3/ATD1CTL3 — ATD Control Register 3
$0063/$01E3
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module
operation at breakpoint)
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint is encountered. These two bits
determine how the ATD will respond when background debug mode
becomes active.
Table 18-1. ATD Response to Background Debug Enable
FRZ1 FRZ0
0
0
0
1
1
0
1
1
ATD Response
Continue conversions in active background mode
Reserved
Finish current conversion, then freeze
Freeze when BDM is active
68HC(9)12D60 — Rev 4.0
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
S10BM
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
0
0
0
0
0
0
0
1
ATD0CTL4/ATD1CTL4 — ATD Control Register 4
$0064/$01E4
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The ATD control register 4 is used to select the clock source and set up
the prescaler. Writes to the ATD control registers initiate a new
conversion sequence. If a write occurs while a conversion is in progress,
the conversion is aborted and ATD activity halts until a write to
ATDxCTL5 occurs.
S10BM — 10 bit Mode
0 = 8 bit operation
1 = 10 bit operation
SMP1, SMP0 — Select Sample Time
Used to select one of four sample times after the buffered sample and
transfer has occurred.
Table 18-2. Final Sample Time Selection
SMP1
0
0
1
1
SMP0
0
1
0
1
Final Sample Time
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
16 A/D clock periods
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ATD Registers
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD
P-Clock Prescaler.
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The binary value written to these bits (1 to 31) selects the divide-by
factor for the modulo counter-based prescaler. The P clock is divided
by this value plus one and then fed into a ÷2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the
output clock signal. Clearing these bits causes the prescale value
default to one which results in a ÷2 prescale factor. This signal is then
fed into the ÷2 logic. The reset state divides the P clock by a total of
four and is appropriate for nominal operation at 2 MHz. Table 18-3
shows the divide-by operation and the appropriate range of system
clock frequencies.
Table 18-3. Clock Prescaler Values
Prescale
Value
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
Total Divisor
Max P Clock(1)
Min P Clock(2)
÷2
÷4
÷6
÷8
÷10
÷12
÷14
÷16
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
Do Not Use
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become
minimum conversion rate that this ATD can perform.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
S8CM
SCAN
MULT
CD
CC
CB
CA
0
0
0
0
0
0
0
0
ATD0CTL5/ATD1CTL5 — ATD Control Register 5
$0065/$01E5
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The ATD control register 5 is used to select the conversion modes, the
conversion channel(s), and initiate conversions.
Read or write any time. Writes to the ATD control registers initiate a new
conversion sequence. If a conversion sequence is in progress when a
write occurs, that sequence is aborted and the SCF and CCF bits are
reset.
S8CM — Select 8 Channel Mode
0 = Conversion sequence consists of four conversions
1 = Conversion sequence consists of eight conversions
SCAN — Enable Continuous Channel Scan
0 = Single conversion sequence
1 = Continuous conversion sequences (scan mode)
When a conversion sequence is initiated by a write to the ATDxCTL
register, the user has a choice of performing a sequence of four (or
eight, depending on the S8CM bit) conversions or continuously
performing four (or eight) conversion sequences.
MULT — Enable Multichannel Conversion
0 = ATD sequencer runs all four or eight conversions on a single
input channel selected via the CD, CC, CB, and CA bits.
1 = ATD sequencer runs each of the four or eight conversions on
sequential channels in a specific group. Refer to Table 18-4.
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ATD Registers
CD, CC, CB, and CA — Channel Select for Conversion
Table 18-4. Multichannel Mode Result Register Assignment
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S8CM
CD
CC
CA
Channel Signal
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Reserved
Reserved
Reserved
Reserved
VRH
0
1
VRL
ADRx1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(VRH + VRL)/2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
TEST/Reserved
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Reserved
Reserved
Reserved
Reserved
VRH
ADRx2
ADRx3
ADRx0
ADRx1
ADRx2
ADRx3
ADRx4
ADRx5
ADRx6
ADRx7
ADRx0
ADRx1
ADRx2
ADRx3
ADRx4
1
0
1
VRL
ADRx5
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
Result in ADRxx
if MULT = 1
ADRx0
ADRx1
ADRx2
ADRx3
ADRx0
ADRx1
ADRx2
ADRx3
ADRx0
ADRx1
ADRx2
ADRx3
CB
1
ADRx0
(VRH + VRL)/2
1
1
0
ADRx6
1
1
1
TEST/Reserved
ADRx7
Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight
channels make up a conversion sequence. When MULT = 0, all four bits (CD,
CC, CB, and CA) must be specified and a conversion sequence consists of
four or eight consecutive conversions of the single specified channel.
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NOTE:
RESET:
Conversion of (VRH-VRL)/2 returns $7F, $80 or $81 in 8-bit mode.
Bit 7
6
5
4
3
2
1
Bit 0
SCF
0
0
0
0
CC2
CC1
CC0
0
0
0
0
0
0
0
0
ATD0STAT0/ATD1STAT0 — ATD Status Register
RESET:
$0066/$01E6
Bit 7
6
5
4
3
2
1
Bit 0
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
0
ATD0STAT1/ATD1STAT1 — ATD Status Register
$0067/$01E7
The ATD status registers contain the flags indicating the completion of
ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits
may also be written.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the
single conversion sequence mode (SCAN = 0 in ATDxCTL5) and is
set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDxCTL5). When AFFC = 0, SCF is
cleared when a write is performed to ATDxCTL5 to initiate a new
conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight
Conversions
This 3-bit value reflects the contents of the conversion counter pointer
in a four or eight count sequence. This value also reflects which result
register will be written next, indicating which channel is currently being
converted.
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ATD Registers
CCF[7:0] — Conversion Complete Flags
Each of these bits are associated with an individual ATD result
register. For each register, this bit is set at the end of conversion for
the associated ATD channel and remains set until that ATD result
register is read. It is cleared at that time if AFFC bit is set, regardless
of whether a status register read has been performed (i.e., a status
register read is not a pre-qualifier for the clearing mechanism when
AFFC = 1). Otherwise the status register must be read to clear the
flag.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
SAR9
SAR8
SAR7
SAR6
SAR5
SAR4
SAR3
SAR2
0
0
0
0
0
0
0
0
ATD0TESTH/ATD1TESTH — ATD Test Register
RESET:
$0068/$01E8
Bit 7
6
5
4
3
2
1
Bit 0
SAR1
SAR0
RST
TSTOUT
TST3
TST2
TST1
TST0
0
0
0
0
0
0
0
0
ATD0TESTL/ATD1TESTL — ATD Test Register
$0069/$01E9
The test registers control various special modes which are used
during manufacturing. The test register can be read or written only in
the special modes. In the normal modes, reads of the test register
return zero and writes have no effect.
SAR[9:0] — SAR Data
Reads of this byte return the current value in the SAR. Writes to this
byte change the SAR to the value written. Bits SAR[9:0] reflect the ten
SAR bits used during the resolution process for a 10-bit result.
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RST — Module Reset Bit
When set, this bit causes all registers and activity in the module to
assume the same state as out of power-on reset (except for ADPU bit
in ATDCTL2, which remains set, allowing the ATD module to remain
enabled).
TSTOUT — Multiplex Output of TST[3:0] (Factory Use)
TST[3:0] — Test Bits 3 to 0 (Reserved)
Selects one of 16 reserved factory testing modes
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
PADx7
PADx6
PADx5
PADx4
PADx3
PADx2
PADx1
PADx0
0
0
0
0
0
0
0
0
PORTAD0/PORTAD1 — Port AD Data Input Register
$006F/$01EF
PADx[7:0] — Port AD Data Input Bits
After reset these bits reflect the state of the input pins.
May be used for general-purpose digital input. When the software
reads PORTADx, it obtains the digital levels that appear on the
corresponding port AD pins. Pins with signals not meeting VIL or VIH
specifications will have an indeterminate value. Writes to this register
have no meaning at any time.
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ATD Registers
8-bit mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10-bit mode
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESET:
u
u
u
u
u
u
u
u
ADRx0H — A/D Conversion Result Register High 0
ADRx1H — A/D Conversion Result Register High 1
ADRx2H — A/D Conversion Result Register High 2
ADRx3H — A/D Conversion Result Register High 3
ADRx4H — A/D Conversion Result Register High 4
ADRx5H — A/D Conversion Result Register High 5
ADRx6H — A/D Conversion Result Register High 6
ADRx7H — A/D Conversion Result Register High 7
$0070/$01F0
$0072/$01F2
$0074/$01F4
$0076/$01F6
$0078/$01F8
$007A/$01FA
$007C/$01FC
$007E/$01FE
ADRxxH[7:0] — ATD Conversion result (high)
The reset condition for these registers is undefined.
In 8-bit mode, these registers contain the left-justified, unsigned result
from the 8-bit ATD conversion.
In 10-bit mode these registers contain the high order bits of the
conversion result.
8-bit mode
—
—
—
—
—
—
—
—
10-bit mode
Bit 1
Bit 0
—
—
—
—
—
—
RESET:
u
u
u
u
u
u
u
u
ADRx0L — A/D Conversion Result Register Low 0
ADRx1L — A/D Conversion Result Register Low 1
ADRx2L — A/D Conversion Result Register Low 2
ADRx3L — A/D Conversion Result Register Low 3
ADRx4L — A/D Conversion Result Register Low 4
ADRx5L — A/D Conversion Result Register Low 5
ADRx6L — A/D Conversion Result Register Low 6
ADRx7L — A/D Conversion Result Register Low 7
$0071/$01F1
$0073/$01F3
$0075/$01F5
$0077/$01F7
$0079/$01F9
$007B/$01FB
$007D/$01FD
$007F/$01FF
ADRxxL[7:0] — ATD Conversion result (low)
The reset condition for these registers is undefined.
In 8-bit mode, these registers bits are reserved.
In 10-bit mode these registers contain the remaining two low order
bits of the conversion result in bits 6 and 7.
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The channel from which this result was obtained is dependent on the
conversion mode selected. The registers are always read-only in normal
mode.
18.5 ATD Mode Operation
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STOP — causes all clocks to halt (if the S bit in the CCR is zero). The
system is placed in a minimum-power standby mode. This aborts any
conversion sequence in progress.
WAIT — ATD conversion continues unless AWAI bit in ATDxCTL2
register is set.
BDM — Debug options available as set in register ATDxCTL3.
USER — ATD continues running unless ADPU is cleared.
ADPU — ATD operations are stopped if ADPU = 0, but registers are
accessible.
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Section 19. Development Support
19.1 Contents
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
19.3
Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
19.4
Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
19.5
Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
19.6
Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
19.2 Introduction
Development support involves complex interactions between
68HC(9)12D60 resources and external development systems. The
following section concerns instruction queue and queue tracking signals,
background debug mode, and instruction tagging.
19.3 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program
information to the CPU when instruction execution begins. The CPU12
always completely finishes executing an instruction before beginning to
execute the next instruction. Status signals IPIPE[1:0] provide
information about data movement in the queue and indicate when the
CPU begins to execute instructions. This makes it possible to monitor
CPU activity on a cycle-by-cycle basis for debugging. Information
available on the IPIPE[1:0] pins is time multiplexed. External circuitry
can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges. Table
19-1 shows the meaning of data on the pins.
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Table 19-1I. PIPE Decoding
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock(1)
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No Movement
0:1
LAT
Latch Data From Bus
1:0
ALD
Advance Queue and Load From Bus
1:1
ALL
Advance Queue and Load From Latch
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Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock(2)
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No Start
0:1
INT
Start Interrupt Sequence
1:0
SEV
Start Even Instruction
1:1
SOD
Start Odd Instruction
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
Program information is fetched a few cycles before it is used by the CPU.
In order to monitor cycle-by-cycle CPU activity, it is necessary to
externally reconstruct what is happening in the instruction queue.
Internally the MCU only needs to buffer the data from program fetches.
For system debug it is necessary to keep the data and its associated
address in the reconstructed instruction queue. The raw signals required
for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and
status signals IPIPE[1:0].
The instruction queue consists of two 16-bit queue stages and a holding
latch on the input of the first stage. To advance the queue means to
move the word in the first stage to the second stage and move the word
from either the holding latch or the data bus input buffer into the first
stage. To start even (or odd) instruction means to execute the opcode in
the high-order (or low-order) byte of the second stage of the instruction
queue.
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19.4 Background Debug Mode
Background debug mode (BDM) is used for system development, incircuit testing, field testing, and programming. BDM is implemented in
on-chip hardware and provides a full set of debug options.
Because BDM control logic does not reside in the CPU, BDM hardware
commands can be executed while the CPU is operating normally. The
control logic generally uses free CPU cycles to execute these
commands, but can steal cycles from the CPU when necessary. Other
BDM commands are firmware based, and require the CPU to be in active
background mode for execution. While BDM is active, the CPU executes
a firmware program located in a small on-chip ROM that is available in
the standard 64-Kbyte memory map only while BDM is active.
The BDM control logic communicates with an external host development
system serially, via the BKGD pin. This single-wire approach minimizes
the number of pins needed for development support.
19.4.1 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before
firmware commands can be executed. BDM is enabled by setting the
ENBDM bit in the BDM STATUS register via the single wire interface
(using a hardware command; WRITE_BD_BYTE at $FF01). BDM must
then be activated to map BDM registers and ROM to addresses $FF00
to $FFFF and to put the MCU in active background mode.
After the firmware is enabled, BDM can be activated by the hardware
BACKGROUND command, by the BDM tagging mechanism, or by the
CPU BGND instruction. An attempt to activate BDM before firmware has
been enabled causes the MCU to resume normal instruction execution
after a brief delay.
BDM becomes active at the next instruction boundary following
execution of the BDM BACKGROUND command, but tags activate BDM
before a tagged instruction is executed.
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In special single-chip mode, background operation is enabled and active
immediately out of reset. This active case replaces the M68HC11 boot
function, and allows programming a system with blank memory.
While BDM is active, a set of BDM control registers are mapped to
addresses $FF00 to $FF06. The BDM control logic uses these registers
which can be read anytime by BDM logic, not user programs. Refer to
BDM Registers for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows
suspending the peripheral function during BDM. For example, if the timer
control is enabled, the timer counter is stopped while in BDM. Once
normal program flow is continued, the timer counter is re-enabled to
simulate real-time operations.
19.4.2 BDM Serial Interface
The BDM serial interface requires the external controller to generate a
falling edge on the BKGD pin to indicate the start of each bit time. The
external controller provides this falling edge whether data is transmitted
or received.
BKGD is a pseudo-open-drain pin that can be driven either by an
external controller or by the MCU. Data is transferred MSB first at 16 Bclock cycles per bit (nominal speed). The interface times out if 512 Bclock cycles occur between falling edges from the host. The hardware
clears the command register when a time-out occurs.
The BKGD pin can receive a high or low level or transmit a high or low
level. The following diagrams show timing for each of these cases.
Interface timing is synchronous to MCU clocks but asynchronous to the
external host. The internal clock signal is shown for reference in counting
cycles.
Figure 19-1 shows an external host transmitting a logic one or zero to the
BKGD pin of a target 68HC(9)12D60 MCU. The host is asynchronous to
the target so there is a 0-to-1 cycle delay from the host-generated falling
edge to where the target perceives the beginning of the bit time. Ten
target B cycles later, the target senses the bit level on the BKGD pin.
Typically the host actively drives the pseudo-open-drain BKGD pin
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during host-to-target transmissions to speed up rising edges. Since the
target does not drive the BKGD pin during this period, there is no need
to treat the line as an open-drain signal during host-to-target
transmissions.
B CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
TARGET SENSES BIT
EARLIEST
START OF
NEXT BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
Figure 19-1. BDM Host to Target Serial Bit Timing
B CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
PERCEIVED
START OF BIT
TIME
HIGH-IMPEDANCE
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
Figure 19-2. BDM Target to Host Serial Bit Timing (Logic 1)
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Figure 19-2 shows the host receiving a logic one from the target
68HC(9)12D60 MCU. Since the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host
holds the BKGD pin low long enough for the target to recognize it (at
least two target B cycles). The host must release the low drive before the
target MCU drives a brief active-high speed-up pulse seven cycles after
the perceived start of the bit time. The host should sample the bit level
about ten cycles after it started the bit time.
B CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
Figure 19-3. BDM Target to Host Serial Bit Timing (Logic 0)
Figure 19-3 shows the host receiving a logic zero from the target
68HC(9)12D60 MCU. Since the host is asynchronous to the target MCU,
there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target 68HC(9)12D60 finishes it. Since
the target wants the host to receive a logic zero, it drives the BKGD pin
low for 13 B-clock cycles, then briefly drives it high to speed up the rising
edge. The host samples the bit level about ten cycles after starting the
bit time.
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19.4.3 BDM Commands
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The BDM command set consists of two types: hardware and firmware.
Hardware commands allow target system memory to be read or written.
Target system memory includes all memory that is accessible by the
CPU12 including EEPROM, on-chip I/O and control registers, and
external memory that is connected to the target HC12 MCU. Hardware
commands are implemented in hardware logic and do not require the
HC12 MCU to be in BDM mode for execution. The control logic watches
the CPU12 buses to find a free bus cycle to execute the command so the
background access does not disturb the running application programs.
If a free cycle is not found within 128 B-clock cycles, the CPU12 is
momentarily frozen so the control logic can steal a cycle. Commands
implemented in BDM control logic are listed in Table 19-2.
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Table 19-2. Hardware Commands(1)
BACKGROUND
Opcode
(Hex)
90
READ_BD_BYTE(1)
E4
16-bit address
16-bit data out
READ_BD_WORD(1)
EC
16-bit address
16-bit data out
READ_BYTE
E0
16-bit address
16-bit data out
READ_WORD
E8
16-bit address
16-bit data out
WRITE_BD_BYTE(1)
C4
16-bit address
16-bit data in
WRITE_BD_WORD(1)
CC
16-bit address
16-bit data in
WRITE_BYTE
C0
16-bit address
16-bit data in
WRITE_WORD
C8
16-bit address
16-bit data in
Command
Data
Description
None
Enter background mode if firmware enabled.
Read from memory with BDM in map (may steal
cycles if external access) data for odd address on
low byte, data for even address on high byte.
Read from memory with BDM in map (may steal
cycles if external access). Must be aligned access.
Read from memory with BDM out of map (may steal
cycles if external access) data for odd address on
low byte, data for even address on high byte.
Read from memory with BDM out of map (may steal
cycles if external access). Must be aligned access.
Write to memory with BDM in map (may steal cycles
if external access) data for odd address on low
byte, data for even address on high byte.
Write to memory with BDM in map (may steal cycles
if external access). Must be aligned access.
Write to memory with BDM out of map (may steal
cycles if external access) data for odd address on
low byte, data for even address on high byte.
Write to memory with BDM out of map (may steal
cycles if external access). Must be aligned access.
1. Use these commands only for reading/writing to BDM locations.The BDM firmware ROM and BDM registers are not normally in the HC12 MCU memory map.Since these locations have the same addresses as some of the normal application
memory map, there needs to be a way to decide which physical locations are being accessed by the hardware BDM
commands.This gives rise to needing separate memory access commands for the BDM locations as opposed to the
normal application locations.In logic, this is accomplished by momentarily enabling the BDM memory resources, just for
the access cycles of the READ_BD and WRITE_BD commands.This logic allows the debugging system to unobtrusively
access the BDM locations even if the application program is running out of the same memory area in the normal application memory map.
The second type of BDM commands are firmware commands
implemented in a small ROM within the HC12 MCU. The CPU must be
in background mode to execute firmware commands. The usual way to
get to background mode is by the hardware command BACKGROUND.
The BDM ROM is located at $FF20 to $FFFF while BDM is active. There
are also seven bytes of BDM registers located at $FF00 to $FF06 when
BDM is active. The CPU executes code in the BDM firmware to perform
the requested operation. The BDM firmware watches for serial
commands and executes them as they are received. The firmware
commands are shown in Table 19-3.
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Background Debug Mode
Table 19-3. BDM Firmware Commands
READ_NEXT
READ_PC
READ_D
READ_X
READ_Y
READ_SP
WRITE_NEXT
WRITE_PC
WRITE_D
WRITE_X
WRITE_Y
WRITE_SP
GO
Opcode
(Hex)
62
63
64
65
66
67
42
43
44
45
46
47
08
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
16-bit data in
None
TRACE1
10
None
TAGGO
18
None
Command
Data
Description
X = X + 2; Read next word pointed to by X
Read program counter
Read D accumulator
Read X index register
Read Y index register
Read stack pointer
X = X + 2; Write next word pointed to by X
Write program counter
Write D accumulator
Write X index register
Write Y index register
Write stack pointer
Go to user program
Execute one user instruction then return to
BDM
Enable tagging and go to user program
Each of the hardware and firmware BDM commands start with an 8-bit
command code (opcode). Depending upon the commands, a 16-bit
address and/or a 16-bit data word is required as indicated in the tables
by the command. All the read commands output 16-bits of data despite
the byte/word implication in the command name.
The external host should wait 150 BCLK cycles for a non-intrusive BDM
command to execute before another command is sent. This delay
includes 128 BCLK cycles for the maximum delay for a free cycle. For
data read commands, the host must insert this delay between sending
the address and attempting to read the data. In the case of a write
command, the host must delay after the data portion before sending a
new command to be sure that the write has finished.
The external host should delay about 32 target BCLK cycles between a
firmware read command and the data portion of these commands. This
allows the BDM firmware to execute the instructions needed to get the
requested data into the BDM SHIFTER register.
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The external host should delay about 32 target BCLK cycles after the
data portion of firmware write commands to allow BDM firmware to
complete the requested write operation before a new serial command
disturbs the BDM SHIFTER register.
The external host should delay about 64 target BCLK cycles after a
TRACE1 or GO command before starting any new serial command. This
delay is needed because the BDM SHIFTER register is used as a
temporary data holding register during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is
completed. If an operation can be completed in a single cycle, it does not
intrude on normal CPU12 operation. However, if an operation requires
multiple cycles, CPU12 clocks are frozen until the operation is complete.
19.4.4 BDM Lockout
The access to the MCU resources by BDM may be prevented by
enabling the BDM lockout feature. When enabled, the BDM lockout
mechanism prevents the BDM from being active. In this case the BDM
ROM is disabled and does not appear in the MCU memory map.
BDM lockout is enabled by clearing NOBDML bit of EEMCR register.
The NOBDML bit is loaded at reset from the SHADOW byte of EEPROM
module. Modifying the state of the NOBDML and corresponding
EEPROM SHADOW bit is only possible in special modes.
Please refer to EEPROM Memory for NOBDML information.
19.4.5 Enabling BDM lockout
Enabling the BDM lockout feature is only possible in special modes
(SMODN=0) and is accomplished by the following steps.
1. Remove the SHADOW byte protection by clearing SHPROT bit in
EEPROT register.
2. Clear NOSHB bit in EEMCR register to make the SHADOW byte
visible at $0FC0.
3. Program bit 7 of the SHADOW byte like a regular EEPROM
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location at address $0FC0 (write $7F into address $0FC0). Do not
program other bits of the SHADOW byte (location $0FC0);
otherwise some regular EEPROM array locations will not be
visible. At the next reset, the SHADOW byte is loaded into the
EEMCR register. NOBDML bit in EEMCR will be cleared and BDM
will not be operational.
4. Protect the SHADOW byte by setting SHPROT bit in EEPROT
register.
19.4.6 Disabling BDM lockout
Disabling the BDM lockout is only possible in special modes
(SMODN=0) except in special single chip mode. Follow the same steps
as for enabling the BDM lockout, but erase the SHADOW byte.
At the next reset, the SHADOW byte is loaded into the EEMCR register.
NOBDML bit in EEMCR will be set and BDM becomes operational.
NOTE:
When the BDM lockout is enabled it is not possible to run code from the
reset vector in special single chip mode.
19.4.7 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address
space when BDM is active. Mapping is shown in Table 19-4.
Table 19-4. BDM registers
Address
Register
$FF00
BDM Instruction Register
$FF01
BDM Status Register
$FF02 - $FF03
BDM Shift Register
$FF04 - $FF05
BDM Address Register
$FF06
BDM CCR Holding Register
•
The INSTRUCTION register content is determined by the type of
background command being executed.
•
The STATUS register indicates BDM operating conditions.
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•
The SHIFT register contains data being received or transmitted
via the serial interface.
•
The ADDRESS register is temporary storage for BDM commands.
•
The CCRSAV register preserves the content of the CPU12 CCR
while BDM is active.
The only registers of interest to users are the STATUS register and the
CCRSAV register. The other BDM registers are only used by the BDM
firmware to execute commands. The registers are accessed by means
of the hardware READ_BD and WRITE_BD commands, but should not
be written during BDM operation (except the CCRSAV register which
could be written to modify the CCR value).
19.4.8 STATUS
The STATUS register is read and written by the BDM hardware as a
result of serial data shifted in on the BKGD pin.
Read: all modes.
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the
INSTRUCTION register is a one. A user would never write ones to bits
3 through 5 because these bits are only used by BDM firmware.
RESET:
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
ENBDM
BDMACT
ENTAG
SDV
TRACE
CLKSW
-
-
0
(NOTE 1)
1
0
0
0
0
0
0
Special Single Chip
& Periph
0
0
0
0
0
0
0
0
All other
modes
STATUS— BDM Status Register(1)
$FF01
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.
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Background Debug Mode
ENBDM — Enable BDM (permit active background debug mode)
0 = BDM cannot be made active (hardware commands still
allowed).
1 = BDM can be made active to allow firmware commands.
BDMACT — Background Mode Active Status
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BDMACT becomes set as active BDM mode is entered so that the
BDM firmware ROM is enabled and put into the map. BDMACT is
cleared by a carefully timed store instruction in the BDM firmware as
part of the exit sequence to return to user code and remove the BDM
memory from the map. This bit has 4 clock cycles write delay.
0 = BDM is not active. BDM ROM and registers are not in map.
1 = BDM is active and waiting for serial commands. BDM ROM and
registers are in map
The user should be careful that the state of the BDMACT bit is not
unintentionally changed with the WRITE_NEXT firmware command.
If it is unintentionally changed from 1 to 0, it will cause a system
runaway because it would disable the BDM firmware ROM while the
CPU12 was executing BDM firmware. The following two commands
show how BDMACT may unintentionally get changed from 1 to 0.
WRITE_X with data $FEFE
WRITE_NEXT with data $C400
The first command writes the data $FEFE to the X index register. The
second command writes the data $C4 to the $FF00 INSTRUCTION
register and also writes the data $00 to the $FF01 STATUS register.
ENTAG — Tagging Enable
Set by the TAGGO command and cleared when BDM mode is
entered. The serial system is disabled and the tag function enabled
16 cycles after this bit is written.
0 = Tagging not enabled, or BDM active.
1 = Tagging active. BDM cannot process serial commands while
tagging is active.
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SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
TRACE — Asserted by the TRACE1 command
CLKSW — Clock Switch
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
19.4.9 INSTRUCTION - Hardware Instruction Decode
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
RESET:
BIT 7
6
5
4
3
2
1
BIT 0
H/F
DATA
R/W
BKGND
W/B
BD/U
0
0
0
0
0
0
0
0
0
0
INSTRUCTION — BDM Instruction Register (hardware command explanation)
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The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
0 = Firmware command
1 = Hardware command
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DATA — Data Flag - Shows that data accompanies the command.
0 = No data
1 = Data follows the command
R/W — Read/Write Flag
0 = Write
1 = Read
BKGND — Hardware request to enter active background mode
0 = Not a hardware background command
1 = Hardware background command (INSTRUCTION = $90)
W/B — Word/Byte Transfer Flag
0 = Byte transfer
1 = Word transfer
BD/U — BDM Map/User Map Flag
Indicates whether BDM registers and ROM are mapped to addresses
$FF00 to $FFFF in the standard 64-Kbyte address space. Used only
by hardware read/write commands.
0 = BDM resources not in map
1 = BDM ROM and registers in map
Bit 7
6
5
H/F
DATA
R/W
4
3
2
TTAGO
INSTRUCTION — BDM Instruction Register (firmware command bit explanation)
1
Bit 0
REGN
$FF00
The bits in the BDM instruction register have the following meanings
when a firmware command is executed.
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H/F — Hardware/Firmware Flag
0 = Firmware command
1 = Hardware command
DATA — Data Flag - Shows that data accompanies the command.
0 = No data
1 = Data follows the command
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R/W — Read/Write Flag
0 = Write
1 = Read
TTAGO — Trace, Tag, Go Field
Table 19-5. TTAGO Decoding
Table 19-6TTAGO Value
Table 19-7Instruction
00
—
01
GO
10
TRACE1
11
TAGGO
REGN — Register/Next Field
Indicates which register is being affected by a command. In the case
of a READ_NEXT or WRITE_NEXT command, index register X is
pre-incriminated by 2 and the word pointed to by X is then read or
written.
Table 19-8. REGN Decoding
REGN Value
Instruction
000
—
001
—
010
READ/WRITE NEXT
011
PC
100
D
101
X
110
Y
111
SP
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Background Debug Mode
19.4.10 SHIFTER
This 16-bit shift register contains data being received or transmitted via
the serial interface. It is also used by the BDM firmware for temporary
storage.
Read: all modes (but not normally accessed by users)
Write: all modes (but not normally accessed by users)
RESET:
BIT 15
14
13
12
11
10
9
BIT 8
S15
S14
S13
S12
S11
S10
S9
S8
X
X
X
X
X
X
X
X
SHIFTER— BDM Shift Register - High Byte
RESET:
$FF02
BIT 7
6
5
4
3
2
1
BIT 0
S7
S6
S5
S4
S3
S2
S1
S0
X
X
X
X
X
X
X
X
SHIFTER— BDM Shift Register - Low Byte
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19.4.11 ADDRESS
This 16-bit address register is temporary storage for BDM hardware and
firmware commands.
Read: all modes (but not normally accessed by users)
Write: only by BDM hardware (state machine)
RESET:
BIT 15
14
13
12
11
10
9
BIT 8
A15
A14
A13
A12
A11
A10
A9
A8
X
X
X
X
X
X
X
X
ADDRESS— BDM Address Register - High Byte
RESET:
$FF04
BIT 7
6
5
4
3
2
1
BIT 0
A7
A6
A5
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
ADDRESS— BDM Address Register - Low Byte
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Breakpoints
19.4.12 CCRSAV
The CCRSAV register is used to save the CCR of the users program
when entering BDM. It is also used for temporary storage in the BDM
firmware.
Read and write: all modes
RESET:
NOTE 1 (1)
BIT 7
6
5
4
3
2
1
BIT 0
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
X
X
X
X
X
X
X
X
CCRSAV— BDM CCR Holding Register
$FF06
1. Initialized to equal the CPU12 CCR register by the firmware.
19.5 Breakpoints
Hardware breakpoints are used to debug software on the
68HC(9)12D60 by comparing actual address and data values to
predetermined data in setup registers. A successful comparison will
place the CPU in background debug mode (BDM) or initiate a software
interrupt (SWI). Breakpoint features designed into the 68HC(9)12D60
include:
•
Mode selection for BDM or SWI generation
•
Program fetch tagging for cycle of execution breakpoint
•
Second address compare in dual address modes
•
Range compare by disable of low byte address
•
Data compare in full feature mode for non-tagged breakpoint
•
Byte masking for high/low byte data compares
•
R/W compare for non-tagged compares
•
Tag inhibit on BDM TRACE
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19.5.1 Breakpoint Modes
Three modes of operation determine the type of breakpoint in effect.
•
Dual address-only breakpoints, each of which will cause a
software interrupt (SWI)
•
Single full-feature breakpoint which will cause the part to enter
background debug mode (BDM)
•
Dual address-only breakpoints, each of which will cause the part
to enter BDM
Breakpoints will not occur when BDM is active.
19.5.2 SWI Dual Address Mode
In this mode, dual address-only breakpoints can be set, each of which
cause a software interrupt. This is the only breakpoint mode which can
force the CPU to execute a SWI. Program fetch tagging is the default in
this mode; data breakpoints are not possible. In the dual mode each
address breakpoint is affected by the BKPM bit and the BKALE bit. The
BKxRW and BKxRWE bits are ignored. In dual address mode the
BKDBE becomes an enable for the second address breakpoint. The
BKSZ8 bit will have no effect when in a dual address mode.
19.5.3 BDM Full Breakpoint Mode
A single full feature breakpoint which causes the part to enter
background debug mode. BDM mode may be entered by a breakpoint
only if an internal signal from the BDM indicates background debug
mode is enabled.
•
Breakpoints are not allowed if the BDM mode is already active.
Active mode means the CPU is executing out of the BDM ROM.
•
BDM should not be entered from a breakpoint unless the ENABLE
bit is set in the BDM. This is important because even if the
ENABLE bit in the BDM is negated the CPU actually does execute
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Breakpoints
the BDM ROM code. It checks the ENABLE and returns if not set.
If the BDM is not serviced by the monitor then the breakpoint
would be re-asserted when the BDM returns to normal CPU flow.
•
There is no hardware to enforce restriction of breakpoint operation
if the BDM is not enabled.
19.5.4 BDM Dual Address Mode
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Dual address-only breakpoints, each of which cause the part to enter
background debug mode. In the dual mode each address breakpoint is
affected, consistent across modes, by the BKPM bit, the BKALE bit, and
the BKxRW and BKxRWE bits. In dual address mode the BKDBE
becomes an enable for the second address breakpoint. The BKSZ8 bit
will have no effect when in a dual address mode. BDM mode may be
entered by a breakpoint only if an internal signal from the BDM indicates
background debug mode is enabled.
•
BKDBE will be used as an enable for the second address only
breakpoint.
•
Breakpoints are not allowed if the BDM mode is already active.
Active mode means the CPU is executing out of the BDM ROM.
•
BDM should not be entered from a breakpoint unless the ENABLE
bit is set in the BDM. This is important because even if the
ENABLE bit in the BDM is negated the CPU actually does execute
the BDM ROM code. It checks the ENABLE and returns if not set.
If the BDM is not serviced by the monitor then the breakpoint
would be re-asserted when the BDM returns to normal CPU flow.
There is no hardware to enforce restriction of breakpoint operation
if the BDM is not enabled.
19.5.5 Breakpoint Registers
Breakpoint operation consists of comparing data in the breakpoint
address registers (BRKAH/BRKAL) to the address bus and comparing
data in the breakpoint data registers (BRKDH/BRKDL) to the data bus.
The breakpoint data registers can also be compared to the address bus.
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The scope of comparison can be expanded by ignoring the least
significant byte of address or data matches.
The scope of comparison can be limited to program data only by setting
the BKPM bit in breakpoint control register 0.
To trace program flow, setting the BKPM bit causes address comparison
of program data only. Control bits are also available that allow checking
read/write matches.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
BKEN1
BKEN0
BKPM
0
BK1ALE
BK0ALE
0
0
0
0
0
0
0
0
0
0
BRKCT0 — Breakpoint Control Register 0
$0020
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1, BKEN0 — Breakpoint Mode Enable
Table 19-9. Breakpoint Mode Control
BKEN1 BKEN0
Mode Selected
0
0
Breakpoints Off
0
1
SWI — Dual Address Mode
1
0
BDM — Full Breakpoint Mode
1
1
BDM — Dual Address Mode
BRKAH/L Usage BRKDH/L Usage
—
—
Address Match
Address Match
Address Match
Data Match
Address Match
Address Match
R/W
—
No
Yes
Yes
Range
—
Yes
Yes
Yes
BKPM — Break on Program Addresses
This bit controls whether the breakpoint will cause a break on a match
(next instruction boundary) or on a match that will be an executable
opcode. Data and non-executed opcodes cannot cause a break if this
bit is set. This bit has no meaning in SWI dual address mode. The
SWI mode only performs program breakpoints.
0 = On match, break at the next instruction boundary
1 = On match, break if the match is an instruction that will be
executed. This uses tagging as its breakpoint mechanism.
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Breakpoints
BK1ALE — Breakpoint 1 Range Control
Only valid in dual address mode.
0 = BRKDL will not be used to compare to the address bus.
1 = BRKDL will be used to compare to the address bus.
BK0ALE — Breakpoint 0 Range Control
Valid in all modes.
0 = BRKAL will not be used to compare to the address bus.
1 = BRKAL will be used to compare to the address bus.
Table 19-10. Breakpoint Address Range Control
BK1ALE BK0ALE
Address Range Selected
–
0
Upper 8-bit address only for full mode or dual mode BKP0
–
1
Full 16-bit address for full mode or dual mode BKP0
0
–
Upper 8-bit address only for dual mode BKP1
1
–
Full 16-bit address for dual mode BKP1
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
0
BKDBE
BKMBH
BKMBL
BK1RWE
BK1RW
BK0RWE
BK0RW
0
0
0
0
0
0
0
0
BRKCT1 — Breakpoint Control Register 1
$0021
This register is read/write in all modes.
BKDBE — Enable Data Bus
Enables comparing of address or data bus values using the BRKDH/L
registers.
0 = The BRKDH/L registers are not used in any comparison
1 = The BRKDH/L registers are used to compare address or data
(depending upon the mode selections BKEN1,0)
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BKMBH — Breakpoint Mask High
Disables the comparing of the high byte of data when in full breakpoint
mode. Used in conjunction with the BKDBE bit (which should be set)
0 = High byte of data bus (bits 15:8) are compared to BRKDH
1 = High byte is not used in comparisons
BKMBL — Breakpoint Mask Low
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Disables the matching of the low byte of data when in full breakpoint
mode. Used in conjunction with the BKDBE bit (which should be set)
0 = Low byte of data bus (bits 7:0) are compared to BRKDL
1 = Low byte is not used in comparisons.
BK1RWE — R/W Compare Enable
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is NOT useful in program breakpoints or in
full breakpoint mode. This bit is used in conjunction with a second
address in dual address mode when BKDBE=1.
0 = R/W is not used in comparisons
1 = R/W is used in comparisons
BK1RW — R/W Compare Value
When BK1RWE = 1, this bit determines the type of bus cycle to
match.
0 = A write cycle will be matched
1 = A read cycle will be matched
BK0RWE — R/W Compare Enable
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is not useful in program breakpoints.
0 = R/W is not used in the comparisons
1 = R/W is used in comparisons
BK0RW — R/W Compare Value
When BK0RWE = 1, this bit determines the type of bus cycle to match
on.
0 = Write cycle will be matched
1 = Read cycle will be matched
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Breakpoints
Table 19-11. Breakpoint Read/Write Control
BK1RWE BK1RW BK0RWE BK0RW
Read/Write Selected
–
–
0
X
R/W is don’t care for full mode or dual mode BKP0
–
–
1
0
R/W is write for full mode or dual mode BKP0
–
–
1
1
R/W is read for full mode or dual mode BKP0
0
X
–
–
R/W is don’t care for dual mode BKP1
1
0
–
–
R/W is write for dual mode BKP1
1
1
–
–
R/W is read for dual mode BKP1
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
BRKAH — Breakpoint Address Register, High Byte
$0022
These bits are used to compare against the most significant byte of the
address bus.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKAL — Breakpoint Address Register, Low Byte
$0023
These bits are used to compare against the least significant byte of the
address bus. These bits may be excluded from being used in the match
if BK0ALE = 0.
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RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
BRKDH — Breakpoint Data Register, High Byte
$0024
These bits are compared to the most significant byte of the data bus or
the most significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the
breakpoint comparison.
RESET:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKDL — Breakpoint Data Register, Low Byte
$0025
These bits are compared to the least significant byte of the data bus or
the least significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
19.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
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TAGHI signal shares a pin with the BKGD signal. Tagging information is
latched on the falling edge of ECLK.
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Table 19-12 shows the functions of the two tagging pins. The pins
operate independently - the state of one pin does not affect the function
of the other. The presence of logic level zero on either pin at the fall of
ECLK performs the indicated function. Tagging is allowed in all modes.
Tagging is disabled when BDM becomes active and BDM serial
commands are not processed while tagging is active.
Table 19-12. Tag Pin Function
TAGHI
TAGLO
Tag
1
1
no tag
1
0
low byte
0
1
high byte
0
0
both bytes
The tag follows program information as it advances through the queue.
When a tagged instruction reaches the head of the queue, the CPU
enters active background debugging mode rather than execute the
instruction.
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Section 20. Electrical Specifications
20.1 Contents
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
20.3
Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
20.2 Introduction
This section contains the most accurate electrical information for the
68HC(9)12D60 microcontroller available at the time of publication.
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20.3 Tables of Data
Table 20-1. Maximum Ratings(1)
Rating
Supply voltage
Input voltage
Symbol
Value
Unit
VDD, VDDA, VDDX, VDDPLL
−0.3 to +6.5
V
VIN
−0.3 to +6.5
V
TA
TL to TH
0 to +70
−40 to +85
–40 to +105
–40 to +125
°C
TA
TL to TH
0 to +70
−40 to +85
–40 to +105
–40 to +125
°C
Tstg
−55 to +150
°C
IIN
±25
mA
VDD−VDDX
6.5
V
Operating temperature range
68HC(9)12D60PV8
68HC(9)12D60CPV8
68HC(9)12D60VPV8
68HC(9)12D60MPV8 (single chip mode only)
Operating temperature range
68HC(9)12D60FU8
68HC(9)12D60CFU8
68HC(9)12D60VFU8
68HC(9)12D60MFU8 (single chip mode only)
Storage temperature range
Current drain per pin(2)
Excluding VDD and VSS
VDD differential voltage
1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes.
2. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused
by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage
higher than maximum-rated voltages to this high-impedance circuit. Extended operation at the maximum ratings can adversely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or VDD) enhances
reliability of operation.
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Tables of Data
Table 20-2. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Average junction temperature
TJ
TA + (PD × ΘJA)
°C
Ambient temperature
TA
User-determined
°C
Package thermal resistance (junction-to-ambient)
68HC912D60 80-pin quad flat pack (QFP)
112-pin thin quad flat pack (TQFP)
ΘJA
65
46
°C/W
Package thermal resistance (junction-to-ambient)
68HC12D60 80-pin quad flat pack (QFP)
112-pin thin quad flat pack (TQFP)
ΘJA
70
48
°C/W
PINT + PI/O
Total power
dissipation(1)
Device internal power dissipation
I/O pin power
dissipation(2)
A constant(3)
or
PD
K
------------------------T J + 273°C
W
PINT
IDD × VDD
W
PI/O
User-determined
W
K
PD × (TA + 273°C) +
ΘJA × PD2
W · °C
1. This is an approximate value, neglecting PI/O.
2. For most applications PI/O « PINT and can be neglected.
3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of
K to solve for PD and TJ iteratively for any value of TA.
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Electrical Specifications
Table 20-3. DC Electrical Characteristics
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs
VIH
0.7 × VDD
VDD + 0.3
V
Input low voltage, all inputs
VIL
VSS−0.3
0.2 × VDD
V
Output high voltage, all I/O and output pins except XTAL
Normal drive strength
IOH = −10.0 µA
IOH = −0.8 mA
Reduced drive strength
IOH = −4.0 µA
IOH = −0.3 mA
VOH
VDD − 0.2
VDD − 0.8
—
—
V
V
VDD − 0.2
VDD − 0.8
—
—
V
V
Output low voltage, all I/O and output pins except XTAL
Normal drive strength
IOL = 10.0 µA
IOL = 1.6 mA
Reduced drive strength
IOL = 3.6 µA
IOL = 0.6 mA
VOL
—
—
VSS+0.2
VSS+0.4
V
V
—
—
VSS+0.2
VSS+0.4
V
V
Input leakage current(1)
Vin = VDD or VSSAll input only pins except ATD(2) and VFP
Vin = VDD or VSS
Iin
—
—
±2.5
±10
µA
µA
Three-state leakage, I/O ports, BKGD, and RESET
IOZ
—
±2.5
µA
Input capacitance
All input pins and ATD pins (non-sampling)
ATD pins (sampling)
All I/O pins
Cin
—
—
—
10
15
20
pF
pF
pF
Output load capacitance
All outputs except PS[7:4]
PS[7:4] when configured as SPI
CL
—
—
90
200
pF
pF
50
50
50
500
500
500
µA
µA
µA
Programmable active pull-up current
XIRQ, IRQ, DBE, LSTRB, R/W, ports A, B, CAN, P,S, T
MODA, MODB active pull down during reset
BKGD passive pull up
IAPU
1. Specification is for parts in the -40 to +85°C range. Higher temperature ranges will result in increased current leakage.
2. See Table 20-5.
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Tables of Data
Table 20-4. Supply Current
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Maximum total supply current
RUN:
Single-chip mode
Expanded mode
Symbol
2 MHz(1) 4 MHz(1)
IDD
8 MHz
Unit
18
30
30
50
50
85
mA
mA
WAIT: (All peripheral functions shut down)
Single-chip mode
Expanded mode
WIDD
4
5
6
9
8
12
mA
mA
STOP:
Single-chip mode, no clocks
−40 to +85
+85 to +105
+105 to +125
SIDD
10
50
50
10
50
50
10
50
50
µA
µA
µA
Maximum power dissipation(2)
Single-chip mode
Expanded mode
PD
100
165
165
275
275
467
mW
mW
1. These are typical values only and are not tested.
2. Includes IDD and IDDA.
Table 20-5. ATD DC Electrical Characteristics
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic
Symbol
Min
Max
Unit
Analog supply voltage
VDDA
4.5
5.5
V
Analog supply current, normal operation(1)
IDDA
1.0
mA
Reference voltage, low
VRL
VSSA
VDDA/2
V
Reference voltage, high
VRH
VDDA/2
VDDA
V
VRH−VRL
4.5
5.5
V
VINDC
VSSA
VDDA
V
VREF differential reference voltage(2)
Input voltage(3)
Input current, off channel(4)
IOFF
100
nA
Reference supply current
IREF
250
µA
CINN
CINS
10
15
pF
pF
Input capacitance
Not Sampling
Sampling
1. For each ATD module
2. Accuracy is guaranteed at VRH − VRL = 5.0V ±10%.
3. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA.
4. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10°C
decrease from maximum temperature.
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Table 20-6. Analog Converter Characteristics (Operating)
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic
Symbol
8-bit resolution(1)
Min
Typical
1 count
Max
20
Unit
mV
8-bit differential non-linearity(2)
DNL
−0.5
+0.5
count
8-bit integral non-linearity(2)
INL
−1
+1
count
8-bit absolute error,(3)2, 4, 8, and 16 ATD sample clocks
AE
−1
+1
count
10-bit resolution(1)
1 count
5
mV
10-bit differential non-linearity(2)
DNL
–2
2
count
10-bit integral non-linearity(2)
INL
–2
2
count
10-bit absolute error(3) 2, 4, 8, and 16 ATD sample clocks
AE
–2.5
2.5
count
Maximum source impedance
RS
See
note(4)
KΩ
20
1. VRH − VRL ≥ 5.12V; VDDA − VSSA = 5.12V
2. At VREF = 5.12V, one 8-bit count = 20 mV, and one 10-bit count = 5mV.
INL and DNL are characterized using the process window parameters affecting the ATD accuracy, but they are not tested.
3. These values include quantization error which is inherently 1/2 count for any A/D converter. Accuracy tested when when
VRL=VSS, VRH=VDD and external source impedence is close to zero.
4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into
the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result
value due to junction leakage is expressed in voltage (VERRJ):
VERRJ = RS × IOFF
where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD
clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge pump leakage
is computed as follows:
VERRJ = .25pF × VDDA × RS × ATDCLK/(8 × number of channels)
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Table 20-7. ATD AC Characteristics (Operating)
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted
Characteristic
Symbol
Min
Max
Unit
MCU clock frequency (p-clock)
fPCLK
2.0
8.0
MHz
ATD operating clock frequency
fATDCLK
0.5
2.0
MHz
ATD 8-Bit conversion period
clock cycles(1)
conversion time(2)
nCONV8
tCONV8
18
9
32
16
cycles
µs
ATD 10-Bit conversion period
clock cycles(1)
conversion time(2)
nCONV10
tCONV10
20
10
34
17
cycles
µs
10
µs
Stop and ATD power up recovery time(3)
VDDA = 5.0V
tSR
1. The minimum time assumes a final sample period of 2 ATD clock cycles while the maximum time assumes a final sample
period of 16ATD clocks.
2. This assumes an ATD clock frequency of 2.0MHz.
3. From the time ADPU is asserted until the time an ATD conversion can begin.
Table 20-8. ATD Maximum Ratings
Characteristic
Symbol
Value
Units
ATD reference voltage
VRH ≤ VDDA
VRL ≥ VSSA
VRH
VRL
−0.3 to +6.5
−0.3 to +6.5
V
V
VSS differential voltage
|VSS−VSSA|
0.1
V
VDD differential voltage
VDD−VDDA
VDDA−VDD
6.5
0.3
V
V
VREF differential voltage
|VRH−VRL|
6.5
V
|VRH−VDDA|
6.5
V
Reference to supply differential voltage
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Table 20-9. EEPROM Characteristics
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Symbol
Min
Minimum programming clock frequency(1)
fPROG
1.0
Programming time
tPROG
10
Typical
tERASE
10.5
ms
tPROG+ 1
ms
10.5
ms
10
Write/erase endurance
10,000
Data retention
Unit
MHz
Clock recovery time, following STOP, to continue programming tCRSTOP
Erase time
Max
30,000
cycles
(2)
10
years
1. RC oscillator must be enabled if programming is desired and fSYS < fPROG.
2. If average TH is below 85° C.
Table 20-10. Flash EEPROM Characteristics (68HC912D60 only)
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Symbol
Min
Typical
Max
Units
Program/erase supply voltage:
Read only
Program / erase / verify
VFP
VDD−0.35
11.4
VDD
12
VDD+0.5
12.6
V
V
Program/erase supply current
Word program(VFP = 12V)
Erase(VFP = 12V)
IFP
30
4
mA
mA
Number of programming pulses
nPP
50
pulses
25
µs
Programming pulse
tPPULSE
20
Program to verify time
tVPROG
10
µs
Program margin
pm
100(1)
%
Number of erase pulses
nEP
5
pulses
10
ms
Erase pulse
tEPULSE
5
Erase to verify time
tVERASE
1
ms
em
100(1)
%
Program/erase endurance
100
cycles
Data retention
10
years
Erase margin
1. The number of margin pulses required is the same as the number of pulses used to program or erase.
Use of an external circuit to condition VFP is recommended. Figure 20-1
shows a simple circuit that maintains required voltages and filters
transients. VFP is pulled to VDD via Schottky diode D2. Application of
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programming voltage via diode reverse-biases D2, protecting VDD from
excessive reverse current. D2 also protects the FLASH from damage
should programming voltage go to 0. Programming power supply
voltage must be adjusted to compensate for the forward-bias drop
across D1. The charge time constant of R1 and C1 filters transients,
while R2 provides a discharge bleed path to C1. Allow for RC charge and
discharge time constants when applying and removing power. When
using this circuit, keep leakage from external devices connected to the
VFP pin low, to minimize diode voltage drop.
PROGRAMMING VOLTAGE
POWER SUPPLY
D1
R1
10Ω
4.5V
D2
VFP
VDD
PIN
R2
22kΩ
C1
0.1µF
Figure 20-1VFP Conditioning Circuit
30ns MAXIMUM
13.5V
12.8V
VFP ENVELOPE
VDD ENVELOPE
11.4V
COMBINED VDD AND VFP
tER
6.5V
4.5V
4.15V
0V
–0.30V
POWER
ON
NORMAL
READ
PROGRAM
ERASE
VERIFY
POWER
DOWN
Figure 20-2VFP Operating Range
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Table 20-11. Pulse Width Modulator Characteristics
VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Symbol
Min
Max
Unit
E-clock frequency
feclk
0.004
8.0
MHz
A-clock frequency
Selectable
faclk
feclk
Hz
B-clock frequency
Selectable
fbclk
feclk
Hz
Left-aligned PWM frequency
8-bit
16-bit
flpwm
feclk/1M
feclk/256M
feclk/2
feclk/2
Hz
Hz
Left-aligned PWM resolution
rlpwm
feclk/4K
feclk
Hz
Center-aligned PWM frequency
8-bit
16-bit
fcpwm
feclk/2M
feclk/512M
feclk
feclk
Hz
Hz
Center-aligned PWM resolution
rcpwm
feclk/4K
feclk
Hz
feclk/128
feclk/128
Table 20-12. Control Timing
Characteristic
Symbol
8.0 MHz
Unit
Min
Max
fo
0.004
8.0
MHz
E-clock period
tcyc
0.125
250
µs
External oscillator frequency
feo
0.5
16.0(1)
MHz
Processor control setup time
tPCSU = tcyc/2 + 20
tPCSU
82
—
PWRSTL
32
2
—
—
tcyc
tcyc
Mode programming setup time
tMPS
4
—
tcyc
Mode programming hold time
tMPH
10
—
ns
PWIRQ
270
—
ns
tWRS
—
4
tcyc
PWTIM
270
—
ns
Frequency of operation
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ = 2tcyc + 20
Wait recovery startup time
Timer input capture pulse width
PWTIM = 2tcyc + 20
ns
1. When using a quartz crystal, operation should be restricted to 8MHz.
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NOTE:
RESET is recognized during the first clock cycle it is held low. Internal
circuitry then drives the pin low for 16 clock cycles, releases the pin, and
samples the pin level 8 cycles later to determine the source of the
interrupt.
PT[7:0]1
PWTIM
PT[7:0]2
PT71
PWPA
PT72
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
Figure 20-3. Timer Inputs
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NOTE: Reset timing is subject to change.
INTERNAL
ADDRESS
MODA, MODB
RESET
ECLK
EXTAL
VDD
4098 tcyc
FFFE
FFFE
FREE
1ST
PIPE
2ND
PIPE
3RD
PIPE
tPCSU
1ST
EXEC
FFFE
PWRSTL
tMPS
FFFE
FFFE
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tMPH
FREE
1ST
PIPE
2ND
PIPE
3RD
PIPE
1ST
EXEC
Electrical Specifications
Figure 20-4. POR and External Reset Timing Diagram
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SP-8
SP-8
SP-6
SP-6
SP-9
SP-9
PWIRQ
tSTOPDELAY3
NOTES:
1. Edge Sensitive IRQ pin (IRQE bit = 1)
2. Level sensitive IRQ pin (IRQE bit = 0)
3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0.
4. XIRQ with X bit in CCR = 1.
5. IRQ or (XIRQ with X bit in CCR = 0).
ADDRESS5
ADDRESS4
ECLK
IRQ
or XIRQ
IRQ1
INTERNAL
CLOCKS
FREE
FREE
OPT
FETCH
1ST
EXEC
VECTOR
FREE
1ST
PIPE
2ND
PIPE
3RD
PIPE
1ST
EXEC
Resume program with instruction which follows the STOP instruction.
FREE
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Figure 20-5. STOP Recovery Timing Diagram
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SP – 2
NOTE: RESET also causes recovery from WAIT.
R/W
ADDRESS
IRQ, XIRQ,
OR INTERNAL
INTERRUPTS
ECLK
SP – 6 . . . SP – 9
PC, IY, IX, B:A, , CCR
STACK REGISTERS
SP – 4
SP – 9
SP – 9 . . . SP – 9
SP – 9
tPCSU
VECTOR
ADDRESS
tWRS
FREE
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1ST
PIPE
2ND
PIPE
3RD
PIPE
1ST
EXEC
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Figure 20-6. WAIT Recovery Timing Diagram
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VECT
DATA
NOTES:
1. Edge sensitive IRQ pin (IRQE bit = 1)
2. Level sensitive IRQ pin (IRQE bit = 0)
R/W
VECTOR
ADDR
PWIRQ
tPCSU
ADDRESS
IRQ2, XIRQ,
OR INTERNAL
INTERRUPT
IRQ1
ECLK
PC
SP – 2
PROG
FETCH
1ST
PIPE
IY
SP – 4
IX
SP – 6
PROG
FETCH
2ND
PIPE
B:A
SP – 8
CCR
SP – 9
PROG
FETCH
3RD
PIPE
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1ST
EXEC
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Figure 20-7. Interrupt Timing Diagram
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Table 20-13. Peripheral Port Timing
Characteristic
Symbol
8.0 MHz
Unit
Min
Max
fo
0.004
8.0
MHz
tcyc
0.125
250
µs
Peripheral data setup time
MCU read of portstPDSU = tcyc/2 + 40
tPDSU
102
—
ns
Peripheral data hold time
MCU read of ports
tPDH
0
—
ns
Delay time, peripheral data write
MCU write to ports except Port CAN
tPWD
—
40
ns
Delay time, peripheral data write
MCU write to Port CAN
tPWD
—
71
ns
Frequency of operation (E-clock frequency)
E-clock period
MCU READ OF PORT
ECLK
tPDSU
tPDH
PORTS
Figure 20-8. Port Read Timing Diagram
MCU WRITE TO PORT
ECLK
tPWD
PORT A
PREVIOUS PORT DATA
NEW DATA VALID
Figure 20-9. Port Write Timing Diagram
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Table 20-14. Multiplexed Expansion Bus Timing
VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic(1), (2), (3), (4)
Num
8 MHz
Delay Symbol
Frequency of operation (E-clock frequency)
Min
Max
2MHz
Min
Max
Unit
fo
0.004 8.0
0.004
2.0
MHz
0.125 250
0.5
250
µs
1
Cycle timetcyc = 1/fo
—
tcyc
2
Pulse width, E lowPWEL = tcyc/2 + delay
−4
PWEL
58
246
ns
3
Pulse width, E high(5)PWEH = tcyc/2 + delay
−2
PWEH
60
248
ns
5
Address delay timetAD = tcyc/4 + delay
27
tAD
7
Address valid time to ECLK risetAV = PWEL − tAD
—
tAV
0
94
ns
8
Multiplexed address hold timetMAH = tcyc/4 + delay
−18
tMAH
13
107
ns
9
Address Hold to Data Valid
—
tAHDS
20
20
ns
10
Data Hold to High ZtDHZ = tAD − 20
—
tDHZ
11
Read data setup time
—
tDSR
25
25
ns
12
Read data hold time
—
tDHR
0
0
ns
13
Write data delay time
—
tDDW
14
Write data hold time
—
tDHW
20
20
ns
15
Write data setup time(5)tDSW = PWEH − tDDW
—
tDSW
13
83
ns
16
Read/write delay timetRWD = tcyc/4 + delay
18
tRWD
17
Read/write valid time to E risetRWV = PWEL − tRWD
—
tRWV
9
103
ns
18
Read/write hold time
—
tRWH
20
20
ns
19
Low strobe(6) delay timetLSD = tcyc/4 + delay
18
tLSD
20
Low strobe(6) valid time to E risetLSV = PWEL − tLSD
—
tLSV
9
103
ns
21
Low strobe(6) hold time
—
tLSH
20
20
ns
22
Address access time(5)tACCA = tcyc − tAD − tDSR
—
tACCA
42
323
ns
23
Access time from E rise(5)tACCE = PWEH − tDSR
—
tACCE
35
223
ns
24
DBE delay from ECLK rise(5)tDBED = tcyc/4 + delay
8
tDBED
39
133
ns
25
DBE valid timetDBE = PWEH − tDBED
—
tDBE
21
26
DBE hold time from ECLK fall
tDBEH
–3
58
152
38
132
47
165
49
143
49
143
115
10
–3
ns
ns
ns
ns
ns
ns
10
ns
1. All timings are calculated for normal port drives.
2. Crystal input is required to be within 45% to 55% duty.
3. Reduced drive must be off to meet these timings.
4. Unequalled loading of pins will affect relative timing numbers.
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5. This characteristic is affected by clock stretch.
Add N × tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.
6. Without TAG enabled.
1
2
3
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ECLK
16
17
18
19
20
21
R/W
LSTRB
(W/O TAG ENABLED)
5
23
7
11
22
10
12
ADDRESS
READ
ADDRESS/DATA
MULTIPLEXED
DATA
9
8
13
WRITE
ADDRESS
15
14
DATA
24
25
26
DBE
NOTE: Measurement points shown are 20% and 70% of VDD
Figure 20-10. Multiplexed Expansion Bus Timing Diagram
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Tables of Data
Table 20-15. SPI Timing
(VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH , 200 pF load on all SPI pins)(1)
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop
1/256
1/256
1/2
1/2
feclk
1
SCK Period
Master
Slave
tsck
2
2
256
—
tcyc
tcyc
2
Enable Lead Time
Master
Slave
tlead
1/2
1
—
—
tsck
tcyc
3
Enable Lag Time
Master
Slave
tlag
1/2
1
—
—
tsck
tcyc
4
Clock (SCK) High or Low Time
Master
Slave
twsck
tcyc − 30
tcyc − 30
128 tcyc
—
ns
ns
5
Sequential Transfer Delay
Master
Slave
ttd
1/2
1
—
—
tsck
tcyc
6
Data Setup Time (Inputs)
Master
Slave
tsu
30
30
—
—
ns
ns
7
Data Hold Time (Inputs)
Master
Slave
thi
0
30
—
—
ns
ns
8
Slave Access Time
ta
—
1
tcyc
9
Slave MISO Disable Time
tdis
—
1
tcyc
10
Data Valid (after SCK Edge)
Master
Slave
tv
—
—
50
50
ns
ns
11
Data Hold Time (Outputs)
Master
Slave
tho
0
0
—
—
ns
ns
12
Rise Time
Input
Output
tri
tro
—
—
tcyc − 30
30
ns
ns
13
Fall Time
Input
Output
tfi
tfo
—
—
tcyc − 30
30
ns
ns
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
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SS1
(OUTPUT)
5
2
1
SCK
(CPOL = 0)
(OUTPUT)
4
13
SCK
(CPOL = 1)
(OUTPUT)
6
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3
12
4
7
MISO
(INPUT)
MSB IN2
BIT 6 .
10
. .
1
LSB IN
10
MOSI
(OUTPUT)
MSB OUT2
11
BIT 6 .
. .
1
LSB OUT
1.
SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
A) SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
5
1
2
13
12
12
13
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
6
MISO
(INPUT)
7
MSB IN2
. .
1
LSB IN
11
10
MOSI
(OUTPUT) PORT DATA
BIT 6 .
MASTER MSB OUT2
BIT 6 .
. .
1
MASTER LSB OUT
PORT DATA
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
B) SPI Master Timing (CPHA = 1)
Figure 20-11. SPI Timing Diagram (1 of 2)
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Tables of Data
SS
(INPUT)
5
1
13
12
12
13
3
SCK
(CPOL = 0)
(INPUT)
4
2
4
SCK
(CPOL = 1)
(INPUT)
9
8
MISO
(OUTPUT)
10
6
MOSI
(INPUT)
BIT 6 .
MSB OUT
SLAVE
11
11
. .
1
SLAVE LSB OUT
SEE
NOTE
7
BIT 6 .
MSB IN
. .
1
LSB IN
NOTE: Not defined but normally MSB of character just received.
A) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
5
3
1
2
13
12
12
13
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
9
11
10
SLAVE
MSB OUT
6
BIT 6 .
. .
1
SLAVE LSB OUT
7
MSB IN
BIT 6 .
. .
1
LSB IN
NOTE: Not defined but normally LSB of character just received.
B) SPI Slave Timing (CPHA = 1)
Figure 20-12. SPI Timing Diagram (2 of 2)
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Table 20-16. CGM Characteristics
5.0 Volts ±10%
Characteristic
Symbol
Min.
PLL reference frequency, crystal oscillator range
fREF
Bus frequency
VCO range
Max.
Unit
0.5
8
MHz
fBUS
0.004
8
MHz
fVCO
2.5
8
MHz
fVCOMIN
0.5
2.5
MHz
∆trk
3%
4%
—
∆Lock
0%
1.5%
—
Un-Lock Detection
∆unl
0.5%
2.5%
—
Lock Detector transition from Tracking to
Acquisition mode(1)
∆unt
6%
8%
—
Minimum leakage resistance on crystal oscillator
pins
rleak
1
VCO Limp-Home frequency
Lock Detector transition from Acquisition to
Tracking mode(1)
Lock Detection
Typ.
1
MΩ
PLL Stabilization delay(2)
PLL Total Stabilization Delay(3)
tstab
3
ms
PLLON Acquisition mode stabilization delay.(3)
tacq
1
ms
tal
2
ms
PLLON tracking mode stabilization delay.(3)
1. AUTO bit set
2. PLL stabilization delay is highly dependent on operational requirement and external component values (i.e. crystal, XFC
filter component values|). Note (3) shows typical delay values for a typical configuration. Appropriate XFC filter values
should be chosen based on operational requirement of system.
3. fREF = 4MHz, fBUS = 8MHz (REFDV = #$00, SYNR = #$01), XFC:Cs = 33nF, Cp = 3.3nF, Rs = 2.7KΩ.
Table 20-17. Key Wake-up
VDD = 5.0V dc ± 10%
Characteristic
STOP Key Wake-Up Filter time
Key Wake-Up Single Pulse Time Interval
Symbol
tKWSTP
Min.
2
tKWSP
20
Max.
10
Unit
µs
µs
Table 20-18. msCAN12 Wake-up Time from Sleep Mode
VDD = 5.0V dc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Characteristic
Wake-Up time
Symbol
twup
Min.
2
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Max.
5
Unit
µs
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Section 21. Appendix: CGM Practical Aspects
21.1 Contents
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
21.3
A Few Hints For The CGM Crystal Oscillator Application. . . . 387
21.4
Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .390
21.5
Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .395
21.2 Introduction
This sections provides useful and practical pieces of information
concerning the implementation of the CGM module.
21.3 A Few Hints For The CGM Crystal Oscillator Application
21.3.1 What Loading Capacitors To Choose?
First, from small-signal analysis, it is known that relatively large values
for C1 and C2 have a positive impact on the phase margin. However, the
higher loading they represent decreases the loop gain. Alternatively,
small values for these capacitors will lead to higher open loop gain, but
as the frequency of oscillation approaches the parallel resonance, the
phase margin, and consequently the ability to start-up correctly, will
decrease. From this it is clear that relatively large capacitor values
(>33pF), are reserved for low frequency crystals in the MHz range.
NOTE:
Using the recommended loading capacitor CL value from the crystal
manufacturer is a good starting point. Taking into account unavoidable
strays, this equates to about (CL-2pF).
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Theoretically speaking, nothing precludes the use of non-identical
values for C1 and C2. As this complicate a bit the management of the
final board device list, this is not recommended. However, if
asymmetrical capacitors are chosen, the value of C1 should be higher
than C2 (because the reflected loading is proportional to the square of
the impedance of C2).
21.3.2 DC Bias
Due to the nature of the translated ground Colpitts oscillator a DC
voltage bias is applied to the crystal.
Please contact the crystal manufacturer for specific DC bias conditions
and recommended capacitance value (if applicable).
21.3.3 What Is the Final Oscillation Frequency?
The exact calculation is not straightforward as it takes into account the
resonator characteristics and the loading capacitors values as well as
internal design parameters which can vary with Process Voltage
Temperature (PVT) conditions. Nevertheless, if L is the series
inductance, R is the series resistance, C is the series capacitance and
Cc the parallel capacitance of the crystal, we can then use the following
simplified equation:
1
1 - + --------------------------------------------1
Fosc = ------ ⋅ ------2π
LC L ⋅ ( Cc + C1 || C2 )
C1=C2=Cl yields to
1
1 - + -------------------------------------1
Fosc = ------ ⋅ ------2π
LC L ⋅ ( Cc + Cl ⁄ 2 )
21.3.4 How Do I Control The Peak to Peak Oscillation Amplitude?
The CGM oscillator is equipped with an Amplitude Limitation Control
loop which integrates the peak to peak ‘extal’ amplitude and in return
reduces the steady current of the transconductor device until a stable
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A Few Hints For The CGM Crystal Oscillator Application
quiescent point is reached. Controlling this final peak to peak amplitude
can be performed by three means:
1. Reducing the values of C1 and C2. This decreases the loading so
that the necessary gm value required to sustain oscillation can be
smaller. The consequently smaller current will be reached with a
larger ‘extal’ swing.
2. Using VDDPLL=VSS (i.e. shutting off the PLL). Doing so
increases the starting current by approximately 50%. All other
parameters staying the same, a larger ‘extal’ swing will be required
to reduce this starting current to its quiescent value.
3. Also, placing a high value resistor (>1MΩ) across the EXTAL and
XTAL pins significantly increased the oscillation amplitude.
Because this complicates the design analysis as it transforms a
pure susceptance jωC1 into a complex admittance G+jωC1,
Motorola cannot promote this application trick.
21.3.5 What Do I Do In Case The Oscillator Does Not Start-up?
1. First, verify that the application schematic respects the principle of
operation, i.e. crystal mounted between EXTAL and VSS,
Capacitor C1 between XTAL and EXTAL, Capacitor C2 between
XTAL and VSS, nothing else. This is not the conventional MCU
application schematic of the Pierce oscillator as it can be seen on
other HC12 derivatives!
2. Re-consider the choice of the tuning capacitors.
3. The oscillator circuitry is powered internally from a core VDD pad
and the return path is the VSSPLL pad. Verify on the application
PCB the correct connection of these pads (especially VSSPLL),
but also verify the waveform of the VDD voltage as it is imposed
on the pad. Sometimes external components (for instance choke
inductors), can cause oscillations on the power line. This is of
course detrimental to the oscillator circuitry.
4. If possible, consider using a resonator with built-in tuning
capacitors. They may offer better performances with respect to
their discrete elements implementation.
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21.4 Practical Aspects For The PLL Usage
21.4.1 Synthesized Bus Frequency
Starting from a ceramic resonator or quartz crystal frequency FXTAL, if
‘refdv’ and ‘synr’ are the decimal content of the REFDV and SYNR
registers respectively, then the MCU bus frequency will simply be:
F XTAL ⋅ ( synr + 1 )
F BUS = F VCO = ----------------------------------------------( refdv + 1 )
synr ∈ { 0,1,2,3...63}
refdv ∈ { 0,1,2,3...7}
NOTE:
It is not allowed to synthesize a bus frequency that is lower than the
crystal frequency, as the correct functioning of some internal
synchronizers would be jeopardized (e.g. the MCLK and XCLK clock
generators).
21.4.2 Operation Under Adverse Environmental Conditions
The normal operation for the PLL is the so-called ‘automatic bandwidth
selection mode’ which is obtained by having the AUTO bit set in the
PLLCR register. When this mode is selected and as the VCO frequency
approaches its target, the charge pump current level will automatically
switch from a relatively high value of around 40 µA to a lower value of
about 3 µA. It can happen that this low level of charge pump current is
not enough to overcome leakages present at the XFC pin due to adverse
environmental conditions. These conditions are frequently encountered
for uncoated PCBs in automotive applications. The main symptom for
this failure is an unstable characteristic of the PLL which in fact ‘hunts’
between acquisition and tracking modes. It is then advised for the
running software to place the PLL in manual, forced acquisition mode by
clearing both the AUTO and the ACQ bits in the PLLCR register. Doing
so will maintain the high current level in the charge pump constantly and
will permit to sustain higher levels of leakages at the XFC pin. This latest
revision of the Clock Generator Module maintains the lock detection
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Appendix: CGM Practical Aspects
Practical Aspects For The PLL Usage
feature even in manual bandwidth control, offering then to the
application software the same flexibility for the clocking control as the
automatic mode.
21.4.3 Filter Components Selection Guide
21.4.3.1 Equations Set
Freescale Semiconductor, Inc...
These equations can be used to select a set of filter components. Two
cases are considered:
1. The ‘tracking’ mode. This situation is reached normally when the
PLL operates in automatic bandwidth selection mode (AUTO=1 in
the PLLCR register).
2. The ‘acquisition’ mode. This situation is reached when the PLL
operates in manual bandwidth selection mode and forced
acquisition (AUTO=0, ACQ=0 in the PLLCR register).
In both equations, the power supply should be 5V. Start with the target
loop bandwidth as a function of the other parameters, but obviously,
nothing prevents the user from starting with the capacitor value for
example. Also, remember that the smoothing capacitor is always
assumed to be one tenth of the series capacitance value.
So with:
m:
R:
C:
Fbus:
ζ:
Fc:
the multiplying factor for the reference frequency (i.e. (synr+1))
the series resistance of the low pass filter in Ω
the series capacitance of the low pass filter in nF
the target bus frequency expressed in MHz
the desired damping factor
the desired loop bandwidth expressed in Hz
for the ‘tracking’ mode:
9
2
– F bus⎞
⎛ 1.675
---------------------------⎝ 10.795 ⎠
2 ⋅ 10 ⋅ ζ
37.78 ⋅ e
⋅R
F c = ------------------------- = -----------------------------------------------------π⋅R⋅C
2⋅π⋅m
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and for the ‘acquisition’ mode:
9
2
– F bus⎞
⎛ 1.675
---------------------------⎝ 10.795 ⎠
2 ⋅ 10 ⋅ ζ
415.61 ⋅ e
⋅R
F c = ------------------------- = --------------------------------------------------------π⋅R⋅C
2⋅π⋅m
21.4.3.2 Particular Case of an 8MHz Synthesis
Freescale Semiconductor, Inc...
Assume that a desired value for the damping factor of the second order
system is close to 0.9 as this leads to a satisfactory transient response.
Then, derived from the equations above, Table 21-1 and Table 21-2
suggest sets of values corresponding to several loop bandwidth
possibilities in the case of an 8MHz synthesis for the two cases
mentioned above.
The filter components values are chosen from standard series (e.g. E12
for resistors). The operating voltage is assumed to be 5V (although there
is only a minor difference between 3V and 5V operation). The smoothing
capacitor Cp in parallel with R0 and C0 is set to be 1/10 of the value of
C0. The reference frequencies mentioned in this table correspond to the
output of the fine granularity divider controlled by the REFDV register.
This means that the calculations are irrespective of the way the
reference frequency is generated (directly for the crystal oscillator or
after division). The target frequency value also has an influence on the
calculations of the filter components because the VCO gain is NOT
constant over its operating range.
The bandwidth limit corresponds to the so-called Gardner’s criteria. It
corresponds to the maximum value that can be chosen before the
continuous time approximation ceases to be justified. It is of course
advisable to stay far away from this limit.
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Appendix: CGM Practical Aspects
Practical Aspects For The PLL Usage
Table 21-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode)
Reference [MHz]
SYNR
Fbus [MHz]
C0 [nF]
R0 [kΩ]
Cp [nF]
Loop
Bandwidth
[kHz]
Bandwidth
Limit [kHz]
0.614
$0C
7.98
100
4.3
10
1.1
157
0.614
$0C
7.98
4.7
20
0.47
5.3
157
0.614
$0C
7.98
1.0
43
0.1
11.5
157
0.614
$0C
7.98
0.33
75
0.033
20
157
0.8
$09
8.00
220
2.7
22
0.9
201
0.8
$09
8.00
10
12
1.0
4.2
201
0.8
$09
8.00
2.2
27
0.22
8.6
201
0.8
$09
8.00
0.47
56
0.047
19.2
201
1
$07
8.00
220
2.4
22
1
251
1
$07
8.00
10
11
1.0
4.7
251
1
$07
8.00
2.2
24
0.22
9.9
251
1
$07
8.00
0.47
51
0.047
21.4
251
1.6
$05
8.00
330
1.5
33
1
402
1.6
$05
8.00
10
9.1
1.0
5.9
402
1.6
$05
8.00
3.3
15
0.33
10.2
402
1.6
$05
8.00
1.0
27
0.1
18.6
402
2
$03
8.00
470
1.1
47
0.96
502
2
$03
8.00
22
5.1
2.2
4.4
502
2
$03
8.00
4.7
11
0.47
9.6
502
2
$03
8.00
1.0
24
0.1
20.8
502
2.66
$02
8.00
220
1.5
22
1.6
668
2.66
$02
8.00
22
4.7
2.2
5.1
668
2.66
$02
8.00
4.7
10
0.47
11
668
2.66
$02
8.00
1.0
22
0.1
24
668
4
$01
8.00
220
1.2
22
1.98
1005
4
$01
8.00
33
3
3.3
5.1
1005
4
$01
8.00
10
5.6
1.0
9.3
1005
4
$01
8.00
2.2
12
0.22
19.8
1005
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Table 21-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode)
Reference
[MHz]
SYNR
Fbus [MHz]
C0 [nF]
R0 [kΩ]
Cp [nF]
Loop
Bandwidth
[kHz]
Bandwidth
Limit [kHz]
0.614
$0C
7.98
1000
0.43
100
1.2
157
0.614
$0C
7.98
47
2
4.7
5.5
157
0.614
$0C
7.98
10
4.3
1.0
12
157
0.614
$0C
7.98
3.3
7.5
0.33
21
157
0.8
$09
8.00
2200
0.27
220
0.9
201
0.8
$09
8.00
100
1.2
10
4.4
201
0.8
$09
8.00
22
2.4
2.2
9.3
201
0.8
$09
8.00
4.7
5.6
0.47
20.1
201
1
$07
8.00
2200
0.22
220
1
251
1
$07
8.00
100
1.0
10
4.8
251
1
$07
8.00
2.
2.2
2.2
10.4
251
1
$07
8.00
4.7
4.7
0.47
22.5
251
1.6
$05
8.00
3300
0.15
330
1.1
402
1.6
$05
8.00
100
0.82
10
6.2
402
1.6
$05
8.00
33
1.5
3.3
10.7
402
1.6
$05
8.00
10
2.7
1.0
19.5
402
2
$03
8.00
4700
0.1
470
1
502
2
$03
8.00
220
0.51
22
4.6
502
2
$03
8.00
47
1.0
4.7
10
502
2
$03
8.00
10
2.4
1.0
21.8
502
2.66
$02
8.00
2200
0.12
220
1.7
668
2.66
$02
8.00
220
0.43
22
5.3
668
2.66
$02
8.00
47
1.0
4.7
11.6
668
2.66
$02
8.00
10
2
1.0
25.1
668
4
$01
8.00
2200
0.1
220
2.1
1005
4
$01
8.00
330
0.27
33
5.4
1005
4
$01
8.00
100
0.51
10
9.7
1005
4
$01
8.00
22
1.0
2.2
20.8
1005
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Printed Circuit Board Guidelines
21.5 Printed Circuit Board Guidelines
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Printed Circuit Boards (PCBs) are the board of choice for volume
applications. If designed correctly, a very low noise system can be built
on a PCB with consequently good EMI/EMC performances. If designed
incorrectly, PCBs can be extremely noisy and sensitive modules, and
the CGM could be disrupted. Some common sense rules can be used to
prevent such problems.
•
Use a ‘star’ style power routing plan as opposed to a ‘daisy chain’.
Route power and ground from a central location to each chip
individually, and use the widest trace practical (the more the chip
draws current, the wider the trace). NEVER place the MCU at the
end of a long string of serially connected chips.
•
When using PCB layout software, first direct the routing of the
power supply lines as well as the CGM wires (crystal oscillator and
PLL). Layout constraints must be then reported on the other
signals and not on these ‘hot’ nodes. Optimizing the ‘hot’ nodes at
the end of the routing process usually gives bad results.
•
Avoid notches in power traces. These notches not only add
resistance (and are not usually accounted for in simulations), but
they can also add unnecessary transmission line effects.
•
Avoid ground and power loops. This has been one of the most
violated guidelines of PCB layout. Loops are excellent noise
transmitters and can be easily avoided. When using multiple layer
PCBs, the power and ground plane concept works well but only
when strictly adhered to (do not compromise the ground plane by
cutting a hole in it and running signals on the ground plane layer).
Keep the spacing around via holes to a minimum (but not so small
as to add capacitive effects).
•
Be aware of the three dimensional capacitive effects of multilayered PCBs.
•
Bypass (decouple) the power supplies of all chips as close to the
chip as possible. Use one decoupling capacitor per power supply
pair (VDD/VSS, VDDX/VSSX...). Two capacitors with a ratio of
about 100 sometimes offer better performances over a broader
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spectrum. This is especially the case for the power supply pins
close to the E port, when the E clock and/or the calibration clock
are used.
•
On the general VDD power supply input, a ‘T’ low pass filter LCL
can be used (e.g. 10µH-47µF-10µH). The ‘T’ is preferable to the
‘Π’ version as the exhibited impedance is more constant with
respect to the VDD current. Like many modular micro controllers,
HC12 devices have a power consumption which not only varies
with clock edges but also with the functioning modes.
•
Keep high speed clock and bus trace length to a minimum. The
higher the clock speed, the shorter the trace length. If noisy
signals are sent over long tracks, impedance adjustments should
be considered at both ends of the line (generally, simple resistors
suffice).
•
Bus drivers like the CAN physical interface should be installed
close to their connector, with dedicated filtering on their power
supply.
•
Mount components as close to the board as possible. Snip excess
lead length as close to the board as possible. Preferably use
Surface Mount Devices (SMDs).
•
Mount discrete components as close to the chip that uses them as
possible.
•
Do not cross sensitive signals ON ANY LAYER. If a sensitive
signal must be crossed by another signal, do it as many layers
away as possible and at right angles.
•
Always keep PCBs clean. Solder flux, oils from fingerprints,
humidity and general dirt can conduct electricity. Sensitive circuits
can easily be disrupted by small amounts of leakage.
•
Choose PCB coatings with care. Certain epoxies, paints, gelatins,
plastics and waxes can conduct electricity. If the manufacturer
cannot provide the electrical characteristics of the substance, do
not use it.
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Printed Circuit Board Guidelines
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In addition to the above general pieces of advice, the following
guidelines should be followed for the CGM pins (but also more generally
for any sensitive analog circuitry):
•
Parasitic capacitance on EXTAL is absolutely critical – probably
the most critical layout consideration. The XTAL pin is not as
sensitive. All routing from the EXTAL pin through the resonator
and the blocking cap to the actual connection to VSS must be
considered.
•
For minimum capacitance there should ideally be no ground /
power plane around the EXTAL pin and associated routing.
However, practical EMC considerations obviously should be taken
into consideration for each application.
•
The clock input circuitry is sensitive to noise so excellent supply
routing and decoupling is mandatory. Connect the ground point of
the oscillator circuit directly to the VSSPLL pin.
•
Good isolation of PLL / Oscillator Power supply is critical. Use
1nF+ 100nF and keep tracks as low impedance as possible
•
Load capacitors should be low leakage and stable across
temperature – use NPO or C0G types.
•
The load capacitors may ‘pull’ the target frequency by a few ppm.
Crystal manufacturer specs show symmetrical values but the
series device capacitance on EXTAL and XTAL are not
symmetrical. It may be possible to adjust this by changing the
values of the load capacitors – start-up conditions should be
evaluated.
•
Keep the adjacent Port H / Port E and RESET signals noise free.
Don’t connect these to external signals and / or add series filtering
– a series resistor is probably adequate.
•
Any DC-blocking capacitor should be as low ESR as possible – for
the range of crystals we are looking at anything over 1 Ohm is too
much.
•
Mount oscillator components on MCU side of board – avoid using
vias in the oscillator circuitry.
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•
Mount the PLL filter and oscillator components as close to the
MCU as possible.
•
Do not allow the EXTAL and XTAL signals to interfere with the
XFC node. Keep these tracks as short as possible.
•
Do not cross the CGM signals with any other signal on any level.
•
Remember that the reference voltage for the XFC filter is
VDDPLL.
•
As the return path for the oscillator circuitry is VSSPLL, it is
extremely important to CONNECT VSSPLL to VSS even if the
PLL is not to be powered. Surface mount components reduce the
susceptibility of signal contamination.
•
Ceramic resonators with built-in capacitors are available. This is
an interesting solution because the parasitic components involved
are minimized due to the close proximity of the resonating
elements.
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Section 22. Appendix: 68HC912D60A Flash EEPROM
22.1 Contents
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
22.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
22.4
Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .400
22.5
Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
22.6
Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
22.7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
22.8
Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 404
22.9
Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 405
22.10 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
22.2 Introduction
The two Flash EEPROM modules (32-Kbyte and 28-Kbyte) for the
68HC912D60A serve as electrically erasable and programmable, nonvolatile ROM emulation memory. The modules can be used for program
code that must either execute at high speed or is frequently executed,
such as operating system kernels and standard subroutines, or they can
be used for static data which is read frequently. The Flash EEPROM is
ideal for program storage for single-chip applications allowing for field
reprogramming.
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22.3 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may
be read as either bytes, aligned words or misaligned words. Access time
is one bus cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
Programming is by aligned word. The Flash EEPROM module supports
bulk erase only.
Each Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and programprotected 8-Kbyte block for boot routines is located at $6000–$7FFF or
$E000–$FFFF depending upon the mapped location of the Flash
EEPROM arrays.
22.4 Flash EEPROM Control Block
A 4-byte register block for each module controls the Flash EEPROM
operation. Configuration information is specified and programmed
independently from the contents of the Flash EEPROM array. At reset,
the 4-byte register section starts at address $00F4/$00F8.
22.5 Flash EEPROM Arrays
After reset, the 32K Flash EEPROM array is located from addresses
$8000 to $FFFF and the 28K Flash EEPROM array is from $1000 to
$7FFF. In expanded modes, the Flash EEPROM arrays are turned off.
The Flash EEPROM can be mapped to an alternate address range. See
Operating Modes and Resource Mapping.
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Flash EEPROM Registers
22.6 Flash EEPROM Registers
FEE32LCK/FEE28LCK — Flash EEPROM Lock Control Register
RESET:
$00F4/$00F8
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
LOCK
0
0
0
0
0
0
0
0
In normal modes the LOCK bit can only be written once after reset.
LOCK — Lock Register Bit
0 = Enable write to FEEMCR register
1 = Disable write to FEEMCR register
FEE32MCR/FEE28MCR — Flash EEPROM Module Configuration Register
RESET:
$00F5/$00F9
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
BOOTP
0
0
0
0
0
0
0
1
This register controls the operation of the Flash EEPROM array. BOOTP
cannot be changed when the LOCK control bit in the FEELCK register is
set or if ENPE in the FEECTL register is set.
BOOTP — Boot Protect
The boot blocks are located at $6000–$7FFF and $E000–$FFFF for
each Flash EEPROM module.
0 = Enable erase and program of 8K byte boot block
1 = Disable erase and program of 8K byte boot block
FEE32CTL/FEE28CTL — Flash EEPROM Control Register
RESET:
$00F7/$00FB
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
FEESWAI
HVEN
0
ERAS
PGM
0
0
0
0
0
0
0
0
This register controls the programming and erasure of the Flash
EEPROM.
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FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait
mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
HVEN — High-Voltage Enable
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This bit enables the charge pump to supply high voltages for program
and erase operations in the array. HVEN can only be set if either PGM
or ERAS are set and the proper sequence for program or erase is
followed.
0 = Disables high voltage to array and charge pump off
1 = Enables high voltage to array and charge pump on
ERAS — Erase Control
This bit configures the memory for erase operation. ERAS is
interlocked with the PGM bit such that both bits cannot be equal to 1
or set to1 at the same time.
0 = Erase operation is not selected.
1 = Erase operation selected.
PGM — Program Control
This bit configures the memory for program operation. PGM is
interlocked with the ERAS bit such that both bits cannot be equal to 1
or set to1 at the same time.
0 = Program operation is not selected.
1 = Program operation selected.
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Operation
22.7 Operation
The Flash EEPROM can contain program and data. On reset, it can
operate as a bootstrap memory to provide the CPU with internal
initialization information during the reset sequence.
22.7.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by
fetching the first program address from address $FFFE.
22.7.2 Normal Operation
The Flash EEPROM allows a byte or aligned word read in one bus cycle.
Misaligned word read require an additional bus cycle. The Flash
EEPROM array responds to read operations only. Write operations are
ignored.
22.7.3 Program/Erase Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit
must be programmed to change its state from one to zero. Erasing a bit
returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash
EEPROM is accomplished by a series of control register writes.
Programming is restricted to aligned word at a time as determined by
internal signal SZ8 and ADDR[0]. The Flash EEPROM must first be
completely erased prior to programming final data values.
Programming and erasing of Flash locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tFPGM maximum (40µs).
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22.8 Programming the Flash EEPROM
Programming the Flash EEPROM is done on a row basis. A row consists
of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80
and $XXC0. Use this step-by-step procedure to program a row of Flash
memory.
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1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Write to any Flash address with any data within the row address
range desired.
3. Wait for a time, tNVS (min. 10µs).
4. Set the HVEN bit.
5. Wait for a time, tPGS (min. 5µs).
6. Write to the Flash address with data to the word desired to be
programmed. If BOOTP is asserted, an attempt to program an
address in the boot block will be ignored.
7. Wait for a time, tFPGM (min. 30µs).
8. Repeat steps 6 and 7 until all the words within the row are
programmed.
9. Clear the PGM bit.
10. Wait for a time, tNVH (min. 5µs).
11. Clear the HVEN bit.
12. After time, tRCV (min 1µs), the memory can be accessed in read
mode again.
This program sequence is repeated throughout the memory until all data
is programmed. For minimum overall programming time and least
program disturb effect, the sequence should be part of an intelligent
operation which iterates per row.
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22.9 Erasing the Flash EEPROM
The following sequence demonstrates the recommended procedure for
erasing any of the Flash EEPROM array.
1. Set the ERAS bit.
2. Write to any valid address in the Flash array. The data written and
the address written are not important. The boot block will be
erased only if the control bit BOOTP is negated.
3. Wait for a time, tNVS (min. 10µs).
4. Set the HVEN bit.
5. Wait for a time, tERAS (min. 8ms).
6. Clear the ERAS bit.
7. Wait for a time, tNVHL (min. 100µs).
8. Clear the HVEN bit.
9. After time, tRCV (min 1µs), the memory can be accessed in read
mode again.
22.10 Stop or Wait Mode
When stop or wait commands are executed, the MCU puts the Flash
EEPROM in stop or wait mode. In these modes the Flash module will
cease erasure or programming immediately.
CAUTION:
It is advised not to enter stop or wait modes when program or erase
operation of the Flash array is in progress.
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Section 23. Appendix: 68HC912D60A EEPROM
23.1 Contents
23.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
23.3
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .408
23.4
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 409
23.5
Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .415
23.6
Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
23.7
Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 416
23.2 Introduction
The 68HC912D60A EEPROM nonvolatile memory is arranged in a 16bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in normal modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the
internal VDD supply with an internal charge pump.
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23.3 EEPROM Programmer’s Model
The EEPROM module consists of two separately addressable sections.
The first is an eight-byte memory mapped control register block used for
control, testing and configuration of the EEPROM array. The second
section is the EEPROM array itself.
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At reset, the eight-byte register section starts at address $00EC and the
EEPROM array is located from addresses $0C00 to $0FFF. Registers
$00EC-$00ED are reserved.
Read/write access to the memory array section can be enabled or
disabled by the EEON control bit in the INITEE register ($0012). This
feature allows the access of memory mapped resources that have lower
priority than the EEPROM memory array. EEPROM control registers can
be accessed regardless of the state of EEON. For information on remapping the register block and EEPROM address space, refer to
Operating Modes and Resource Mapping.
CAUTION:
It is strongly recommended to discontinue program/erase operations
during WAIT (when EESWAI=1) or STOP modes since all
program/erase activities will be terminated abruptly and considered
unsuccessful.
For lowest power consumption during WAIT mode, it is advised to turn
off EEPGM.
The EEPROM module contains an extra word called SHADOW word
which is loaded at reset into the EEMCR, EEDIVH and EEDIVL
registers. To program the SHADOW word, when in special modes
(SMODN=0), the NOSHW bit in EEMCR register must be cleared.
Normal programming routines are used to program the SHADOW word
which becomes accessible at address $0FC0-$0FC1 when NOSHW is
cleared. At the next reset the SHADOW word data is loaded into the
EEMCR, EEDIVH and EEDIVL registers. The SHADOW word can be
protected from being programmed or erased by setting the SHPROT bit
of EEPROT register.
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EEPROM Control Registers
A steady internal self-time clock is required to provide accurate counts
to meet EEPROM program/erase requirements. This clock is generated
via a programmable 10-bit prescaler register. Automatic program/erase
termination is also provided.
In ordinary situations, with crystal operating properly, the steady internal
self-time clock is derived from the input clock source (EXTALi). The
divider value is as in EEDIVH:EEDIVL. In limp-home mode, where the
oscillator clock has malfunctioned or is unavailable, the self-time clock is
derived from the PLL with approximately 1 MHz frequency, with a
predefined divider value of $0023. Program/erase operation is not
guaranteed in limp-home mode. The clock switching function is only
applicable for permanent loss of crystal condition, so the program/erase
will also not be guaranteed when the loss of crystal condition is
intermittent.
It is strongly recommended that the clock monitor is enabled to ensure
that the program/erase operation will be shutdown in the event of loss of
crystal with a clock monitor reset, or switch to a limp-home mode clock.
This will prevent unnecessary stress on the emulated EEPROM during
oscillator failure.
23.4 EEPROM Control Registers
EEDIVH — EEPROM Modulus Divider
Bit 7
0
0
RESET:
6
0
0
$00EE
5
0
0
4
0
0
3
0
0
2
0
0
1
EEDIV9
—(1)
Bit 0
EEDIV8
—(1)
1. Loaded from SHADOW word.
EEDIVL — EEPROM Modulus Divider
RESET:
Bit 7
EEDIV7
—(1)
6
EEDIV6
—(1)
5
EEDIV5
—(1)
$00EF
4
EEDIV4
—(1)
3
EEDIV3
—(1)
2
EEDIV2
—(1)
1
EEDIV1
—(1)
Bit 0
EEDIV0
—(1)
1. Loaded from SHADOW word.
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EEDIV[9:0] — Prescaler divider
Loaded from SHADOW word at reset.
Read anytime. Write once in normal modes (SMODN =1) if EELAT =
0 and anytime in special modes (SMODN =0) if EELAT = 0.
The prescaler divider is required to produce a self-time clock with a
fixed frequency around 28.6 Khz for the range of oscillator
frequencies. The divider is set so that the oscillator frequency can be
divided by a divide factor that can produce a 35 µs +/- 2µs pulse.
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CAUTION:
An incorrect or uninitialized value on EEDIV can result in overstress of
EEPROM array during program/erase operation. It is also strongly
recommend not to program EEPROM with oscillator frequencies less
than 250 Khz.
The EEDIV value is determined by the following formula:
–6
EEDIV = INT [ EXTALi (hz) x 35 ×10
NOTE:
+ 0.5 ]
INT[A] denotes the round down integer value of A. Program/erase cycles
will not be activated when EEDIV = 0.
Table 23-1. EEDIV Selection
Osc Freq.
16 Mhz
8 Mhz
4 Mhz
2 Mhz
1 Mhz
500 Khz
250 Khz
Osc Period
62.5ns
125ns
250ns
500ns
1µs
2µs
4µs
Divide Factor
560
280
140
70
35
18
9
EEDIV
$0230
$0118
$008C
$0046
$0023
$0012
$0009
EEMCR — EEPROM Module Configuration
Bit 7
RESET:
6
NOBDML
NOSHW
—(2)
—(2)
5
$00F0
4
3
2
1
Bit 0
(1)
1
EESWAI
PROTLCK
DMY
1
1
0
0
RESERVED
—(2)
—(2)
1. Bits 4 and 5 have test functions and should not be programmed.
2. Loaded from SHADOW word.
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EEPROM Control Registers
Bits[7:4] are loaded at reset from the EEPROM SHADOW word.
NOTE:
The bits 5 and 4 are reserved for test purposes. These locations in
SHADOW word should not be programmed otherwise some locations of
regular EEPROM array will not be visible.
NOBDML — Background Debug Mode Lockout Disable
0 = The BDM lockout is enabled.
1 = The BDM lockout is disabled.
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Loaded from SHADOW word at reset.
Read anytime. Write anytime in special modes (SMODN=0).
NOSHW — SHADOW Word Disable
0 = The SHADOW word is enabled and accessible at address
$0FC0-$0FC1.
1 = Regular EEPROM array at address $0FC0-$0FC1.
Loaded from SHADOW word at reset.
Read anytime. Write anytime in special modes (SMODN=0).
When NOSHW cleared, the regular EEPROM array bytes at address
$0FC0 and $0FC1 are not visible. The SHADOW word is accessed
instead for both read and program/erase operations. Bits[7:4] from
the high byte of the SHADOW word, $0FC0, are loaded to
EEMCR[7:4]. Bits[1:0] from the high byte of the SHADOW word,
$0FC0,are loaded to EEDIVH[1:0]. Bits[7:0] from the low byte of the
SHADOW word, $0FC1,are loaded to EEDIVL[7:0]. BULK
program/erase only applies if SHADOW word is enabled.
NOTE:
Bit 6 from high byte of SHADOW word should not be cleared (set to '0')
in order to have the full EEPROM array visible. If Bit 6 from the high byte
of the SHADOW word is cleared then the following thirty bytes
$0FC2–$0FFF have no meaning and are reserved by Motorola.
EESWAI — EEPROM Stops in Wait Mode
0 = The module is not affected during WAIT mode
1 = The module ceases to be clocked during WAIT mode
Read and write anytime.
NOTE:
The EESWAI bit should be cleared if the WAIT mode vectors are
mapped in the EEPROM array.
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PROTLCK — Block Protect Write Lock
0 = Block protect bits and bulk erase protection bit can be written
1 = Block protect bits are locked
Read anytime. Write once in normal modes (SMODN = 1), set and
clear any time in special modes (SMODN = 0).
DMY— Dummy bit
Read and write anytime.
EEPROT — EEPROM Block Protect
RESET:
Bit 7
SHPROT
1
6
1
1
$00F1
5
BPROT5
1
4
BPROT4
1
3
BPROT3
1
2
BPROT2
1
1
BPROT1
1
Bit 0
BPROT0
1
Prevents accidental writes to EEPROM. Read anytime. Write anytime if
EEPGM = 0 and PROTLCK = 0.
SHPROT — SHADOW Word Protection
0 = The SHADOW word can be programmed and erased.
1 = The SHADOW word is protected from being programmed and
erased.
BPROT[5:0] — EEPROM Block Protection
0 = Associated EEPROM block can be programmed and erased.
1 = Associated EEPROM block is protected from being
programmed and erased.
Table 23-22. K byte EEPROM Block Protection
Bit Name
BPROT5
BPROT4
BPROT3
BPROT2
BPROT1
BPROT0
Block Protected
$0800 to $0BFF
$0C00 to $0DFF
$0E00 to $0EFF
$0F00 to $0F7F
$0F80 to $0FBF
$0FC0 to $0FFF
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Block Size
1024 Bytes
512 Bytes
256 Bytes
128 Bytes
64 Bytes
64 Bytes
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EEPROM Control Registers
.
EEPROG — EEPROM Control
RESET:
Bit 7
BULKP
1
6
0
0
$00F3
5
AUTO
0
4
BYTE
0
3
ROW
0
2
ERASE
0
1
EELAT
0
Bit 0
EEPGM
0
BULKP — Bulk Erase Protection
0 = EEPROM can be bulk erased.
1 = EEPROM is protected from being bulk or row erased.
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Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.
AUTO — Automatic shutdown of program/erase operation.
EEPGM is cleared automatically after the program/erase cycles are
finished when AUTO is set.
0 = Automatic clear of EEPGM is disabled.
1 = Automatic clear of EEPGM is enabled.
Read anytime. Write anytime if EEPGM = 0.
BYTE — Byte and Aligned Word Erase
0 = Bulk or row erase is enabled.
1 = One byte or one aligned word erase only.
Read anytime. Write anytime if EEPGM = 0.
ROW — Row or Bulk Erase (when BYTE = 0)
0 = Erase entire EEPROM array.
1 = Erase only one 32-byte row.
Read anytime. Write anytime if EEPGM = 0.
BYTE and ROW have no effect when ERASE = 0
Table 23-3. Erase Selection
BYTE
0
0
1
1
ROW
0
1
0
1
Block size
Bulk erase entire EEPROM array
Row erase 32 bytes
Byte or aligned word erase
Byte or aligned word erase
If BYTE = 1 only the location specified by the address written to the
programming latches will be erased. The operation will be a byte or
an aligned word erase depending on the size of written data.
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ERASE — Erase Control
0 = EEPROM configuration for programming.
1 = EEPROM configuration for erasure.
Read anytime. Write anytime if EEPGM = 0.
Configures the EEPROM for erasure or programming.
Unless BULKP is set, erasure is by byte, aligned word, row or bulk.
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EELAT — EEPROM Latch Control
0 = EEPROM set up for normal reads.
1 = EEPROM address and data bus latches set up for
programming or erasing.
Read anytime.
Write anytime except when EEPGM = 1 or EEDIV = 0.
BYTE, ROW, ERASE and EELAT bits can be written simultaneously
or in any sequence.
EEPGM — Program and Erase Enable
0 = Disables program/erase voltage to EEPROM.
1 = Applies program/erase voltage to EEPROM.
The EEPGM bit can be set only after EELAT has been set. When
EELAT and EEPGM are set simultaneously, EEPGM remains clear
but EELAT is set.
The BULKP, AUTO, BYTE, ROW, ERASE and EELAT bits cannot be
changed when EEPGM is set. To complete a program or erase cycle
when AUTO bit is clear, two successive writes to clear EEPGM and
EELAT bits are required before reading the programmed data. When
AUTO bit is set, EEPGM is automatically cleared after the program or
erase cycle is over. A write to an EEPROM location has no effect
when EEPGM is set. Latched address and data cannot be modified
during program or erase.
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Program/Erase Operation
23.5 Program/Erase Operation
A program or erase operation should follow the sequence below if AUTO
bit is clear:
1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1
2. Write a byte or an aligned word to an EEPROM address
3. Write EEPGM = 1
4. Wait for programming, tPROG or erase, tERASE delay time (10ms)
5. Write EEPGM = 0
6. Write EELAT = 0
If AUTO bit is set, steps 4 and 5 can be replaced by a step to poll the
EEPGM bit until is cleared.
It is possible to program/erase more bytes or words without intermediate
EEPROM reads, by jumping from step 5 to step 2.
23.6 Shadow Word Mapping
The shadow word is mapped to location $_FC0 and $_FC1 when the
NOSHW bit in EEMCR register is zero. The value in the shadow word is
loaded to the EEMCR, EEDIVH and EEDIVL after reset. Table 23-4
shows the mapping of each bit from shadow word to the registers
Table 23-4. Shadow word mapping
Shadow word location
Register / Bit
$_FC0 bit 7
EEMCR / NOBDML
$_FC0, bit 6
EEMCR / NOSHW
$_FC0, bit 5
EEMCR / bit 5(1)
$_FC0, bit 4
EEMCR / bit 4(1)
$_FC0, bit 3:2
not mapped(2))
$_FC0, bit 1:0
EEDIVH / bit 1:0
$_FC1, bit 7:0
EEMCR / bit 7:0
1. Reserved for testing. Must be set to one in user application.
2. Reserved. Must be set to one in user application for future compatibility.
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23.7 Programming EEDIVH and EEDIVL Registers
The EEDIVH and EEDIVL registers must be correctly set according to
the oscillator frequency before any EEPROM location can be
programmed or erased.
23.7.1 Normal mode
The EEDIVH and EEDIVL registers are write once in normal mode.
Upon system reset, the application program is required to write correct
divider value to EEDIVH and EEDIVL registers based on the oscillator
frequency. After the first write, the value in the EEDIVH and EEDIVL
registers is locked from been overwritten until the next reset. The
EEPROM is then ready for standard program/erase routines.
CAUTION:
Runaway code can possibly corrupt the EEDIVH and EEDIVL registers
if they are not initialized for the write once.
23.7.2 Special mode
If an existing application code with EEPROM program/erase routines is
already fixed and the system is already operating at a known oscillator
frequency, it is recommended to initialize the shadow word with the
corresponding EEDIVH and EEDIVL values in special mode. The
shadow word initializes EEDIVH and EEDIVL registers upon system
reset to ensure software compatibility with existing code. Initializing the
EEDIVH and EEDIVL registers in special modes (SMODN=0) is
accomplished by the following steps.
1. Write correct divider value to EEDIVH and EEDIVL registers
based on the oscillator frequency as per Table17.
2. Remove the SHADOW word protection by clearing SHPROT bit in
EEPROT register.
3. Clear NOSHW bit in EEMCR register to make the SHADOW word
visible at $0FC0-$0FC1.
4. Write NOSHW bit in EEMCR register to make the SHADOW word
visible at $0FC0-$0FC1.
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Programming EEDIVH and EEDIVL Registers
5. Program bits 1 and 0 of the high byte of the SHADOW word and
bits 7 to 0 of the low byte of the SHADOW word like a regular
EEPROM location at address $0FC0 and $0FC1. Do not program
other bits of the high byte of the SHADOW word (location $0FC0);
otherwise some regular EEPROM array locations will not be
visible. At the next reset, the SHADOW values are loaded into the
EEDIVH and EEDIVL registers. They do not require further
initialization as long as the oscillator frequency of the target
application is not changed.
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6. Protect the SHADOW word by setting SHPROT bit in EEPROT
register.
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Glossary
A — See “accumulators (A and B or D).”
accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers
in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic
and logic operations.
acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking
mode’.
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC12 CPU has 15 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
analogue-to-digital converter (ATD) — The ATD module is an 8-channel, multiplexed-input
successive-approximation analog-to-digital converter.
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
ATD — See “analogue-to-digital converter”.
B — See “accumulators (A and B or D).”
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
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binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — The break module allows software to halt program execution at a
programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — See "CPU clock".
byte — A set of eight bits.
CAN — See "Motorola scalable CAN."
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — The CGM module generates a base clock signal from which
the system clocks are derived. The CGM may include a crystal oscillator circuit and/or
phase-locked loop (PLL) circuit.
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
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computer operating properly module (COP) — A counter module that resets the MCU if
allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask
bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
CPU — See “central processor unit (CPU).”
CPU12 — The CPU of the MC68HC12 Family.
CPU clock — Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL)
determine which clock drives SYSCLK for the main system, including the CPU and buses.
When EXTALi drives the SYSCLK, the CPU or bus clock frequency (fo) is equal to the
EXTALi frequency divided by 2.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC12 are:
•
A (8-bit accumulator)
•
B (8-bit accumulator)
–
D (16-bit accumulator formed by concatenation of accumulators A and B)
•
IX (16-bit index register)
•
IY (16-bit index register)
•
SP (16-bit stack pointer)
•
PC (16-bit program counter)
•
CCR (8-bit condition code register)
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cycle time — The period of the operating frequency: tCYC = 1/fOP.
D — See “accumulators (A and B or D).”
decimal number system — Base 10 numbering system that uses the digits zero through nine.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
ECT — See “enhanced capture timer.”
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically erased and reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features
of the HC12 Standard Timer module enhanced by additional features in order to enlarge
the field of applications.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing
modes, the CPU uses the contents of IX or IY to determine the effective address of the
operand. IX and IY can also serve as a temporary data storage locations.
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input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
inter-IC bus (I2C) — A two-wire, bidirectional serial bus that provides a simple, efficient method
of data exchange between devices.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
M68HC12 — A Motorola family of 16-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
MCU — Microcontroller unit. See “microcontroller.”
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memory location — Each M68HC12 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
MI-Bus — See "Motorola interconnect bus".
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
most significant bit (MSB) — The leftmost digit of a binary number.
Motorola interconnect bus (MI-Bus) — The Motorola Interconnect Bus (MI Bus) is a serial
communications protocol which supports distributed real-time control efficiently and with
a high degree of noise immunity.
Motorola scalable CAN (msCAN) — The Motorola scalable controller area network is a serial
communications protocol that efficiently supports distributed real-time control with a very
high level of data integrity.
msCAN — See "Motorola scalable CAN".
MSI — See "multiple serial interface".
multiple serial interface — A module consisting of multiple independent serial I/O sub-systems,
e.g. two SCI and one SPI.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
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operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A clock generator circuit in which a voltage controlled oscillator
produces an oscillation which is synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
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program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the
next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module that supports asynchronous
communication.
serial peripheral interface module (SPI) — A module that supports synchronous
communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
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shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — A mode of PLL operation with narrow loop bandwidth. Also see ‘acquisition
mode.’
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two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
.
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Revision History
This section lists the revision history of the document since the first
release. Data for previous internal drafts is unavailable.
23.8 Changes from Rev 3.0 to Rev 4.0
Section
Page (in Rev 4.0)
Description of change
EEPROM
118, 411
Note referring to bit 6 of the SHADOW byte/word has been modified.
23.9 Changes from Rev 2.0 to Rev 3.0
Section
Page (in Rev 3.0)
Pinout and Signal
Descriptions
Clock Functions
Description of change
43
Ca in Figure 3-5 changed to Cp
45
Note added about consideration of crystal selection due to EMC
emissions
145
Note added about consideration of crystal selection due to EMC
emissions
149
Major rewrite of Limp-Home and Fast STOP Recovery modes.
167
System Clock Frequency Formulae updated for clarification.
169
Figure 12-6 modified for clarification.
172
Figure 12-9 modified for clarification.
291
First two bullets of sleep mode description updated
304
SLPRQ = 1 description updated
MSCAN Controller
68HC(9)12D60 — Rev 4.0
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Revision History
Section
Electrical
Specifications
Appendix: CGM
Practical Aspects
Page (in Rev 3.0)
Description of change
365
Sentence about preliminary status removed
369
Added note about typical values for 2 and 4Hz columns of Table 20-4.
Added note for analog supply current in Table 20-5.
370
Expanded table note 3 to define conditions for accuracy testing.
372
Changes to maximum EEPROM erase and data retention times
374
fXTAL removed
374
Footnote added restricting external oscillator operating frequency to
8MHz when using a quartz crystal
386
Table footnote removed from Table 20-16 regarding VDDPLL
388
Added section on DC bias.
389
Point 3 removed regarding high frequency resonators
392
In paragraph 2, C changed to C0, R changed to R0
393
In Table 21-1
In header, C changed to C0, R changed to R0
Extra column added for Cp
394
In Table 21-2
In header, C changed to C0, R changed to R0
Extra column added for Cp
397
New bullets added
23.10 Changes from Rev 1.0 to Rev 2.0
Section
Page (in Rev 2.0)
Description of change
MSI
230
Clarification of SP0DR register state on reset.
Electrical
Specifications
354
Change to operating conditions of Key Wake-up table.
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68HC(9)12D60 — Rev 4.0
Revision History
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