Samsung K4S160822DT-G/F10 2mx8 sdram 1m x 8bit x 2 banks synchronous dram lvttl Datasheet

K4S160822D
CMOS SDRAM
2Mx8 SDRAM
1M x 8bit x 2 Banks
Synchronous DRAM
LVTTL
Revision 1.0
October 1999
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
Revision History
Revision 1.0 (October 1999)
-2-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
1M x 8Bit x 2 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The K4S160822D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 8 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.
•
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS latency ( 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle(2K/32ms)
ORDERING INFORMATION
Part No.
Max Freq.
K4S160822DT-G/F7
143MHz
K4S160822DT-G/F8
125MHz
K4S160822DT-G/FH
100MHz
K4S160822DT-G/FL
100MHz
K4S160822DT-G/F10
100MHz
Interface Package
LVTTL
44
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
LWE
LDQM
Bank Select
1M x 8
Output Buffer
Sense AMP
Row Decoder
ADD
Row Buffer
Refresh Counter
DQi
Column Decoder
Col. Buffer
LCBR
LRAS
Address Register
CLK
1M x 8
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VSSQ
DQ1
VDDQ
DQ2
VSSQ
DQ3
VDDQ
N.C
N.C
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
N.C/RFU
N.C
DQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
44Pin TSOP (II)
(400mil x 725mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA8
BA
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ 7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
-4-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Note
Input logic high voltage
VIH
2.0
3.0
VDDQ+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current (Inputs)
ILI
-10
-
10
uA
3
input leakage current (I/O pins)
ILO
-10
-
10
uA
3,4
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Symbol
Min
Max
Unit
CCLK
2.5
4.0
pF
CIN
2.5
5.0
pF
Address
CADD
2.5
5.0
pF
DQ0 ~ DQ7
COUT
4.0
6.5
pF
-5-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current in
power-down mode
Symbol
ICC1
ICC2P
ICC2PS
ICC2N
Precharge standby current in
non power-down mode
ICC2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
ICC3NS
Test Condition
CAS
Latency
Burst length = 1
tRC ≥ tRC(min)
Io = 0 mA
Version
-7
-8
-H
-L
-10
100
90
85
85
75
CKE ≤ VIL(max), tCC = 15ns
2
CKE & CLK ≤ VIL(max), tCC = ∞
2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
15
Unit
Note
mA
1
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
5
CKE ≤ VIL(max), tCC = 15ns
3
CKE & CLK ≤ VIL(max), tCC = ∞
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
25
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
15
mA
Io = 0 mA
Page burst
2Banks activated
tCCD = 2CLKs
Operating current
(Burst mode)
ICC4
Refresh current
ICC5
tRC ≥ tRC(min)
Self refresh current
ICC6
CKE ≤ 0.2V
mA
3
120
110
95
95
95
2
95
85
95
85
85
mA
1
mA
2
1
mA
3
250
uA
4
90
80
Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 32ms.
4. K4S160822DT-G**
5. K4S160822DT-F**
-6-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
AC OPERATING TEST CONDITIONS
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Output
Z0 = 50Ω
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-7
-8
-H
-L
-10
Unit
Note
Row active to row active delay
tRRD(min)
14
16
20
20
20
ns
1
RAS to CAS delay
tRCD(min)
20
20
20
20
26
ns
1
Row precharge time
Row active time
tRP(min)
20
20
20
20
26
ns
1
tRAS(min)
48
48
50
50
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
68
68
70
70
80
ns
1
Last data in to row precharge
tRDL(min)
7
8
10
10
12
ns
2
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
CAS latency=3
2
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
-7-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-7
Symbol
Min
CLK cycle time
CAS latency=3
tCC
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
7
-8
Max
Min
1000
10
tSAC
CAS latency=2
tOH
CAS latency=2
8
-H
Max
1000
12
Min
10
-L
Max
1000
10
Min
10
-10
Max
1000
12
Min
10
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
13
6
6
6
6
7
6
6
6
7
8
3
3
3
3
3
3
3
3
3
3
CLK high pulse width
tCH
3
3
3
3
3.5
ns
3
CLK low pulse width
tCL
3
3
3
3
3.5
ns
3
Input setup time
tSS
2
2
2
2
2.5
ns
3
Input hold time
tSH
1
1
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
6
6
6
6
7
6
6
6
7
8
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Output rise time
trh
Measure in linear
region : 1.2V ~1.8V
Output fall time
tfh
Output rise time
Output fall time
Typ
Max
Unit
Notes
1.37
4.37
Volts/ns
4
Measure in linear
region : 1.2V ~1.8V
1.30
3.8
Volts/ns
4
trh
Measure in linear
region : 1.2V ~1.8V
2.8
3.9
5.6
Volts/ns
1,2,3
tfh
Measure in linear
region : 1.2V ~1.8V
2.0
2.9
5.0
Volts/ns
1,2,3
Notes : 1. Output rise and fall time must be guaranteed across VDD and process range.
2. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
3. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
4. Measured into 50pF only, use these values to characterize to.
5. All measurements done with respect to VSS.
-8-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
IBIS SPECIFICATION
66MHz and 100MHz Pull-up
0
IOH Characteristics (Pull-up)
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
100MHz
Max
I (mA)
-2.4
-27.3
-74.1
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
-0.7
-7.5
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
0.5
1
1.5
2
2.5
3
3.5
3
3.5
0
66MHz
Min
I (mA)
-100
-200
mA
Voltage
100MHz
Min
I (mA)
-300
-400
-500
-600
Voltage
IOH Min (100MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz)
66MHz and 100MHz Pull-down
IOL Characteristics (Pull-down)
(V)
0.0
0.4
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
3.45
100MHz
Min
I (mA)
0.0
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
100MHz
Max
I (mA)
0.0
70.2
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
66MHz
Min
I (mA)
0.0
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
250
200
150
mA
Voltage
100
50
0
0
0.5
1
1.5
2
2.5
Voltage
IOL Min (100MHz)
IOL Min (66MHz)
IOL Max (100MHz)
-9-
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
Minimum VDD clamp characteristic
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
mA
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
-3
-2
-1
0
0
-10
-20
mA
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-30
-40
-50
-60
Voltage
I (mA)
- 10
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
K4S160822DT-7
(Unit : Number of clock)
Frequency
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
68ns
48ns
20ns
14ns
20ns
7ns
7ns
7ns
143MHz (7.0ns)
3
10
7
3
2
3
1
1
1
125MHz (8.0ns)
3
9
6
3
2
3
1
1
1
100MHz (10.0ns)
2
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
4
2
2
2
1
1
1
75MHz (13.0ns)
2
6
4
2
2
2
1
1
1
66MHz (15.0ns)
2
5
4
2
1
2
1
1
1
(Unit : Number of clock)
K4S160822DT-8
Frequency
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
68ns
48ns
20ns
16ns
20ns
8ns
8ns
8ns
125MHz (8.0ns)
3
9
6
3
2
3
1
1
1
100MHz (10.0ns)
3
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
4
2
2
2
1
1
1
75MHz (13.0ns)
2
6
4
2
2
2
1
1
1
66MHz (15.0ns)
2
5
4
2
2
2
1
1
1
K4S160822DT-H
(Unit : Number of clock)
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
100MHz (10.0ns)
2
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
5
2
2
2
1
1
1
75MHz (13.0ns)
2
6
4
2
2
2
1
1
1
66MHz (15.0ns)
2
5
4
2
2
2
1
1
1
60MHz (16.7ns)
2
5
3
2
2
2
1
1
1
Frequency
(Unit : Number of clock)
K4S160822DT-L
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
100MHz (10.0ns)
3
7
5
2
2
2
1
1
1
83MHz (12.0ns)
2
6
5
2
2
2
1
1
1
75MHz (13.0ns)
2
6
4
2
2
2
1
1
1
66MHz (15.0ns)
2
5
4
2
2
2
1
1
1
60MHz (16.7ns)
2
5
3
2
2
2
1
1
1
Frequency
(Unit : Number of clock)
K4S160822DT-10
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
80ns
50ns
26ns
20ns
26ns
10ns
10ns
12ns
100MHz (10.0ns)
3
8
5
3
2
3
1
1
2
83MHz (12.0ns)
3
7
5
3
2
3
1
1
1
75MHz (13.0ns)
2
7
4
2
2
2
1
1
1
66MHz (15.0ns)
2
6
4
2
2
2
1
1
1
60MHz (16.7ns)
2
5
3
2
2
2
1
1
1
Frequency
- 11
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Auto Refresh
Refresh
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP CODE
L
L
L
H
X
X
H
Entry
Self
Refresh
Exit
H
BA
L
H
L
H
H
H
H
X
X
X
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
Auto Precharge Enable
Precharge
H
X
L
H
L
L
X
H
X
X
L
L
H
L
H
H
L
V
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
Column
Address
(A0~A8)
L
L
X
X
Both Banks
Clock Suspend or
Active Power Down
L
Column
Address
(A0~A8)
H
H
L
DQM
H
No Operation Command
H
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
3
Row Address
H
Auto Precharge Enable
Bank Selection
3
3
X
Burst Stop
1, 2
X
H
Auto Precharge Disable
Note
3
Read &
Column Address
Write &
Column Address
A9~ A0
L
Bank Active & Row Addr.
Auto Precharge Disable
A10/AP
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A10/AP, BA : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
- 12
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
BA
RFU
Address
Function
A10/AP
RFU
A9
W.B.L
A8
A7
A6
TM
Test Mode
CAS Latency
A7
Type
A6
A5
A4
Latency
0
0
Mode Register Set
0
0
0
0
1
Reserved
0
0
0
Reserved
0
1
Reserved
1
Write Burst Length
A3
BT
A2
A1
Burst Length
A0
Burst Length
Burst Type
A8
1
A5
A4
CAS Latency
Type
A2
A1
A0
BT = 0
BT = 1
Reserved
A3
0
Sequential
0
0
0
1
1
1
-
1
Interleave
0
0
1
2
2
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
A9
0
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
Full Page Length : x4 (1024), x8 (512), x16 (256)
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
- 13
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
A2
Initial Address
A1
A0
Sequential
Interleave
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
- 14
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
DEVICE OPERATIONS
CLOCK (CLK)
ADDRESS INPUTS (A0 ~ A10/AP)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and ICC specifications.
: In case x 4
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA during read
or write command.
CLOCK ENABLE (CKE)
: In case x 8
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + tSS" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA during read or write
command.
: In case x 16
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA during read or write
command.
BANK ADDRESS (BA)
NOP and DEVICE DESELECT
: In case x 4
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
This SDRAM is organized as two independent banks of
2,097,152 words x 4 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.
: In case x 8
POWER-UP
This SDRAM is organized as two independent banks of
1,048,576 words x 8 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.
1. Apply power and start clock, Attempt to maintain CKE= "H",
DQM= "H" and the other pins are NOP condition at the
inputs.
2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode
register.
cf.) Sequence of 4 & 5 is regardless of the order.
: In case x 16
This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA input is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank select BA is latched at bank active,
read, write, mode register set and precharge operations.
The device is now ready for normal operation.
- 15
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
DEVICE OPERATIONS (Continued)
MODE REGISTER SET (MRS)
active to initiate sensing and restoring the complete row of
The mode register stores the data for controlling the various
dynamic cells is determined by tRAS(min). Every SDRAM bank
activate command must satisfy tRAS(min) specification before a
operating modes of SDRAM. It programs the CAS latency, burst
precharge command to that active bank can be asserted. The
type, burst length, test mode and various vendor specific options
maximum time any bank can be in the active state is determined
to make SDRAM useful for variety of different applications. The
by tRAS(max). The number of cycles for both tRAS(min) and
default value of the mode register is not defined, therefore the
tRAS(max) can be calculated similar to tRCD specification.
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
BURST READ
RAS, CAS and WE (The SDRAM should be in active mode with
The burst read command is used to access burst of data on con-
CKE already high prior to writing the mode register). The state of
secutive clock cycles from an active row in an active bank. The
address pins A0 ~ A10/AP and BA in the same cycle as CS,
burst read command is issued by asserting low on CS and CAS
RAS, CAS and WE going low is the data written in the mode
with WE being high on the positive edge of the clock. The bank
register. Two clock cycles is required to complete the write in the
must be active for at least tRCD(min) before the burst read com-
mode register. The mode register contents can be changed
mand is issued. The first output appears in CAS latency number
using the same command and clock cycle requirements during
of clock cycles after the issue of burst read command. The burst
operation as long as all banks are in the idle state. The mode
length, burst sequence and latency from the burst read com-
register is divided into various fields depending on the fields of
mand is determined by the mode register which is already pro-
functions. The burst length field uses A0 ~ A2, burst type uses
grammed. The burst read can be initiated on any column
A3, CAS latency (read latency from column address) uses A4 ~
address of the active row. The address wraps around if the initial
A6, vendor specific options or test mode use A7 ~ A8, A10/AP
address does not start from a boundary such that number of out-
and BA. The write burst length is programmed using A9. A7 ~ A8,
puts from each I/O are equal to the burst length programmed in
A10/AP, BA must be set to low for normal SDRAM operation.
the mode register. The output goes into high-impedance at the
Refer to the table for specific codes for various burst length,
end of the burst, unless a new burst read was initiated to keep
burst type and CAS latencies.
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
BANK ACTIVATE
other active bank or a precharge command to the same bank.
The bank activate command is used to select a random row in
The burst stop command is valid at every page burst length.
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
BURST WRITE
operation can occur after a time delay of tRCD(min) from the time
The burst write command is similar to burst read command and
of bank activation. tRCD is an internal timing parameter of
is used to write data into the SDRAM on consecutive clock
SDRAM, therefore it is dependent on operating clock frequency.
cycles in adjacent addresses depending on burst length and
The minimum number of clock cycles required between bank
burst sequence. By asserting low on CS, CAS and WE with valid
activate and read or write command should be calculated by
column address, a write burst is initiated. The data inputs are
dividing tRCD(min) with cycle time of the clock and then rounding
provided for the initial address in the same clock cycle as the
off the result to the next higher integer. The SDRAM has two
burst write command. The input buffer is deselected at the end
internal banks in the same chip and shares part of the internal
of the burst length, even though the internal writing can be com-
circuitry to reduce chip area, therefore it restricts the activation
pleted yet. The writing can be completed by issuing a burst read
of two banks simultaneously. Also the noise generated during
and DQM for blocking data inputs or burst write in the same or
sensing of each bank of SDRAM is high, requiring some time for
another active bank. The burst stop command is valid at every
power supplies to recover before the other bank can be sensed
burst length. The write burst can also be terminated by using
reliably. tRRD(min) specifies the minimum time required between
DQM for blocking data and procreating the bank tRDL after the
activating different bank. The number of clock cycles required
last data input to be written into the active row.
between different bank activation must be calculated similar to
See DQM
OPERATION also.
tRCD specification. The minimum time required for the bank to be
- 16
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
DEVICE OPERATIONS (Continued)
DQM OPERATION
AUTO REFRESH
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.
The storage cells of SDRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by tRFC(min). The minimum number of
clock cycles required can be calculated by driving tRFC with
PRECHARGE
clock cycle time and them rounding up to the next higher integer.
The precharge operation is performed on an active bank by
The auto refresh command must be followed by NOP's until the
asserting low on CS, RAS, WE and A10/AP with valid BA of the
auto refresh operation is completed. Both banks will be in the
bank to be precharged. The precharge command can be
idle state at the end of auto refresh operation. The auto refresh
asserted anytime after tRAS(min) is satisfied from the bank active
is the preferred refresh mode when the SDRAM is being used
command in the desired bank. tRP is defined as the minimum
for normal data transactions. The auto refresh cycle can be per-
number of clock cycles required to complete row precharge is
formed once in 15.6us or a burst of 2048 auto refresh cycles
calculated by dividing tRP with clock cycle time and rounding up
once in 32ms.
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
SELF REFRESH
before precharge command is asserted. The maximum time any
The self refresh is another refresh mode available in the
bank can be active is specified by tRAS(max). Therefore, each
SDRAM. The self refresh is the preferred refresh mode for data
bank activate command. At the end of precharge, the bank
retention and low power operation of SDRAM. In self refresh
enters the idle state and is ready to be activated again. Entry to
mode, the SDRAM disables the internal clock and all the input
Power down, Auto refresh, Self refresh and Mode register set
buffers except CKE. The refresh addressing and timing are
etc. is possible only when both banks are in idle state.
internally generated to reduce power consumption.
AUTO PRECHARGE
The self refresh mode is entered from both banks idle state by
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
asserting low on CS, RAS, CAS and CKE with high on WE.
BOTH BANKS PRECHARGE
auto refresh cycles immediately after exiting in self refresh
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of tRFC before the SDRAM reaches idle state to
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 2048
mode.
Both banks can be precharged at the same time by using precharge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after both banks have satisfied tRAS(min)
requirement, performs precharge on both banks. At the end of
tRP after performing precharge to all the banks, both banks are
in idle state.
- 17
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2) Clock Suspended During Read (BL=4)
1) Clock Suspended During Write (BL=4)
CLK
CMD
WR
RD
CKE
Masked by CKE
Masked by CKE
Internal
CKE
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Q0
D
Q01
Q2
Q3
Q0
Q1
Q2
Not Written
Q3
Suspended Dout
2. DQM Operation
2) Read Mask (BL=4)
1) Write Mask (BL=4)
CLK
CMD
WR
RD
DQM
Masked by DQM
DQ(CL2)
D0
DQ(CL3)
D0
D1
Masked by DQM
D3
D1
Q0
Hi-Z
Hi-Z
D3
DQM to Data-in Mask = 0
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) Note 2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Hi-Z
Q2
Hi-Z
Q1
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
- 18
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
3. CAS Interrupt (I)
Note 1
1) Read interrupted by Read (BL=4)
CLK
CMD
RD
RD
ADD
A
B
DQ(CL2)
QA0
DQ(CL3)
QB0
QB1
QB2
QB3
QA0
QB0
QB1
QB2
QB3
tCCD
Note 2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CMD
WR
WR
tCCD
Note 2
ADD
A
B
DQ
DA0
DB0
tCDL
Note 3
WR
RD
tCCD
A
DB1
Note 2
B
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0
QB1
QB0
QB1
tCDL
Note 3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
- 19
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
3. CAS Interrupt (I)
Note 1
1) Read interrupted by Read (BL=4)
CLK
CMD
RD
RD
ADD
A
B
DQ(CL2)
QA0
DQ(CL3)
QB0
QB1
QB2
QB3
QA0
QB0
QB1
QB2
QB3
tCCD
Note 2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CMD
WR
WR
tCCD
Note 2
ADD
A
B
DQ
DA0
DB0
tCDL
Note 3
WR
RD
tCCD
A
DB1
Note 2
B
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0
QB1
QB0
QB1
tCDL
Note 3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
- 20
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
( Continued )
(b) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
D0
DQ
RD
iii) CMD
WR
DQM
D0
DQ
RD
iii) CMD
WR
DQM
Hi-Z
DQ
D0
RD
iv) CMD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
5. Write Interrupted by Precharge & DQM
CLK
CMD
WR
PRE
Note 2
DQM
DQ
Note 3
D0
D1
D2
D3
Masked by DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only the other bank precharge of dual banks operation.
- 21
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
WR
DQ
D0
PRE
D1
D2
D3
tRDL
Note 2
2) Normal Read (BL=4)
CLK
CMD
RD
PRE
1
DQ(CL2)
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Note 2
DQ(CL3)
Q3
2
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
WR
DQ
D0
D1
D2
D3
Note 3
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Note 3
Auto Precharge Starts
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.
- 22
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
2) Write Burst Stop (BL=8)
CLK
CLK
CMD
WR
CMD
PRE
DQM
WR
STOP
DQM
DQ
D0
D1
D2
DQ
D3
tRDL
D0
D1
D2
D3
Note 1
D4
tBDL
3) Read Interrupted by Precharge (BL=4)
D5
Note 2
4) Read Burst Stop (BL=4)
CLK
CLK
CMD
RD
PRE
DQ(CL2)
Q0
DQ(CL3)
CMD
Q1
Q0
RD
STOP
1
DQ(CL2)
Note 3
2
Q1
DQ(CL3)
Q0
Q1
Q0
1
Note 3
Q1
2
9. MRS
1) Mode Register Set
CLK
Note 4
CMD
MRS
PRE
tRP
ACT
tMRS = 2CLK
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at both banks precharge state.
- 23
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down)
CLK
CLK
CKE
CKE
tSS
Internal
CLK
tSS
Internal
CLK
Note 1
CMD
Note 2
CMD
RD
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh & Self Refresh
Note 3
CLK
¡ó
Note 4
CMD
Note 5
PRE
AR
CMD
¡ó
CKE
¡ó
tRP
2) Self Refresh
tRFC
¡ó
Note 6
CLK
¡ó
Note 4
CMD
PRE
SR
CMD
CKE
¡ó
¡ó
tRP
tRFC
*Note : 1. Active power down : one or both banks active state.
2. Precharge power down : both banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst
auto refresh cycle (2048 cycles) is recommended.
- 24
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
12. About Burst Type Control
Basic
MODE
Random
MODE
Sequential Counting
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page.
Interleave Counting
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010".
8
At MRS A2,1,0 = "011".
Full Page
Special
MODE
BRSW
Random
MODE
Burst Stop
Interrupt
MODE
RAS Interrupt
(Interrupted by Precharge)
CAS Interrupt
At MRS A2,1,0 = "111".
At the end of the burst length, burst will be stop automatically.
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, tRAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
- 25
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Precharging
CS
RAS
CAS
WE
BA
ADDR
ACTION
Note
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA, A10/AP
ILLEGAL
2
L
L
H
H
BA
RA
L
L
H
L
BA
A10/AP
L
L
L
H
X
X
L
L
L
L
OP code
OP code
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
L
H
L
H
BA
CA, A10/AP
Begin Read ; latch CA ; determine AP
L
H
L
L
BA
CA, A10/AP
Begin Write ; latch CA ; determine AP
L
L
H
H
BA
RA
ILLEGAL
L
L
H
L
BA
A10/AP
Precharge
Row (& Bank) Active ; Latch RA
NOP
4
Auto Refresh or Self Refresh
5
Mode Register Access
5
2
2
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP
Term burst, New Read, Determine AP
L
H
L
L
BA
CA, A10/AP
Term burst, New Write, Determine AP
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
Term burst, Precharge timing for Reads
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
H
X
X
NOP (Continue Burst to End --> Row Active)
L
H
H
L
X
X
Term burst --> Row active
L
H
L
H
BA
CA, A10/AP
Term burst, New read, Determine AP
3
L
H
L
L
BA
CA, A10/AP
Term burst, New Write, Determine AP
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
Term burst, precharge timing for Writes
3
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
CA, A10/AP
ILLEGAL
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
2
H
X
X
X
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
H
X
X
NOP (Continue Burst to End --> Precharge)
L
H
H
L
X
X
ILLEGAL
L
H
L
X
BA
CA, A10/AP
ILLEGAL
L
L
H
X
BA
RA, RA10
ILLEGAL
L
L
L
X
X
X
ILLEGAL
2
H
X
X
X
X
X
NOP --> Idle after tRP
L
H
H
H
X
X
NOP --> Idle after tRP
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
NOP --> Idle after tRPL
4
- 26
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
Row
Activating
Refreshing
Mode
Register
Accessing
CS
RAS
CAS
WE
BA
ADDR
ACTION
Note
L
L
L
X
X
X
H
X
X
X
X
X
NOP --> Row Active after tRCD
L
H
H
H
X
X
NOP --> Row Active after tRCD
L
H
H
L
X
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10/AP
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after tRFC
L
H
H
X
X
X
NOP --> Idle after tRFC
L
H
L
X
X
X
ILLEGAL
L
L
H
X
X
X
ILLEGAL
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after 2 clocks
L
H
H
H
X
X
NOP --> Idle after 2 clocks
L
H
H
L
X
X
ILLEGAL
L
H
L
X
X
X
ILLEGAL
L
L
X
X
X
X
ILLEGAL
Abbreviations : RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
- 27
Rev. 1.0 (Oct. 1999)
K4S160822D
CMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
(n-1)
CKE
n
CS
RAS
CAS
WE
ADDR
ACTION
Note
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh --> Idle after tRFC (ABI)
6
L
H
L
H
H
H
X
Exit Self Refresh --> Idle after tRFC (ABI)
6
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Power Down --> ABI
L
H
L
H
H
H
X
Exit Power Down --> ABI
7
L
H
L
H
H
L
X
ILLEGAL
7
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
8
H
L
L
H
H
L
X
ILLEGAL
8
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
H
RA
H
L
L
L
L
H
X
H
L
L
L
L
L
OP Code
Row (& Bank) Active
8
Enter Self Refresh
Mode Register Access
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
9
L
H
X
X
X
X
X
Exit Clock Suspend next cycle
9
L
L
X
X
X
X
X
Maintain Clcok Suspend
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
- 28
Rev. 1.0 (Oct. 1999)
KM48S2120D
CMOS SDRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
tRAS
tRC
*Note 1
tSH
CS
tRCD
tRP
tSS
tSH
RAS
tSS
tCCD
tSH
CAS
tSH
ADDR
Ra
tSS
tSS
Ca
Cb
Cc
Rb
tSH
tSS
*Note 2
*Note 2,3
*Note 2,3
BA
BS
BS
BS
A10/AP
Ra
*Note 3
*Note 2,3 *Note 4
BS
*Note 3
BS
*Note 3 *Note 4
tRAC
Rb
tSH
tSAC
Qa
DQ
*Note 2
BS
Db
tSLZ
Qc
tSS
tOH
tSH
WE
tSS
tSS
tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don't care
- 29
Rev.1.0 (Mar. 1999)
KM48S2120D
0
1
CMOS SDRAM
*Note : 1. All inputs expect CKE & DQM can be don ¡Ç t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
2
3
4
5
6
7
BA
Active & Read/Write
0
Bank A
1
Bank B
8
10
9
11
12
13
14
15
16
17
18
19
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA
0
1
Operation
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA
Precharge
0
0
0
1
Bank B
1
X
Both Banks
Bank A
- 30
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Power Up Sequence
0
1
2
3
4
6
7
8
9
10
11
12
13
∼
∼
∼
∼
∼
CKE
5
∼
CLOCK
14
15
16
17
18
19
High level is necessary
CS
tRP
tRC
tRC
RAS
∼ ∼
∼ ∼
CAS
∼ ∼
∼ ∼
ADDR
∼ ∼
∼ ∼
BA
∼ ∼
∼ ∼
A10/AP
∼ ∼
∼ ∼
∼
∼
DQM
RAa
∼ ∼
∼ ∼
WE
RAa
∼
∼
High-Z
DQ
Key
High level is necessary
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
: Don't care
- 31
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Read & Write Cycle at Same Bank @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
tOH
DQ
CL=2
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tRAC
*Note 3
tSAC
tSHZ
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
tRAC
*Note 3
tSAC
tSHZ
Db2
Db3
tRDL
*Note 4
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
- 32
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Page Read & Write Cycle at Same Bank @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
tRDL
DQ
CL=2
Qa0
CL=3
Qa1
Qb0
Qb1 Qb2
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Qb1
tCDL
WE
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
- 33
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Page Read Cycle at Different Bank @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAc
CBb
CAe
CBd
BA
A10/AP
DQ
RAa
RBb
QAa0 QAa1 QAa2 QAa3
CL=2
CL=3
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
QAa0 QAa1 QAa2 QAa3
QBd0 QBd1 QAe0 QAe1
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
QBd0 QBd1 QAe0 QAe1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
: Don't care
*Note :
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
- 34
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Page Write Cycle at Different Bank @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
DBb0 DBb1 DBb2 DBb3
DAc0
CBd
BA
A10/AP
RAa
DQ
RBb
DAa0 DAa1 DAa2
DAa3
DAc1
DBd0 DBd1
tCDL
tRDL
WE
*Note 1
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(Both Banks)
Write
(B-Bank)
: Don't care
*Note :
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
- 35
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Read & Write Cycle at Different Bank @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
tCDL
DQ
CL=2
QAa0 QAa1 QAa2 QAa3
CL=3
QAa0 QAa1 QAa2 QAa3
DBb0
DBb1 DBb2 DBb3
DBb0
DBb1 DBb2 DBb3
*Note 1
QAc0
QAc1 QAc2
QAc0
QAc1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
: Don't care
*Note :
1. tCDL should be met to complete write.
- 36
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Read & Write Cycle with Auto Precharge I @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Ra
Cb
Ca
BA
A10/AP
DQ
Ra
CL=2
Qa0
CL=3
Qa1
Qb0
Qb1
Qb2
Qb3
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
Da0
Da1
WE
DQM
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank)*¨ç
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don't care
*Note:
¨ç When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
.
- 37
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Read & Write Cycle with Auto Precharge II @Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Rb
BA
A10/AP
DQ
Rb
Ra
CL=2
Qa0
CL=3
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qb0
Qa3
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb3
WE
DQM
*¨ç
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don't care
*Note :
¨ç Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
- 38
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
DQ
Qa0
Qa1
Qa2
Qb0
Qa3
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Write
DQM
Read DQM
Write
DQM
Write
Clock
Suspension
: Don't care
*Note :
1. DQM is needed to prevent bus contention.
- 39
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
DQ
RAa
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
*Note 2
CL=3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 0. 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
- 40
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tBDL
tRDL
*Note 2
DQ
DAb0 DAb1 DAb2 DAb3 DAb4
DAa0 DAa1 DAa2 DAa3 DAa4
DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
- 41
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Burst Read Single bit Write Cycle @Burst Length=2
1
0
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
17
18
19
CLOCK
*Note 1
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
DQ
RAa
RBb
CL=2
DAa0
CL=3
DAa0
RAc
QAb0
QAb1
QAb0
DBc0
QAb1
QAd0 QAd1
DBc0
QAd0 QAd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
- 42
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
∼
tSS
tSS
*Note 1
tSS
*Note 2
*Note 2
∼
∼
CKE
10
9
∼ ∼
0
CLOCK
*Note 3
∼ ∼
Ca
∼ ∼
∼ ∼
A10/AP
Ra
∼ ∼
∼ ∼
BA
∼ ∼
∼ ∼
ADDR
∼ ∼
∼ ∼
CAS
∼ ∼
∼ ∼
RAS
∼ ∼
CS
Ra
tSHZ
∼
∼
DQ
Precharge
Power-down
Entry
Qa2
∼ ∼
∼ ∼
DQM
Qa1
∼ ∼
∼ ∼
WE
Qa0
Row Active
Precharge
Power-down
Exit
Read
Active
Power-down
Entry
Precharge
Active
Power-down
Exit
: Don't care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (32ms)
- 43
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Self Refresh Entry & Exit Cycle
2
3
4
5
6
7
8
9
10
11
12
*Note 4
*Note 2
13
14
15
16
17
18
19
∼
∼ ∼
1
0
CLOCK
tRCmin
∼
*Note 1
*Note 6
*Note 3
∼
CKE
tSS
∼ ∼
∼ ∼
∼ ∼
RAS
*Note 5
∼ ∼
∼ ∼
ADDR
∼ ∼
∼ ∼
BA
Hi-Z
∼ ∼
∼ ∼
WE
∼ ∼
∼ ∼
DQM
∼
∼
Hi-Z
DQ
∼ ∼
∼ ∼
A10/AP
*Note 7
∼ ∼
∼ ∼
CAS
∼
CS
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note :
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
- 44
Rev.1.0 (Mar. 1999)
KM48S2120D
CMOS SDRAM
Mode Register Set Cycle
0
1
2
3
4
5
Auto Refresh Cycle
6
7
8
09
110
2
11
3
12
4
13
5
14
HIGH
HIGH
CKE
6
15
7
16
8
17
9
18
10
19
∼ ∼
CLOCK
∼
CS
*Note 2
tRC
∼ ∼
RAS
*Note 1
∼ ∼
CAS
Key
Ra
Hi-Z
Hi-Z
∼
DQ
∼ ∼
*Note 3
ADDR
∼ ∼
WE
∼ ∼
DQM
MRS
New
Command
Auto Refresh
New Command
: Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note :
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
- 45
Rev.1.0 (Mar. 1999)
K4S160822D
CMOS SDRAM
PACKAGE DIMENSIONS
50-TSOP2-400F
Unit : Millimeters
0~8°
#1
#25
10.16
0.400
0.125+0.075
-0.035
0.005+0.003
-0.001
21.35
MAX
0.841
20.95
0.825
0.10
MAX
0.004
(
0.805
)
0.032
± 0.10
1.20
MAX
0.047
± 0.004
0.30 +0.10
-0.05
0.012 +0.004
-0.002
0.80
0.0315
( 0.50 )
0.020
#26
11.76±0.20
0.463±0.008
#50
0.45~0.75
0.018~0.030
0.25
TYP
0.010
1.00 ± 0.10
0.039 ± 0.004
0.05
MIN
0.002
- 46
Rev. 1.0 (Oct. 1999)