ESD7451, SZESD7451 ESD Protection Diodes Micro−Packaged Diodes for ESD Protection The ESD7451 is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, the part is well suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. http://onsemi.com 1 Cathode 2 Anode Features • • • • • • • • • Ultra−Low Capacitance (0.35 pF Max) Low Clamping Voltage Stand−off Voltage: 3.3 V Low Leakage Response Time is < 1 ns Low Dynamic Resistance < 1 W IEC61000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • RF Signal ESD Protection • RF Switching, PA, and Antenna ESD Protection • Near Field Communications MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Air Value Unit ±25 ±25 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 250 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) MARKING DIAGRAM XDFN2 CASE 711AM E M EM G = Specific Device Code = Date Code ORDERING INFORMATION Device Package Shipping† ESD7451N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel SZESD7451N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 2 1 Publication Order Number: ESD7451/D ESD7451, SZESD7451 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage (Note 2) Symbol Conditions Min Typ VRWM VBR IT = 1 mA Max Unit 3.3 V 6.0 Reverse Leakage Current IR VRWM = 3.3 V < 1.0 Clamping Voltage (Note 3) VC Clamping Voltage (Note 3) VC ESD Clamping Voltage VC Per IEC61000−4−2 Junction Capacitance CJ VR = 0 V, f = 1 MHz VR = 0 V, f = 1 GHz 0.25 0.22 Dynamic Resistance RDYN TLP Pulse 0.55 V 50 nA IPP = 1 A 10 V IPP = 3 A 13 V 0.35 0.35 pF 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. http://onsemi.com 2 W ESD7451, SZESD7451 1.0 1.E−04 0.9 1.E−05 0.8 CAPACITANCE (pF) 1.E−03 1.E−06 I (A) 1.E−07 1.E−08 1.E−09 1.E−10 0.7 0.6 0.5 0.4 0.3 0.2 1.E−11 0.1 1.E−12 −8 −6 −4 −2 0 V (V) 2 4 6 0 8 −3 −2 Figure 1. IV Characteristics 1 2 3 2.0 1.8 0 1.6 −2 CAPACITANCE (pF) −4 −6 −8 −10 1.4 1.2 1.0 0.8 0.6 0.4 −12 0.2 −14 1.E+08 1.E+09 FREQUENCY (Hz) 0.0 1.E+10 1.0 Figure 3. RF Insertion Loss 3.0 4.0 5.0 6.0 7.0 FREQUENCY (GHz) 8.0 9.0 10 Figure 4. Capacitance over Frequency 8 16 8 −16 −14 6 12 10 EQUIVALENT VIEC (kV) TLP CURRENT (A) 14 6 −12 −10 4 8 6 2 4 2 0 0 2.0 4 −8 −6 −4 2 −2 2 4 6 10 8 12 14 VC, VOLTAGE (V) 16 18 0 20 0 0 Figure 5. Positive TLP I−V Curve 2 4 6 8 10 12 14 VC, VOLTAGE (V) 16 Figure 6. Negative TLP I−V Curve http://onsemi.com 3 18 0 20 EQUIVALENT VIEC (kV) Db (ESD7451_882..S(2,1)) 0 VBias (V) Figure 2. CV Characteristics 2 TLP CURRENT (A) −1 ESD7451, SZESD7451 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 7. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 8. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 9. 8 X 20 ms Pulse Waveform http://onsemi.com 4 80 ESD7451, SZESD7451 PACKAGE DIMENSIONS XDFN2 1.0x0.6, 0.65P (SOD−882) CASE 711AM ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C A B D ÉÉ PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW NOTE 3 0.10 C A 0.10 C A1 C SIDE VIEW MILLIMETERS MIN MAX 0.34 0.44 −−− 0.05 0.43 0.53 1.00 BSC 0.60 BSC 0.65 BSC 0.20 0.30 RECOMMENDED SOLDER FOOTPRINT* SEATING PLANE 1.20 2X e 2X 0.47 0.60 b e/2 0.05 M PIN 1 C A B 1 DIMENSIONS: MILLIMETERS 2X L 0.05 M *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. C A B BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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