Burr-Brown OPA658N Wideband, low power current feedback operational amplifier Datasheet

®
OPA658
OPA
658
OPA
658
Wideband, Low Power Current Feedback
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● UNITY GAIN STABLE BANDWIDTH:
900MHz
● LOW POWER: 50mW
● MEDICAL IMAGING
● HIGH-RESOLUTION VIDEO
● HIGH-SPEED SIGNAL PROCESSING
● LOW DIFFERENTIAL GAIN/PHASE ERRORS:
0.025%/0.02°
● COMMUNICATIONS
● PULSE AMPLIFIERS
● ADC/DAC GAIN AMPLIFIER
● HIGH SLEW RATE: 1700V/µs
● GAIN FLATNESS: 0.1dB to 135MHz
● HIGH OUTPUT CURRENT (80mA)
● MONITOR PREAMPLIFIER
● CCD IMAGING AMPLIFIER
DESCRIPTION
current make the OPA658 a perfect choice for numerous video, imaging and communications applications.
The OPA658 is an ultra-wideband, low power current
feedback video operational amplifier featuring high
slew rate and low differential gain/phase error. The
current feedback design allows for superior large signal bandwidth, even at high gains. The low differential
gain/phase errors, wide bandwidth and low quiescent
The OPA658 is optimized for low gain operation and
is also available in dual (OPA2658) and quad
(OPA4658) configurations.
+VS
Current Mirror
IBIAS
In+
In–
Buffer
VOUT
CCOMP
IBIAS
Current Mirror
–VS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1994 Burr-Brown Corporation
PDS-1268F
1
Printed in U.S.A. March, 1998
OPA658
SPECIFICATIONS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
OPA658P, U, N
PARAMETER
CONDITION
FREQUENCY RESPONSE
Closed-Loop Bandwidth(2)
Slew Rate(3)
At Minimum Specified Temperature
Settling Time: 0.01%
0.1%
1%
Spurious Free Dynamic Range
Third Order Intercept Point
Differential Gain
Differential Phase
Bandwidth for 0.1dB Flatness
OFFSET VOLTAGE
Input Offset Voltage
Over Temperature Range
Power Supply Rejection Ratio
INPUT BIAS CURRENT
Non-Inverting
Over Temperature Range
Inverting
Over Temperature Range
NOISE
Input Voltage Noise Density
f = 100Hz
f = 2kHz
f = 10kHz
f = 1MHz
fB = 100Hz to 200MHz
Input Bias Current Noise Density
Inverting: f = 1MHz
Non-Inverting: f = 1MHz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Temperature Range
Common-Mode Rejection
INPUT IMPEDANCE
Non-Inverting
Inverting
OPEN-LOOP TRANSRESISTANCE
Open-Loop Transresistance
Over Temperature Range
OUTPUT
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Voltage Output
Over Temperature Range
Output Current, Sourcing
Over Temperature
Output Current, Sinking
Over Temperature
Short Circuit Current
Output Resistance
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
Over Temperature Range
MIN
G = +1(4)
G = +2
G = +5
G = +10
G = +2, 2V Step
VCM = 0V
55
VCM = 0V
VCM = 0V
±2.5
45
VCM = ±1V
MAX
900
680
370
200
1700
1500
15
11.5
6
68
56
40
0.025
0.02
135(5)
G = +2, 2V Step
G = +2, 2V Step
G = +2, 2V Step
f = 5MHz, G = +2, VO = 2Vp-p
f = 20MHz, G= +2, VO = 2Vp-p
f = 10MHz, 4dBm Each Tone
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω
G = +2
VS = ±4.7 to ±5.5V
TYP
OPA658UB, NB
MIN
400
1000
900
±3
±5
64
±5.5
±8
±5.7
±10
±1.1
±30
±30
±80
±35
±75
58
TYP
MAX
✻(1)
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
UNITS
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
dBc
dBc
dBm
%
degrees
MHz
±2
±4
67
±4.5
±7
mV
mV
dB
✻
✻
✻
✻
±18
±35
✻
✻
µA
µA
µA
µA
16
4.9
3.2
3.2
45.3
✻
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
32
11.9
✻
✻
pA/√Hz
pA/√Hz
✻
✻
V
dB
✻
✻
kΩ || pF
Ω
±2.9
50
✻
✻
500 || 1
50
VO = ±2V, RL = 100Ω
VO = ±2V, RL = 100Ω
150
100
190
200
150
250
kΩ
kΩ
No Load
±2.7
±2.5
±2.7
±2.5
±2.2
±2.0
80
70
60
35
±2.9
±2.75
±2.9
±2.7
±2.8
±2.5
120
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
V
V
mA
mA
mA
mA
mA
Ω
RL = 250Ω
RL = 100Ω
80
✻
✻
150
0.02
0.1MHz, G = +2
±4.5
VS = ±5V
TEMPERATURE RANGE
Specification: P, U, N, UB, NB
Thermal Resistance, θJA
P
8-Pin DIP
U
SO-8
N
SOT23-5
–40
100
125
150
±5
±5
±5.5
✻
✻
✻
±5.75
±6.5
V
V
mA
mA
✻
✻
°C
✻
✻
✻
°C/W
°C/W
°C/W
±5.5
±7.75
±8.5
✻
+85
±4.5
±4.7
NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The
demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90%
of output voltage step. (4) At G = +1, RFB = 560Ω for PDIP and 402Ω for SO-8. (5) This specification is PC board layout dependent.
®
OPA658
2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply ............................................................................................... ±5.5V
Internal Power Dissipation .......................... See Thermal Considerations
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: P, U, UB, N, NB ............ –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(soldering, SOIC 3s) ...................................................................... +260°C
Junction Temperature (TJ ) ............................................................ +175°C
Top View
DIP/SO-8
NC
1
8
NC
–Input
2
7
+VS
+Input
3
6
Output
–VS
4
5
NC
ELECTROSTATIC
DISCHARGE SENSITIVITY
SOT23-5
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published specifications.
Output
1
–VS
2
+Input
3
5
+VS
4
–Input
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA658U
OPA658UB
OPA658N
SO-8 Surface Mount
SO-8 Surface Mount
5-pin SOT23-5
182
182
331
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OPA658U
OPA658UB
A58
OPA658NB
5-pin SOT23-5
331
–40°C to +85°C
A58B
8-Pin Plastic DIP
006
–40°C to +85°C
OPA658P
OPA658P
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
OPA658U
OPA658UB
OPA658N-250
OPA658N-3k
OPA658NB-250
OPA658NB-3k
OPA658P
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade of the SO-8 will be
marked with a “B” by pin 8. The “B” grade of the SOT23-5 will be marked with a “B” near pins 3 and 4. (3) The SOT23-5 is only available on a 7" tape and reel (e.g. ordering
250 pieces of “OPA658N-250” will get a single 250 piece tape and reel. Ordering 3000 pieces of “OPA658N-3k” will get a single 3000 piece tape and reel). Please refer
to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA658
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
PSRR AND CMR vs TEMPERATURE
55
PSRR , CMR (dB)
70
Common-Mode Rejection (dB)
75
PSRR
65
PSR+
60
PSR–
55
CMR
50
45
–75
50
45
40
35
30
25
–50
–25
0
25
50
75
100
–4
125
–3
–2
–1
0
1
2
3
4
100
125
Common-Mode Voltage (V)
Temperature (°C)
OUTPUT CURRENT vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
120
Output Current (±mA)
Supply Current (±mA)
IO+
5
4
110
100
90
80
IO–
70
–75
–50
–25
0
25
50
75
100
–75
125
25
50
75
OUTPUT SWING vs TEMPERATURE
NON-INVERTING INPUT BIAS CURRENT
vs TEMPERATURE
Non-Inverting Input Bias Current IB+ (µA)
RL = 250Ω
3.0
Output Swing (V)
0
Ambient Temperature (°C)
3.10
–VO
+VO
2.90
2.80
2.70
–VO
2.60
+VO
RL = 100Ω
2.50
2.40
2.30
–40
–25
Ambient Temperature (°C)
3.20
–60
–50
–20
0
20
40
60
80
100
8
6
4
2
–75
Temperature (°C)
–50
–25
0
25
50
Ambient Temperature (°C)
®
OPA658
10
4
75
100
125
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
OPEN-LOOP TRANSIMPEDANCE AND PHASE
vs FREQUENCY
INVERTING INPUT BIAS CURRENT
vs TEMPERATURE
106
Transimpedance
105
1.6
1.4
1.2
1.0
0.8
0.6
0
104
–45
Phase
103
–90
102
–135
101
–180
–225
1
0.4
–75
–50
–25
0
25
50
75
100
1k
125
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
100M
1G
CLOSED-LOOP BANDWIDTH
60
6
Gain
SO-8 Bandwidth = 881MHz, RFB = 402Ω
0
20
–45
0
–90
3
G = +1
Gain (dB)
Phase
Open-Loop Phase (°)
40
Open-Loop Gain (dB)
Open-Loop Phase (°)
1.8
Transimpedance (Ω)
Inverting Input Bias Current IB– (µA)
2.0
0
–3
–20
–135
–40
–180
–6
–225
–9
–60
1k
10k
100k
1M
10M
100M
DIP Bandwidth = 949MHz, RFB = 560Ω
1G
1M
10M
Frequency (Hz)
100M
1G
Frequency (Hz)
CLOSED-LOOP BANDWIDTH
CLOSED-LOOP BANDWIDTH
20
9
G = +5
G = +2
17
6
SO-8/DIP Bandwidth= 372MHz
14
Gain (dB)
Gain (dB)
DIP Bandwidth = 682MHz
3
0
11
8
SO-8 Bandwidth = 680MHz
–3
5
2
–6
1M
10M
100M
1M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
®
5
OPA658
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
SMALL SIGNAL TRANSIENT RESPONSE
CLOSED-LOOP BANDWIDTH
160
26
SO-8/DIP Bandwidth = 200MHz
Output Voltage (mV)
G = +10
20
Gain (dB)
G = +2
120
23
17
14
11
80
40
0
–40
–80
–120
–160
8
1M
10M
100M
Time (5ns/div)
1G
Frequency (Hz)
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
LARGE SIGNAL TRANSIENT RESPONSE
1.6
40
G = +2
1.2
G = +2
Output Voltage (V)
Isolation Resistance
35
30
RISO
25
OPA658
20
CL
402Ω
15
1kΩ
0.8
0.4
0
–0.4
–0.8
402Ω
–1.2
–1.6
10
10
20
Time (5ns/div)
30
40 50 60 70 80 90 100
Capacitive Load (pf)
HARMONIC DISTORTION vs FREQUENCY
5MHz HARMONIC DISTORTION vs OUTPUT SWING
–60
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–65
–60
–70
–80
2fO
–90
3fO
3fO
–70
2fO
–75
G = +2
–80
–85
–90
–95
–100
–100
100k
1M
10M
0
100M
®
OPA658
1
2
Output Swing (Vp-p)
Frequency (Hz)
6
3
4
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.
HARMONIC DISTORTION vs TEMPERATURE
(VO = 2Vp-p, G = +2)
10MHz HARMONIC DISTORTION vs OUTPUT SWING
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–60
–70
2fO
–80
3fO
–90
–100
0.01
3fO
–70
2fO
–75
–80
–85
1
0.1
4V
10
–75
–50
–25
0
25
50
75
100
Output Swing (Vp-p)
Temperature (°C)
HARMONIC DISTORTION vs GAIN
(fO = 5MHz, VO = 2Vp-p)
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
125
100
–50
–55
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Harmonic Distortion (dBc)
–65
2fO
–60
3fO
–65
–70
Inverting Current Noise
Non-Inverting Noise
10
Voltage Noise
1
–75
0
1
2
3
4
5
6
7
8
9
102
10
103
104
105
106
107
Frequency (Hz)
Non-Inverting Gain (V/V)
®
7
OPA658
APPLICATIONS INFORMATION
For non-inverting operation, the input signal is applied to the
non-inverting (high impedance buffer) input. The output
(buffer) error current (IE) is generated at the low impedance
inverting input. The signal generated at the output is fed back
to the inverting input such that the overall gain is (1 + RFB/RFF).
Where a voltage-feedback amplifier has two symmetrical high
impedance inputs, a current feedback amplifier has a low
inverting (buffer output) impedance and a high non-inverting
(buffer input) impedance.
The closed-loop gain for the OPA658 can be calculated
using the following equations:
R 
–  FB 
 R FF 
Inverting Gain =
1
(1)
1+
Loop Gain
THEORY OF OPERATION
Conventional op amps depend on feedback to drive their
inputs to the same potential, however the current feedback
op amp’s inverting and non-inverting inputs are connected
by a unity gain buffer, thus enabling the inverting input to
automatically assume the same potential as the non-inverting input. This results in very low impedance at the inverting
input to sense the feedback as an error current signal.
DISCUSSION OF PERFORMANCE
The OPA658 is a low-power, unity gain stable, current
feedback operational amplifier which operates on ±5V power
supply. The current feedback architecture offers the following important advantages over voltage feedback architectures: (1) the high slew rate allows the large signal performance to approach the small signal performance, and (2)
there is very little bandwidth degradation at higher gain
settings.
The current feedback architecture of the OPA658 provides
the traditional strength of excellent large signal response
plus wide bandwidth, making it a good choice for use in high
resolution video, medical imaging and DAC I/V Conversion. The low power requirements make it an excellent
choice for numerous portable applications.
 R FB 
1 +

R FF 
Non−Inverting Gain = 
1
1+
Loop Gain
(2)




TO

where Loop Gain = 


R FB  
 R FB + R S  1 +

R FF  


At higher gains the small value inverting input impedance
causes an apparent loss in bandwidth. This can be seen from
the equation:
ƒ ( A = +2 ) BW x (1. 25)
V
(3)
ƒ ACTUAL BW ≈
  RS  


R FB
1 + 
 × 1 +

R FF  
  R FB  
[
DC GAIN TRANSFER CHARACTERISTICS
The circuit in Figure 1 shows the equivalent circuit for
calculating the DC gain. When operating the device in the
inverting mode, the input signal error current (IE) is amplified by the open loop transimpedance gain (TO). The output
signal generated is equal to TO x IE. Negative feedback is
applied through RFB such that the device operates at a gain
equal to –RFB/RFF.
]
This loss in bandwidth at high gains can be corrected
without affecting stability by lowering the value of the
feedback resistor from the specified value of 402Ω.
OFFSET VOLTAGE AND NOISE
The output offset is the algebraic sum of the input offset
voltage and bias current errors. The output offset for noninverting operation is calculated by the following equation:
CC
+
IE
RFF
RS
LS
TO
–
VN
R 

(4)
Output Offset Voltage = ±Ib N × R N  1 + F B  ±
R FF 


R FB 
V IO  1 +
 ±Ib I × R FB
R FF 

VO
If all terms are divided by the gain (1 + RFB/RFF) it can be
observed that input referred offsets improve as gain increases.
The effective noise at the output can be determined by taking
(50Ω)
C1
VI
RFB
RFF
RFB
IbI
IbN
RN
VIO
FIGURE 1. Equivalent Circuit.
FIGURE 2. Output Offset Voltage Equivalent Circuit.
®
OPA658
8
The 402Ω used in setting the specification achieves a nominal maximally flat butterworth response while assuming a
2pF output pin parasitic. Increasing the feedback resistor
will over compensate the amplifier, rolling off the frequency
response, while decreasing it will decrease phase margin,
peaking up the frequency response. Note that a non-inverting, unity gain buffer application still requires a feedback
resistor for stability (560Ω for SO-8, 402Ω for PDIP, and
324Ω for SOT23).
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RISO from
the plot of recommended RISO vs capacitive load. Low
parasitic loads may not need an RISO since the OPA658 is
nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimensions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
the root sum of the squares of equation (4) and applying the
spectral noise values found in the Typical Performance Curve
graph section. This applies to noise from the op amp only.
Note that both the noise figure (NF) and the equivalent input
offset voltages improve as the closed loop gain increases (by
keeping RFB fixed and reducing RFF with RN = 0Ω).
INCREASING BANDWIDTH AT HIGH GAINS
The closed-loop bandwidth can be extended at high gains by
reducing the value of the feedback resistor RFB. This bandwidth reduction is caused by the feedback current being split
between RS and RFF (refer to Figure 1). As the gain increases
(for a fixed RFB), more feedback current is shunted through
RFF, which reduces closed-loop bandwidth.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency amplifier like the OPA658 requires careful attention to layout
parasitics and selection of external components. Recommendations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external components will preserve the high frequency performance of the
OPA658. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to
the package pins. Other network components, such as noninverting input termination resistors, should also be placed
close to the package.
The feedback resistor value acts as the frequency response
compensation element for a current feedback type amplifier.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Socketing a high speed part like the OPA658 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
The OPA658 is nominally specified for operation using
±5V power supplies. A 10% tolerance on the supplies, or an
ECL –5.2V for the negative supply, is within the maximum
®
9
OPA658
specified total supply voltage of 11V. Higher supply voltages
can break down internal junctions possibly leading to catastrophic failure. Single supply operation is possible as long as
common mode voltage constraints are observed. The common mode input and output voltage specifications can be
interpreted as a required headroom to the supply voltage.
Observing this input and output headroom requirement will
allow non-standard or single supply operation. Figure 3
shows one approach to single-supply operation.
+VS
Output Impedance (Ω)
100
+VS
10
1
0.1
G = +2
0.01
0.001
10k
100k
1M
10M
100M
Frequency (Hz)
V
VOUT = S + AV VAC
2
VS
2
FIGURE 4. Closed-Loop Output Impedance vs Frequency.
ROUT
VAC
OPA658
THERMAL CONSIDERATIONS
The OPA658 will not require heatsinking under most operating conditions. Maximum desired junction temperature
will set a maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T J ) is given by
TA + PD • θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional power
dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. PDL
will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to 1/2 either supply
voltage (for equal bipolar supplies). Under this condition
PDL = VS2/(4 • RL) where RL includes feedback network
loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an example, compute the maximum TJ for an OPA658N
at AV = +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, and the
specified maximum TA = +85°C. PD = 10V • 8.5mA + 52/
[4 • (100Ω || 804Ω)] = 155mW. Maximum TJ = 85°C +
0.155W • 150°C/W = 108°C.
RL
402Ω
402Ω
AV = +2
FIGURE 3. Single Supply Operation.
ESD PROTECTION
ESD static damage has been well recognized for MOSFET
devices, but any semiconductor device deserves protection
from this potentially damaging source. This is particularly
true for very high speed, fine geometry processes.
ESD static damage can cause subtle changes in amplifier
input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
static protection is strongly recommended when handling
the OPA658.
OUTPUT DRIVE CAPABILITY
DRIVING CAPACITIVE LOADS
The OPA658’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 5pF
should be buffered by connecting a small resistance, usually
10Ω to 35Ω, in series with the output as shown in Figure 5.
This is particularly important when driving high capacitance
loads such as flash A/D converters.
In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated
with its characteristic impedance.
The OPA658 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 2Vp-p into a 75Ω load.
This high-output drive capability makes the OPA658 an
ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded.
Many demanding high-speed applications such as
ADC/DAC buffers require op amps with low wideband
output impedance. For example, low output impedance is
essential when driving the signal-dependent capacitances at
the inputs of flash A/D converters. As shown in Figure 4,
the OPA658 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with
frequency.
®
OPA658
10
402Ω
402Ω
close-in spurious tones will appear at fO ±3 • ∆f. The two
tone, third-order spurious plot shown in Figure 7 indicates
how far below these two equal power, closely spaced, tones
the intermodulation spurious will be. The single tone power
is at a matched 50Ω load. The unique design of the OPA658
provides much greater spurious free range than what a twotone third-order intermodulation intercept specification would
predict. This can be seen in Figure 7 as the spurious free
range actually increases at the higher output power levels.
10Ω to 35Ω
RISO
OPA658
RL
50Ω
CL
FIGURE 5. Driving Capacitive Loads.
TWO TONE, THIRD-ORDER SPURIOUS LEVELS
–65
Third-Order Spurious Level (dBc)
COMPENSATION
The OPA658 is internally compensated and is stable in unity
gain with a phase margin of approximately 62°, and approximately 64° in a gain of +2V/V when used with the recommended feedback resistor value. Frequency response for
other gains are shown in the Typical Performance Curves.
The high-frequency response of the OPA658 in a good
layout is very flat with frequency.
DISTORTION
5MHz
–80
–85
–6
–4
–2
0
2
4
FIGURE 7. Third-Order Spurious Level vs Frequency.
DIFFERENTIAL GAIN AND PHASE
Differential Gain (dG) and Differential Phase (dP) are among
the more important specifications for video applications. dG
is defined as the percent change in closed-loop gain over a
specified change in output voltage level. dP is defined as the
change in degrees of the closed-loop phase over the same
output voltage change. Both dG and dP are specified at the
NTSC sub-carrier frequency of 3.58MHz and the PAL subcarrier of 4.43MHz. All NTSC measurements were performed using a Tektronix model VM700A Video Measurement Set.
–60
G = +2, VO = 2Vp-p, fO = 5MHz
–65
3fO
–70
dG/dP of the OPA658 were measured with the amplifier in a
gain of +2V/V with 75Ω input impedance and the output
back-terminated in 75Ω. The input signal selected from the
generator was a 0V to 1.4V modulated ramp with sync pulse.
With these conditions the test circuit shown in Figure 8
delivered a 100IRE modulated ramp to the 75Ω input of the
videoanalyzer. The signal averaging feature of the analyzer
–75
2fO
–85
100
–8
Single Tone Power (dBm)
–55
Harmonic Distortion (dBc)
10MHz
–18 –16 –14 –12 –10
5MHz HARMONIC DISTORTION vs
LOAD RESISTANCE (G = +2)
10
–75
–90
The OPA658’s Harmonic Distortion characteristics into a
100Ω load are shown versus frequency and power output in
the Typical Performance Curves. Distortion can be further
improved by increasing the load resistance as illustrated in
Figure 6. Remember to include the contribution of the
feedback resistance when calculating the effective load resistance seen by the amplifier.
–80
20MHz
–70
1k
Load Resistance (Ω)
FIGURE 6. 5MHz Harmonic Distortion vs Load Resistance.
75Ω
75Ω
Narrowband communication channel requirements will benefit from the OPA658’s wide bandwidth and low
intermodulation distortion on low quiescent power. If output
signal power at two closely spaced frequencies is required,
third-order nonlinearities in any amplifier will cause spurious power at frequencies very near the two fundamental frequencies. If the two test frequencies, f1 and f2,
are specified in terms of average and delta frequency,
fO = (f1 + f2)/2 and ∆f =  f2 – f1, the two, third-order,
OPA658
75Ω
402Ω
75Ω
402Ω
TEK TSG 130A
TEK VM700A
FIGURE 8. Configuration for Testing Differential Gain/Phase.
®
11
OPA658
was used to establish a reference against which the performance of the amplifier was measured. Signal averaging was
also used to measure the dg and dp of the test signal in order
to eliminate the generator’s contribution to measured amplifier performance. Typical performance of the OPA658 is
0.025% differential gain and 0.02° differential phase to both
NTSC and PAL standards.
Demonstration boards are available for each OPA658 package style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration board
is:
SPICE MODELS AND EVALUATION BOARDS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE
models are available on a disk from the Burr-Brown Applications Department.
R3
J2
DEM-OPA65xP
8-Pin DIP for the OPA658P
DEM-OPA65xU
SO-8 for the OPA658U
DEM-OPA6xxN
SOT23 for the OPA658N
Contact your local Burr-Brown sales office or distributor to
order demonstration boards.
R4
–In
402Ω
C1
2.2µF
+
R5
1
2
R6
J1
3
+In
+5V
2
C3
0.1µF
GND
P1
7
OPA658
4
6
R1
J1
Out
1
R5
C2
0.1µF
R7
C4
2.2µF
+
FIGURE 9. Layout Detail For DEM-OPA65xP Demonstration Board.
®
OPA658
12
GND
2
–5V
P2
DEM-OPA65xP Demonstration Board Layout
(A)
(B)
(C)
(D)
FIGURE 10a. Evaluation Board Silkscreen (Bottom). 10b. Evaluation Board Silkscreen (Top). 10c. Evaluation Board Layout
(Solder Side). 10d. Evaluation Board Layout (Layout Side).
TYPICAL APPLICATION
402Ω
402Ω
75Ω Transmission Line
75Ω
V OUT
OPA658
Video
Input
75Ω
75Ω
FIGURE 11. Low Distortion Video Amplifier.
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13
OPA658