LR38516 Timing Generator IC for 350 k-pixel Progressive Scan Color CCDs LR38516 DESCRIPTION PIN CONNECTIONS The LR38516 is a CMOS timing generator IC which is designed for video-camcorders, and which generates timing pulses for driving 350 k-pixel progressive scan color CCD area sensors, synchronous pulses for TV signals and processing pulses for video signals. TOP VIEW DBLK GND ADCK NC VDD4 FH2 GND FH1 VDD4 CLRX CCD2 CCD1 48-PIN QFP 48 47 46 45 44 43 42 41 40 39 38 37 36 TST3 35 ED2 34 ED1 33 ED0 32 HD 31 GND 30 VDD3 29 DMVD 28 DCLK 27 CLK 26 CKO 25 CKI VTAX 1 VTBX 2 VTCX 3 VTDX 4 OFDX 5 VDD3 6 GND 7 VHAX 8 VHCX 9 ID 10 WEN 11 TST1 12 FEATURES • Designed for 350 k-pixel progressive scan color CCD area sensors • Frame rate : 30 frame/s • Shutter speed can be controlled in 1H period using a serial code • TV mode selection, power mode selection and the phase selection of DCLK can be also controlled by using a serial code • +3 V, +4.5 V and +5 V power supplies • Package : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch PBLK BCPX BPX CLPX GND FCDS FS VDD5 RS FR GND TST2 13 14 15 16 17 18 19 20 21 22 23 24 (QFP048-P-0707) In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38516 TST3 ED2 ED1 ED0 HD GND VDD3 DMVD DCLK CLK CKO CKI BLOCK DIAGRAM 36 35 34 33 32 31 30 29 28 27 26 25 OSC CCD1 37 24 TST2 DATA LATCH & SHUTTER CONTROL CCD2 38 23 GND CLRX 39 22 FR VDD4 40 1/2 1/2 21 RS RESET FH1 41 20 VDD5 1/2 GND 42 19 FS H COUNTER FH2 43 RESET 18 FCDS GATE VDD4 44 17 GND NC 45 LEVEL SHIFTER DECODER RESET 16 CLPX ADCK 46 15 BPX V COUNTER 2 OFDX VDD3 7 8 9 10 11 12 TST1 6 WEN 5 ID 4 VHCX 3 VHAX 2 GND 1 VTDX 13 PBLK VTCX DBLK 48 VTBX 14 BCPX VTAX GND 47 LR38516 PIN DESCRIPTION PIN NO. SYMBOL 1 2 3 4 VTAX VTBX VTCX VTDX I/O POLARITY PIN NAME Vertical transfer pulse output 1 O3 Vertical transfer pulse output 2 O3 Vertical transfer O3 pulse output 3 Vertical transfer O3 pulse output 4 DESCRIPTION A vertical transfer pulse for CCD. Connect to V1AX pin of the vertical driver IC. For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". A vertical transfer pulse for CCD. Connect to V2AX pin of the vertical driver IC. For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". A vertical transfer pulse for CCD. Connect to V3AX pin of the vertical driver IC. For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". A vertical transfer pulse for CCD. Connect to V4AX pin of the vertical driver IC. For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". A pulse that sweeps the charge of the photo-diode OFDX O3 6 VDD3 – – Power supply 7 GND – – Ground A grounding pin. Readout pulse A pulse that transfers the charge of the photo-diode to the vertical shift register. 8 9 10 VHAX VHCX ID O3 For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". A pulse that transfers the charge of the photo-diode to the vertical shift register. For details, see "CONNECTION OF VERTICAL TRANSFER PULSES". The pulse is used in color separator. The signal switches H and L at every line. H : R color line Write enable output L : B color line Write enable output for low-speed shutter pulse. Test pin 1 A test pin. Set open or to L level in the normal mode. O5 Pre-blanking pulse output A pulse that corresponds to the cease period of the horizontal transfer pulse. O5 Optical black clamp pulse output WEN O3 ICD3 BCPX output 3 Held at H level at normal mode. Supply of +3 V power. Line index pulse output TST1 14 Readout pulse O3 12 PBLK output 1 O3 11 13 OFD pulse output for the electronic shutter. Connect to OFD pin of CCD through the vertical driver IC and DC offset circuit. 5 – A pulse to clamp the optical black signal. Output stays low during the absence of effective pixels within the vertical blanking. 15 BPX O5 Clamp pulse output A pulse to clamp the signal. The phase is same as BCPX (pin 14). This pulse is continuous at horizontal cycle. 16 CLPX O5 Clamp pulse output A pulse to clamp the dummy outputs of CCD. The pulse stays high during the sweep-out period. 17 GND – Ground A grounding pin. – 3 LR38516 PIN NO. SYMBOL 18 FCDS I/O POLARITY O6MA5 PIN NAME CDS pulse output 1 DESCRIPTION A pulse to clamp the feed-through level from CCD. The polarity can be changed by serial data. The output phase of FCDS is selected by serial data. A pulse to sample-hold the signal from CCD. 19 FS 20 VDD5 21 RS O6MA5 – – O6MA5 CDS pulse output 2 The polarity can be changed by serial data. The output phase of FS is selected by serial data. Power supply Supply of +5 V power. A pulse to sample-hold the signal from CDS circuit. S/H pulse output The polarity can be changed by serial data. The output phase of RS is selected by serial data. A pulse to reset the charge of output circuit. 22 FR O6MA52 Reset pulse output Connect to ØR pin of CCD through the DC offset circuit. The output phase of FR is selected by serial data. 23 GND – – Ground A grounding pin. 24 TST2 ICD3 – Test pin 2 A test pin. Set open or to L level in the normal mode. An input pin for reference clock oscillation. 25 CKI OSCI3 – Clock input Connect to CKO (pin 26) with R. Frequency : 24.54545 MHz (1 560 fH) Clock output An output pin for reference clock oscillation. The output is the inverse of CKI (pin 25). fH = Horizontal frequency 26 CKO OSCO3 27 CLK O6MA3 – Clock output An output pin to generate HD and VD pulses. Connect to clock input pin of SSG IC. Frequency : 12.27273 MHz (780 fH) 28 DCLK O6MA3 IC3 Clock output An output pin for DSP IC. The output phase of DCLK is selected by serial data step by 90˚. Vertical reference Frequency : 12.27273 MHz (780 fH) An input pin for reference of vertical pulse. Connect to VD pin of DSP IC. Supply of +3 V power. A grounding pin. 29 DMVD 30 VDD3 – – pulse input Power supply 31 GND – – Ground Horizontal reference An input pin for reference of horizontal pulse. pulse input Connect to HD pin of DSP IC. 32 HD IC3 33 ED0 IC3 – Strobe pulse input 34 ED1 IC3 – Shift register clock input 35 ED2 IC3 – Shift register data input 36 TST3 ICD3 – Test pin 3 An input pin for the strobe pulse, to control the functions of LR38516. For details, see "Serial Data Control". An input pin for the clock of the shift register, to control the functions of LR38516. For details, see "Serial Data Control". An input pin for the data of the shift register, to control the functions of LR38516. For details, see "Serial Data Control". A test pin. Set open or to L level in the normal mode. 4 LR38516 PIN NO. SYMBOL 37 38 CCD1 CCD2 I/O POLARITY PIN NAME ICU4 – CCD selection input 1 At CCD1 = H and CCD2 = H CCD selection input 2 1/4-type 350 k-pixel CCD (at NTSC) At CCD1 = H and CCD2 = L ICU4 – DESCRIPTION An input pin to select CCD. 1/3-type 350 k-pixel CCD (at NTSC) An input pin for resetting all serial data at power on. 39 CLRX ICU4 – Data clear input Connect VDD through the diode and GND through the capacitor. 40 VDD4 – – Power supply Supply of +4.5 V power. Horizontal transfer pulse output 1 A horizontal transfer pulse for CCD. Connect to ØH1 pin of CCD. – Ground Horizontal transfer A grounding pin. A horizontal transfer pulse for CCD. pulse output 2 Connect to ØH2 pin of CCD. – – Power supply No connection Supply of +4.5 V power. No connection. AD clock output An output pin for A/D converter. The output phase of ADCK is selected by serial data step by 90˚. 41 FH1 O6MA43 42 GND – 43 FH2 O6MA43 44 45 VDD4 NC – – 46 ADCK O6MA4 47 GND – 48 DBLK IC3 ICU4 ICD3 O3 O6MA3 O6MA4 : : : : : : O3 – Ground A grounding pin. Dummy composite output Composite blanking pulse. Vertical : 33H period O6MA43 O5 O6MA5 O6MA52 OSCI3 OSCO3 Input pin (CMOS level) Input pin (CMOS level with pull-up resistor) Input pin (CMOS level with pull-down resistor) Output pin Output pin Output pin : : : : : : Output pin Output pin Output pin Output pin Input pin for oscillation Output pin for oscillation CONNECTION OF VERTICAL TRANSFER PULSES OUTPUT PULSE VTAX VHAX VTCX VHCX VTBX VTDX LEVEL SHIFT, INVERT, MIX 1/4-TYPE 350 k 1/3-TYPE 350 k, 380 k AND 450 k 3-level pulse with V driver ØV3B ØV1 3-level pulse with V driver ØV3A ØV3 2-level pulse with V driver 2-level pulse with V driver ØV2 ØV1 ØV2 ØV4 5 LR38516 Serial Data Control SERIAL DATA INPUT TIMING ED0 ED1 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 ... D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 ED2 The data on ED2 is latched in the register at the rising edge of ED1. The data of D13 is effective. Other data are effective at next horizontal line of readout horizontal line while VHAX and VHCX are active. ED0 has to be kept L level in effective data input period. SERIAL DATA INPUTS DATA NAME D00-D09 SD0-SD9 D10 SMD0 D11 SMD1 D12 D13 TVMD PWSA D14 D15 ML1 ML2 D16 MA1 D17 MA2 D18 PLCH D19 MR1 D20 D21 MR2 MC1 D22 MC2 D23 MS1 D24 MS2 D25 MF1 MF2 D26 FUNCTION DATA = L DATA = H AT CLRX = L Electronic shutter speed control – All L Electronic shutter mode control – L L TV mode selection Power save control – Power save NTSC Normal L L – Phase control L – Polarity control of FCDS, FS and Negative RS pulses – Phase control – – 6 L Positive – L – L L L L L L L L L LR38516 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature RATING –0.3 to +6.0 –0.3 to VDD3 + 0.3 –0.3 to VDD4 + 0.3 –0.3 to VDD3 + 0.3 –0.3 to VDD4 + 0.3 –0.3 to VDD5 + 0.3 –20 to +70 –55 to +150 SYMBOL VDD3, VDD4, VDD5 VI3 VI4 VO3 VO4 VO5 TOPR TSTG UNIT V V V V V V ˚C ˚C ELECTRICAL CHARACTERISTICS DC Characteristics (VDD3 = 3.0±0.3 V, VDD4 = 4.5±0.45 V, VDD5 = 5.0±0.5 V, TOPR = –20 to +70 ˚C) PARAMETER Input "Low" voltage Input "High" voltage Input "Low" voltage Input "High" voltage Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage SYMBOL VIL3 VIH3 VIL4 VIH4 |IIL3-1| |IIH3-1| |IIL3-2| |IIH3-2| |IIL4| |IIH4| VOL3-1 VOH3-1 VOL3-2 VOH3-2 VOL3-3 VOH3-3 VOL4-1 VOH4-1 VOL4-2 VOH4-2 VOL5-1 VOH5-1 VOL5-2 VOH5-2 VOL5-3 VOH5-3 MIN. CONDITIONS TYP. 0.8VDD3 0.8VDD4 VI = 0 V VI = VDD3 VI = 0 V VI = VDD3 VI = 0 V VI = VDD4 IOL = 2 mA IOH = –2 mA IOL = 2 mA IOH = –1 mA IOL = 3 mA IOH = –3 mA IOL = 4 mA IOH = –4 mA IOL = 12 mA IOH = –12 mA IOL = 4 mA IOH = –2 mA IOL = 6 mA IOH = –6 mA IOL = 12 mA IOH = –12 mA 2.0 4.0 VDD3 – 0.5 VDD3 – 0.5 VDD3 – 0.5 VDD4 – 0.5 VDD4 – 0.5 VDD5 – 0.5 VDD5 – 0.5 VDD5 – 0.5 NOTES : 6. 7. 8. 9. 10. 11. 1. 2. 3. 4. Applied to inputs (IC3, OSCI3). Applied to input (ICD3). Applied to input (ICU4). Applied to output (OSCO3). (Output (OSCO3) measures on condition that input (OSCI3) level is 0 V or VDD3.) 5. Applied to output (O3). 7 Applied Applied Applied Applied Applied Applied to to to to to to output output output output output output (O6MA3). (O6MA4). (O6MA43). (O5). (O6MA5). (O6MA52). MAX. UNIT V 0.2VDD3 V V 0.2VDD4 V µA 1.0 µA 1.0 µA 1.0 µA 30 µA 60 µA 2.0 V 0.4 V V 0.4 V V 0.4 V V 0.4 V V 0.4 V V 0.4 V V 0.4 V 0.4 V V NOTE 1, 2 3 1 2 3 4 5 6 7 8 9 10 11 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 48 QFP (QFP048-P-0707) 0.15±0.05 0.2±0.08 M (1.0) 25 36 37 48 13 7.0±0.2 12 (1.0) 0.1±0.1 8 0.1 8.0±0.2 0.65±0.2 1.45±0.2 9.0±0.3 Package base plane 1 (1.0) (1.0) 7.0±0.2 0.08 24 9.0±0.3 0.5TYP.