TI1 MAX3222CDWRE4 Multichannel line driver/receiver with esd protection Datasheet

± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
D RS-232 Bus-Pin ESD Protection Exceeds
D
D
D
D
D
D
D
D
D
DB, DW, OR PW PACKAGE
(TOP VIEW)
±15 kV Using Human-Body Model (HBM)
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Operates Up To 250 kbit/s
Two Drivers and Two Receivers
Low Standby Current . . . 1 µA Typical
External Capacitors . . . 4 × 0.1 µF
Accepts 5-V Logic Input With 3.3-V Supply
Alternative High-Speed Pin-Compatible
Device (1 Mbit/s)
− SNx5C3222
Applications
− Battery-Powered Systems, PDAs,
Notebooks, Laptops, Palmtop PCs, and
Hand-Held Equipment
EN
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
ROUT2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PWRDOWN
VCC
GND
DOUT1
RIN1
ROUT1
NC
DIN1
DIN2
NC
NC − No internal connection
description/ordering information
The MAX3222 consists of two line drivers, two line receivers, and a dual charge-pump circuit with
±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the
requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication
controller and the serial-port connector. The charge pump and four small external capacitors allow operation
from a single 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s and a maximum
of 30-V/µs driver output slew rate.
ORDERING INFORMATION
SOIC (DW)
−0°C to 70°C
SSOP (DB)
TSSOP (PW)
SOIC (DW)
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP (DB)
TSSOP (PW)
Tube of 25
MAX3222CDW
Reel of 2000
MAX3222CDWR
Tube of 70
MAX3222CDB
Reel of 2000
MAX3222CDBR
Tube of 70
MAX3222CPW
Reel of 2000
MAX3222CPWR
Tube of 25
MAX3222IDW
Reel of 2000
MAX3222IDWR
Tube of 70
MAX3222IDB
Reel of 2000
MAX3222IDBR
Tube of 70
MAX3222IPW
Reel of 2000
MAX3222IPWR
TOP-SIDE
MARKING
MAX3222C
MA3222C
MA3222C
MAX3222I
MB3222I
MB3222I
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(
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%$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',(
$(%$1 #++ )#!#"($(!%
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
description/ordering information (continued)
The MAX3222 can be placed in the power-down mode by setting PWRDOWN low, which draws only 1 µA from
the power supply. When the device is powered down, the receivers remain active while the drivers are placed
in the high-impedance state. Also, during power down, the onboard charge pump is disabled; V+ is lowered to
VCC, and V− is raised toward GND. Receiver outputs also can be placed in the high-impedance state by setting
EN high.
Function Tables
EACH DRIVER
INPUTS
DIN
PWRDOWN
OUTPUT
DOUT
X
L
Z
L
H
H
H
H
L
H = high level, L = low level, X = irrelevant,
Z = high impedance
EACH RECEIVER
INPUTS
RIN
EN
OUTPUT
ROUT
H
L
L
H
L
L
X
H
Z
Open
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), Open = input
disconnected or connected driver off
logic diagram (positive logic)
DIN1
DIN2
PWRDOWN
EN
ROUT1
ROUT2
2
13
17
12
8
20
DOUT1
DOUT2
Powerdown
1
15
16
10
9
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• DALLAS, TEXAS 75265
RIN1
RIN2
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Positive output supply voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Negative output supply voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to −7 V
Supply voltage difference, V+ − V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V
Input voltage range, VI: Drivers, EN, PWRDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 V to 25 V
Output voltage range, VO: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −13.2 V to 13.2 V
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Package thermal impedance, θJA (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4 and Figure 5)
Supply voltage
VCC = 3.3 V
VCC = 5 V
VIH
Driver and control high-level input voltage
DIN, EN, PWRDOWN
VIL
VI
Driver and control low-level input voltage
DIN, EN, PWRDOWN
Driver and control input voltage
DIN, EN, PWRDOWN
VI
Receiver input voltage
VCC = 3.3 V
VCC = 5 V
MAX3222C
TA
Operating free-air temperature
MAX3222I
MIN
NOM
MAX
3
3.3
3.6
4.5
5
5.5
UNIT
V
2
V
2.4
0.8
V
0
5.5
V
−25
25
V
0
70
−40
85
°C
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 5)
PARAMETER
II
ICC
TEST CONDITIONS
Input leakage current (EN, PWRDOWN)
Supply current
No load, PWRDOWN at VCC
MIN
TYP‡
MAX
±0.01
±1
µA
0.3
1
mA
10
µA
Supply current (powered off)
No load, PWRDOWN at GND
1
‡ All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
3
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 5)
PARAMETER
TEST CONDITIONS
MIN
TYP†
VOH
VOL
High-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = GND
5
5.4
Low-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = VCC
−5
−5.4
IIH
IIL
High-level input current
VI = VCC
VI at GND
Low-level input current
IOS
Short-circuit output current‡
VCC = 3.6 V,
VCC = 5.5 V,
ro
Output resistance
VCC, V+, and V− = 0 V,
VO = ±2 V
PWRDOWN = GND,
VCC = 3 V to 3.6 V
VO = ±12 V,
PWRDOWN = GND,
VCC = 4.5 V to 5.5 V
VO = ±10 V,
Ioff
Output leakage current
VO = 0 V
VO = 0 V
300
MAX
UNIT
V
V
±0.01
±1
µA
±0.01
±1
µA
±35
±60
mA
Ω
10M
±25
µA
±25
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
‡ Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output
should be shorted at a time.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 5)
PARAMETER
TEST CONDITIONS
MIN
TYP†
150
250
kbit/s
300
ns
MAX
Maximum data rate
CL = 1000 pF,
One DOUT switching,
RL = 3 kΩ,
See Figure 1
tsk(p)
Pulse skew§
CL = 150 pF to 2500 pF,
See Figure 2
RL = 3 kΩ to 7 kΩ,
SR(tr)
Slew rate, transition region
(See Figure 1)
RL = 3 kΩ to 7 kΩ,
VCC = 3.3 V
CL = 150 pF to 1000 pF
6
30
CL = 150 pF to 2500 pF
4
30
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
§ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V/µs
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
RECEIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 5)
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
IOH = −1 mA
IOL = 1.6 mA
Low-level output voltage
VIT+
Positive-going input threshold voltage
VCC = 3.3 V
VCC = 5 V
VIT−
Negative-going input threshold voltage
VCC = 3.3 V
VCC = 5 V
Vhys
Ioff
Input hysteresis (VIT+ − VIT−)
TYP†
MIN
VCC − 0.6 V
MAX
VCC − 0.1 V
V
0.4
1.5
2.4
1.8
2.4
0.6
1.2
0.8
1.5
±0.05
EN = VCC
ri
Input resistance
VI = ±3 V to ±25 V
3
5
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
V
V
V
0.3
Output leakage current
UNIT
V
±10
µA
7
kΩ
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
tPLH
tPHL
Propagation delay time, low- to high-level output
CL = 150 pF, See Figure 3
300
ns
Propagation delay time, high- to low-level output
CL= 150 pF, See Figure 3
300
ns
ten
Output enable time
CL= 150 pF, RL = 3 kΩ,
See Figure 4
200
ns
tdis
Output disable time
CL= 150 pF, RL = 3 kΩ,
See Figure 4
200
ns
tsk(p) Pulse skew‡
See Figure 3
300
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
5
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
CL
(see Note A)
3V
PWRDOWN
tTHL
tTLH
VOH
3V
3V
Output
−3 V
−3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) +
t
THL
6V
or t
TLH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 1. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL
tPLH
VOH
3V
PWRDOWN
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 2. Driver Pulse Skew
EN
0V
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 3. Receiver Propagation Delay Times
6
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• DALLAS, TEXAS 75265
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
S1
GND
RL
Output
3 V or 0 V
CL
(see Note A)
EN
3V
Input
1.5 V
0V
tPZH
(S1 at GND)
tPHZ
S1 at GND)
VOH
Output
50%
0.3 V
Generator
(see Note B)
1.5 V
50 Ω
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 4. Receiver Enable and Disable Times
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
± SLLS408G − JANUARY 2000 − REVISED MARCH 2004
APPLICATION INFORMATION
1
EN
2
+
C1
−
3
C3†
+
20
Powerdown
VCC
C1+
V+
GND
PWRDOWN
19
18
+ C
BYPASS
− = 0.1 µF
−
4
5
17
C1−
16
C2+
DOUT1
RIN1
+
C2
−
6
7
C4
DOUT2
RIN2
ROUT2
−
15
C2−
14
V−
ROUT1
NC
+
8
13
9
12
10
11
DIN1
DIN2
NC
† C3 can be connected to VCC or GND.
NOTES: A. Resistor values shown are nominal.
B. NC − No internal connection
C. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
VCC vs CAPACITOR VALUES
VCC
3.3 V " 0.3 V
C1
0.1 µF
C2, C3, and C4
0.1 µF
5 V " 0.5 V
0.047 µF
0.33 µF
3 V to 5.5 V
0.1 µF
0.47 µF
Figure 5. Typical Operating Circuit and Capacitor Values
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MAX3222CDB
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CDBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CDBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
MAX3222CDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
MAX3222CDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
MAX3222CDWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MAX3222C
MAX3222CPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222CPWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
MA3222C
MAX3222IDB
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IDBG4
ACTIVE
SSOP
DB
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IDBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IDBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MAX3222I
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MAX3222IDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MAX3222I
MAX3222IDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MAX3222I
MAX3222IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
MAX3222IPWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
MB3222I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MAX3222CDBR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
MAX3222CDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
MAX3222CPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
MAX3222IDBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
MAX3222IDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
MAX3222IPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MAX3222CDBR
SSOP
DB
20
2000
367.0
367.0
38.0
MAX3222CDWR
SOIC
DW
20
2000
367.0
367.0
45.0
MAX3222CPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
MAX3222IDBR
SSOP
DB
20
2000
367.0
367.0
38.0
MAX3222IDWR
SOIC
DW
20
2000
367.0
367.0
45.0
MAX3222IPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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