ICST ICS844004AGI-04LF Femtoclocksâ ¢ crystal/lvcmos-to-lvds frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844004I-04 is a 4 output LVDS
Synthesizer optimized to generate clock
HiPerClockS™ frequencies for a variety of high performance
applications and is a member of the
HiPerClocks TM family of high perfor mance
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a singleended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS’ 3 rd generation
low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple por t line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
• Four LVDS outputs
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
XTAL_IN
OSC
0
÷1
0
÷4
1
XTAL_OUT
CLK Pulldown
1
Phase
Detector
VCO
Q0
nQ0
INPUT_SEL Pulldown
M = ÷32
MR
F_SEL0
Pulldown
Pullup
0
Q1
1
nQ1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
VDDO
Q3
nQ3
GND
F_SEL2
INPUT_SEL
CLK
GND
XTAL_IN
XTAL_OUT
ICS844004I-04
F_SEL1 Pullup
F_SEL2
nQ1
Q1
VDD o
Q0
nQ0
MR
F_SEL3
nc
VDDA
F_SEL0
VDD
F_SEL1
0
Q2
1
nQ2
0
Q3
1
nQ3
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
F_SEL3 Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
Q0, nQ0
Ouput
6
MR
Input
7,
10,
12,
18
8
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
nc
Unused
9
VDDA
Power
Analog supply pin.
11
Power
15, 19
VDD
XTAL_OUT,
XTAL_IN
GND
Power
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
16
CL K
Input
17
INPUT_SEL
Input
20, 21
nQ3, Q3
Output
23, 24
Q2, nQ2
Output
13, 14
Type
Description
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Input
Pullup
Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
Input
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
TABLE 3. OUTPUT CONFIGURATION
Inputs
AND
Minimum
Maximum
Units
FREQUENCY RANGE FUNCTION TABLE
N Divider Value
Output Frequency (MHz)
N0:N3
Q0/nQ0:Q3/nQ3
622.08
1
622.08
622.08
4
155.52
F_SELx
XTAL (MHz)
VCO
(MHz)
0
19.44
1
19.44
0
18.75
60 0
1
600
1
18.75
600
4
150
0
19.53125
625
1
625
1
19.53125
625
4
156.25
0
20.141601
644.5312
1
644.5312
1
20.141601
644.5312
4
161.13
844004AGI-04
Typical
www.icst.com/products/hiperclocks.html
2
Application
SONET/SDH
SATA
10 Gigabit Ethernet
10 Gigabit Ethernet
66B/64B FEC
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
70°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
IDD
Power Supply Current
V
80
mA
IDDA
Analog Supply Current
8
mA
IDDO
Output Supply Current
87
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
ΔV/ΔT
Input High Current
Input Low Current
Input Edge Rate
Test Conditions
Minimum Typical
2
-0.3
Maximum
VDD + 0.3
Units
V
0.8
V
CLK,
MR, INPUT_SEL
VDD = VIN = 3.465
150
µA
F_SEL0:F_SEL3
VDD = VIN = 3.465
5
µA
CLK,
MR, INPUT_SEL
VDD = 3.465V, VIN = 0V
-5
µA
F_SEL0:F_SEL3
VDD = 3.465V, VIN = 0V
-150
µA
CLK
20% - 80%
TBD
V/ns
Maximum
Units
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
350
mV
Δ VOD
VOD Magnitude Change
40
mV
VOS
Offset Voltage
1.35
V
Δ VOS
VOS Magnitude Change
50
mV
844004AGI-04
Test Conditions
Minimum
www.icst.com/products/hiperclocks.html
3
Typical
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
21.25
MHz
Fundamental
Frequency
17.5
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
t R / tF
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
Output Divider = ÷1
560
680
MHz
Output Divider = ÷4
140
170
MH z
155.52MHz,
Integration Range: 12kHz - 20MHz
156.25MHz,
Integration Range: 1.875MHz - 20MHz
622.08MHz,
Integration Range: 12kHz - 20MHz
20% to 80%
Typical
TBD
ps
0.75
ps
0.51
ps
0.71
ps
29 0
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844004AGI-04
www.icst.com/products/hiperclocks.html
4
%
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 155.52MHZ AT 3.3V
➤
0
-10
-20
OC3 SONET Filter
-30
-40
-50
155.52MHz
RMS Phase Jitter (Random)
12kHz to 5MHz = 0.75ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
➤
-110
-120
-130
-140
-150
➤
NOISE POWER dBc
Hz
-60
-160
Phase Noise Result by adding
OC3 SONET Filter to raw data
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 622.08MHZ AT 3.3V
➤
0
-10
-20
OC 12 SONET Filter
-40
-50
622.08MHz
-60
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.71ps (typical)
-70
-80
-90
Raw Phase Noise Data
➤
-100
-110
-120
-130
➤
NOISE POWER dBc
Hz
-30
-140
-150
Phase Noise Result by adding
OC 12 SONET Filter to raw data
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844004AGI-04
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
V DD
nQx
SCOPE
Qx
Qx
Power Supply
+
Float GND
nQy
LVDS
-
Qy
nQx
tsk(o)
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Noise Power
nQ0:nQ3
Q0:Q3
t PW
Phase Noise Mask
f1
Offset Frequency
t
odc =
f2
PERIOD
t PW
x 100%
t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
out
80%
DC Input
VSW I N G
Clock
Outputs
LVDS
➤
80%
20%
20%
tR
➤
out
tF
VOS/Δ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
➤
out
➤
LVDS
100
VOD/Δ VOD
out
➤
DC Input
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844004AGI-04
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844004I-04 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
parallel resonant crystal and were chosen to minimize
the ppm error.
The ICS844004I-04 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 19.44MHz 18pF
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
ICS844004I-04
Figure 2. CRYSTAL INPUt INTERFACE
844004AGI-04
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT
AND
OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVDS
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844004AGI-04
www.icst.com/products/hiperclocks.html
8
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
SCHEMATIC EXAMPLE
Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R2, C3 and C4
should also be located as close to the VCCA pin as possible.
For LVDS driver, the unused output pairs should be terminated
with a 100Ω resistor across.
Figure 4 shows a schematic example for ICS844004i-04. In this
example, the input is a 19.44MHz parallel resonant crystal with
load capacitor CL=18pF. The 22pF frequency fine tuning
capacitors are used C1 and C2. This example also shows general
logic control input handling. For decoupling capacitors, it is
recommended to have one decouple capacitor per power pin.
VCC
VCCA
R2
10
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
VCC
VCCO
R3
100
C6
0.1u
F_SEL1
VDD
F_SEL0
VDDA
NC
F_SEL3
MR
nQ0
Q0
VDDO
Q1
nQ1
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
U1
844004i-04
XTAL_OUT
XTAL_IN
GND
CLK
INPUT_SEL
F_SEL2
GND
nQ3
Q3
VDDO
Q2
nQ2
RU1
1K
Set Logic
Input to
'0'
VCC
-
VCC=3.3V
VCCO=3.3V
13
14
15
16
17
18
19
20
21
22
23
24
Set Logic
Input to
'1'
VCC
Zo = 50 Ohm
C7
0.1u
12
11
10
9
8
7
6
5
4
3
2
1
Logic Control Input Examples
Zo = 50 Ohm
+
C2
33pF
VCC
R4
100
X1
19.44MHz
18pF
Zo = 50 Ohm
VCCO
C9
0.1u
C1
27pF
-
C8
0.1u
FIGURE 4. ICS844004I-04 SCHEMATIC EXAMPLE
844004AGI-04
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844004I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844004I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 8mA) = 304.92mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 87mA = 301.45mW
Total Power_MAX = 304.92mW + 301.45mW = 606.37mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability
of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7
below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.606W * 65°C/W = 124°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
844004AGI-04
0
1
2.5
70°C/W
65°C/W
62°C/W
www.icst.com/products/hiperclocks.html
10
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844004I-04 is: 2285
844004AGI-04
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844004AGI-04
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 26, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-04
FEMTOCLOCKS™CRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844004AGI-04
ICS844004AI04
24 Lead TSSOP
tube
-40°C to 85°C
ICS844004AGI-04T
ICS844004AI04
24 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS844004AGI-04LF
ICS44004AI04L
24 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS844004AGI-04LFT
ICS44004AI04L
24 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844004AGI-04
www.icst.com/products/hiperclocks.html
13
REV. A JANUARY 26, 2006
Similar pages