DATASHEET NO R OBSOLET E conta COMMEN E PRODU C ct ou DED r 1-888 REPL T -INTE Technica A CEM l RSIL ICL8038 or ww Support C ENT en w.inte rsil.c ter at Precision Waveform Generator/Voltage Controlled Oscillator om/ts c The ICL8038 waveform generator is a monolithic integrated circuit capable of producing high accuracy sine, square, triangular, sawtooth and pulse waveforms with a minimum of external components. The frequency (or repetition rate) can be selected externally from 0.001Hz to more than 300kHz using either resistors or capacitors, and frequency modulation and sweeping can be accomplished with an external voltage. The ICL8038 is fabricated with advanced monolithic technology, using Schottky barrier diodes and thin film resistors, and the output is stable over a wide range of temperature and supply variations. These devices may be interfaced with phase locked loop circuitry to reduce temperature drift to less than 250ppm/oC. FN2864 Rev.4.00 Apr 2001 Features • Low Frequency Drift with Temperature. . . . . . 250ppm/oC • Low Distortion . . . . . . . . . . . . . . . 1% (Sine Wave Output) • High Linearity . . . . . . . . . . . 0.1% (Triangle Wave Output) • Wide Frequency Range . . . . . . . . . . . .0.001Hz to 300kHz • Variable Duty Cycle . . . . . . . . . . . . . . . . . . . . . 2% to 98% • High Level Outputs. . . . . . . . . . . . . . . . . . . . . . TTL to 28V • Simultaneous Sine, Square, and Triangle Wave Outputs • Easy to Use - Just a Handful of External Components Required Ordering Information STABILITY TEMP. RANGE (oC) ICL8038CCPD 250ppm/oC (Typ) 0 to 70 14 Ld PDIP E14.3 ICL8038CCJD 250ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3 ICL8038BCJD 180ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3 ICL8038ACJD 120ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3 PART NUMBER Pinout PACKAGE PKG. NO. Functional Diagram ICL8038 (PDIP, CERDIP) TOP VIEW SINE WAVE 1 ADJUST 14 NC SINE WAVE OUT 2 13 NC TRIANGLE OUT 3 12 SINE WAVE ADJUST 4 11 V- OR GND 5 10 TIMING CAPACITOR V+ 6 9 SQUARE WAVE OUT FM BIAS 7 8 FM SWEEP INPUT DUTY CYCLE FREQUENCY ADJUST 10 2I C CURRENT SOURCE #2 COMPARATOR #2 FLIP-FLOP 11 9 V+ COMPARATOR #1 I BUFFER FN2864 Rev.4.00 Apr 2001 6 CURRENT SOURCE #1 V- OR GND SINE CONVERTER BUFFER 3 2 Page 1 of 12 ICL8038 Absolute Maximum Ratings Thermal Information Supply Voltage (V- to V+). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Input Voltage (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Input Current (Pins 4 and 5). . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Sink Current (Pins 3 and 9) . . . . . . . . . . . . . . . . . . . . . 25mA Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 115 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range ICL8038AC, ICL8038BC, ICL8038CC . . . . . . . . . . . . 0oC to 70oC Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = 10V or +20V, TA = 25oC, RL = 10k, Test Circuit Unless Otherwise Specified PARAMETER Supply Voltage Operating Range Supply Current SYMBOL TEST CONDITIONS ICL8038CC MIN ICL8038BC TYP MAX MIN ICL8038AC TYP MAX MIN TYP MAX UNITS VSUPPLY V+ Single Supply +10 - +30 +10 - +30 +10 - +30 V V+, V- Dual Supplies 5 - 15 5 - 15 5 - 15 V 12 20 - 12 20 - 12 20 mA ISUPPLY VSUPPLY = 10V (Note 2) FREQUENCY CHARACTERISTICS (All Waveforms) Max. Frequency of Oscillation fMAX 100 - - 100 - - 100 - - kHz Sweep Frequency of FM Input fSWEEP - 10 - - 10 - - 10 - kHz Sweep FM Range (Note 3) - 35:1 - - 35:1 - - 35:1 - FM Linearity 10:1 Ratio - 0.5 - - 0.2 - - 0.2 - - - 120 - 0.05 - %/V % Frequency Drift with Temperature (Note 5) f/T 0oC to 70oC - 250 - - 180 ppm/oC Frequency Drift with Supply Voltage f/V Over Supply Voltage Range - 0.05 - - 0.05 Leakage Current IOLK V9 = 30V - - 1 - - 1 - - 1 A Saturation Voltage VSAT ISINK = 2mA - 0.2 0.5 - 0.2 0.4 - 0.2 0.4 V Rise Time tR RL = 4.7k - 180 - - 180 - - 180 - ns Fall Time tF RL = 4.7k - 40 - - 40 - - 40 - ns Typical Duty Cycle Adjust (Note 6) D 98 2 - 98 2 - 98 % OUTPUT CHARACTERISTICS Square Wave 2 Triangle/Sawtooth/Ramp Amplitude VTRIAN- RTRI = 100k 0.30 0.33 - 0.30 0.33 - 0.30 0.33 - xVSUPPLY - 0.1 - - 0.05 - - 0.05 - % - 200 - - 200 - - 200 - GLE Linearity Output Impedance FN2864 Rev.4.00 Apr 2001 ZOUT IOUT = 5mA Page 2 of 12 ICL8038 Electrical Specifications PARAMETER VSUPPLY = 10V or +20V, TA = 25oC, RL = 10k, Test Circuit Unless Otherwise Specified (Continued) SYMBOL ICL8038CC ICL8038BC ICL8038AC TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX RSINE = 100k 0.2 0.22 - 0.2 0.22 - 0.2 0.22 - xVSUPPLY UNITS Sine Wave Amplitude VSINE THD THD RS = 1M (Note 4) - 2.0 5 - 1.5 3 - 1.0 1.5 % THD Adjusted THD Use Figure 4 - 1.5 - - 1.0 - - 0.8 - % NOTES: 2. RA and RB currents not included. 3. VSUPPLY = 20V; RA and RB = 10k, f 10kHz nominal; can be extended 1000 to 1. See Figures 5A and 5B. 4. 82k connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use RA and RB.) 5. Figure 1, pins 7 and 8 connected, VSUPPLY = 10V. See Typical Curves for T.C. vs VSUPPLY. 6. Not tested, typical value for design purposes only. Test Conditions PARAMETER RA RB RL C SW1 MEASURE Supply Current 10k 10k 10k 3.3nF Closed Current Into Pin 6 Sweep FM Range (Note 7) 10k 10k 10k 3.3nF Open Frequency at Pin 9 Frequency Drift with Temperature 10k 10k 10k 3.3nF Closed Frequency at Pin 3 Frequency Drift with Supply Voltage (Note 8) 10k 10k 10k 3.3nF Closed Frequency at Pin 9 Sine 10k 10k 10k 3.3nF Closed Pk-Pk Output at Pin 2 Triangle 10k 10k 10k 3.3nF Closed Pk-Pk Output at Pin 3 Leakage Current (Off) (Note 9) 10k 10k 3.3nF Closed Current into Pin 9 Saturation Voltage (On) (Note 9) 10k 10k 3.3nF Closed Output (Low) at Pin 9 Rise and Fall Times (Note 11) 10k 10k 4.7k 3.3nF Closed Waveform at Pin 9 Max 50k ~1.6k 10k 3.3nF Closed Waveform at Pin 9 Min ~25k 50k 10k 3.3nF Closed Waveform at Pin 9 Triangle Waveform Linearity 10k 10k 10k 3.3nF Closed Waveform at Pin 3 Total Harmonic Distortion 10k 10k 10k 3.3nF Closed Waveform at Pin 2 Output Amplitude (Note 10) Duty Cycle Adjust (Note 11) NOTES: 7. The hi and lo frequencies can be obtained by connecting pin 8 to pin 7 (fHI) and then connecting pin 8 to pin 6 (fLO). Otherwise apply Sweep Voltage at pin 8 (2/3 VSUPPLY +2V) VSWEEP VSUPPLY where VSUPPLY is the total supply voltage. In Figure 5B, pin 8 should vary between 5.3V and 10V with respect to ground. 8. 10V V+ 30V, or 5V VSUPPLY 15V. 9. Oscillation can be halted by forcing pin 10 to +5V or -5V. 10. Output Amplitude is tested under static conditions by forcing pin 10 to 5V then to -5V. 11. Not tested; for design purposes only. FN2864 Rev.4.00 Apr 2001 Page 3 of 12 ICL8038 Test Circuit +10V RA 10K 7 RL 10K RB 10K 4 5 6 9 SW1 N.C. 8 ICL8038 3 RTRI 10 11 12 2 C 3300pF RSINE 82K -10V FIGURE 1. TEST CIRCUIT Detailed Schematic 6 CURRENT SOURCES R1 8 11K 7 Q1 Q2 REXT B REXT A 5 4 R41 4K Q14 Q4 Q48 R8 5K Q3 R2 Q 39K 6 Q9 Q8 10 Q16Q17 CEXT Q10 R3 30K Q11 R7B R7A 15K 10K Q12 Q30 R4 100 Q32 R13 620 Q24 Q23 R11 270 R12 2.7K Q25 R16 1.8K Q27 R15 470 Q29 R17 4.7K R18 4.7K R41 27K Q36 Q 38 R35 330 Q42 R25 33K R26 33K R27 33K R45 33K R28 33K R29 33K R30 33K R31 33K R23 Q39 Q40 3 R44 1K 2.7K R24 R42 BUFFER AMPLIFIER 27K 11 Application Information (See Functional Diagram) An external capacitor C is charged and discharged by two current sources. Current source #2 is switched on and off by a flip-flop, while current source #1 is on continuously. Assuming that the flip-flop is in a state such that current source #2 is off, and the capacitor is charged with a current I, the voltage across the capacitor rises linearly with time. When this voltage reaches the level of comparator #1 (set at 2/3 of the supply voltage), the flip-flop is triggered, changes states, and releases current source #2. This current source normally carries a current 2I, thus the capacitor is discharged with a net-current I and the voltage R36 1600 Q50 R37 330 Q51 Q52 R38 375 Q53 Q54 800 R39 200 Q55 Q56 FLIP-FLOP FN2864 Rev.4.00 Apr 2001 10K Q37 Q35 Q28 Q26 Q49 R22 R43 27K R14 27K 9 10K Q41 R10 5K Q33 Q34 R9 5K Q44 Q43 Q22 Q19 R6 100 R5 100 2.7K R21 R34 375 Q45 Q20 Q21 Q13 Q31 Q46 800 R20 Q18 Q15 R46 40K 1 R33 200 Q47 R19 Q5 COMPARATOR Q7 V+ R32 5.2K 2 R40 5.6K 12 REXTC 82K SINE CONVERTER across it drops linearly with time. When it has reached the level of comparator #2 (set at 1/3 of the supply voltage), the flip-flop is triggered into its original state and the cycle starts again. Four waveforms are readily obtainable from this basic generator circuit. With the current sources set at I and 2I respectively, the charge and discharge times are equal. Thus a triangle waveform is created across the capacitor and the flipflop produces a square wave. Both waveforms are fed to buffer stages and are available at pins 3 and 9. Page 4 of 12 ICL8038 The levels of the current sources can, however, be selected over a wide range with two external resistors. Therefore, with the two currents set at values different from I and 2I, an asymmetrical sawtooth appears at Terminal 3 and pulses with a duty cycle from less than 1% to greater than 99% are available at Terminal 9. The sine wave is created by feeding the triangle wave into a nonlinear network (sine converter). This network provides a decreasing shunt impedance as the potential of the triangle moves toward the two extremes. Waveform Timing The symmetry of all waveforms can be adjusted with the external timing resistors. Two possible ways to accomplish this are shown in Figure 3. Best results are obtained by keeping the timing resistors RA and RB separate (A). RA controls the rising portion of the triangle and sine wave and the 1 state of the square wave. The magnitude of the triangle waveform is set at 1/3 VSUPPLY; therefore the rising portion of the triangle is, FIGURE 2A. SQUARE WAVE DUTY CYCLE - 50% RA C C 1/3 V SUPPLY R A CV t 1 = -------------- = ------------------------------------------------------------------- = -----------------0.22 V SUPPLY 0.66 I The falling portion of the triangle and sine wave and the 0 state of the square wave is: t2 R R C C 1/3V SUPPLY A B CV = ------------- = ----------------------------------------------------------------------------------- = ------------------------------------V 1 V 2R A – R B 0.66 SUPPLY SUPPLY 2 0.22 ------------------------ – 0.22 -----------------------R R B A Thus a 50% duty cycle is achieved when RA = RB. If the duty cycle is to be varied over a small range about 50% only, the connection shown in Figure 3B is slightly more convenient. A 1k potentiometer may not allow the duty cycle to be adjusted through 50% on all devices. If a 50% duty cycle is required, a 2k or 5k potentiometer should be used. With two separate timing resistors, the frequency is given by: 1 1 f = ---------------- = -----------------------------------------------------t1 + t2 RA C RB ------------ 1 + ------------------------ 0.66 2R A – R B or, if RA = RB = R 0.33 f = ----------- (for Figure 3A) RC FIGURE 2B. SQUARE WAVE DUTY CYCLE - 80% FIGURE 2. PHASE RELATIONSHIP OF WAVEFORMS V+ V+ RA 7 4 5 8 RL RB 6 ICL8038 10 11 C 1k RA 9 7 3 8 12 2 4 5 6 ICL8038 10 82K RL RB 11 9 3 12 2 C 100K V- OR GND FIGURE 3A. V- OR GND FIGURE 3B. FIGURE 3. POSSIBLE CONNECTIONS FOR THE EXTERNAL TIMING RESISTORS FN2864 Rev.4.00 Apr 2001 Page 5 of 12 ICL8038 Neither time nor frequency are dependent on supply voltage, even though none of the voltages are regulated inside the integrated circuit. This is due to the fact that both currents and thresholds are direct, linear functions of the supply voltage and thus their effects cancel. Reducing Distortion To minimize sine wave distortion the 82k resistor between pins 11 and 12 is best made variable. With this arrangement distortion of less than 1% is achievable. To reduce this even further, two potentiometers can be connected as shown in Figure 4; this configuration allows a typical reduction of sine wave distortion close to 0.5%. V+ 1k RA 7 4 5 8 RL RB 6 ICL8038 10 11 12 9 2 100k C 10k 100k 10k V- OR GND FIGURE 4. CONNECTION TO ACHIEVE MINIMUM SINE WAVE DISTORTION Selecting RA, RB and C For any given output frequency, there is a wide range of RC combinations that will work, however certain constraints are placed upon the magnitude of the charging current for optimum performance. At the low end, currents of less than 1A are undesirable because circuit leakages will contribute significant errors at high temperatures. At higher currents (I > 5mA), transistor betas and saturation voltages will contribute increasingly larger errors. Optimum performance will, therefore, be obtained with charging currents of 10A to 1mA. If pins 7 and 8 are shorted together, the magnitude of the charging current due to RA can be calculated from: R 1 V+ – V- 1 0.22 V+ – V- I = ---------------------------------------- -------- = ----------------------------------- R1 + R2 RA RA R1 and R2 are shown in the Detailed Schematic. A similar calculation holds for RB. The capacitor value should be chosen at the upper end of its possible range. FN2864 Rev.4.00 Apr 2001 The waveform generator can be operated either from a single power supply (10V to 30V) or a dual power supply (5V to 15V). With a single power supply the average levels of the triangle and sine wave are at exactly one-half of the supply voltage, while the square wave alternates between V+ and ground. A split power supply has the advantage that all waveforms move symmetrically about ground. The square wave output is not committed. A load resistor can be connected to a different power supply, as long as the applied voltage remains within the breakdown capability of the waveform generator (30V). In this way, the square wave output can be made TTL compatible (load resistor connected to +5V) while the waveform generator itself is powered from a much higher voltage. Frequency Modulation and Sweeping 3 1 Waveform Out Level Control and Power Supplies The frequency of the waveform generator is a direct function of the DC voltage at Terminal 8 (measured from V+). By altering this voltage, frequency modulation is performed. For small deviations (e.g. 10%) the modulating signal can be applied directly to pin 8, merely providing DC decoupling with a capacitor as shown in Figure 5A. An external resistor between pins 7 and 8 is not necessary, but it can be used to increase input impedance from about 8k (pins 7 and 8 connected together), to about (R + 8k). For larger FM deviations or for frequency sweeping, the modulating signal is applied between the positive supply voltage and pin 8 (Figure 5B). In this way the entire bias for the current sources is created by the modulating signal, and a very large (e.g. 1000:1) sweep range is created (f = Minimum at VSWEEP = 0, i.e., Pin 8 = V+). Care must be taken, however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the supply voltage (yet the trigger thresholds still are) and thus the frequency becomes dependent on the supply voltage. The potential on Pin 8 may be swept down from V+ by (1/3 VSUPPLY - 2V). V+ RA 7 4 RL RB 5 6 9 R 8 FM ICL8038 10 11 C 3 12 2 81K V- OR GND FIGURE 5A. CONNECTIONS FOR FREQUENCY MODULATION Page 6 of 12 ICL8038 V+ V+ SWEEP VOLTAGE 4 5 8 6 ICL8038 10 9 7 3 8 4 15K 5 9 ICL8038 1N914 11 12 2 11 RB RA RL RB RA 10 2 1N914 C 81K C V- OR GND STROBE 2N4392 100K -15V OFF FIGURE 5B. CONNECTIONS FOR FREQUENCY SWEEP FIGURE 5. ON +15V (+10V) -15V (-10V) FIGURE 7. STROBE TONE BURST GENERATOR Typical Applications The sine wave output has a relatively high output impedance (1k Typ). The circuit of Figure 6 provides buffering, gain and amplitude adjustment. A simple op amp follower could also be used. V+ RB RA 7 4 5 6 2 8 ICL8038 10 11 The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as shown in Figure 10. AMPLITUDE 100K + 741 - To obtain a 1000:1 Sweep Range on the ICL8038 the voltage across external resistors RA and RB must decrease to nearly zero. This requires that the highest voltage on control Pin 8 exceed the voltage at the top of RA and RB by a few hundred mV. The Circuit of Figure 8 achieves this by using a diode to lower the effective supply voltage on the ICL8038. The large resistor on pin 5 helps reduce duty cycle variations with sweep. +10V 20K 1N457 DUTY CYCLE 4.7K 0.1F C 15K 1K 4.7K 4.7K V- FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS With a dual supply voltage the external capacitor on Pin 10 can be shorted to ground to halt the ICL8038 oscillation. Figure 7 shows a FET switch, diode ANDed with an input strobe signal to allow the output to always start on the same slope. 5 10K FREQ. 8 4 ICL8038 10 20K 15M 11 0.0047F 6 9 3 12 2 DISTORTION 100K -10V FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY FN2864 Rev.4.00 Apr 2001 Page 7 of 12 ICL8038 R1 FM BIAS V1+ SQUARE WAVE OUT VCO IN INPUT DEMODULATED FM AMPLIFIER PHASE DETECTOR V2+ DUTY CYCLE FREQUENCY ADJUST 7 4 TRIANGLE OUT 6 5 3 SINE WAVE OUT 9 8 R2 ICL8038 10 2 11 12 SINE WAVE ADJ. TIMING CAP. LOW PASS FILTER SINE WAVE ADJ. 1 V-/GND FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP HIGH FREQUENCY SYMMETRY 1k 10k 500 4.7k 1N753A (6.2V) 4.7k 1M 100k 1,000pF 4 5 6 100k LOW FREQUENCY SYMMETRY 9 +15V - 1k 741 + -VIN 8 ICL8038 FUNCTION GENERATOR P4 10k OFFSET 10 11 12 3,900pF +15V 3 SINE WAVE OUTPUT 2 + 741 + 50F 100k 15V SINE WAVE DISTORTION -15V FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR Use in Phase Locked Loops Its high frequency stability makes the ICL8038 an ideal building block for a phase locked loop as shown in Figure 9. In this application the remaining functional blocks, the phase detector and the amplifier, can be formed by a number of available ICs (e.g., MC4344, NE562). In order to match these building blocks to each other, two steps must be taken. First, two different supply voltages are used and the square wave output is returned to the supply of the phase detector. This assures that the VCO input voltage will not exceed the capabilities of the phase detector. If a smaller VCO signal is required, a simple resistive voltage divider is connected between pin 9 of the waveform generator and the VCO input of the phase detector. FN2864 Rev.4.00 Apr 2001 Second, the DC output level of the amplifier must be made compatible to the DC level required at the FM input of the waveform generator (pin 8, 0.8V+). The simplest solution here is to provide a voltage divider to V+ (R1, R2 as shown) if the amplifier has a lower output level, or to ground if its level is higher. The divider can be made part of the low-pass filter. This application not only provides for a free-running frequency with very low temperature drift, but is also has the unique feature of producing a large reconstituted sinewave signal with a frequency identical to that at the input. For further information, see Intersil Application Note AN013, “Everything You Always Wanted to Know About the ICL8038”. Page 8 of 12 ICL8038 Definition of Terms Supply Voltage (VSUPPLY). The total supply voltage from V+ to V-. Supply Current. The supply current required from the power supply to operate the device, excluding load currents and the currents through RA and RB. Frequency Range. The frequency range at the square wave output through which circuit operation is guaranteed. FM Linearity. The percentage deviation from the best fit straight line on the control voltage versus output frequency curve. Output Amplitude. The peak-to-peak signal amplitude appearing at the outputs. Saturation Voltage. The output voltage at the collector of Q23 when this transistor is turned on. It is measured for a sink current of 2mA. Rise and Fall Times. The time required for the square wave output to change from 10% to 90%, or 90% to 10%, of its final value. Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep voltage to pin 8. For correct operation, the sweep voltage should be within the range: Triangle Waveform Linearity. The percentage deviation from the best fit straight line on the rising and falling triangle waveform. (2/3 VSUPPLY + 2V) < VSWEEP < VSUPPLY Total Harmonic Distortion. The total harmonic distortion at the sine wave output. Typical Performance Curves 1.03 NORMALIZED FREQUENCY SUPPLY CURRENT (mA) 20 -55oC 15 125oC 25oC 10 5 5 10 15 20 25 1.02 1.01 1.00 0.99 0.98 30 5 10 15 SUPPLY VOLTAGE (V) FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE 25 30 FIGURE 12. FREQUENCY vs SUPPLY VOLTAGE 200 1.03 1.02 150 10V 20V 30V 1.00 20V 10V 30V RISE TIME 125oC 1.01 25oC TIME (ns) NORMALIZED FREQUENCY 20 SUPPLY VOLTAGE (V) -55oC 100 125oC 25oC FALL TIME 0.99 -55oC 50 0.98 -50 -25 0 25 75 TEMPERATURE (oC) FIGURE 13. FREQUENCY vs TEMPERATURE FN2864 Rev.4.00 Apr 2001 125 0 0 2 4 6 8 LOAD RESISTANCE (k) FIGURE 14. SQUARE WAVE OUTPUT RISE/FALL TIME vs LOAD RESISTANCE Page 9 of 12 10 ICL8038 Typical Performance Curves (Continued) NORMALIZED PEAK OUTPUT VOLTAGE SATURATION VOLTAGE 2 1.5 125oC 1.0 25oC -55oC 0.5 0 0 2 4 6 8 1.0 25oC 0.9 -55oC 0.8 LOAD CURRENT TO V+ 0 10 2 4 LOAD CURRENT (mA) 6 8 12 14 16 18 20 FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE vs LOAD CURRENT 1.2 10.0 1.1 LINEARITY (%) 1.0 0.9 0.8 1.0 0.1 0.7 0.6 10 100 1K 10K 100K 0.01 1M 10 100 1K 10K 100K 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE vs FREQUENCY FIGURE 18. TRIANGLE WAVE LINEARITY vs FREQUENCY 12 1.1 10 DISTORTION (%) NORMALIZED OUTPUT VOLTAGE 10 LOAD CURRENT (mA) FIGURE 15. SQUARE WAVE SATURATION VOLTAGE vs LOAD CURRENT NORMALIZED OUTPUT VOLTAGE 125oC LOAD CURRENT TO V - 1.0 0.9 8 6 4 ADJUSTED UNADJUSTED 2 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 19. SINE WAVE OUTPUT VOLTAGE vs FREQUENCY FN2864 Rev.4.00 Apr 2001 0 10 100 1K 10K 100K FREQUENCY (Hz) FIGURE 20. SINE WAVE DISTORTION vs FREQUENCY Page 10 of 12 1M ICL8038 Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 D1 0.005 - 0.13 - 5 A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 19.68 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 0.300 BSC 7.62 BSC 6 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.150 2.93 3.81 4 N 14 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 14 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). © Copyright Intersil Americas LLC 2001. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2864 Rev.4.00 Apr 2001 Page 11 of 12 ICL8038 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL (c) E b1 M M (b) -Bbbb S C A-B S D BASE PLANE Q -C- SEATING PLANE A L S1 eA A A b2 b ccc M SECTION A-A D S C A-B S e D S eA/2 c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - 3.81 BSC - eA/2 L 0.150 BSC 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. N 14 14 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. FN2864 Rev.4.00 Apr 2001 Page 12 of 12