MC14020B 14-Bit Binary Counter The MC14020B 14−stage binary counter is constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 14 stages of ripple−carry binary counter. The device advances the count on the negative−going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency−dividing circuits. http://onsemi.com Features • • • • • • • • • Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range Buffered Outputs Available from stages 1 and 4 thru 14 Common Reset Line Pin−for−Pin Replacement for CD4020B NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD Parameter Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA Power Dissipation, per Package (Note 1) 500 mW DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F PIN ASSIGNMENT Q12 1 16 VDD Q13 2 15 Q11 Q14 3 14 Q10 Q6 4 13 Q8 Q5 5 12 Q9 Q7 6 11 R Q4 7 10 C VSS 8 9 Q1 MARKING DIAGRAMS 16 14020BG AWLYWW 1 SOIC−16 TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C 16 14 020B ALYWG G Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1 TSSOP−16 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 9 1 Publication Order Number: MC14020B/D MC14020B TRUTH TABLE Clock Reset Output State X 0 0 1 No Change Advance to Next State All Outputs are Low X = Don’t Care LOGIC DIAGRAM Q1 Q4 9 Q5 7 Q12 1 5 Q13 2 Q14 3 CLOCK C 10 C R Q C Q C R Q C Q C R Q C Q C R Q C Q C R Q C Q C Q R RESET 11 Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 13 Q9 = PIN 12 Q10 = PIN 14 Q11 = PIN 15 VDD = PIN 16 VSS = PIN 8 ORDERING INFORMATION Package Shipping† MC14020BDG SOIC−16 (Pb−Free) 48 Units / Rail MC14020BDR2G SOIC−16 (Pb−Free) 2500 Units / Tape & Reel NLV14020BDR2G* SOIC−16 (Pb−Free) 2500 Units / Tape & Reel MC14020BDTG TSSOP−16 (Pb−Free) 96 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14020B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.42 mA/kHz)f + IDD IT = (0.85 mA/kHz)f + IDD IT = (1.43 mA/kHz)f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 MC14020B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q1 tPHL, tPLH = (1.7 ns/pF) CL + 175 ns tPHL, tPLH = (0.66 ns/pF) CL + 82 ns tPHL, tPLH = (0.5 ns/pF) CL + 55 ns tPLH, tPHL Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns Clock to Q14 tPHL, tPLH − (1.7 ns/pF) CL + 1735 ns tPHL, tPLH = (0.66 ns/pF) CL + 772 ns tPHL, tPLH = (0.5 ns/pF) CL + 535 ns 5.0 10 15 − − − 260 115 80 520 230 160 5.0 10 15 − − − 1820 805 560 3900 1725 1200 ns Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 285 ns tPHL = (0.66 ns/pF) CL + 122 ns tPHL = (0.5 ns/pF) CL + 90 ns tPHL Clock Pulse Width Clock Pulse Frequency Clock Rise and Fall Time VDD Vdc ns 5.0 10 15 − − − 370 155 115 740 310 230 tWH 5.0 10 15 500 165 125 140 55 38 − − − ns fmax 5.0 10 15 1.0 3.0 4.0 2.0 6.0 8.0 − − − MHz tTLH, tTHL 5.0 10 15 − No Limit Reset Pulse Width tWL 5.0 10 15 3000 550 420 320 120 80 − − − ns Reset Recovery Time trec 5.0 10 15 − − − 65 25 15 130 50 30 ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14020B VDD VDD 500 mF PULSE GENERATOR 0.01 mF CERAMIC ID C Q1 Q4 Qn R C Q1 Q4 Q R n 20 ns CL 20 ns CLOCK 90% 50% 10% tWH 20 ns VDD 90% 50% 10% 50% DUTY CYCLE tPLH VSS Figure 1. Power Dissipation Test Circuit and Waveform 4 8 16 tPHL 90% 50% 10% Q tTHL tTLH 2 CL CL CL 20 ns 1 CL VSS VSS CLOCK PULSE GENERATOR Figure 2. Switching Time Test Circuit and Waveforms 32 64 128 256 512 CLOCK RESET Q1 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Figure 3. Timing Diagram http://onsemi.com 5 1024 2048 4096 8192 16,384 CL MC14020B PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 SECTION N−N B −U− L J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC14020B PACKAGE DIMENSIONS SOIC−16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE K −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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