CD4013BMS CMOS Dual ‘D’-Type Flip-Flop December 1992 Features Pinout • High-Voltage Type (20V Rating) Q1 1 14 VDD Q1 2 13 Q2 CLOCK 1 3 12 Q2 • Set-Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely With Clock Level Either “High” Or “Low” • Medium-Speed Operation - 16 MHz (typ.) Clock Toggle Rate at 10V RESET 1 4 11 CLOCK 2 D1 5 10 RESET 2 9 D2 SET 1 6 • Standardized Symmetrical Output Characteristics 8 SET 2 VSS 7 • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Functional Diagram VDD 14 • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” SET 1 D1 CLOCK 1 Applications RESET 1 • Registers SET 2 • Counters D2 • Control Circuits CLOCK 2 Description RESET 2 CD4013BMS consists of two identical, independent data type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively. 6 5 3 2 F/F1 1 Q1 Q1 4 8 9 11 12 13 F/F2 Q2 Q2 10 7 VSS The CD4013BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-62 File Number 3080 Specifications CD4013BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) GROUP A SUBGROUPS LIMITS TEMPERATURE o 1 +25 C oC 2 +125 3 -55o o C MIN MAX UNITS - 2 µA - 200 µA - 2 µA 1 +25 C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 0.7 2.8 V Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 7-63 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4013BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Q, Q SYMBOL TPHL1 TPLH1 Propagation Delay Set to Q, Reset to Q TPHL2 Propagation Delay Set to Q, Reset to Q TPLH2 Transition Time Clock to Q, Q Maximum Clock Input Frequency CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 300 ns - 405 ns - 400 ns - 540 ns - 300 ns - 405 ns - 200 ns - 270 ns 9 +25oC 3.5 - MHz 10, 11 +125oC, -55oC 3.5/1.35 - MHz MIN MAX UNITS - 1.0 µA - 30 µA - 2.0 µA - 60 µA NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 - 2.0 µA +125oC - 120 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -1.6 mA +125oC - -0.9 mA -55oC - -4.2 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 7-64 Specifications CD4013BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Source) IOH15 Input Voltage Low VIL CONDITIONS VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, - 3 V 1, 2 -55oC Input Voltage High VIH Propagation Delay Clock to Q, Q Propagation Delay Set to Q Reset to Q Propagation Delay Set to Q Reset to Q Transition Time Clock to Q, Q Maximum Clock Input Frequency Minimum Data Setup Time TPHL1 TPLH1 TPHL2 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TPLH2 VDD = 10V VDD = 15V TTHL TTLH FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Set or Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance CIN Any Input 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC - 130 ns 1, 2, 3 +25oC - 90 ns 1, 2, 3 +25oC - 170 ns o 1, 2, 3 +25 C - 120 ns 1, 2, 3 +25oC - 130 ns 1, 2, 3 +25oC - 90 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC 8 - MHz 1, 2, 3 +25oC 12 - MHz 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25oC - 15 ns 1, 2, 3 +25oC - 140 ns 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25oC - 40 ns 2, 3 +25oC - 180 ns 2, 3 +25oC - 80 ns 2, 3 +25oC - 50 ns 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC 7-65 MIN MAX UNITS - 7.5 µA -2.8 -0.2 V Specifications CD4013BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL NOTES TEMPERATURE MIN MAX UNITS VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V ∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns N Threshold Voltage Delta ∆VNTH P Threshold Voltage P Threshold Voltage Delta Functional F CONDITIONS VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-66 Specifications CD4013BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 1, 2, 12, 13 3-11 14 Static Burn-In 2 (Note 1) 1, 2, 12, 13 7 3-6, 8-11, 14 Dynamic BurnIn (Note 1) - 4, 6-8, 10 14 1, 2, 12, 13 7 3-6, 8-11, 14 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 1, 2, 12, 13 3, 11 5, 9 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram *4(10) RESET MASTER SECTION CL DATA SLAVE SECTION p TG n p TG n *5(9) CL CL CL CL CL p TG n p TG n CL CL *6(8) Q 1(13) SET CL BUFFERED OUTPUTS CL Q *3(11) 2(12) CL 14 VDD 7 VSS * All inputs are protected by CMOS protection network FIGURE 1. ONE OF TWO IDENTICAL FLIP-FLOPS TRUTH TABLE CL* D R S Q Q 0 0 0 0 1 1 0 0 1 0 X 0 0 Q Q X X 1 0 0 1 X X 0 1 1 0 X X 1 1 1 1 Logic 0 = Low Logic 1 = High * = Level change X = Don’t care N(N) = FF1/FF2 terminal assignments 7-67 No Change CD4013BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -30 -5 -10V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 150 10V 15V 50 20 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 250 0 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 100 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 40 60 80 100 LOAD CAPACITANCE (CL) (pF) AMBIENT TEMPERATURE (TA) = +25oC 250 200 SUPPLY VOLTAGE (VDD) = 5V 150 10V 100 15V 50 0 FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (CLOCK OR SET TO Q, CLOCK OR RESET TO Q) 7-68 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (SET TO Q OR RESET TO Q) CD4013BMS Typical Performance Characteristics (Continued) DISSIPATION PER DEVICE (PD) (µW) CLOCK FREQUENCY (fCL) (MHz) 104 AMBIENT TEMPERATURE (TA) = +25oC tr, tf = 5ns CL = 50pF 30 25 20 15 10 5 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 103 8 6 4 10V 10V 2 102 8 6 4 5V CL = 50pF CL = 15pF 2 10 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC INPUT tr = tf = 20ns 2 0 5 10 15 SUPPLY VOLTAGE (VDD) (V) 1 20 102 FIGURE 8. TYPICAL MAXIMUM CLOCK FREQUENCY vs SUPPLY VOLTAGE 2 4 6 8 103 2 E FO IC FF S O E AL L CA S LO YO N CO Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, PASSIVATION: BOND PADS: AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 4 68 2 4 68 2 4 68 FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY R CT TA 2 104 105 106 INPUT FREQUENCY (ft) (HZ) Chip Dimensions and Pad Layout UR 4 68 0.0198 inches - 0.0218 inches 7-69 CD4013BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 File Number 70