CCD Delay Line Series MN3880S NTSC CCD Video Signal Delay Element Overview The MN3880S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3880S samples the input using the supplied clock signal with a frequency of 7.15909 MHz, twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Features Pin Assignment VBIASC 1 16 VINC VOC 2 15 N.C. N.C. 3 14 N.C. VDD 4 13 X1 –VBB 5 12 VSS N.C. 6 11 N.C. VOY 7 10 N.C. VBIASY 8 9 Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for chrominance signal after passing through a low pass filter Applications VINY (TOP VIEW) SOP016-P-0225 VCRs 1 MN3880S CCD Delay Line Series VBIASC VDD 1 4 12 VSS Block Diagram Bias circuit VINC 16 Charge input block øS driver CCD 454 stages ø1 driver ø2 driver Charge detection block øR driver Resampling output amplifier 2 VOC øSH driver øSH driver Timing adjustment XI 13 Waveform amplitude adjustment block Timing adjustment øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Clamp circuit –VBB 2 CCD 454 stages Charge detection block Resampling output amplifier 8 Charge input block VBIASY 9 5 VINY 7 VOY CCD Delay Line Series MN3880S Pin Descriptions Pin No. 1 Symbol VBIASC Pin Name Output gate connection (C) 2 VOC Signal output (C) 3 N.C. No connection 4 VDD Power supply 5 –VBB Substrate connection 6 N.C. No connection 7 VOY Signal output (Y) 8 VBIASY 9 VINY Remarks Negative voltage pin Output gate connection (Y) Signal output (Y) 10 N.C. No connection 11 N.C. No connection 12 VSS GND 13 XI Clock input 14 N.C. No connection 15 N.C. No connection 16 VINC Signal output (C) 3 MN3880S CCD Delay Line Series Application Circuit Example 10µF (0.01µF) 1 0.1µF VBIASC + 4 VDD 12 VSS – Bias circuit VINC 16 Charge input block CCD 454 stages Charge detection block 2 VOC Resampling output amplifier (0.01µF) øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver ø1 driver ø2 driver øR driver øSH driver øSH driver Timing adjustment XI 13 1000pF Waveform amplitude adjustment block Timing adjustment øS driver Clamp circuit CCD 454 stages Charge detection block Resampling output amplifier 7 (0.01µF) VBIASY 8 Charge input block –VBB 5 VINY 9 – + 0.47µF (0.01µF) Note: If the external capacitor attached to pin 5 is an electrolytic capacitor, attach the negative pole to pin 5. 4 VOY CCD Delay Line Series MN3880S Package Dimensions (Unit:mm) SOP016-P-0225 10.10±0.20 16 9 1.27 0.40±0.10 SEATING PLANE 1.60 -0.20 +0.10 0.15 -0.05 0 to 10° 0.40min. 0.10±0.10 (0.6) +0.50 8 1.50±0.20 1 6.50±0.20 4.30±0.20 1.10±0.20 5