AD ADP2380AREZ 20 v, 4 a synchronous step-down regulator with low-side driver Datasheet

20 V, 4 A Synchronous Step-Down
Regulator with Low-Side Driver
ADP2380
Data Sheet
FEATURES
TYPICAL APPLICATIONS CIRCUIT
VIN
1
2
CIN
3
4
5
ROSC
6
7
CSS
8
PVIN
BST
PVIN
SW
UVLO
SW
ADP2380
LD
PGOOD
RT
VREG
SYNC
PGND
EN/SS
GND
FB
COMP
16
CBST
15
L
VOUT
14
COUT
FET
13
12
CVREG
11
10
RTOP
9
RBOT
CC_EA
RC_EA
09939-001
Input voltage: 4.5 V to 20 V
Integrated 44 mΩ high-side MOSFET
0.6 V ± 1% reference voltage over temperature
Continuous output current: 4 A
Programmable switching frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
180° out-of-phase synchronization
Programmable UVLO
Power-good output
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
CCP_EA
APPLICATIONS
Figure 1.
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load application
100
95
90
EFFICIENCY (%)
85
80
75
70
65
60
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
09939-002
VOUT = 1.2V
VOUT = 3.3V
VOUT = 5V
55
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 250 kHz
GENERAL DESCRIPTION
The ADP2380 is a current mode control, synchronous, step-down,
dc-to-dc regulator. It integrates a 44 mΩ high-side power MOSFET
and a low-side driver to provide a high efficiency solution. The
ADP2380 runs from an input voltage of 4.5 V to 20 V and can
deliver 4 A of output current. The output voltage can be adjusted
to 0.6 V to 90% of the input voltage. The switching frequency of
the ADP2380 can be programmed from 250 kHz to 1.4 MHz or
fixed at 290 kHz or 540 kHz. The synchronization function allows
the switching frequency to be synchronized to an external clock
to minimize system noise.
Rev. 0
External compensation and an adjustable soft start provide
design flexibility. The power-good output provides simple and
reliable power sequencing. Additional features include
programmable undervoltage lockout (UVLO), overvoltage
protection (OVP), overcurrent protection (OCP), and thermal
shutdown (TSD).
The ADP2380 operates over the −40°C to +125°C junction
temperature range and is available in a 16-lead TSSOP_EP
package.
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ADP2380
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Applications ....................................................................................... 1
Input Capacitor Selection .......................................................... 15
Typical Applications Circuit............................................................ 1
Output Voltage Setting .............................................................. 15
General Description ......................................................................... 1
Voltage Conversion Limitations ............................................... 15
Revision History ............................................................................... 2
Inductor Selection ...................................................................... 15
Specifications..................................................................................... 3
Output Capacitor Selection....................................................... 17
Absolute Maximum Ratings ............................................................ 5
Low-Side Power Device Selection ............................................ 17
Thermal Information ................................................................... 5
Programming Input Voltage UVLO ........................................ 18
ESD Caution .................................................................................. 5
Compensation Design ............................................................... 18
Pin Configuration and Function Descriptions ............................. 6
ADIsimPower Design Tool ....................................................... 19
Typical Performance Characteristics ............................................. 7
Design Example .............................................................................. 20
Functional Block Diagram ............................................................ 12
Output Voltage Setting .............................................................. 20
Theory of Operation ...................................................................... 13
Frequency Setting ....................................................................... 20
Control Scheme .......................................................................... 13
Inductor Selection ...................................................................... 20
Internal Regulator (VREG) ....................................................... 13
Output Capacitor Selection....................................................... 20
Bootstrap Circuitry .................................................................... 13
Low-Side MOSFET Selection ................................................... 21
Low-Side Driver.......................................................................... 13
Compensation Components ..................................................... 21
Oscillator ..................................................................................... 13
Soft Start Time Program ........................................................... 21
Synchronization .......................................................................... 13
Input Capacitor Selection .......................................................... 21
Enable and Soft Start .................................................................. 13
Recommended External Components ........................................ 22
Power Good ................................................................................. 14
Circuit Board Layout Recommendations ................................... 24
Peak Current-Limit and Short-Circuit Protection................. 14
Typical Applications Circuits ........................................................ 26
Overvoltage Protection (OVP) ................................................. 14
Outline Dimensions ....................................................................... 27
Undervoltage Lockout (UVLO) ............................................... 14
Ordering Guide .......................................................................... 27
Thermal Shutdown ..................................................................... 14
REVISION HISTORY
12/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP2380
SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
FB
FB Regulation Voltage
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
High-Side On Resistance 1
High-Side Peak Current Limit
Negative Current-Limit Threshold Voltage 2
SW Minimum On Time
SW Minimum Off Time
LOW-SIDE DRIVER (LD)
Rising Time2
Falling Time2
Sourcing Resistor
Sinking Resistor
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
EN/SS
Enable Threshold
Internal Soft Start
SS Pin Pull-Up Current
Symbol
VPVIN
IQ
ISHDN
VFB
Test Conditions/Comments
No switching
EN/SS = GND
PVIN rising
PVIN falling
0°C < TJ < 85°C
−40°C < TJ < +125°C
Min
4.5
2.2
85
3.7
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
340
45
45
470
60
60
590
75
75
µS
µA
µA
7.7
8
350
100
8.4
V
mV
mA
44
7
20
120
195
70
9
155
280
20
10
4
2
6.5
4.5
ns
ns
Ω
Ω
4.7
5
5.6
V
210
410
440
250
290
540
500
350
650
560
1400
kHz
kHz
kHz
kHz
1400
kHz
ns
ns
V
V
CDL = 2.2 nF; see Figure 17
CDL = 2.2 nF; see Figure 20
fSW
130
mΩ
A
mV
ns
ns
tMIN_ON
tMIN_OFF
RT pin connected to GND
RT pin open
ROSC = 100 kΩ
V
mA
µA
V
V
V
V
µA
4.8
fSW
20
3.4
170
4.5
0.606
0.609
0.1
VBST − VSW = 5 V
VBOOT
Unit
0.6
0.6
0.01
65
tR
tF
2.8
125
4.3
3.9
Max
0.594
0.591
IFB
gm
ISOURCE
ISINK
Typ
250
100
100
1.3
0.4
0.5
ISS_UP
2.4
Rev. 0 | Page 3 of 28
1600
3.2
3.6
V
Clock cycles
µA
ADP2380
Parameter
POWER GOOD (PGOOD)
PGOOD Range
PGOOD Deglitch Time
PGOOD Leakage Current
PGOOD Output Low Voltage
UVLO
Rising Threshold
Falling Threshold
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Data Sheet
Symbol
Test Conditions/Comments
Min
FB rising threshold
FB falling threshold
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
IPGOOD = 1 mA
Typ
95
90
1024
16
0.01
125
1.06
1.2
1.1
150
25
Pin-to-pin measurement.
Guaranteed by design.
Rev. 0 | Page 4 of 28
Max
Unit
0.1
185
%
%
Clock cycles
Clock cycles
µA
mV
1.24
V
V
°C
°C
Data Sheet
ADP2380
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN, PGOOD
SW
BST
UVLO, FB, EN/SS, COMP, SYNC, RT
VREG, LD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
THERMAL INFORMATION
Table 3. Thermal Resistance
Package Type
16-lead TSSOP_EP
θJA
39.48
Unit
°C/W
θJA is specified for the worst-case conditions, that is, a device
soldered in circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
ESD CAUTION
Rev. 0 | Page 5 of 28
ADP2380
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PVIN
1
16
BST
PVIN
2
15
SW
UVLO
3
14
SW
PGOOD
4
13
LD
RT
5
12
VREG
SYNC
6
11
PGND
EN/SS
7
10
GND
COMP
8
9
TOP VIEW
(Not to Scale)
FB
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO A LARGE EXTERNAL COPPER GROUND PLANE
UNDERNEATH THE IC FOR THERMAL DISSIPATION.
09939-003
ADP2380
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
1, 2
Mnemonic
PVIN
3
4
UVLO
PGOOD
5
RT
6
SYNC
7
EN/SS
8
9
10
11
12
13
14, 15
16
17
COMP
FB
GND
PGND
VREG
LD
SW
BST
EPAD
Description
Power Input. Connect PVIN to the input power source and connect a bypass capacitor between this pin
and PGND.
Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold.
Power-Good Output (Open Drain). It is recommended that a pull-up resistor of 10 kΩ to 100 kΩ be
connected to PGOOD.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency
between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290 kHz.
If the RT pin is open, the switching frequency is set to 540 kHz.
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details).
Enable (EN). When this pin voltage falls below 0.5 V, the regulator is disabled.
Soft Start (SS). This pin can also be used to set the soft start time. Connect a capacitor from SS to GND to
program the slow soft start time. If this pin is open, the regulator is enabled and uses the internal soft start.
Error Amplifier Output. Connect an RC network from COMP to FB.
Feedback Voltage Sense Input. Connect this pin to a resistor divider from VOUT.
Analog Ground. Connect this pin to the ground plane.
Power Ground. Connect this pin to the source of the synchronous N-channel MOSFET.
Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND.
Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET.
Switch Node Output. Connect this pin to the output inductor.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST.
Exposed Pad. The exposed pad should be soldered to a large external copper ground plane underneath
the IC for thermal dissipation.
Rev. 0 | Page 6 of 28
Data Sheet
ADP2380
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
85
85
EFFICIENCY (%)
80
75
70
65
80
75
70
65
50
0
0.5
1.0
1.5
2.0
2.5
3.0
4.0
3.5
INDUCTOR: FDVE1040-6R8M
MOSFET: FDS6298
55
OUTPUT CURRENT (A)
50
0
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
1.5
2.0
2.5
3.0
80
75
70
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
75
70
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
55
60
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INDUCTOR: FDVE1040-1R5M
MOSFET: FDS6298
55
4.0
OUTPUT CURRENT (A)
50
09939-005
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS6298
4.0
80
65
60
3.5
Figure 7. Efficiency at VIN = 12 V, fSW = 250 kHz
65
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 500 kHz
Figure 8. Efficiency at VIN = 5 V, fSW = 500 kHz
160
3.2
TJ = –40°C
TJ = +25°C
TJ = +125°C
TJ = –40°C
TJ = +25°C
TJ = +125°C
3.0
QUIESCENT CURRENT (mA)
150
140
130
120
110
100
2.8
2.6
2.4
2.2
2.0
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
20
1.8
09939-009
SHUTDOWN CURRENT (μA)
1.0
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 500 kHz
90
0.5
09939-008
INDUCTOR: FDVE1040-3R3M
MOSFET: FDS6298
55
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
09939-004
60
09939-007
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. 0 | Page 7 of 28
18
20
09939-006
EFFICIENCY (%)
TA = 25oC, VIN = 12 V, VOUT = 3.3 V, L = 4.7 µH, COUT = 2 × 100 µF, fSW = 500 kHz, unless otherwise noted.
ADP2380
4.5
Data Sheet
1.30
RISING
FALLING
4.4
RISING
FALLING
UVLO PIN THRESHOLD (V)
PVIN UVLO THRESHOLD (V)
1.25
4.3
4.2
4.1
4.0
3.9
3.8
1.20
1.15
1.10
1.05
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
1.00
–40
09939-010
3.6
–40
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. PVIN UVLO Threshold vs. Temperature
Figure 13. UVLO Pin Threshold vs. Temperature
3.3
606
604
3.2
FEEDBACK VOLTAGE (mV)
SS PULL-UP CURRENT (μA)
–20
09939-011
3.7
3.1
3.0
602
600
598
2.9
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
594
–40
09939-012
2.8
–40
0
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
530
–20
09939-013
596
Figure 14. FB Voltage vs. Temperature
8.4
ROSC = 100kΩ
8.3
520
VREG VOLTAGE (V)
500
490
8.1
8.0
7.9
7.8
480
470
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
7.6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 15. VREG Voltage vs. Temperature
Figure 12. Frequency vs. Temperature
Rev. 0 | Page 8 of 28
09939-015
7.7
09939-014
FREQUENCY (kHz)
8.2
510
Data Sheet
ADP2380
8.0
PEAK CURRENT-LIMIT THRESHOLD (A)
70
50
40
20
–40
–20
0
20
40
60
80
100
7.0
6.5
6.0
5.5
5.0
–40
09939-016
30
7.5
120
TEMPERATURE (°C)
–20
0
20
40
60
80
100
09939-019
MOSFET RESISTOR (mΩ)
60
120
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
SW
SW
1
1
LD
LD
2
CH2 5.00V
M20.0ns
T 50.00%
A CH2
5.50V
CH1 5.00V
Figure 17. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
CH2 5.00V
M20.0ns
T 40.00%
A CH2
3.70V
09939-020
CH1 5.00V
09939-017
2
Figure 20. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
VOUT (AC)
EN/SS
1
3
IL
1
VOUT
SW
IOUT
4
4
2
2
B
W
M2.00µs
CH2 10V
CH4 2A Ω BW T 50.20%
A CH2
8.00V
CH1 2.00V BW CH2 5.00V
M2.00ms
CH3 5.00V BW CH4 2.00A Ω BW T 60.40%
Figure 18. Working Mode Waveform
A CH2
Figure 21. Soft Start with Full Load
Rev. 0 | Page 9 of 28
4.40V
09939-021
CH1 10mV
09939-018
PGOOD
ADP2380
Data Sheet
SYNC
EN/SS
3
3
VOUT
1
2
SW
PGOOD
2
IL
4.40V
CH3 5.00V BW
Figure 22. Precharged Output
CH2 10.0V
M1.00µs
T 50.40%
A CH2
7.40V
09939-025
A CH2
13.8V
09939-026
CH1 2.00V BW CH2 5.00V
M2.00ms
CH3 5.00V BW CH4 2.00A Ω BW T 60.40%
09939-022
4
Figure 25. External Synchronization
VOUT (AC)
VOUT (AC)
1
1
VIN
SW
IOUT
3
2
CH1 100mV
B
M200µs
W
CH4 2.00A Ω BW T 70.40%
A CH4
2.96A
09939-023
4
Figure 23. Load Transient Response, 1 A to 4 A
B
CH1 20mV
W
CH3 5V Ω BW
CH2 10V BW
M1ms A CH3
T 30%
Figure 26. Line Transient Response, VIN from 10 V to 16 V, IOUT = 4 A
VOUT
VOUT
1
1
SW
SW
2
2
IL
IL
4
A CH1
1.32V
CH1 2.00V BW CH2 10.0V
CH4 5.00A Ω BW
Figure 24. Output Short Entry
M4.00ms A CH1
T 70.20%
Figure 27. Output Short Recovery
Rev. 0 | Page 10 of 28
1.96V
09939-027
CH1 2.00V BW CH2 10.0V
M4.00ms
CH4 5.00A Ω BW T 20.40%
09939-024
4
ADP2380
5
4
4
3
2
1
0
45
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
55
3
2
1
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
0
45
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
Figure 28. Load Current vs. Ambient Temperature, VIN = 12 V,
fSW = 500 kHz
Figure 29. Load Current vs. Ambient Temperature, VIN = 12 V,
fSW = 250 kHz
Rev. 0 | Page 11 of 28
09939-029
LOAD CURRENT (A)
5
09939-028
LOAD CURRENT (A)
Data Sheet
ADP2380
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
VREG
ADP2380
CLK
RT
BIAS AND DRIVER
REGULATOR
OSCILLATOR
SYNC
PVIN
SLOPE RAMP
UVLO
PVIN
320kΩ
UVLO
BOOST
REGULATOR
+
125kΩ
1.2V
+
ACS
–
–
SLOPE RAMP
Σ
IMAX
+
OCP
–
HICCUP
MODE
COMP
BST
ISS
0.6V
+
EN/SS
+
FB
–
0.7V
+
CMP
–
AMP
–
NFET
DRIVER
SW
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
OVP
+
VREG
CLK
0.54V
LD
DRIVER
–
PGND
+
PGOOD
GND
+
Figure 30. Functional Block Diagram
Rev. 0 | Page 12 of 28
09939-030
NEGATIVE
CURRENT-LIMIT
CMP
–
DEGLITCH
Data Sheet
ADP2380
THEORY OF OPERATION
CONTROL SCHEME
The ADP2380 uses fixed frequency, peak current mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. Current in the inductor increases until
the current sense signal crosses the peak inductor current threshold that turns off the high-side N-MOSFET and turns on the
low-side N-MOSFET. This puts a negative voltage across the
inductor, causing the inductor current to decrease. The lowside N-MOSFET stays on for the rest of the cycle.
INTERNAL REGULATOR (VREG)
The internal regulator provides a stable supply for the internal
circuits and provides bias voltage for the low-side gate driver.
Placing a 1 µF ceramic capacitor between VREG and GND is
recommended. The internal regulator also includes a currentlimit circuit to protect the circuit if the maximum external
load is added.
BOOTSTRAP CIRCUITRY
1400
1200
1000
800
600
400
200
0
20
60
100
140
180
220
ROSC (kΩ)
260
300
09939-031
The ADP2380 can operate with an input voltage from 4.5 V to
20 V and regulate the output voltage down to 0.6 V. Additional
features for design flexibility include programmable switching
frequency, soft start, external compensation, and power-good pin.
A 100 kΩ resistor sets the frequency to 500 kHz, and a 215 kΩ
resistor sets the frequency to 250 kHz. Figure 31 shows the typical
relationship between fSW and ROSC.
SWITCHING FREQUENCY (kHz)
The ADP2380 is a synchronous, step-down, dc-to-dc regulator.
It uses current mode architecture with an integrated high-side
power switch and a low-side driver. It targets high performance
applications that require high efficiency and design flexibility.
Figure 31. Switching Frequency vs. ROSC
SYNCHRONIZATION
To synchronize the ADP2380, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the
range of 250 kHz to 1.4 MHz. During synchronization, the
switching rising edge runs 180° out of phase with the external
clock rising edge.
When the ADP2380 is being synchronized, connect a resistor
from the RT pin to GND to program the internal oscillator to
run at 90% to 110% of the external synchronization clock.
The ADP2380 has integrated the boot regulator to provide the
gate drive voltage for the high-side N-MOSFET. It generates a
5 V bootstrap voltage between BST and SW by differential
sensing.
ENABLE AND SOFT START
It is recommended to place a 0.1 µF, X7R or X5R ceramic
capacitor between the BST pin and the SW pin.
The ADP2380 has an internal digital soft start. The internal soft
start time can be calculated by using the following equation:
When the voltage of the EN/SS pin exceeds 0.5 V, the ADP2380
starts operation.
LOW-SIDE DRIVER
t SS _ INT =
The LD pin provides the gate driver for the low-side N-channel
MOSFET. Internal circuitry monitors the external MOSFET to
ensure break-before-make switching to prevent cross conduction.
OSCILLATOR
The ADP2380 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 290 kHz. If the RT pin is open, the switching frequency is
set to 540 kHz. A resistor connected from RT to GND can
program the switching frequency according to the following
equation:
f SW [kHz] =
57,600
ROSC [kΩ] + 15
1600
( ms)
f SW [ kHz ]
A slow soft start time can be programmed by the EN/SS pin.
Place a capacitor between the EN/SS pin and GND. An internal
current charges this capacitor to establish the soft start ramp.
The soft start time can be calculated by using the following
equation:
t SS _ EXT =
0.6 V × C SS
I SS _ UP
where:
CSS is the soft start capacitance.
ISS_UP is the soft start pull-up current (3.2 µA).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the EN/SS voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
Rev. 0 | Page 13 of 28
ADP2380
Data Sheet
If the output voltage is charged prior to turn-on, the ADP2380
prevents the low-side MOSFET from turning on, which discharges
the output voltage until the soft start voltage exceeds the voltage
on the FB pin.
When the regulator is disabled or a current fault happens, the
soft start capacitor is discharged, and the internal digital soft
start is reset to 0 V.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires a pull-up resistor. A logic high indicates
that the voltage at the FB pin (and, therefore, the output
voltage) is above 95% of the reference voltage and there is a
1024 cycle waiting period before PGOOD is pulled high. A logic
low indicates that the voltage at the FB pin is below 90% of the
reference voltage and there is a 16-cycle waiting period before
PGOOD is pulled low.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2380 has a peak current-limit protection circuit to
prevent current runaway. During soft start, the ADP2380 uses
frequency foldback to prevent output current runaway. The
switching frequency is reduced according to the voltage on the
FB pin, which allows more time for the inductor to discharge.
The correlation between the switching frequency and FB pin
voltage is shown in Table 5.
The ADP2380 also provides a sink current limit to prevent the
low-side MOSFET from sinking a large amount of current from
the load. When the voltage across the low-side MOSFET exceeds
the sink current-limit threshold, which is typically 20 mV, the
low-side MOSFET turns off immediately for the rest of this cycle.
Both high-side and low-side MOSFETs turn off until the next
clock cycle.
In some cases, the input voltage (PVIN) ramp rate is too slow or
the output capacitor is too large to support the setting regulation
voltage during the soft start, causing the regulator to enter hiccup
mode. To avoid such cases, use a resistor divider at the UVLO
pin to program the UVLO input voltage, or use a longer soft
start time.
OVERVOLTAGE PROTECTION (OVP)
The ADP2380 provides an overvoltage protection feature to
protect the system against an output that shorts to a higher
voltage supply or the occurrence of a strong load transient.
If the feedback voltage increases to 0.7 V, the internal high-side
MOSFET and low-side driver are turned off until the voltage at FB
decreases to 0.63 V. At that time, the ADP2380 resumes normal
operation.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO pin enable threshold is 1.2 V with 100 mV hysteresis.
The ADP2380 has an internal voltage divider that consists of
two resistors from PVIN to GND, with 320 kΩ for the high-side
resistor and 125 kΩ for the low-side resistor. An external resistor
divider from PVIN to GND can be used to override the internal
resistor divider.
Table 5. Switching Frequency and FB Pin Voltage
FB Pin Voltage
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
If the current-limit fault is cleared, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
Switching Frequency
fSW
fSW/2
fSW/4
For heavy load protection, the ADP2380 uses hiccup mode for
overcurrent protection. When the inductor peak current reaches
the current-limit value, the high-side MOSFET turns off and
the low-side driver turns on until the next cycle, while the
overcurrent counter increments. If the overcurrent counter
reaches 10, or the FB pin voltage falls to ≤0.4 V after the soft
start, the regulator enters hiccup mode. The high-side MOSFET
and low-side MOSFET are both turned off. The regulator remains
in this mode for 4096 clock cycles and then attempts to restart.
THERMAL SHUTDOWN
In the event that the ADP2380 junction temperatures rise above
150°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 25°C hysteresis is included so that, when thermal
shutdown occurs, the ADP2380 does not return to operation until
the on-chip temperature drops below 125°C. Upon recovery, soft
start is initiated prior to normal operation.
Rev. 0 | Page 14 of 28
Data Sheet
ADP2380
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2380 is
typically 90%.
INPUT CAPACITOR SELECTION
The input decoupling capacitor is used to attenuate high
frequency noise on the input. This capacitor should be a
ceramic capacitor in the range of 10 µF to 47 µF. Place the
capacitor close to the PVIN pin. The loop composed of this
input capacitor, high-side NFET, and low-side NFET must be
kept as small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the following equation:
OUTPUT VOLTAGE SETTING
The output voltage of ADP2380 can be set by an external
resistive divider using the following equation:
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:




VOUT_MAX = DMAX × VIN
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
As Equation 1 to Equation 3 show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
INDUCTOR SELECTION
Table 6. Resistor Divider for Different Output Voltages
RTOP, ±1% (kΩ)
10
10
15
20
47.5
10
22
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response but degrades
efficiency, due to larger inductor ripple current; whereas, using
a large inductor value leads to smaller ripple current and better
efficiency but results in a slower transient response.
RBOT, ±1% (kΩ)
15
10
10
10
15
2.21
3
As a guideline, the inductor ripple current, ΔIL, is typically set
to 1/3 of the maximum load current. The inductor can be
calculated using the following equation:
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2380 is typically 120 ns. The
minimum output voltage at a given input voltage and frequency
can be calculated using the following equation:
VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
IOUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
VOUT_MIN is the minimum output voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
(3)
where DMAX is the maximum duty.
Table 6 lists the recommended resistor divider values for
various output voltage options.
VOUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX
(2)
where:
VOUT_MAX is the maximum output voltage.
tMIN_OFF is the minimum off time.
IOUT_MAX is the maximum output current.
I C IN _ RMS = I OUT × D × (1 − D )

R
VOUT = 0.6 × 1 + TOP
RBOT

The maximum output voltage limited by the minimum off time
at a given input voltage and frequency can be calculated using
the following equation:
(1)
L=
(V
IN
− VOUT )
∆I L × f SW
×D
where:
VIN is the input voltage.
VOUT is the output voltage.
ΔIL is the inductor current ripple.
fSW is the switching frequency.
D is the duty cycle.
D=
VOUT
VIN
The ADP2380 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle
is larger than 50%. The internal slope compensation limits the
minimum inductor value.
Rev. 0 | Page 15 of 28
ADP2380
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by the following equation:
L(Minimum) =
VOUT × (1 − D )
2 × f SW
The inductor peak current is calculated using the following
equation:
The saturation current of the inductor must be larger than
the peak inductor current. For the ferrite core inductors with
a quick saturation characteristic, the saturation current rating
of the inductor must be higher than the current-limit threshold of
the switch to prevent the inductor from becoming saturated.
The rms current of the inductor can be calculated by
∆I L
IPEAK = IOUT +
2
2
I RMS = I OUT
+
∆I L2
12
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
Table 7. Recommended Inductors
Vendor
Toko
Vishay
Würth Elektronik
Part No.
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
FDVE1040-6R8M
FDVE1040-100M
IHLP4040DZ-1R0M-01
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
IHLP4040DZ-6R8M-01
IHLP4040DZ-100M-01
744 325 120
744 325 180
744 325 240
744 325 330
744 325 420
744 325 550
Value (µH)
1.5
2.2
3.3
4.7
6.8
10
1.0
1.5
2.2
3.3
4.7
6.8
10
1.2
1.8
2.4
3.3
4.2
5.5
Rev. 0 | Page 16 of 28
ISAT (A)
13.7
11.4
9.8
8.2
7.1
6.1
36
27.5
25.6
18.6
17
13.5
12
25
18
17
15
14
12
IRMS (A)
14.6
11.6
9.0
8.0
7.1
5.2
17.5
15
12
10
9.5
8.0
6.8
20
16
14
12
11
10
DCR (mΩ)
4.6
6.8
10.1
13.8
20.2
34.1
4.1
5.8
9
14.4
16.5
23.3
36.5
1.8
3.5
4.75
5.9
7.1
10.3
Data Sheet
ADP2380
OUTPUT CAPACITOR SELECTION
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
performance.
The output capacitor selection affects both the output ripple
voltage and the loop dynamics of the regulator.
During a load step transient on the output, for example, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp up the inductor
current, which causes the output to undershoot. The output
capacitance required to satisfy the voltage droop requirement
can be calculated using the following equation:
KUV × ∆I STEP × L
=
2 × (VIN − VOUT ) × ∆VOUT _ UV
2
COUT _ UV
The selected output capacitor voltage rating should be greater
than the output voltage. The rms current rating of the output
capacitor should be larger than the result of the following equation:
I COUT _ RMS =
LOW-SIDE POWER DEVICE SELECTION
The selected MOSFET must meet the following requirements:
•
Another case occurs when a load is suddenly removed from
the output. The energy stored in the inductor rushes into the
capacitor, which causes the output to overshoot. The output
capacitance required to meet the overshoot requirement can
be calculated using the following equation:
K OV × ∆I STEP × L
•
•
2
(V
OUT
+ ∆VOUT _ OV
)
2
− VOUT
•
2
where:
KOV is a factor, typically, of 2.
ΔVOUT_OV is the allowable overshoot on the output voltage.
The output ripple is determined by the ESR and the capacitance. Use the following equation to select a capacitor that can
meet the output ripple requirements:
COUT _ RIPPLE =
RESR =
8 × f SW
12
The ADP2380 has an integrated low-side MOSFET driver that
drives the low-side NFET. The selection of the low-side NFET
affects the dc-to-dc regulator performance.
where:
KUV is a factor typically of 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
C OUT _ OV =
∆I L
∆I L
× ∆VOUT _ RIPPLE
PFET_LOW = IOUT2 × RDSON × (1 – D)
•
∆VOUT _ RIPPLE
∆I L
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR is the equivalent series resistance of the output capacitor.
Drain-source voltage (VDS) must be greater than
1.2 × VIN.
Drain current (ID) must be greater than 1.2 × ILIMIT_MAX,
which is the selected maximum current-limit threshold.
The ADP2380 low-side gate drive voltage is 8 V. Ensure
that the selected MOSFET can fully turn on at 8 V. Total
gate charge (Qg at 8 V) must be less than 50 nC. Lower Qg
characteristics constitute higher efficiency.
The low-side MOSFET carries the inductor current when
the high-side MOSFET is turned off. For low duty cycle
applications, the low-side MOSFET carries the output
current during most of the period. To achieve higher
efficiency, it is important to select a low on-resistance
MOSFET. The power conduction loss of the low-side
MOSFET can be calculated by using the following
equation:
where RDSON is the on resistance of the low-side MOSFET.
Make sure that the MOSFET can handle the thermal
dissipation due to the power loss.
Some recommended MOSFETs are listed in Table 8.
Table 8. Recommended MOSFETs
Vendor
Fairchild
Fairchild
Fairchild
Vishay
AOS
AOS
Part No.
FDS6298
FDS8880
FDMS7578
SiA430DJ
AON7402
AO4884L
VDS (V)
30
30
25
20
30
40
ID (A)
13
10.7
17
10.8
39
10
Rev. 0 | Page 17 of 28
RDSON (mΩ)
12
12
8
18.5
15
16
Qg (nC)
10
12
8
5.3
7.1
13.6
ADP2380
Data Sheet
PROGRAMMING INPUT VOLTAGE UVLO
The control to output transfer function is given by
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling threshold
of PVIN and UVLO are listed in Table 9. For a more accurate,
externally adjustable UVLO, these default values can be replaced
by using an external voltage divider, as shown in Figure 32.
Lower values of the external resistors are recommended to obtain
a high accuracy UVLO threshold because the values of the internal
320 kΩ and 125 kΩ resistors may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin
PVIN
UVLO
Rising Threshold (V)
4.28
1.2
Falling Threshold (V)
3.92
1.1
ADP2380
VIN
320kΩ
UVLO
125kΩ
Figure 32. External Programmable UVLO
A 1 kΩ resistor is an appropriate choice for R2. Use the following
equation to obtain the value of R1 for a chosen input voltage
rising threshold:
(V
R1 =
IN _ RISING
fP =
1
2 × π × R ESR × C OUT
1
2 × π × ( R + R ESR ) × C OUT
where:
AVI = 8.7 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
Compensation Network Between COMP and GND
09939-032
R2
fZ =
The external voltage loop is compensated by a transconductance
amplifier with a simple external RC network placed either between
COMP and GND or between COMP and FB, as shown in
Figure 33 and Figure 34, respectively.
PVIN
R1


s
1 +

2
π
f
×
×
VOUT ( s )
Z 

GVD ( s ) =
= AVI × R ×
s
VCOMP ( s )
1+
2 ×π × f P
)
Figure 33 shows the simplified peak current mode control,
small signal circuit with a compensation network placed
between COMP and GND.
VOUT
VOUT
ADP2380
RTOP
− 1.2 V × R2
1.2 V
RBOT
where VIN_RISING is the rising threshold of VIN.
–
gm
+
+
AVI
COUT
R
RC
GND
–
CCP
RESR
CC
09939-033
The falling threshold of VIN can be determined by
V IN _ FALLING =
COMP VCOMP
FB
1.1 V × R1
+ 1.1 V
R2
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
where VIN_FALLING is the falling threshold of VIN.
The RC and CC compensation components contribute a zero,
and the optional CCP and RC contribute an optional pole.
COMPENSATION DESIGN
The ADP2380 uses a peak current mode control architecture
for excellent load and line transient response. For peak current
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
The closed-loop transfer function is as follows:
Rev. 0 | Page 18 of 28
TV ( s ) =
−gm
R BOT
×
×
R BOT + RTOP C C + C CP
1 + RC × C C × s
 R ×C ×C

s × 1 + C C CP × s 
+
C
C
C
CP


× GVD ( s )
Data Sheet
ADP2380
Use the following design guidelines to select the RC, CC, and CCP
compensation components:
•
•
Determine the cross frequency, fC. Generally, fc is between
fSW/12 and fSW/6.
RC can be calculated by
RC =
•
RC C C = RC _ EAC C _ EA −
CCP is optional, and it can be used to cancel the zero caused
by the ESR of the output capacitors.
RESR × COUT
RC
r0 (C CP + C C ) + RC C C =
r0 (C CP _ EA + C C _ EA ) + RC _ EA C C _ EA +
(C CP _ EA + C C _ EA )( RTOP // R BOT )(1 + g m × r0 )
where:
r0 is the equivalent output impedance of the transconductance
amplifier, 40 MΩ.
RTOP // RBOT =
RTOP RBOT
RTOP + RBOT
Solve the preceding equations to obtain
Compensation Network Between COMP and FB
CC _ EA = B × g m −
The compensation RC network can also be placed between
COMP and FB, as shown in Figure 34.
RC _ EA =
CCP_EA
RC_EA
CCP _ EA =
CC_EA
VOUT
VOUT
COMP
FB
RBOT
–
gm
+
+
AVI
r0 RC CC CCP
( B + RC CC )( r0 + A)
B + RC CC
CC _ EA
r0 RC CC CCP
( B + RC CC )( r0 + A)
where:
ADP2380
RTOP
gm
RC _ EAC C _ EAC CP _ EA ( RTOP // R BOT )(1 + g m × r0 )
( R + RESR ) × COUT
RC
CCP =
C CP _ EA + C C _ EA
r0 RC C C C CP = r0 RC _ EAC C _ EAC CP _ EA +
2 ×π ×VOUT × COUT × f C
VREF × g m × AVI
where:
VREF = 0.6 V.
gm = 470 µS.
Place the compensation zero at the domain pole, fP. CC can
be determined by
CC =
•
Assuming that the compensation networks of Figure 33 and
Figure 34 have the same pole and zero,
A = ( RTOP // RBOT )(1 + g m × r0 )
COUT
B=
VCOMP
R
–
RESR
ADIsimPOWER DESIGN TOOL
09939-034
GND
Figure 34. Small Signal Circuit with Compensation Network Between COMP
and FB
When connecting the compensation network as shown in
Figure 34, it requires the same pole and zero as in Figure 33
to maintain the same compensation performance.
r0 (CCP + CC )
1 + g m ( A + r0 )
The ADP2380 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about the ADIsimPower design tools, visit
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
Rev. 0 | Page 19 of 28
ADP2380
Data Sheet
DESIGN EXAMPLE
This section provides the procedures for selecting the external
components based on the example specifications listed in Table 10.
The schematic of this design example is shown in Figure 36.
Calculate the rms current flowing through the inductor using
the following equation:
I RMS = I OUT 2 +
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
Specification
VIN = 12.0 V ± 10%
VOUT = 3.3 V
IOUT = 4 A
∆VOUT_RIPPLE = 33 mV
±5%, 1 A to 4 A, 2 A/μs
fSW = 500 kHz
This results in IRMS = 4.01 A.
According to the calculated rms and peak inductor current
values, select an inductor with a minimum rms current rating of
4.01 A and a minimum saturation current rating of 4.51 A.
To protect the inductor from reaching its saturation limit, the
inductor should be rated for at least a 7 A saturation current for
reliable operation.
OUTPUT VOLTAGE SETTING
Choose a 10 kΩ resistor as the top feedback resistor (RTOP) and
calculate the bottom feedback resistor (RBOT).


0.6

RBOT = RTOP × 

−
0
.
6
V
 OUT

Based on these requirements, select a 4.7 μH inductor, such as
the FDVE1040-4R7M from Toko, which has a 13.8 mΩ DCR
and an 8.2 A saturation current.
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple requirement and the load transient response.
To set the output voltage to 3.3 V, the resistors values are
RTOP = 10 kΩ, RBOT = 2.21 kΩ.
FREQUENCY SETTING
Connect a 100 kΩ resistor from the RT pin to GND to set the
switching frequency at 500 kHz.
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance of the output
capacitor:
C OUT _ RIPPLE =
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
(V − VOUT ) × D
L = IN
∆I L × f SW
This results in COUT_RIPPLE = 7.7 μF and RESR = 32 mΩ.
K OV × ∆I STEP × L
(VOUT + ∆VOUT _ OV ) 2 − VOUT
2
K UV × ∆I STEP × L
2 × (V IN − VOUT ) × ∆VOUT _ UV
2
C OUT _ UV =
− VOUT ) × D
L × f SW
where:
KOV = KUV = 2, the coefficients for estimation purposes.
∆ISTEP = 3 A, the load transient step.
∆VOUT_OV = 5%VOUT, the overshoot voltage.
∆VOUT_UV = 5%VOUT, the undershoot voltage.
This results in COUT_OV = 76 μF and COUT_UV = 30 μF.
This results in ∆IL = 1.02 A.
Calculate the peak inductor current using the following equation:
∆I L
2
∆I L
2
Calculate the peak-to-peak inductor ripple current using the
following equation:
I PEAK = I OUT +
∆VOUT _ RIPPLE
C OUT _ OV =
This results in L = 3.987 μH. Choose the standard inductor
value of 4.7 μH.
(V IN
RESR =
∆I L
8 × f SW × ∆VOUT _ RIPPLE
To meet the ±5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
where:
VIN = 12 V.
VOUT = 3.3 V.
D = VOUT/VIN = 0.275.
∆IL = 1.2A.
fSW = 500 kHz.
∆I L =
∆I L 2
12
According to the preceding calculation, the output capacitance
must be larger than 76 μF, and the ESR of the output capacitor
must be smaller than 32 mΩ. It is recommended that two pieces
of 47 μF/X5R/6.3 V ceramic capacitors be used, such as the
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
This results in IPEAK = 4.51 A.
Rev. 0 | Page 20 of 28
Data Sheet
ADP2380
LOW-SIDE MOSFET SELECTION
This results in the following:
RC_EA = 52.3 kΩ.
CC_EA = 1055 pF.
CCP_EA = 2.45 pF.
A low RDSON N-channel MOSFET is chosen as a high efficiency
solution. The breakdown voltage of the MOSFET must be
higher than 1.2 × VIN, and the drain current must be larger than
1.2 × ILIMIT.
Choose the standard values for RC_EA = 49.9 kΩ, CC_EA = 1000 pF,
and CCP_EA = 2.2 pF.
It is recommended to use a 30 V, N-channel MOSFET, such as
the FDS6298 from Fairchild. The RDSON of the FDS6298 at a 4.5 V
driver voltage is 9.4 mΩ, and the total gate charge at 5 V is 10 nC.
60
180
For better load transient and stability performance, set the cross
frequency, fC, at fSW/10. In this case, fC = 1/500 kHz = 50 kHz.
48
144
36
108
24
72
12
36
0
0
RC _ EA
MAGNITUDE (dB)
C C _ EA
r0 RC C C C CP
= B × gm −
( B + RC C C )( r0 + A)
B + RC C C
=
C C _ EA
C CP _ EA =
r0 RC C C C CP
( B + RC C C )( r0 + A)
where:
RC =
RC
B=
–108
–48
–144
–180
10k
100k
1M
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
=
CSS =
R ESR × C OUT
0.002 Ω × 2 × 32 μF
= 4.73 pF
=
RC
27.1 kΩ
1
2
3
ROSC
100kΩ
4
5
6
7
CSS
22nF
8
BST
PVIN
SW
SW
ADP2380
LD
PGOOD
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
1000pF
4 ms × 3.2 μA
= 21.3 nF
0.6 V
A minimum 10 μF ceramic capacitor must be placed near the
PVIN pin. In this application, one 10 μF, X5R, 25 V ceramic
capacitor is recommended.
PVIN
UVLO
=
INPUT CAPACITOR SELECTION
r0 (C CP + C C )
40 MΩ × ( 4.73 pF + 1.96 nF)
=
=
1 + g m ( A + r0 ) 1 + 470 μS × (3.4 × 10 7 + 40 MΩ
2.26 × 10−6
VIN = 12V
0.6 V
Choose a standard component value, CSS = 22 nF.
RTOP R BOT
(1 + g m × r0 ) = 10 kΩ × 2.21 kΩ ×
10 kΩ + 2.21 kΩ
RTOP + R BOT
(1 + 470 µS × 40 MΩ) = 3.4 × 107
CIN
10µF
25V
t SS _ EXT × I SS _ UP
16
15
L1
4.7µH
CBST
0.1µF
14
M1
FDS6298
13
12
11
VOUT = 3.3V
COUT1
47µF
6.3V
COUT2
47µF
6.3V
CVREG
1µF
10
9
RC_EA
49.9kΩ
RTOP
10kΩ
1%
RBOT
2.21kΩ
1%
09939-036
A=
–72
–36
FREQUENCY (Hz)
(3.3 V/ 4 A + 0.002 Ω) × 2 × 32 μF
= 1.96 nF
27.1 kΩ
CCP =
–24
Figure 35. Bode Plot at 4 A
2 × π × 3.3 V × 2 × 32 μF × 50 kHz
= 27.1 kΩ
0.6 V × 470 μS × 8.7 A/V
CC =
–36
–60
1k
2 × π × VOUT × COUT × f C
=
V REF × g m × AVI
(R + RESR ) × COUT
–12
09939-035
COMPENSATION COMPONENTS
PHASE (dB)
Figure 35 shows the Bode plot at 4 A. The cross frequency is
43 kHz, and the phase margin is 59°.
CCP_EA
2.2pF
Figure 36. Design Example Schematic
Rev. 0 | Page 21 of 28
ADP2380
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS
Table 11. Recommended External Components for Typical Applications with Compensation Network Between COMP and GND Pins,
4 A Output Current
fSW (kHz)
250
500
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
3.3
3.3
4.7
4.7
6.8
6.8
10
3.3
3.3
3.3
3.3
4.7
3.3
2.2
2.2
2.2
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1.5
1.5
2.2
2.2
1
1
1
1
1
1
COUT (µF) 1
680 + 2 × 100
680
680
470
3 × 100
2 × 100
100 + 47
680 + 2 × 100
680
470
3 × 100
2 × 100
2 × 100
470
3 × 100
2 × 100
2 × 100
2 × 100
100
470
3 × 100
3 × 100
2 × 100
2 × 47
100 + 47
2 × 100
100
100
100
3 × 100
2 × 100
100 + 47
2 × 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
20
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
15
2.21
3
15
10
10
10
15
2.21
RC (kΩ)
47
47
60.4
51
28
24
29.4
47
47
39
20
18.2
24
68
33
26.7
37.4
47
37.4
56
26.7
33
26.7
21
37.4
51
37.4
47
69
43.2
33
33
30
37.4
47
CC (pF)
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
CCP (pF)
150
100
100
100
10
10
6.8
150
100
100
15
10
10
68
10
10
6.8
4.7
3.3
68
10
10
10
6.8
4.7
4.7
3.3
2.2
1
8.2
6.8
4.7
4.7
3.3
2.2
680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 22 of 28
Data Sheet
ADP2380
Table 12. Recommended External Components for Typical Applications with Compensation Network Between COMP and FB Pins,
4 A Output Current
fSW (kHz)
250
500
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
3.3
3.3
4.7
4.7
6.8
6.8
10
3.3
3.3
3.3
3.3
4.7
3.3
2.2
2.2
2.2
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1.5
1.5
2.2
2.2
1
1
1
1
1
1
COUT (µF) 1
680 + 2 × 100
680
680
470
3 × 100
2 × 100
100 + 47
680 + 2 × 100
680
470
3 × 100
2 × 100
2 × 100
470
3 × 100
2 × 100
2 × 100
2 × 100
100
470
3 × 100
3 × 100
2 × 100
2 × 47
100 + 47
2 × 100
100
100
100
3 × 100
2 × 100
100 + 47
2 × 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
20
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
15
2.21
3
15
10
10
10
15
2.21
RC_EA (kΩ)
191
169
237
220
187
47
69.8
191
169
169
88.7
124
47
237
130
110
249
95.3
86.6
220
95.3
130
110
147
75
232
232
95.3
169
180
127
140
137
249
93.1
CC_EA (pF)
1000
1200
1000
1000
680
2200
1800
1000
1200
1000
1000
680
2200
680
470
470
330
1000
820
470
680
470
470
330
1000
220
150
470
470
270
330
270
270
150
470
CCP_EA (pF)
47
33
22
22
1
4.7
2.2
39
39
22
3.9
2.2
15
22
2.2
2.2
1
2.2
1
22
3.3
2.2
2.2
1
1
1
1
1
1
2.2
2.2
1
1
1
1
680 μF: 4V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 23 of 28
ADP2380
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best
performance from the ADP2380. Poor printed circuit board
(PCB) layout degrades the output regulation as well as the
electromagnetic interface (EMI) and electromagnetic
compatibility (EMC) performance. Figure 38 shows a PCB
layout example. For optimum layout, use the following guidelines:
•
•
•
Use separate analog ground and power ground planes.
Connect the ground reference of sensitive analog circuitry,
such as output voltage divider components, to analog
ground. In addition, connect the ground reference of
power components, such as input and output capacitors
and a low-side MOSFET, to power ground. Connect both
ground planes to the exposed pad of the ADP2380.
Place the input capacitor, inductor, low-side MOSFET, and
output capacitor as close to the IC as possible, and use
short traces.
Ensure that the high current loop traces are as short and
as wide as possible. Make the high current path from the
input capacitor through the inductor, the output capacitor,
and the power ground plane back to the input capacitor as
short as possible. To accomplish this, ensure that the input
and output capacitors share a common power ground plane.
VIN
1
2
CIN
3
4
5
ROSC
6
7
CSS
8
•
•
PVIN
BST
PVIN
SW
UVLO
SW
ADP2380
LD
PGOOD
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
16
15
CBST
L
14
COUT
FET
13
12
VOUT
CVREG
11
10
RTOP
9
RBOT
CC_EA
RC_EA
CCP_EA
Figure 37. High Current Path in the PCB Circuit
Rev. 0 | Page 24 of 28
09939-037
•
In addition, ensure that the high current path from the
power ground plane through the external MOSFET,
inductor, and output capacitor back to the power ground
plane is as short as possible by tying the MOSFET source
node to the PGND plane as close as possible to the input
and output capacitors.
Make the low-side driver path from the LD pin of the
ADP2380 to the external MOSFET gate node and back to
the PGND pin of the ADP2380 as short as possible, and
use a wide trace for better noise immunity.
Connect the exposed pad of the ADP2380 to a large copper
plane to maximize its power dissipation capability for
better thermal dissipation.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the
switching node to avoid noise pickup. To further reduce
noise pickup, place an analog ground plane on either side
of the FB trace and ensure that the trace is as short as
possible to reduce parasitic capacitance pickup.
Data Sheet
ADP2380
POWER GROUND PLANE
VIN
+
INPUT
BULK CAP
OUTPUT
CAPACITOR
INPUT
BYPASS
CAP
PULL UP
LOW-SIDE
MOSFET
PVIN
BST
PVIN
SW
UVLO
SW
PGOOD
INDUCTOR
SW
VOUT
LD
RT
VREG
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
CBST
CVREG
RC_EA
RTOP
CSS
ROSC
RBOT
CCP_EA
ANALOG GROUND PLANE
09939-038
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 38. Recommended PCB Layout
Rev. 0 | Page 25 of 28
ADP2380
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
VIN = 12V
1
CIN
10µF
25V
2
3
4
ROSC
100kΩ
5
6
7
CSS
22nF
8
PVIN
BST
PVIN
SW
UVLO
SW
ADP2380
LD
PGOOD
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
16
L1
2.2µH
CBST
0.1µF
15
VOUT = 1.2V
COUT
470µF
6.3V
14
M1
FDS6298
13
12
11
CVREG
1µF
RTOP
10kΩ
1%
10
9
RBOT
10kΩ
1%
RC
68kΩ
CCP
68pF
09939-039
CC
2.2nF
Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz
CIN
10µF
25V
1
R1
7.32kΩ
1%
2
3
R2
1kΩ R
OSC
1% 100kΩ
4
5
6
7
CSS
22nF
8
15
SW
PVIN
UVLO
16
BST
PVIN
12
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
470pF
M1
FDS6298
13
LD
PGOOD
VOUT = 1.8V
COUT1
100µF
6.3V
14
SW
ADP2380
L1
2.2µH
CBST
0.1µF
11
COUT2
100µF
6.3V
CVREG
1µF
RTOP
20kΩ
1%
10
9
RBOT
10kΩ
1%
RC_EA
110kΩ
09939-040
VIN = 12V
CCP_EA
2.2pF
Figure 40. Programming Input Voltage UVLO Rising Threshold at 10 V, VIN = 12 V, VOUT = 1.8 V, IOUT = 4 A, fSW = 500 kHz
CIN
10µF
25V
1
2
3
ROSC
82kΩ
4
5
6
7
8
BST
PVIN
SW
PVIN
UVLO
SW
ADP2380
LD
PGOOD
RT
VREG
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
820pF
16
15
CBST
0.1µF
L1
4.7µH
14
M1
FDS6298
13
12
11
VOUT = 5V
COUT
100µF
6.3V
CVREG
1µF
10
9
RC_EA
100kΩ
CCP_EA
1pF
RTOP
22kΩ
1%
RSOT
3kΩ
1%
09939-041
VIN = 12V
Figure 41. Using Internal Soft Start, Programming Switching Frequency at 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 4 A, fSW = 600 kHz
Rev. 0 | Page 26 of 28
Data Sheet
ADP2380
OUTLINE DIMENSIONS
5.10
5.00
4.90
2.31
1.75
9
16
16
9
4.50
4.40
4.30
1
2.46
1.75
EXPOSED
PAD
6.40 BSC
8
8
1
PIN 1
INDICATOR
BOTTOM VIEW
TOP VIEW
0.95
0.90
0.85
SEATING
PLANE
0.30
0.19
0.65 BSC
0.20
0.09
0.25
8°
0.15 MAX
0°
0.05 MIN
COPLANARITY
0.076
0.70
0.60
0.50
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
08-03-2010-A
1.10 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 42. 16-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP_EP]
(RE-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2380AREZ-R7
ADP2380AREZ
ADP2380-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP_EP, 7” Tape and Reel
16-Lead TSSOP_EP, Tube
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
Package Option
RE-16-3
RE-16-3
ADP2380
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09939-0-12/12(0)
Rev. 0 | Page 28 of 28