TI ADS1248IPW 24-bit analog-to-digital converters for temperature sensor Datasheet

ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
24-Bit Analog-to-Digital Converters for Temperature Sensors
Check for Samples: ADS1246, ADS1247, ADS1248
FEATURES
DESCRIPTION
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The ADS1246, ADS1247, and ADS1248 are
highly-integrated, precision, 24-bit analog-to-digital
converters (ADCs). The ADS1246/7/8 feature an
onboard, low-noise, programmable gain amplifier
(PGA), a precision delta-sigma (ΔΣ) ADC with a
single-cycle settling digital filter, and an internal
oscillator. The ADS1247 and ADS1248 also provide a
built-in, very low drift voltage reference with 10mA
output capacity, and two matched programmable
current digital-to-analog converters (DACs). The
ADS1246/7/8 provide a complete front-end solution
for temperature sensor applications including thermal
couples, thermistors, and RTDs.
1
23
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24 Bits, No Missing Codes
Data Output Rates Up to 2kSPS
Single-Cycle Settling for All Data Rates
Simultaneous 50/60Hz Rejection at 20SPS
4 Differential/7 Single-Ended Inputs (ADS1248)
2 Differential/3 Single-Ended Inputs (ADS1247)
Low-Noise PGA: 48nV at PGA = 128
Matched Current Source DACs
Very Low Drift Internal Voltage Reference:
10ppm/°C (max)
Sensor Burnout Detection
4/8 General-Purpose I/Os (ADS1247/8)
Internal Temperature Sensor
Power Supply and VREF Monitoring
(ADS1247/8)
Self and System Calibration
SPI™-Compatible Serial Interface
Analog Supply Unipolar (+2.7V to
+5.25V)/Bipolar (±2.5V) Operation
Digital Supply: +2.7V to +5.25V
Operating Temperature –40°C to +125°C
APPLICATIONS
•
•
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Temperature Measurement
– RTDs, Thermocouples, and Thermistors
Pressure Measurement
Industrial Process Control
REFP
AVDD
REFN
An input multiplexer supports four differential inputs
for the ADS1248, two for the ADS1247, and one for
the ADS1246. In addition, the multiplexer has a
sensor
burnout
detect,
voltage
bias
for
thermocouples,
system
monitoring,
and
general-purpose digital I/Os (ADS1247 and
ADS1248). The onboard, low-noise PGA provides
selectable gains of 1 to 128. The ΔΣ modulator and
adjustable digital filter settle in only one cycle, for fast
channel cycling when using the input multiplexer, and
support data rates up to 2kSPS. For data rates of
20SPS or less, both 50Hz and 60Hz interference are
rejected by the filter.
The ADS1246 is offered in a small TSSOP-16
package, the ADS1247 is available in a TSSOP-20
package, and the ADS1248 in a TSSOP-28 package.
All three devices are rated over the extended
specified temperature range of –40°C to +105°C.
DVDD
Burnout
Detect
AVDD
REFP0/ REFN0/ ADS1248 Only
GPIO0 GPIO1 REFP1 REFN1 VREFOUT VREFCOM
Burnout
Detect
ADS1246
VBIAS
Voltage
Reference
VREF Mux
VBIAS
DVDD
ADS1247
ADS1248
GPIO
SCLK
DIN
AIN0
AIN1
Input
Mux
PGA
3rd Order
DS
Modulator
Adjustable
Digital
Filter
Serial
Interface
and
Control
DRDY
DOUT/DRDY
CS
START
RESET
Internal Oscillator
AIN0/IEXC
AIN1/IEXC
SCLK
System
Monitor
AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3
Input
Mux
AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5
PGA
DIN
3rd Order
DS
Modulator
Dual
Current
DACs
AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7
ADS1248 Only
Adjustable
Digital
Filter
Serial
Interface
and
Control
DRDY
DOUT/DRDY
CS
START
RESET
Internal Oscillator
Burnout
Detect
Burnout
Detect
AVSS
CLK
DGND
AVSS
IEXC1 IEXC2
ADS1248 Only
CLK
DGND
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
NUMBER OF INPUTS
VOLTAGE REFERENCE
DUAL SENSOR
EXCITATION CURRENT
SOURCES
ADS1246
1 Differential
or
1 Single-Ended
External
NO
TSSOP-16
ADS1247
2 Differential
or
3 Single-Ended
Internal or External
YES
TSSOP-20
ADS1248
4 Differential
or
7 Single-Ended
Internal or External
YES
TSSOP-28
PACKAGELEAD
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
ADS1246, ADS1247, ADS1248
PARAMETER
MIN
MAX
UNIT
AVDD to AVSS
–0.3
+5.5
V
AVSS to DGND
–2.8
+0.3
V
DVDD to DGND
–0.3
+5.5
V
Input current
100, momentary
mA
10, continuous
mA
Analog input voltage to AVSS
AVSS – 0.3
AVDD + 0.3
Digital input voltage to DGND
–0.3
DVDD + 0.3
V
+150
°C
Maximum junction temperature
V
Operating temperature range
–40
+125
°C
Storage temperature range
–60
+150
°C
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
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Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
THERMAL INFORMATION
ADS1246,
ADS1247,
ADS1248
THERMAL METRIC (1)
UNITS
TSSOP (IPW)
28
qJA
Junction-to-ambient thermal resistance (2)
qJC(top)
Junction-to-case(top) thermal resistance
54.6
(3)
11.3
(4)
qJB
Junction-to-board thermal resistance
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
qJC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
13.0
(5)
Junction-to-case(bottom) thermal resistance
0.5
(6)
(7)
°C/W
12.7
n/a
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
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ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at
AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
ADS1246, ADS1247, ADS1248
PARAMETER
CONDITIONS
MIN
TYP
MAX
±VREF/PGA
2.7/PGA
UNIT
ANALOG INPUTS
Full-scale input voltage
(VIN = ADCINP – ADCINN)
(VIN)(Gain)
AVSS + 0.1V +
Common-mode input range
2
Differential input current
AVDD - 0.1V -
(VIN)(Gain)
2
100
Absolute input current
V
V
pA
See Table 11
PGA gain settings
1, 2, 4, 8, 16, 32, 64, 128
Burnout current source
Bias voltage
0.5, 2, or 10
mA
(AVDD + AVSS)/2
V
400
Ω
Bias voltage output impedance
SYSTEM PERFORMANCE
Resolution
No missing codes
Data rate
Integral nonlinearity (INL)
Differential input, end point fit, PGA = 1
Offset error
After calibration (1)
Offset drift
Gain error
24
Bits
5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000
6
SPS
15
–15
15
See Figure 11 to Figure 14
T = +25°C, all PGAs,
data rate = 40, 80, or 160SPS
Gain drift
–0.02
±0.005
mV
nV/°C
0.02
See Figure 19 to Figure 22
ADC conversion time
ppm
%
ppm/°C
Single-cycle settling
Noise
See Table 5 to Table 8
Normal-mode rejection
Common-mode rejection
Power-supply rejection
See Table 13
At dc, PGA = 1
80
90
dB
At dc, PGA = 32
90
125
dB
100
135
dB
AVDD/DVDD at dc, PGA = 32,
data rate = 80SPS
VOLTAGE REFERENCE INPUT
Voltage reference input
(VREF = VREFP – VREFN)
0.5
(AVDD – AVSS) – 1
V
V
Negative reference input (REFN)
AVSS – 0.1
REFP – 0.5
Positive reference input (REFP)
REFN + 0.5
AVDD + 0.1
Reference input current
30
V
nA
ON-CHIP VOLTAGE REFERENCE
Output voltage
2.038
2.048
Output current (2)
Load regulation
TA = –40°C to +105°C
Startup time
(1)
(2)
(3)
4
V
±10
mA
2
10
ppm/°C
6
15
ppm/°C
50
TA = +25°C to +105°C
Drift (3)
2.058
See Table 14
mV/mA
ms
Offset calibration on the order of noise.
Do not exceed this loading on the internal voltage reference.
Specified by the combination of design and final production test.
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Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at
AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
ADS1246, ADS1247, ADS1248
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SOURCES (IDACS)
Output current
50, 100, 250, 500, 750, 1000, 1500
Voltage compliance
All currents
Initial error
All currents, each IDAC
Initial mismatch
All currents, between IDACs
Temperature drift
Each IDAC
Temperature drift matching
Between IDACs
mA
AVDD – 0.7
–6
±1.0
V
6
% of FS
±0.15
% of FS
100
ppm/°C
10
ppm/°C
SYSTEM MONITORS
Temperature
sensor reading
Voltage
TA = +25°C
Drift
118
mV
405
mV/°C
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Logic levels
VIH
0.7AVDD
AVDD
V
VIL
AVSS
0.3AVDD
V
VOH
IOH = 1mA
VOL
IOL = 1mA
0.8AVDD
V
0.2 AVDD
V
DIGITAL INPUT/OUTPUT (other than GPIO)
Logic levels
VIH
0.7DVDD
DVDD
V
VIL
DGND
0.3DVDD
V
VOH
IOH = 1mA
0.8DVDD
VOL
IOL = 1mA
DGND
Input leakage
Clock input
(CLK)
V
DGND < VIN < DVDD
0.2 DVDD
V
±10
mA
MHz
Frequency
1
4.5
Duty cycle
25
75
%
4.3
MHz
Internal oscillator frequency
3.89
4.096
POWER SUPPLY
DVDD
2.7
5.25
V
AVSS
–2.5
0
V
AVDD
AVSS + 2.7
AVSS + 5.25
V
DVDD current
AVDD current
Power dissipation
Normal mode, DVDD = 5V,
data rate = 20SPS, internal oscillator
230
mA
Normal mode, DVDD = 3.3V,
data rate = 20SPS, internal oscillator
210
mA
Sleep mode
0.2
µA
Converting, AVDD = 5V,
data rate = 20SPS, external reference
225
µA
Converting, AVDD = 3.3V,
data rate = 20SPS, external reference
200
µA
Sleep mode
0.1
µA
Additional current with internal reference
enabled
180
mA
AVDD = DVDD = 5V,
data rate = 20SPS, internal oscillator,
external reference
2.3
mW
AVDD = DVDD = 3.3V,
data rate = 20SPS, internal oscillator,
external reference
1.4
mW
TEMPERATURE RANGE
Specified
–40
+105
°C
Operating
–40
+125
°C
Storage
–60
+150
°C
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
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ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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PIN CONFIGURATIONS
PW PACKAGE
TSSOP-28
(TOP VIEW)
6
DVDD
1
28
SCLK
DGND
2
27
DIN
CLK
3
26
DOUT/DRDY
RESET
4
25
DRDY
REFP0/GPIO0
5
24
CS
REFN0/GPIO1
6
23
START
REFP1
7
22
AVDD
REFN1
8
21
AVSS
VREFOUT
9
20
IEXC1
VREFCOM
10
19
IEXC2
AIN0/IEXC
11
18
AIN3/IEXC/GPIO3
AIN1/IEXC
12
17
AIN2/IEXC/GPIO2
AIN4/IEXC/GPIO4
13
16
AIN7/IEXC/GPIO7
AIN5/IEXC/GPIO5
14
15
AIN6/IEXC/GPIO6
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ADS1248
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
ADS1248 (TSSOP-28) PIN DESCRIPTIONS
NAME
PIN NO.
FUNCTION
DVDD
1
Digital
Digital power supply
DESCRIPTION
DGND
2
Digital
Digital ground
CLK
3
Digital input
External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET
4
Digital input
Chip reset (active low). Returns all register values to reset values.
REFP0/GPIO0
5
Analog input
Digital in/out
Positive external reference input 0, or general-purpose digital input/output pin 0
REFN0/GPIO1
6
Analog input
Digital in/out
Negative external reference 0 input, or general-purpose digital input/output pin 1
REFP1
7
Analog input
Positive external reference 1 input
REFN1
8
Analog input
Negative external reference 1 input
VREFOUT
9
Analog output
Positive internal reference voltage output
VREFCOM
10
Analog output
Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.
AIN0/IEXC
11
Analog input
Analog input 0, optional excitation current output
AIN1/IEXC
12
Analog input
Analog input 1, optional excitation current output
AIN4/IEXC/GPIO4
13
Analog input
Digital in/out
Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4
AIN5/IEXC/GPIO5
14
Analog input
Digital in/out
Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5
AIN6/IEXC/GPIO6
15
Analog input
Digital in/out
Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6
AIN7/IEXC/GPIO7
16
Analog input
Digital in/out
Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7
AIN2/IEXC/GPIO2
17
Analog input
Digital in/out
Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2
AIN3/IEXC/GPIO3
18
Analog input
Digital in/out
Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3
IOUT2
19
Analog output
Excitation current output 2
IOUT1
20
Analog output
Excitation current output 1
AVSS
21
Analog
Negative analog power supply
AVDD
22
Analog
Positive analog power supply
START
23
Digital input
Conversion start. See text for complete description.
CS
24
Digital input
Chip select (active low)
DRDY
25
Digital output
Data ready (active low)
DOUT/DRDY
26
Digital output
Serial Data Out Output, or
Data Out combined with Data Ready (active low when DRDY function enabled)
DIN
27
Digital input
Serial data input
SCLK
28
Digital input
Serial clock input
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ADS1247
ADS1248
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PW PACKAGE
TSSOP-20
(TOP VIEW)
DVDD
1
20
SCLK
DGND
2
19
DIN
CLK
3
18
DOUT/DRDY
RESET
4
17
DRDY
REFP0/GPIO0
5
16
CS
REFN0/GPIO1
6
15
START
VREFOUT
7
14
AVDD
VREFCOM
8
13
AVSS
AIN0/IEXC
9
12
AIN3/IEXC/GPIO3
AIN1/IEXC
10
11
AIN2/IEXC/GPIO2
ADS1247
ADS1247 (TSSOP-20) PIN DESCRIPTIONS
NAME
PIN NO.
FUNCTION
DVDD
1
Digital
Digital power supply
DGND
2
Digital
Digital ground
CLK
3
Digital input
External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET
4
Digital input
Chip reset (active low). Returns all register values to reset values.
REFP0/GPIO0
5
Analog input
Digital in/out
Positive external reference input, or general-purpose digital input/output pin 0
REFN0/GPIO1
6
Analog input
Digital in/out
Negative external reference input, or general-purpose digital input/output pin 1
VREFOUT
7
Analog output
Positive internal reference voltage output
VREFCOM
8
Analog output
Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
supply, or to the midvoltage of the power supply when using a bipolar supply.
AIN0/IEXC
9
Analog input
Analog input 0, optional excitation current output
AIN1/IEXC
10
Analog input
Analog input 1, optional excitation current output
AIN2/IEXC/GPIO2
11
Analog input
Digital in/out
Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2
AIN3/IEXC/GPIO3
12
Analog input
Digital in/out
Analog input 3, with or without excitation current output, or general-purpose digital input/output
pin 3
AVSS
13
Analog
Negative analog power supply
AVDD
14
Analog
Positive analog power supply
START
15
Digital input
Conversion start. See text for description of use.
CS
16
Digital input
Chip select (active low)
DRDY
17
Digital output
Data ready (active low)
DOUT/DRDY
18
Digital output
Serial data out output, or
Data out combined with Data Ready (active low when DRDY function enabled)
DIN
19
Digital input
Serial data input
SCLK
20
Digital input
Serial clock input
8
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DESCRIPTION
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
PW PACKAGE
TSSOP-16
(TOP VIEW)
DVDD
1
16
SCLK
DGND
2
15
DIN
CLK
3
14
DOUT/DRDY
RESET
4
13
DRDY
REFP
5
12
CS
REFN
6
11
START
AINP
7
10
AVDD
AINN
8
9
AVSS
ADS1246
ADS1246 (TSSOP-16) PIN DESCRIPTIONS
NAME
PIN NO.
FUNCTION
DVDD
1
Digital
Digital power supply
DESCRIPTION
DGND
2
Digital
Digital ground
CLK
3
Digital input
External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET
4
Digital input
Chip reset (active low). Returns all register values to reset values.
REFP
5
Analog input
Positive external reference input
REFN
6
Analog input
Negative external reference input
AINP
7
Analog input
Positive analog input
AINN
8
Analog input
Negative analog input
AVSS
9
Analog
Negative analog power supply
AVDD
10
Analog
Positive analog power supply
START
11
Digital input
Conversion start. See text for description of use.
CS
12
Digital input
Chip select (active low)
DRDY
13
Digital output
Data ready (active low)
DOUT/DRDY
14
Digital output
Serial data out output, or
Data out combined with Data Ready (active low when DRDY function enabled)
DIN
15
Digital input
Serial data input
SCLK
16
Digital input
Serial clock input
Copyright © 2008–2010, Texas Instruments Incorporated
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ADS1247
ADS1248
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TIMING DIAGRAMS
CS
tCSSC
tSPWH
tSCLK
tSCCS
SCLK
DIN
DIN[0]
tSPWL
tDIHD
tDIST
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[1]
tDOPD
DOUT/DRDY
(1)
DOUT[7]
DOUT[6]
DIN[0]
tDOHD
DOUT[5]
DOUT[4]
DOUT[1]
DOUT[0]
tCSDO
Figure 1. Serial Interface Timing
Table 1. Timing Characteristics for Figure 1
SYMBOL
(1)
DESCRIPTION
tCSSC
CS low to first SCLK high (set up time)
tSCCS
MIN
MAX
UNIT
10
ns
SCLK low to CS high (hold time)
7
tOSC
tDIST
DIN set up time
5
ns
tDIHD
DIN hold time
5
ns
tDOPD
SCLK rising edge to new data valid
tDOHD
DOUT hold time
30
0
(2)
ns
ns
500
ns
tSCLK
SCLK period
tSPWH
SCLK pulse width high
0.25
0.75
tSCLK
tSPWL
SCLK pulse width low
0.25
0.75
tSCLK
tCSDO
CS high to DOUT high impedance
(1)
(2)
64
10
Conversions
ns
DRDY MODE bit = 0.
tOSC = 1/fCLK. The default clock frequency fCLK = 4.096MHz.
tDTS
tPWH
DRDY
1
2
3
4
5
6
7
8
tSTD
SCLK(3)
Figure 2. SPI Interface Timing to Allow Conversion Result Loading (3)
(4)
Table 2. Timing Characteristics for Figure 2
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
tPWH
DRDY pulse width high
3
tOSC
tSTD
SCLK low prior to DRDY low
5
tOSC
tDTS
DRDY falling edge to SCLK rising edge
30
ns
(3)
(4)
10
This timing diagram is applicable only when the CS pin is low. SCLK need not be low during tSTD when CS is high.
SCLK should only be sent in multiples of eight during partial retrieval of output data.
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
tSTART
START
Figure 3. Minimum START Pulse Width
Table 3. Timing Characteristics for Figure 3
SYMBOL
tSTART
DESCRIPTION
MIN
START pulse width high
MAX
3
UNIT
tOSC
tRESET
RESET
CS
SCLK
tRHSC
Figure 4. Reset Pulse Width and SPI Communication After Reset
Table 4. Timing Characteristics for Figure 4
SYMBOL
DESCRIPTION
MIN
t RESET
RESET pulse width low
4
tOSC
tRHSC
RESET high to SPI communication start
0.6 (1)
ms
(1)
MAX
UNIT
Applicable only when fOSC = 4.096MHz and scales proportionately with fOSC frequency.
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ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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NOISE PERFORMANCE
The ADS1246/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the
averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value
reduces the input-referred noise, particularly useful when measuring low-level signals. Table 5 to Table 10
summarize noise performance of the ADS1246/7/8. The data are representative of typical noise performance at
T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured
with the inputs shorted together. A minimum of 128 consecutive readings were used to calculate the RMS and
peak-to-peak noise for each reading.
Table 5, Table 7, and Table 9 list the input-referred noise in units of mVRMS and mVPP for the conditions shown.
Table 6, Table 8, and Table 10 list the corresponding data in units of ENOB (effective number of bits) where:
ENOB = ln(Full-Scale Range/Noise)/ln(2)
(1)
Table 7 to Table 10 use the internal reference available on the ADS1247 and ADS1248. The data though are
also representative of the ADS1246 noise performance when using a low-noise external reference such as the
REF5020.
12
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
Table 5. Noise in mVRMS and (mVPP)
at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
1.10 (4.99)
0.68 (3.80)
0.37 (1.90)
0.19 (0.98)
0.10 (0.44)
0.07 (0.31)
0.05 (0.27)
0.05 (0.21)
10
1.53 (8.82)
0.82 (3.71)
0.50 (2.69)
0.27 (1.33)
0.15 (0.67)
0.08 (0.50)
0.06 (0.36)
0.07 (0.34)
20
2.32 (13.37)
1.23 (6.69)
0.71 (3.83)
0.34 (1.90)
0.18 (1.01)
0.12 (0.71)
0.10 (0.51)
0.09 (0.54)
40
2.72 (17.35)
1.33 (7.65)
0.68 (3.83)
0.38 (2.21)
0.22 (1.13)
0.14 (0.77)
0.15 (0.78)
0.14 (0.76)
80
3.56 (22.67)
1.87 (12.30)
0.81 (5.27)
0.50 (3.49)
0.30 (1.99)
0.19 (1.24)
0.19 (1.16)
0.18 (1.04)
160
5.26 (42.03)
2.52 (17.57)
1.32 (9.22)
0.67 (5.25)
0.41 (2.89)
0.26 (1.91)
0.27 (1.74)
0.26 (1.74)
320
9.39 (74.91)
4.68 (39.48)
2.69 (18.95)
1.24 (9.94)
0.68 (5.25)
0.45 (3.08)
0.38 (2.71)
0.36 (2.46)
640
13.21 (119.66)
6.93 (59.31)
3.59 (28.55)
1.53 (10.68)
0.95 (8.70)
0.63 (4.94)
0.53 (3.74)
0.50 (3.55)
1000
32.34 (443.91)
16.11 (185.67)
11.54 (92.23)
4.65 (37.55)
2.02 (23.14)
1.15 (12.29)
0.77 (7.42)
0.64 (4.98)
2000
32.29 (372.54)
15.99 (182.27)
8.02 (91.73)
4.08 (45.89)
2.19 (24.14)
1.36 (12.32)
1.08 (8.03)
1.00 (6.93)
Table 6. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
21.8 (19.6)
21.5 (19.0)
21.4 (19.0)
21.4 (19.0)
21.3 (19.2)
20.9 (18.7)
20.2 (17.8)
19.4 (17.2)
10
21.4 (18.8)
21.3 (19.1)
21.0 (18.5)
20.8 (18.6)
20.7 (18.6)
20.6 (18.0)
19.9 (17.5)
18.9 (16.5)
20
20.8 (18.2)
20.7 (18.2)
20.5 (18.0)
20.5 (18.0)
20.4 (18.0)
20.0 (17.5)
19.3 (16.9)
18.4 (15.9)
40
20.5 (17.8)
20.6 (18.0)
20.5 (18.0)
20.4 (17.8)
20.2 (17.8)
19.8 (17.4)
18.7 (16.3)
17.8 (15.4)
80
20.1 (17.5)
20.1 (17.3)
20.3 (17.6)
20.0 (17.2)
19.7 (17.0)
19.4 (16.7)
18.4 (15.7)
17.5 (14.9)
160
19.6 (16.6)
19.6 (16.8)
19.6 (16.8)
19.5 (16.6)
19.3 (16.4)
18.9 (16.0)
17.9 (15.2)
16.9 (14.2)
320
18.7 (15.7)
18.7 (15.7)
18.5 (15.7)
18.7 (15.7)
18.5 (15.6)
18.1 (15.3)
17.4 (14.5)
16.5 (13.7)
640
18.2 (15.1)
18.2 (15.1)
18.1 (15.1)
18.4 (15.5)
18.0 (14.8)
17.6 (14.7)
16.9 (14.1)
16.0 (13.1)
1000
17.0 (13.2)
17.0 (13.4)
16.4 (13.4)
16.7 (13.7)
17.0 (13.4)
16.8 (13.3)
16.4 (13.1)
15.6 (12.6)
2000
17.0 (13.4)
17.0 (13.5)
17.0 (13.4)
16.9 (13.4)
16.8 (13.4)
16.5 (13.3)
15.9 (13.0)
15.0 (12.2)
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ADS1248
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Table 7. Noise in mVRMS and (mVPP)
at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
1.35 (7.78)
0.70 (4.17)
0.35 (2.03)
0.17 (0.95)
0.10 (0.53)
0.06 (0.32)
0.05 (0.31)
0.05 (0.29)
10
1.80 (10.82)
0.88 (5.26)
0.50 (2.75)
0.24 (1.47)
0.13 (0.80)
0.09 (0.49)
0.07 (0.39)
0.07 (0.40)
20
2.62 (14.32)
1.22 (7.05)
0.66 (3.88)
0.35 (2.05)
0.19 (1.09)
0.12 (0.66)
0.10 (0.61)
0.10 (0.55)
40
2.64 (16.29)
1.34 (7.75)
0.69 (4.06)
0.35 (2.07)
0.21 (1.15)
0.15 (0.85)
0.14 (0.81)
0.13 (0.75)
80
3.69 (23.62)
1.82 (10.81)
0.89 (5.48)
0.51 (2.68)
0.30 (1.69)
0.21 (1.32)
0.20 (1.09)
0.18 (0.98)
160
5.70 (35.74)
2.63 (16.90)
1.34 (8.82)
0.68 (4.24)
0.40 (2.65)
0.30 (1.92)
0.28 (1.88)
0.26 (1.57)
320
9.67 (67.44)
4.95 (35.30)
2.59 (17.52)
1.29 (8.86)
0.72 (4.35)
0.49 (3.03)
0.40 (2.44)
0.37 (2.34)
640
13.66 (93.06)
7.04 (45.20)
3.63 (18.73)
1.84 (12.97)
1.02 (6.51)
0.68 (4.20)
0.58 (3.69)
0.53 (3.50)
1000
31.18 (284.59)
16.00 (129.77)
7.58 (61.30)
3.98 (33.04)
2.08 (16.82)
1.16 (9.08)
0.83 (5.42)
0.68 (4.65)
2000
31.42 (273.39)
15.45 (130.68)
8.07 (67.13)
4.06 (36.16)
2.29 (19.22)
1.38 (9.87)
1.06 (6.93)
1.00 (6.48)
Table 8. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V
14
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
21.5 (19.0)
21.5 (18.9)
21.5 (18.9)
21.5 (19.0)
21.3 (18.9)
21.0 (18.6)
20.2 (17.7)
19.2 (16.8)
10
21.1 (18.5)
21.1 (18.6)
21.0 (18.5)
21.0 (18.4)
20.9 (18.3)
20.5 (18.0)
19.8 (17.3)
18.7 (16.3)
20
20.6 (18.1)
20.7 (18.1)
20.6 (18.0)
20.5 (17.9)
20.4 (17.8)
20.1 (17.6)
19.2 (16.7)
18.3 (15.8)
40
20.6 (17.9)
20.5 (18.0)
20.5 (17.9)
20.5 (17.9)
20.2 (17.8)
19.7 (17.2)
18.8 (16.3)
17.9 (15.4)
80
20.1 (17.4)
20.1 (17.5)
20.1 (17.5)
20.0 (17.5)
19.7 (17.2)
19.2 (16.6)
18.3 (15.8)
17.5 (15.0)
160
19.5 (16.8)
19.6 (16.9)
19.5 (16.8)
19.5 (16.9)
19.3 (16.6)
18.7 (16.0)
17.8 (15.1)
16.9 (14.3)
320
18.7 (15.9)
18.7 (15.8)
18.6 (15.8)
18.6 (15.8)
18.4 (15.8)
18.0 (15.4)
17.3 (14.7)
16.4 (13.7)
640
18.2 (15.4)
18.1 (15.5)
18.1 (15.7)
18.1 (15.3)
17.9 (15.3)
17.5 (14.9)
16.8 (14.1)
15.9 (13.2)
1000
17.0 (13.8)
17.0 (13.9)
17.0 (14.0)
17.0 (13.9)
16.9 (13.9)
16.8 (13.8)
16.2 (13.5)
15.5 (12.7)
2000
17.0 (13.9)
17.0 (13.9)
17.0 (13.9)
16.9 (13.8)
16.8 (13.7)
16.5 (13.7)
15.9 (13.2)
15.0 (12.3)
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
Table 9. Noise in mVRMS and (mVPP)
at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
2.50 (14.24)
1.32 (6.92)
0.67 (3.48)
0.32 (1.68)
0.17 (0.90)
0.09 (0.51)
0.08 (0.42)
0.07 (0.39)
10
3.09 (16.85)
1.69 (9.32)
0.82 (4.68)
0.42 (2.41)
0.23 (1.18)
0.11 (0.63)
0.11 (0.66)
0.10 (0.55)
20
4.55 (24.74)
2.19 (12.82)
1.07 (5.94)
0.55 (3.38)
0.28 (1.66)
0.16 (1.00)
0.15 (0.92)
0.14 (0.87)
40
5.06 (34.59)
2.39 (14.49)
1.27 (7.75)
0.66 (4.01)
0.36 (2.18)
0.21 (1.16)
0.21 (1.27)
0.15 (0.84)
80
6.63 (43.46)
3.28 (20.22)
1.79 (10.64)
0.89 (5.48)
0.47 (2.95)
0.29 (1.63)
0.28 (1.64)
0.21 (1.24)
160
9.75 (68.28)
4.89 (32.19)
2.36 (17.74)
1.26 (9.87)
0.65 (4.77)
0.40 (2.60)
0.40 (2.70)
0.30 (2.12)
320
19.22 (140.06)
9.80 (82.24)
4.81 (32.74)
2.47 (18.59)
1.27 (9.45)
0.71 (5.83)
0.50 (3.36)
0.43 (2.86)
640
27.07 (192.96)
13.54 (100.26)
6.88 (49.07)
3.40 (25.93)
1.76 (12.49)
1.02 (7.49)
0.71 (4.81)
0.60 (4.06)
1000
40.83 (388.28)
20.39 (185.96)
10.39 (89.38)
5.09 (43.28)
2.66 (22.78)
1.45 (11.01)
0.93 (6.74)
0.74 (4.86)
2000
42.06 (322.85)
21.15 (166.75)
10.66 (92.68)
5.61 (44.08)
2.92 (23.06)
1.68 (11.71)
1.19 (8.23)
1.05 (6.97)
Table 10. Effective Number of Bits From RMS and (Peak-to-Peak Noise)
at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V
DATA
RATE
(SPS)
PGA SETTING
1
2
4
8
16
32
64
128
5
20.6 (18.1)
20.6 (18.2)
20.5 (18.2)
20.6 (18.2)
20.5 (18.1)
20.4 (17.9)
19.6 (17.2)
18.8 (16.3)
10
20.3 (17.9)
20.2 (17.7)
20.3 (17.7)
20.2 (17.7)
20.1 (17.7)
20.1 (17.6)
19.1 (16.6)
18.3 (15.8)
20
19.8 (17.3)
19.8 (17.3)
19.9 (17.4)
19.8 (17.2)
19.8 (17.2)
19.6 (17.0)
18.7 (16.1)
17.8 (15.2)
40
19.6 (16.9)
19.7 (17.1)
19.6 (17.0)
19.6 (17.0)
19.5 (16.8)
19.2 (16.8)
18.2 (15.6)
17.7 (15.2)
80
19.2 (16.5)
19.3 (16.6)
19.1 (16.6)
19.1 (16.5)
19.0 (16.4)
18.7 (16.3)
17.8 (15.3)
17.2 (14.7)
160
18.7 (15.9)
18.7 (16.0)
18.7 (15.8)
18.6 (15.7)
18.6 (15.7)
18.3 (15.6)
17.3 (14.5)
16.7 (13.9)
320
17.7 (14.8)
17.7 (14.6)
17.7 (14.9)
17.7 (14.7)
17.6 (14.7)
17.5 (14.4)
17.0 (14.2)
16.2 (13.4)
640
17.2 (14.4)
17.2 (14.3)
17.2 (14.3)
17.2 (14.3)
17.1 (14.3)
16.9 (14.1)
16.5 (13.7)
15.7 (12.9)
1000
16.6 (13.4)
16.6 (13.4)
16.6 (13.5)
16.6 (13.5)
16.6 (13.5)
16.4 (13.5)
16.1 (13.2)
15.4 (12.7)
2000
16.6 (13.6)
16.6 (13.6)
16.6 (13.4)
16.5 (13.5)
16.4 (13.4)
16.2 (13.4)
15.7 (12.9)
14.9 (12.2)
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ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
NOISE HISTOGRAM PLOT
NOISE HISTOGRAM PLOT
1800
1400
1600
1400
1200
1000
800
AVDD = 5V
PGA = 32
Data Rate = 20SPS
12k Samples
s = 19
1000
800
600
600
400
400
200
200
0
0
-69
-63
-58
-52
-47
-41
-36
-30
-25
-20
-14
-9
-3
1
7
12
18
23
28
34
39
45
50
56
61
67
73
-53
-49
-45
-41
-37
-33
-29
-26
-22
-18
-14
-10
-6
-3
0
4
8
12
16
19
23
27
31
35
39
43
47
Counts
1200
AVDD = 5V
PGA = 1
Data Rate = 20SPS
12k Samples
s = 13
Counts
1600
1800
(LSB)
(LSB)
Figure 5.
Figure 6.
NOISE HISTOGRAM PLOT
NOISE HISTOGRAM PLOT
1600
1200
Counts
1000
AVDD = 3.3V
PGA = 1
Data Rate = 20SPS
12k Samples
s = 18.5
1200
1000
Counts
1400
1400
800
AVDD = 3.3V
PGA = 32
Data Rate = 20SPS
12k Samples
s = 22
800
600
600
(LSB)
RMS NOISE vs INPUT SIGNAL
AVDD = 5V
PGA = 32
Data Rate = 5SPS
100
60
80
45
25
35
AVDD = 3.3V
PGA = 32
Data Rate = 5SPS
0.25
RMS Noise (mV)
RMS Noise (mV)
5
RMS NOISE vs INPUT SIGNAL
0.30
0.20
0.15
0.10
0.05
0.20
0.15
0.10
0.05
-80
-60
-40
-20
20
40
60
80
100
0
-100
-80
-60
VIN (% of FSR)
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-40
-20
20
40
60
80
100
VIN (% of FSR)
Figure 9.
16
15
Figure 8.
0.30
0
-100
-5
(LSB)
Figure 7.
0.25
-15
-80
-25
0
-35
0
-45
200
-60
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
60
70
80
90
100
110
200
-60
400
400
Figure 10.
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
OFFSET vs TEMPERATURE
OFFSET vs TEMPERATURE
4
8
AVDD = 5V
Data Rate = 20SPS
2
1
AVDD = 5V
Data Rate = 160SPS
6
Input-Referred Offset (mV)
Input-Referred Offset (mV)
3
PGA = 128
0
PGA = 32
-1
PGA = 1
-2
4
2
PGA = 32
0
PGA = 128
-2
-4
PGA = 1
-6
-3
-8
-40
0
-20
20
40
60
80
100
120
-40
0
-20
Temperature (°C)
40
60
80
120
Figure 12.
OFFSET vs TEMPERATURE
OFFSET vs TEMPERATURE
8
15
AVDD = 5V
Data Rate = 640SPS
6
2
Input-Referred Offset (mV)
4
PGA = 32
0
-2
PGA = 128
-4
-6
-8
PGA = 1
-10
AVDD = 5V
Data Rate = 2kSPS
10
5
0
PGA = 32
-5
PGA = 128
-10
PGA = 1
-12
-15
-14
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 13.
Figure 14.
OFFSET vs TEMPERATURE
OFFSET vs TEMPERATURE
4
5
AVDD = 3.3V
Data Rate = 20SPS
2
1
0
-1
PGA = 1
PGA = 32
PGA = 128
-2
AVDD = 3.3V
Data Rate = 160SPS
4
Input-Referred Offset (mV)
3
Input-Referred Offset (mV)
100
Temperature (°C)
Figure 11.
Input-Referred Offset (mV)
20
PGA = 1
3
2
PGA = 32
1
0
-1
PGA = 128
-2
-3
-4
-5
-3
-6
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Temperature (°C)
Figure 15.
20
40
60
80
100
120
Temperature (°C)
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
OFFSET vs TEMPERATURE
OFFSET vs TEMPERATURE
10
8
AVDD = 3.3V
Data Rate = 640SPS
6
PGA = 1
4
PGA = 32
2
0
-2
AVDD = 3.3V
Data Rate = 2kSPS
6
Input-Referred Offset (mV)
Input-Referred Offset (mV)
8
PGA = 128
-4
PGA = 1
4
PGA = 128
2
0
PGA = 32
-2
-4
-6
-6
-8
-40
-20
0
20
40
60
80
100
120
-40
0
-20
20
Temperature (°C)
Figure 17.
GAIN vs TEMPERATURE
80
120
GAIN vs TEMPERATURE
AVDD = 5V
Data Rate = 160SPS
0.02
PGA = 1
0.03
PGA = 1
0.01
Gain Error (%)
0.02
0.01
PGA = 32
0
-0.01
-0.02
0
-0.01
PGA = 32
-0.02
PGA = 128
PGA = 128
-0.03
-0.03
AVDD = 5V
Data Rate = 20SPS
-0.05
-0.04
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Temperature (°C)
20
40
60
80
100
120
Temperature (°C)
Figure 19.
Figure 20.
GAIN vs TEMPERATURE
GAIN vs TEMPERATURE
0.03
0.02
AVDD = 5V
Data Rate = 2kSPS
Data Rate = 640SPS
0.02
0.01
PGA = 1
Gain Error (%)
0.01
Gain Error (%)
100
0.03
0.04
-0.04
60
Figure 18.
0.05
Gain Error (%)
40
Temperature (°C)
PGA = 1
0
-0.01
PGA = 128
0
-0.01
PGA = 128
-0.02
-0.02
PGA = 32
-0.03
-0.03
PGA = 32
-0.04
-0.04
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Figure 21.
18
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20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
GAIN vs TEMPERATURE
GAIN vs TEMPERATURE
0.04
0.04
AVDD = 3.3V
Data Rate = 20SPS
0.03
AVDD = 3.3V
Data Rate = 160SPS
0.03
PGA = 128
0.02
PGA = 32
Gain Error (%)
Gain Error (%)
0.02
0.01
0
PGA = 1
-0.01
PGA = 128
0.01
-0.01
PGA = 32
-0.02
-0.02
-0.03
-0.03
-0.04
PGA = 1
0
-0.04
-40
0
-20
20
40
60
80
100
120
-40
0
-20
20
Temperature (°C)
Figure 23.
60
80
100
120
Figure 24.
GAIN vs TEMPERATURE
GAIN vs TEMPERATURE
0.05
0.05
0.04
AVDD = 3.3V
Data Rate = 640SPS
PGA = 128
0.04
0.03
0.03
0.02
0.02
Gain Error (%)
Gain Error (%)
40
Temperature (°C)
0.01
0
-0.01
-0.02
AVDD = 3.3V
Data Rate = 2kSPS
PGA = 128
0.01
PGA = 32
0
PGA = 1
-0.01
-0.02
PGA = 1
-0.03
-0.03
PGA = 32
-0.04
-0.04
-0.05
-0.05
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Temperature (°C)
20
40
60
80
100
120
Temperature (°C)
Figure 25.
Figure 26.
ANALOG CURRENT vs DATA RATE
DIGITAL CURRENT vs DATA RATE
600
290
550
270
450
AVDD = 5V
400
350
AVDD = 3.3V
300
250
200
Digital Current (mA)
Analog Current (mA)
500
250
DVDD = 5V
230
DVDD = 3.3V
210
190
150
170
100
5
10
20
40
80
160 320 640 1000 2000
5
10
20
Data Rate (SPS)
Figure 27.
40
80
160
320 640 1000 2000
Data Rate (SPS)
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
ANALOG CURRENT vs TEMPERATURE
DIGITAL CURRENT vs TEMPERATURE
800
330
AVDD = 5V
DVDD = 5V
2kSPS
700
310
320/640/1kSPS
500
40/80/160SPS
400
5/10/20SPS
300
200
Digital Current (mA)
Analog Current (mA)
2kSPS
600
290
320/640/1kSPS
270
250
230
40/80/160SPS
100
210
0
190
5/10/20SPS
-40
0
-20
20
40
60
80
100
120
-40
-20
0
20
Temperature (°C)
Figure 29.
60
80
100
120
Figure 30.
ANALOG CURRENT vs TEMPERATURE
DIGITAL CURRENT vs TEMPERATURE
700
310
AVDD = 3.3V
2kSPS
DVDD = 3.3V
600
290
500
320/640/1kSPS
400
40/80/160SPS
300
5/10/20SPS
200
Digital Current (mA)
2kSPS
Analog Current (mA)
40
Temperature (°C)
270
320/640/1kSPS
250
230
40/80/160SPS
100
210
0
190
5/10/20SPS
-40
-20
0
20
40
60
80
100
120
-40
-20
0
Temperature (°C)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
80
100
120
INTEGRAL NONLINEARITY vs INPUT SIGNAL
8
PGA = 1
Data Rate = 20SPS
6
PGA = 32
Data Rate = 20SPS
6
4
INL (ppm of FSR)
4
INL (ppm of FSR)
60
Figure 32.
8
-40°C
2
-10°C
0
-2
+25°C
-4
2
-10°C
0
-40°C
-2
-4
+25°C
-6
+105°C
-6
+105°C
-8
-50
0
50
100
-10
-100
-50
VIN (% of FSR)
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50
100
VIN (% of FSR)
Figure 33.
20
40
Temperature (°C)
Figure 31.
-8
-100
20
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL
INTEGRAL NONLINEARITY vs INPUT SIGNAL
8
8
6
-10°C
4
-40°C
INL (ppm of FSR)
INL (ppm of FSR)
4
-10°C
2
0
-2
+25°C
-4
-6
0
-50
+25°C
2
0
-2
-4
+105°C
-8
-100
50
PGA = 1
Data Rate = 2kSPS
-6
-8
-100
100
50
Figure 36.
DATA RATE ERROR vs TEMPERATURE
(Using Internal Oscillator)
CMRR vs TEMPERATURE
3.0
130
2.5
125
2.0
120
1.5
1.0
CMRR (dB)
DVDD = 5V
DVDD = 3.3V
-0.5
PGA = 32
115
0.5
0
100
VIN (% of FSR)
Figure 35.
Data Rate Error (%)
0
-50
VIN (% of FSR)
-1.0
110
PGA = 128
105
100
95
-1.5
PGA = 1
90
-2.0
85
-2.5
80
-3.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 37.
Figure 38.
INTERNAL VREF vs TEMPERATURE
IDAC LINE REGULATION
2.050
1.002
14 Units
1.001
Normalized Output Current
Output Voltage (V)
+105°C
-40°C
PGA = 128
Data Rate = 20SPS
6
2.049
2.048
2.047
1.000
0.999
50mA
100mA
0.998
0.997
500mA
0.996
250mA
0.995
750mA
0.994
0.993
1mA
0.992
2.046
IDAC Current Settings
1.5mA
0.991
-40
-20
0
20
40
60
80
100
120
2.0
2.5
3.0
Temperature (°C)
Figure 39.
3.5
4.0
4.5
5.0
5.5
6.0
AVDD (V)
Figure 40.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
IDAC DRIFT
POWER-SUPPLY REJECTION vs GAIN
0.004
8
1.5mA Setting, 10 Units
Power-Supply Rejection (mV/V)
IEXC1 - IEXC2 (mA)
0.003
0.002
0.001
0
-0.001
-0.002
-0.003
-0.004
7
2000SPS
6
5
320/640/1000SPS
4
3
40/80/160SPS
2
5/10/20SPS
1
0
-40
-20
0
20
40
60
80
100
120
1
2
4
8
Temperature (°C)
16
32
64
128
Gain
Figure 41.
Figure 42.
INTERNAL VREF INITIAL ACCURACY HISTOGRAM
IDAC INITIAL ACCURACY HISTOGRAM
700
200
2280 Units
180
600
2280 Units
140
400
120
Counts
300
100
80
60
200
40
100
20
0
2.25
2.50
2.00
1.50
1.75
1.00
1.25
0.50
0.75
0
Initial Accuracy (V)
0.25
-0.50
-0.25
-1.00
-1.25
2.0485
2.0484
2.0483
2.0482
2.0481
2.0480
2.0479
2.0478
2.0477
2.0476
2.0475
0
-0.75
Counts
160
500
Initial Accuracy (%)
Figure 43.
Figure 44.
IDAC MISMATCH HISTOGRAM
350
2280 Units
300
Counts
250
200
150
100
50
0.6
0.5
0.4
0.3
0.2
0
0.1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
Initial Accuracy (%)
Figure 45.
22
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GENERAL DESCRIPTION
OVERVIEW
The ADS1247 and ADS1248 also include a flexible
input multiplexer with system monitoring capability
and general-purpose I/O settings, a very low-drift
voltage reference, and two matched current sources
for sensor excitation. Figure 46 and Figure 47 show
the various functions incorporated in each device.
The ADS1246, ADS1247 and ADS1248 are highly
integrated 24-bit data converters. They include a
low-noise, high-impedance programmable gain
amplifier (PGA), a delta-sigma (ΔΣ) ADC with an
adjustable single-cycle settling digital filter, internal
oscillator, and a simple but flexible SPI-compatible
serial interface.
REFP
AVDD
REFN
DVDD
Burnout
Detect
ADS1246
VBIAS
SCLK
DIN
AIN0
AIN1
Input
Mux
3rd Order
DS
Modulator
PGA
Adjustable
Digital
Filter
Serial
Interface
and
Control
DRDY
DOUT/DRDY
CS
START
RESET
Internal Oscillator
Burnout
Detect
AVSS
DGND
CLK
Figure 46. ADS1246 Diagram
AVDD
REFP0/ REFN0/ ADS1248 Only
GPIO0 GPIO1 REFP1 REFN1
VREFOUT VREFCOM
Burnout
Detect
Voltage
Reference
VREF Mux
VBIAS
DVDD
ADS1247
ADS1248
GPIO
AIN0/IEXC
AIN1/IEXC
SCLK
System
Monitor
AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3
Input
Mux
AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5
PGA
DIN
3rd Order
DS
Modulator
Dual
Current
DACs
AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7
ADS1248 Only
Adjustable
Digital
Filter
Serial
Interface
and
Control
DRDY
DOUT/DRDY
CS
START
RESET
Internal Oscillator
Burnout
Detect
AVSS
IEXC1
IEXC2
CLK
DGND
ADS1248 Only
Figure 47. ADS1247, ADS1248 Diagram
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ADC INPUT AND MULTIPLEXER
Any analog input pin can be selected as the positive
input or negative input through the MUX0 register.
The ADS1246/7/8 have a true fully differential mode,
meaning that the input signal range can be from
–2.5V to +2.5V (when AVDD = 2.5V and
AVSS = –2.5V).
The ADS1246/7/8 ADC measures the input signal
through the onboard PGA. All analog inputs are
connected to the internal AINP or AINN analog inputs
through the analog multiplexer. A block diagram of
the analog input multiplexer is shown in Figure 48.
The input multiplexer connects to eight (ADS1248),
four (ADS1247), or two (ADS1246) analog inputs that
can be configured as single-ended inputs, differential
inputs, or in a combination of single-ended and
differential inputs. The multiplexer also allows the
on-chip excitation current and/or bias voltage to be
selected to a specific channel.
AVDD
Through the input multiplexer, the ambient
temperature (internal temperature sensor), AVDD,
DVDD, and external reference can all be selected for
measurement. Refer to the System Monitor section
for details.
On the ADS1247 and ADS1248, the analog inputs
can also be configured as general-purpose
inputs/outputs (GPIOs). See the General-Purpose
Digital I/O section for more details.
AVDD
IDAC2
IDAC1
System Monitors
AVSS
AVDD
VBIAS
AVDD
AVDD
AIN0
AVSS
AVDD
VBIAS
Temperature
Diode
VREFP
VREFN
AIN1
ADS1247/48 Only
AVSS
AVDD
VREFP1/4
VBIAS
VREFN1/4
VREFP0/4
AIN2
AVSS
AVDD
VREFN0/4
VBIAS
AVDD/4
AIN3
AVSS/4
DVDD/4
ADS1248 Only
AVSS
AVDD
DGND/4
VBIAS
AIN4
AVDD
AVSS
AVDD
Burnout Current Source
(0.5mA, 2mA, 10mA)
VBIAS
AIN5
AINP
AVSS
AVDD
VBIAS
AVSS
AVDD
VBIAS
AINN
PGA
To
ADC
AIN6
AIN7
Burnout Current Source
(0.5mA, 2mA, 10mA)
AVSS
Figure 48. Analog Input Multiplexer Circuit
24
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ESD diodes protect the ADC inputs. To prevent these
diodes from turning on, make sure the voltages on
the input pins do not go below AVSS by more than
100mV, and do not exceed AVDD by more than
100mV, as shown in Equation 2. Note that the same
caution is true if the inputs are configured to be
GPIOs.
AVSS – 100mV < (AINX) < AVDD + 100mV
(2)
Settling Time for Channel Multiplexing
The ADS1246/7/8 is a true single-cycle settling ΔΣ
converter. The first data available after the start of a
conversion are fully settled and valid for use. The
time required to settle is roughly equal to the inverse
of the data rate. The exact time depends on the
specific data rate and the operation that resulted in
the start of a conversion; see Table 20 for specific
values.
VOLTAGE REFERENCE INPUT
The voltage reference for the ADS1246/7/8 is the
differential voltage between REFP and REFN:
VREF = VREFP – VREFN
In the case of the ADS1246, these pins are dedicated
inputs. For the ADS1247 and ADS1248, there is a
multiplexer that selects the reference inputs, as
shown in Figure 49. The reference input uses a buffer
to increase the input impedance.
As with the analog inputs, REFP0 and REFN0 can be
configured as digital I/Os on the ADS1247/8.
ADS1248 Only
REFP1 REFN1
REFP0 REFN0
VREFOUT VREFCOM
ANALOG INPUT IMPEDANCE
The ADS1246/7/8 inputs are buffered through a
high-impedance PGA before they reach the ΔΣ
modulator. For the majority of applications, the input
current leakage is minimal and can be neglected.
However, because the PGA is chopper-stabilized for
noise and offset performance, the input impedance is
best described as small absolute input current. The
absolute current leakage for selected channels is
approximately proportional to the selected modulator
clock. Table 11 shows the typical values for these
currents with a differential voltage coefficient and the
corresponding input impedances over data rate.
Internal
Voltage
Reference
Reference Multiplexer
REFP
REFN
ADC
Figure 49. Reference Input Multiplexer
The reference input circuit has ESD diodes to protect
the inputs. To prevent the diodes from turning on,
make sure the voltage on the reference input pin is
not less than AVSS – 100mV, and does not exceed
AVDD + 100mV, as shown in Equation 3:
AVSS – 100mV < (VREFP or VREFN) < AVDD + 100mV
(3)
Table 11. Typical Values for Analog Input Current Over Data Rate (1)
(1)
CONDITION
ABSOLUTE INPUT CURRENT
EFFECTIVE INPUT IMPEDANCE
DR = 5SPS, 10SPS, 20SPS
± (0.5nA + 0.1nA/V)
5000MΩ
DR = 40SPS, 80SPS, 160SPS
± (2nA + 0.5nA/V)
1200MΩ
DR = 320SPS, 640SPS, 1kSPS
± (4nA + 1nA/V)
600MΩ
DR = 2kSPS
± (8nA + 2nA/V)
300MΩ
Input current with VCM = 2.5V. TA = +25°C, AVDD = 5V, and AVSS = 0V.
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LOW-NOISE PGA
MODULATOR
The ADS1246/7/8 feature a low-drift, low-noise, high
input impedance programmable gain amplifier (PGA).
The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64,
or 128 by register SYS0. A simplified diagram of the
PGA is shown in Figure 50.
A third-order modulator is used in the ADS1246/7/8.
The modulator converts the analog input voltage into
a pulse code modulated (PCM) data stream. To save
power, the modulator clock runs from 32kHz up to
512kHz for different data rates, as shown in Table 12.
The PGA consists of two chopper-stabilized
amplifiers (A1 and A2) and a resistor feedback
network that sets the gain of the PGA. The PGA input
is equipped with an electromagnetic interference
(EMI) filter, as shown in Figure 50. Note that as with
any PGA, it is necessary to ensure that the input
voltage stays within the specified common-mode
input range specified in the Electrical Characteristics.
The common-mode input (VCMI) must be within the
range shown in Equation 4:
Table 12. Modulator Clock Frequency for Different
Data Rates
(
AVSS + 0.1V +
)
(
)
(VIN)(Gain)
(V )(Gain)
£ VCMI £ AVDD - 0.1V - IN
2
2
(4)
454W
AINP
7.5pF
A1
R
7.5pF
C
R
ADC
fMOD
(kHz)
5, 10, 20
32
40, 80, 160
128
320, 640, 1000
256
2000
512
DIGITAL FILTER
The ADS1246/7/8 use linear-phase finite impulse
response (FIR) digital filters that can be adjusted for
different output data rates. The digital filter always
settles in a single cycle.
Table 13 shows the exact data rates when an
external oscillator equal to 4.096MHz is used. Also
shown is the signal –3dB bandwidth, and the 50Hz
and 60Hz attenuation. For good 50Hz or 60Hz
rejection, use a data rate of 20SPS or slower.
The frequency responses of the digital filter are
shown in Figure 51 to Figure 61. Figure 54 shows a
detailed view of the filter frequency response from
48Hz to 62Hz for a 20SPS data rate. All filter plots
are generated with 4.096MHz external clock.
7.5pF
A2
454W
DATA RATE
(SPS)
AINN
7.5pF
Figure 50. Simplified Diagram of the PGA
Table 13. Digital Filter Specifications (1)
ATTENUATION
NOMINAL
DATA RATE
ACTUAL
DATA RATE
–3dB
BANDWIDTH
fIN = 50Hz ±0.3Hz
fIN = 60Hz ±0.3Hz
fIN = 50Hz ±1Hz
fIN = 60Hz ±1Hz
5SPS
5.018SPS
2.26Hz
–106dB
–74dB
–81dB
–69dB
10SPS
10.037SPS
4.76Hz
–106dB
–74dB
–80dB
–69dB
20SPS
20.075SPS
14.8Hz
–71dB
–74dB
–66dB
–68dB
40SPS
40.15SPS
9.03Hz
(1)
26
80SPS
80.301SPS
19.8Hz
160SPS
160.6SPS
118Hz
320SPS
321.608SPS
154Hz
495Hz
640SPS
643.21SPS
1000SPS
1000SPS
732Hz
2000SPS
2000SPS
1465Hz
Values shown for fOSC = 4.096MHz.
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0
-60
-20
-70
Magnitude (dB)
Magnitude (dB)
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-40
-60
-80
-80
-90
-100
-110
-100
-120
-120
0
20
40
60
80
48
100 120 140 160 180 200
50
Figure 51. Filter Profile with Data Rate = 5SPS
52
54
56
58
60
62
Frequency (Hz)
Frequency (Hz)
Figure 54. Detailed View of Filter Profile with Data
Rate = 20SPS between 48Hz and 62Hz
0
0
-20
Magnitude (dB)
Magnitude (dB)
-20
-40
-60
-80
-40
-60
-80
-100
-100
-120
0
20
40
60
80
100 120 140 160 180 200
-120
0
Frequency (Hz)
200
400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Figure 52. Filter Profile with Data Rate = 10SPS
Figure 55. Filter Profile with Data Rate = 40SPS
0
0
-20
-40
Gain (dB)
Magnitude (dB)
-20
-40
-60
-80
-60
-80
-100
-100
-120
0
20
40
60
80
100 120 140 160 180 200
Frequency (Hz)
-120
0
200
400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Figure 53. Filter Profile with Data Rate = 20SPS
Figure 56. Filter Profile with Data Rate = 80SPS
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0
0
-20
-20
Magnitude (dB)
Magnitude (dB)
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
200
400 600 800 1000 1200 1400 1600 1800 2000
0
1
2
3
Frequency (Hz)
0
0
-20
-20
-40
-60
-80
-100
6
7
8
9
10
-40
-60
-80
-100
-120
-120
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
2
4
Frequency (Hz)
Figure 58. Filter Profile with Data Rate = 320SPS
6
8
10
12
14
16
18
20
Frequency (kHz)
Figure 61. Filter Profile with Data Rate = 2kSPS
CLOCK SOURCE
0
The ADS1246/7/8 can use either the internal
oscillator or an external clock. Connect the CLK pin to
DGND before power-on or reset to activate the
internal oscillator. Connecting an external clock to the
CLK pin at any time deactivates the internal oscillator,
with the device then operating on the external clock.
After the device switches to the external clock, it
cannot be switched back to the internal oscillator
without cycling the power supplies or resetting the
device.
-20
Magnitude (dB)
5
Figure 60. Filter Profile with Data Rate = 1kSPS
Magnitude (dB)
Magnitude (dB)
Figure 57. Filter Profile with Data Rate = 160SPS
4
Frequency (kHz)
-40
-60
-80
-100
-120
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (Hz)
Figure 59. Filter Profile with Data Rate = 640SPS
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INTERNAL VOLTAGE REFERENCE
EXCITATION CURRENT SOURCE DACS
The ADS1247/8 includes an onboard voltage
reference with a low temperature coefficient. The
output of the voltage reference is 2.048V with the
capability of both sourcing and sinking up to 10mA of
current.
The ADS1247/8 provide two matched excitation
current sources for RTD applications. For three- or
four-wire RTD applications, the matched current
sources can be used to cancel the errors caused by
sensor lead resistance. The output current of the
current source DACs can be programmed to 50mA,
100mA, 250mA, 500mA, 750mA, 1000mA, or 1500mA.
The voltage reference must have a capacitor
connected between VREFOUT and VREFCOM. The
value of the capacitance should be in the range of
1mF to 47mF. Large values provide more filtering of
the reference; however, the turn-on time increases
with capacitance, as shown in Table 14. For stability
reasons, VREFCOM must have a path with an
impedance less than 10Ω to ac ground nodes, such
as GND (for a 0V to 5V analog power supply), or
AVSS (for a ±2.5V analog power supply). In case this
impedance is higher than 10Ω, a capacitor of at least
0.1mF should be connected between VREFCOM and
an ac ground node (for example, GND). Note that
because it takes time for the voltage reference to
settle to the final voltage, care must be taken when
the device is turned off between conversions. Allow
adequate time for the internal reference to fully settle.
Table 14. Internal Reference Settling Time
VREFOUT
CAPACITOR
1mF
4.7mF
47mF
SETTLING
ERROR
TIME TO REACH THE
SETTLING ERROR
±0.5%
70ms
±0.1%
110ms
±0.5%
290ms
±0.1%
375ms
±0.5%
2.2ms
±0.1%
2.4ms
The onboard reference is controlled by the registers;
by default, it is off after startup (see the ADS1247/48
Detailed Register Definitions section for more details).
Therefore, the internal reference must first be turned
on and then connected via the internal reference
multiplexer. Because the onboard reference is used
to generate the current reference for the excitation
current sources, it must be turned on before the
excitation currents become available.
The two matched current sources can be connected
to dedicated current output pins IOUT1 and IOUT2
(ADS1248 only), or to any AIN pin (ADS1247/8); refer
to the ADS1247/48 Detailed Register Definitions
section for more information. It is possible to connect
both current sources to the same pin. Note that the
internal reference must be turned on and properly
compensated when using the excitation current
source DACs.
SENSOR DETECTION
The ADS1246/7/8 provide a selectable current
(0.5mA, 2mA, or 10mA) to help detect a possible
sensor malfunction.
When enabled, two burnout current sources flow
through the selected pair of analog inputs to the
sensor. One sources the current to the positive input
channel, and the other sinks the same current from
the negative input channel.
When the burnout current sources are enabled, a
full-scale reading may indicate an open circuit in the
front-end sensor, or that the sensor is overloaded. It
may also indicate that the reference voltage is
absent. A near-zero reading may indicate a
short-circuit in the sensor.
BIAS VOLTAGE GENERATION
A selectable bias voltage is provided for use with
ungrounded thermocouples. The bias voltage is
(AVDD + AVSS)/2 and can applied to any analog
input channel through internal input multiplexer. The
bias voltage turn-on times for different sensor
capacitances are listed in Table 15.
Table 15. Bias Voltage Settling Time
SENSOR CAPACITANCE
SETTLING TIME
0.1mF
220ms
1mF
2.2ms
10mF
22ms
200mF
450ms
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GENERAL-PURPOSE DIGITAL I/O
Power-Supply Monitor
The ADS1248 has eight pins and the ADS1247 has
four pins that serve a dual purpose as either analog
inputs or general-purpose digital inputs/outputs
(GPIOs).
The system monitor can measure the analog or
digital power supply. When measuring the power
supply, the resulting conversion is approximately 1/4
of the actual power supply voltage.
Figure 62 shows a diagram of how these functions
are combined onto a single pin. Note that when the
pin is configured as a GPIO, the corresponding logic
is powered from AVDD and AVSS. When the
ADS1247/8 are operated with bipolar analog
supplies, the GPIO outputs bipolar voltages. Care
must be taken loading the GPIO pins when used as
outputs because large currents can cause droop or
noise on the analog supplies.
Conversion Result = (VSP/4)/VREF
IOCFG
IODIR
REFx0/GPIOx
AINx/GPIOx
DIO WRITE
To Analog Mux
DIO READ
Figure 62. Analog/Data Interface Pin
SYSTEM MONITOR
The ADS1247 and ADS1248 provide a system
monitor function. This function can measure the
analog power supply, digital power supply, external
voltage reference, or ambient temperature. Note that
the system monitor function provides a coarse result.
When the system monitor is enabled, the analog
inputs are disconnected.
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(5)
Where VSP is the selected supply to be measured.
External Voltage Reference Monitor
The ADS1246/7/8 can be selected to measure the
external voltage reference. In this configuration, the
monitored external voltage reference is connected to
the analog input. The result (conversion code) is
approximately 1/4 of the actual reference voltage.
Conversion Result = (VREX/4)/VREF
Where VREX
monitored.
is
the
external
(6)
reference
to
be
NOTE: The internal reference voltage must be
enabled when measuring an external voltage
reference using the system monitor.
Ambient Temperature Monitor
On-chip
diodes
provide
temperature-sensing
capability. When selecting the temperature monitor
function, the anodes of two diodes are connected to
the ADC. Typically, the difference in diode voltage is
118mV at +25°C with a temperature coefficient of
405mV/°C.
Note that when the onboard temperature monitor is
selected, the PGA is automatically set to '1'.
However, the PGA register bits in are not affected
and the PGA returns to its set value when the
temperature monitor is turned off.
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CALIBRATION
The conversion data are scaled by offset and gain
registers before yielding the final output code. As
shown in Figure 63, the output of the digital filter is
first subtracted by the offset register (OSC) and then
multiplied by the full-scale register (FSC). A digital
clipping circuit ensures that the output code does not
exceed 24 bits. Equation 7 shows the scaling.
+
S
´
OFC
Register
FSC Register
400000h
ADC
-
Output Data
Clipped to 24 Bits
Final
Output
Figure 63. Calibration Block Diagram
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(7)
The values of the offset and full-scale registers are
set by writing to them directly, or they are set
automatically by calibration commands.
Offset Calibration Register: OFC[2:0]
The offset calibration is a 24-bit word, composed of
three 8-bit registers. The offset is in twos complement
format with a maximum positive value of 7FFFFFh
and a maximum negative value of 800000h. This
value is subtracted from the conversion data. A
register value of 000000h provides no offset
correction. Note that while the offset calibration
register value can correct offsets ranging from –FS to
+FS (as shown in Table 16), make sure to avoid
overloading the analog inputs.
Table 16. Final Output Code versus Offset
Calibration Register Setting
full-scale calibration register can correct gain errors
> 1 (with gain scaling < 1), make sure to avoid
overloading the analog inputs. The default or reset
value of FSC depends on the PGA setting. A different
factory-trimmed FSC Reset value is stored for each
PGA setting which provides outstanding gain
accuracy over all the ADS1246/7/8 input ranges.
Note: The factory-trimmed FSC reset value loads
automatically loaded whenever the PGA setting
changes.
Table 17. Gain Correction Factor versus
Full-Scale Calibration Register Setting
FULL-SCALE REGISTER
GAIN SCALING
800000h
2.0
400000h
1.0
200000h
0.5
000000h
0
Calibration Commands
The ADS1246/7/8 provide commands for three types
of calibration: system gain calibration, system offset
calibration and self offset calibration. Where absolute
accuracy is needed, it is recommended that
calibration be performed after power on, a change in
temperature, a change of PGA and in some cases a
change in channel. At the completion of calibration,
the DRDY signal goes low indicating the calibration is
finished. The first data after calibration are always
valid. If the START pin is taken low or a SLEEP
command is issued after any calibration command,
the devices goes to sleep after completing calibration.
System Gain Calibration
System gain calibration corrects for gain error in the
signal path. The system gain calibration is initiated by
sending the SYSGCAL command while applying a
full-scale input to the selected analog inputs.
Afterwards the full-scale calibration register (FSC) is
updated. When a system gain calibration command is
issued, the ADS1246/7/8 stop the current conversion
and start the calibration procedure immediately.
OFFSET REGISTER
FINAL OUTPUT CODE WITH
VIN = 0
7FFFFFh
8000000h
000001h
FFFFFFh
000000h
000000h
System Offset and Self Offset Calibration
FFFFFFh
000001h
8000000h
7FFFFFh
System offset calibration corrects both internal and
external offset errors. The system offset calibration is
initiated by sending the SYSGOCAL command while
applying a zero differential input (VIN = 0) to the
selected analog inputs. The self offset calibration is
initiated by sending the SELFOCAL command.
During self offset calibration, the selected inputs are
disconnected from the internal circuitry and a zero
differential signal is applied internally. With both offset
1. Excludes effects of noise and inherent offset
errors.
Full-Scale Calibration Register: FSC[2:0]
The full-scale or gain calibration is a 24-bit word
composed of three 8-bit registers. The full-scale
calibration value is 24-bit, straight binary, normalized
to 1.0 at code 400000h. Table 17 summarizes the
scaling of the full-scale register. Note that while the
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calibrations the offset calibration register (OFC) is
updated afterwards. When either offset calibration
command is issued, the ADS1246/7/8 stop the
current conversion and start the calibration procedure
immediately.
ADC SLEEP MODE
Calibration Timing
During sleep mode, the internal reference status
depends on the setting of the VREFCON bits in the
MUX1 register; see the Register Descriptions section
for details.
When calibration is initiated, the device performs 16
consecutive data conversions and averages the
results to calculate the calibration value. This
provides a more accurate calibration value. The time
required for calibration is shown in Table 18 and can
be calculated using Equation 8:
50
32
16
+
+
Calibration Time =
fOSC
fMOD
fDATA
(8)
Table 18. Calibration Time versus Data Rate
DATA RATE (SPS)
CALIBRATION TIME (ms)
5
3201.01
10
1601.01
20
801.012
40
400.26
80
200.26
160
100.14
320
50.14
640
25.14
1000
16.14
2000
8.07
1. For fOSC = 4.096MHz.
ADC POWER-UP
When DVDD is pulled up, the internal power-on reset
module generates a pulse that resets all digital
circuitry. All the digital circuits are held in a reset
state for 216 system clocks to allow the analog circuits
and the internal digital power supply to settle. SPI
communication cannot occur until the internal reset is
released.
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Power consumption can be dramatically reduced by
placing the ADS1246/7/8 into sleep mode. There are
two ways to put the device into sleep mode: the sleep
command (SLEEP) and through the START pin.
ADC CONTROL
ADC Conversion Control
The START pin provides easy and precise control of
conversions. Pulse the START pin high to begin a
conversion, as shown in Figure 64 and Table 19. The
conversion completion is indicated by the
DOUT/DRDY pin going low. When the conversion
completes, the ADS1246/7/8 automatically shuts
down to save power. During shutdown, the
conversion result can be retrieved; however, START
must be taken high before communicating with the
configuration registers. The device stays shut down
until the START pin is once again taken high to begin
a new conversion. When the START pin is taken
back high again, the decimation filter is held in a
reset state for 32 modulator clock cycles internally to
allow the analog circuits to settle.
The ADS1246/7/8 can be configured to convert
continuously by holding the START pin high, as
shown in Figure 65. With the START pin held high,
the ADC converts the selected input channels
continuously. This configuration continues until the
START pin is taken low.
The START pin can also be used to perform the
synchronized measurement for the multi-channel
applications by pulsing the START pin.
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tSTART
START
tCONV
DOUT/DRDY
1
2
3
24
SCLK
DRDY
ADS1246/47/48
Status
Shutdown
Converting
Figure 64. Timing for Single Conversion Using START Pin
Table 19. START Pin Conversion Times for Figure 64
SYMBOL
tCONV
DESCRIPTION
DATA RATE (SPS)
VALUE
UNIT
5
200.295
ms
10
100.644
ms
20
50.825
ms
40
25.169
ms
Time from START pulse to DRDY and
DOUT/DRDY going low
START
Data Ready
80
12.716
ms
160
6.489
ms
320
3.247
ms
640
1.692
ms
1000
1.138
ms
2000
0.575
ms
Data Ready
Data Ready
DOUT/DRDY
ADS1246/47/48
Status
Converting
Converting
Converting
Converting
NOTE: SCLK held low in this example.
Figure 65. Timing for Conversion with START Pin High
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RESET
When the RESET pin goes low, the device is
immediately reset. All the registers are restored to
default values. The device stays in reset mode as
long as the RESET pin stays low. When it goes high,
the ADC comes out of reset mode and is able to
convert data. After the RESET pin goes high, and
when the system clock frequency is 4.096MHz, the
digital filter and the registers are held in a reset state
for 0.6ms when fOSC = 4.096MHz. Therefore, valid
SPI communication can only be resumed 0.6ms after
the RESET pin goes high; see Figure 4. When the
RESET pin goes low, the clock selection is reset to
the internal oscillator.
Channel Cycling and Overload Recovery
When cycling through channels, care must be taken
when configuring the ADS1246/7/8 to ensure that
settling occurs within one cycle. For setups that
simply cycle through MUX channels, but do not
change PGA and data rate settings, simply changing
the MUX0 register is sufficient. However, when
changing PGA and data rate settings it is important to
ensure that an overloaded condition cannot occur
during the transmission. When configuration data are
transferred to the ADS1246/7/8, new settings become
active at the end of each byte sent. Therefore, a brief
overload condition can occur during the transmission
of configuration data after the completion of the
MUX0 byte and before completion of the SYS0 byte.
This temporary overload can result in intermittent
incorrect readings. To ensure that an overload does
not occur, it may be necessary to split the
communication into two separate communications
allowing the change of the SYS0 register before the
change of the MUX0 register.
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In the event of an overloaded state, care must also
be taken to ensure single cycle settling into the next
cycle. Because the ADS1246/7/8 implement a
chopper-stabilized PGA, changing data rates during
an overload state can cause the chopper to become
unstable. This instability results in slow settling time.
To prevent this slow settling, always change the PGA
setting or MUX setting to a non-overloaded state
before changing the data rate.
Digital Filter Reset Operation
Apart from the RESET command and the RESET pin,
the digital filter is reset automatically when either a
write operation to the MUX0, VBIAS, MUX1, or SYS0
registers is performed, when a SYNC command is
issued, or the START pin is taken high.
The filter is reset two system clocks after the last bit
of the SYNC command is sent. The reset pulse
created internally lasts for two multiplier clock cycles.
If any write operation takes place in the MUX0
register, the filter is reset regardless of whether the
value changed or not. Internally, the filter pulse lasts
for two system clock periods. If any write activity
takes place in the VBIAS, MUX1, or SYS0 registers,
the filter is reset as well, regardless of whether the
value changed or not. The reset pulse lasts for 32
modulator clocks after the write operation. If there are
multiple write operations, the resulting reset pulse
may be viewed as the ANDed result of the different
active low pulses created individually by each action.
Table 20 shows the conversion time after a filter
reset. Note that this time depends on the operation
initiating the reset. Also, the first conversion after a
filter reset has a slightly different time than the
second and subsequent conversions.
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Table 20. Data Conversion Time
FIRST DATA CONVERSION TIME AFTER FILTER RESET
SYNC COMMAND, MUX0
REGISTER WRITE
(ms) (1)
NO. OF
SYSTEM
CLOCK
CYCLES
5.019
199.264
10
10.038
20
SECOND AND SUBSEQUENT
CONVERSION TIME AFTER
FILTER RESET
(ms) (1)
NO. OF
SYSTEM
CLOCK
CYCLES
(ms)
NO. OF
SYSTEM
CLOCK
CYCLES
816188
200.260
820265
199.250
816128
99.639
408124
100.635
412201
99.625
408064
20.075
49.827
204092
50.822
208169
49.812
204032
40
40.151
24.920
102076
25.172
103106
24.906
102016
80
80.301
12.467
51068
12.719
52098
12.453
51008
160
160.602
6.241
25564
6.492
26594
6.226
25504
320
321.608
3.124
12796
3.250
13314
3.109
12736
640
643.216
1.569
6428
1.695
6946
1.554
6368
1000
1000.000
1.014
4156
1.141
4674
1.000
4096
2000
2000.000
0.514
2108
0.578
2370
0.500
2048
NOMINAL
DATA RATE
(SPS)
EXACT DATA
RATE
(SPS)
5
(1)
HARDWARE RESET, RESET
COMMAND, START PIN HIGH,
WAKEUP COMMAND, VBIAS,
MUX1, or SYS0 REGISTER
WRITE
For fOSC = 4.096MHz.
Data Format
The ADS1246/7/8 output 24 bits of data in binary
twos complement format. The least significant bit
(LSB) has a weight of (VREF/PGA)/(223 – 1). The
positive full-scale input produces an output code of
7FFFFFh and the negative full-scale input produces
an output code of 800000h. The output clips at these
codes for signals exceeding full-scale. Table 21
summarizes the ideal output codes for different input
signals.
Table 21. Ideal Output Code vs Input Signal
INPUT SIGNAL, VIN
(AINP – AINN)
IDEAL OUTPUT CODE
≥ +VREF/PGA
7FFFFFh
(+VREF/PGA)/(223 – 1)
000001h
0
000000h
23
(–VREF/PGA)/(2
– 1)
≤ –(VREF/PGA) × (223/223 – 1)
FFFFFFh
800000h
1. Excludes effects of noise, linearity, offset, and
gain errors.
Digital Interface
The ADS1246/7/8 provide a standard SPI serial
communication interface plus a data ready signal
(DRDY). Communication is full-duplex with the
exception of a few limitations in regards to the RREG
command and the RDATA command. These
limitations are explained in detail in the SPI
Commands section of this data sheet. For the basic
serial interface timing characteristics, see Figure 1
and Figure 2 of this datasheet.
CS
The chip select pin (active low). The CS pin activates
SPI communication. CS must be low before data
transactions and must stay low for the entire SPI
communication period. When CS is high, the
DOUT/DRDY pin enters a high-impedance state.
Therefore, reading and writing to the serial interface
are ignored and the serial interface is reset. DRDY
pin operation is independent of CS.
Taking CS high deactivates only the SPI
communication with the device. Data conversion
continues and the DRDY signal can be monitored to
check if a new conversion result is ready. A master
device monitoring the DRDY signal can select the
appropriate slave device by pulling the CS pin low.
SCLK
The serial clock signal. SCLK provides the clock for
serial communication. It is a Schmitt-trigger input, but
it is highly recommended that SCLK be kept as clean
as possible to prevent glitches from inadvertently
shifting the data. Data are shifted into DIN on the
falling edge of SCLK and shifted out of DOUT on the
rising edge of SCLK.
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ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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DIN
The data input pin. DIN is used along with SCLK to
send data to the device. Data on DIN are shifted into
the device on the falling edge of SCLK.
The communication of this device is full-duplex in
nature. The device monitors commands shifted in
even when data are being shifted out. Data that are
present in the output shift register are shifted out
when sending in a command. Therefore, it is
important to make sure that whatever is being sent on
the DIN pin is valid when shifting out data. When no
command is to be sent to the device when reading
out data, the NOP command should be sent on DIN.
DRDY
The data ready pin. The DRDY pin goes low to
indicate a new conversion is complete, and the
conversion result is stored in the conversion result
buffer. The SPI clock must be low in a short time
frame around the DRDY low transition (see Figure 2)
so that the conversion result is loaded into both the
result buffer and the output shift register. Therefore,
no commands should be issued during this time
frame if the conversion result is to be read out later.
This constraint applies only when CS is asserted.
When CS is not asserted, SPI communication with
other devices on the SPI bus does not affect loading
of the conversion result. After the DRDY pin goes
low, it is forced high on the first falling edge of SCLK
(so that the DRDY pin can be polled for '0' instead of
waiting for a falling edge). If the DRDY pin is not
taken high after it falls low, a short high pulse is
created on it to indicate the next data are ready.
When the DRDY MODE bit is set to '0', this pin
functions as DOUT only. Data are clocked out at
rising edge of SCLK, MSB first (see Figure 66).
When the DRDY MODE bit is set to '1', this pin
functions as both DOUT and DRDY. Data are shifted
out from this pin, MSB first, at the rising edge of
SCLK. This combined pin allows for the same control
but with fewer pins.
When the DRDY MODE bit is enabled and a new
conversion is complete, DOUT/DRDY goes low if it is
high. If it is already low, then DOUT/DRDY goes high
and then goes low (see Figure 67). Similar to the
DRDY pin, a falling edge on the DOUT/DRDY pin
signals that a new conversion result is ready. After
DOUT/DRDY goes low, the data can be clocked out
by providing 24 SCLKs. In order to force
DOUT/DRDY high (so that DOUT/DRDY can be
polled for a '0' instead of waiting for a falling edge), a
no operation command (NOP) or any other command
that does not load the data output register can be
sent after reading out the data. Because SCLKs can
only be sent in multiples of eight, a NOP can be sent
to force DOUT/DRDY high if no other command is
pending. The DOUT/DRDY pin goes high after the
first rising edge of SCLK after reading the conversion
result completely (see Figure 68). The same condition
also applies after an RREG command. After all the
register bits have been read out, the rising edge of
SCLK forces DOUT/DRDY high. Figure 69 illustrates
an example where sending four NOP commands after
an RREG command forces the DOUT/DRDY pin
high.
DOUT/DRDY
This pin has two modes: data out (DOUT) only, or
data out (DOUT) combined with data ready (DRDY).
The DRDY MODE bit determines the function of this
pin. In either mode, the DOUT/DRDY pin goes to a
high-impedance state when CS is taken high.
SCLK
DOUT/DRDY(1)
1
2
D[23]
D[22]
3
D[21]
22
D[2]
23
D[1]
24
1
2
8
D[0]
DRDY
(1) CS tied low.
Figure 66. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
SCLK
DOUT/DRDY(1)
1
2
3
22
D[23]
D[22]
D[21]
D[2]
23
D[1]
24
D[0]
1
2
D[23]
D[22]
NOP
DIN
24
D[0]
NOP
DRDY
(1)
CS tied low.
Figure 67. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)
SCLK
DOUT/DRDY(1)
DIN
1
2
3
22
D[23]
D[22]
D[21]
D[2]
23
D[1]
24
1
2
8
D[0]
NOP
1
2
D[23]
D[22]
NOP
24
D[0]
NOP
DRDY
(1)
DRDY MODE bit enabled, CS tied low.
Figure 68. DOUT/DRDY Forced High After Retrieving the Conversion Result
1
2
7
8
1
2
7
8
SCLK
DOUT/DRDY(1)
reg[7]
DIN
(1)
reg[1] reg[0]
NOP
NOP
DRDY MODE bit enabled, CS tied low.
Figure 69. DOUT/DRDY Forced High After Reading Register Data
The DRDY MODE bit modifies only the DOUT/DRDY
pin functionality. The DRDY pin functionality remains
unaffected.
SPI Reset
SPI communication can be reset in several ways. In
order to reset the SPI interface (without resetting the
registers or the digital filter), the CS pin can be pulled
high. Taking the RESET pin low causes the SPI
interface to be reset along with all the other digital
functions. In this case, the registers and the
conversion are reset.
SPI Communication During Sleep Mode
When the START pin is low or the device is in sleep
mode, only the RDATA, RDATAC, SDATAC,
WAKEUP, and NOP commands can be issued. The
RDATA command can be used to repeatedly read the
last conversion result during sleep mode. Other
commands do not function because the internal clock
is shut down to save power during sleep mode.
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ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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REGISTER DESCRIPTIONS
ADS1246 REGISTER MAP
Table 22. ADS1246 Register Map
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
00h
BCS
BCS1
BCS0
0
0
0
0
0
1
01h
VBIAS
0
0
0
0
0
0
VBIAS1
VBIAS0
02h
MUX1
CLKSTAT
0
0
0
0
MUXCAL2
MUXCAL1
MUXCAL0
03h
SYS0
0
PGA2
PGA1
PGA0
DR3
DR2
DR1
DR0
04h
OFC0
OFC7
OFC6
OFC5
OFC4
OFC3
OFC2
OFC1
OFC0
05h
OFC1
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC9
OFC8
06h
OFC2
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
07h
FSC0
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
08h
FSC1
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
09h
FSC2
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
ID0
DRDY
MODE
0
0
0
0Ah
ID
ID3
ID2
ID1
BIT 0
ADS1246 DETAILED REGISTER DEFINITIONS
BCS—Burnout Current Source Register. These bits control the settling of the sensor burnout detect current
source.
BCS - ADDRESS 00h
RESET VALUE = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BCS1
BCS0
0
0
0
0
0
1
Bits 7:6
BCS1:0
These bits select the magnitude of the sensor burnout detect current source.
00 = Burnout current source off (default)
01 = Burnout current source on, 0.5mA
10 = Burnout current source on, 2mA
11 = Burnout current source on, 10mA
Bits 5:0
These bits must always be set to '000001'.
38
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ADS1246 DETAILED REGISTER DEFINITIONS (continued)
VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs.
VBIAS - ADDRESS 01h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
VBIAS1
VBIAS0
Bits 7:2
These bits must always be set to '000000'.
Bits 1:0
VBIAS1:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0
is for AIN0, and bit 1 is for AIN1.
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied to the analog input
MUX—Multiplexer Control Register.
MUX - ADDRESS 02h
RESET VALUE = x0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CLKSTAT
0
0
0
0
MUXCAL2
MUXCAL1
MUXCAL0
Bit 7
CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:3
These bits must always be set to '0000'.
Bits 2:0
MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from the VBIAS register.
000 = Normal operation (default)
001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally
connected to midsupply (AVDD + AVSS)/2.
010 = Gain calibration. The analog inputs are connected to the voltage reference.
011 = Temperature measurement. The inputs are connected to a diode circuit that produces a
voltage proportional to the ambient temperature of the device..
Table 23 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to
the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.
Table 23. MUXCAL Settings
MUXCAL[2:0]
PGA GAIN SETTING
ADC INPUT
000
Set by SYS0 register
Normal operation
001
Set by SYS0 register
Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2
010
Forced to 1
Gain calibration: VREFP – VREFN (full-scale)
011
Forced to 1
Temperature measurement diode
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ADS1246
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ADS1248
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ADS1246 DETAILED REGISTER DEFINITIONS (continued)
SYS0—System Control Register 0.
SYS0 - ADDRESS 03h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
PGA2
PGA1
PGA0
DOR3
DOR2
DOR1
DOR0
Bit 7
These bits must always be set to '0'.
Bits 6:4
PGA2:0
These bits determine the gain of the PGA.
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
Bits 3:0
DOR3:0
These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the
highest data rate of 2kSPS.
0000 = 5SPS (default)
0001 = 10SPS
0010 = 20SPS
0011 = 40SPS
0100 = 80SPS
0101 = 160SPS
0110 = 320SPS
0111 = 640SPS
1000 = 1000SPS
1001 to 1111 = 2000SPS
OFC23:0
These bits make up the offset calibration coefficient register of the ADS1248.
OFC0—Offset Calibration Coefficient Register 0
OFC0 - ADDRESS 04h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC7
OFC6
OFC5
OFC4
OFC3
OFC2
OFC1
OFC0
OFC1—Offset Calibration Coefficient Register 1
OFC1 - ADDRESS 05h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC9
OFC8
OFC2—Offset Calibration Coefficient Register 2
OFC2 - ADDRESS 06h
40
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
ADS1246 DETAILED REGISTER DEFINITIONS (continued)
FSC23:0
These bits make up the full-scale calibration coefficient register.
FSC0—Full-Scale Calibration Coefficient Register 0
RESET VALUE IS PGA DEPENDENT (1)
FSC0 - ADDRESS 07h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC1—Full-Scale Calibration Coefficient Register 1
RESET VALUE IS PGA DEPENDENT (1)
FSC1 - ADDRESS 08h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC2—Full-Scale Calibration Coefficient Register 2
RESET VALUE IS PGA DEPENDENT (1)
FSC2 - ADDRESS 09h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
ID—ID Register
IDAC0 - ADDRESS 0Ah
RESET VALUE = x0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ID3
ID2
ID1
ID0
DRDY MODE
0
0
0
Bits 7:4
ID3:0
Read-only, factory-programmed bits; used for revision identification.
Bit 3
DRDY MODE
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY
pin continues to indicate data ready, active low.
0 = DOUT/DRDY pin functions only as Data Out (default)
1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low
Bits 2:0
These bits must always be set to '000'.
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ADS1246
ADS1247
ADS1248
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
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ADS1247 AND ADS1248 REGISTER MAP
Table 24. ADS1247 and ADS1248 Register Map
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
MUX0
BCS1
BCS0
MUX_SP2
MUX_SP1
MUX_SP0
MUX_SN2
MUX_SN1
MUX_SN0
01h
VBIAS
VBIAS7
VBIAS6
VBIAS5
02h
MUX1
CLKSTAT
42
VREFCON1 VREFCON0
VBIAS4
VBIAS3
VBIAS2
VBIAS1
VBIAS0
REFSELT1
REFSELT0
MUXCAL2
MUXCAL1
MUXCAL0
03h
SYS0
0
PGA2
PGA1
PGA0
DR3
DR2
DR1
DR0
04h
OFC0
OFC7
OFC6
OFC5
OFC4
OFC3
OFC2
OFC1
OFC0
05h
OFC1
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC9
OFC8
06h
OFC2
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
07h
FSC0
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
08h
FSC1
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
09h
FSC2
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
0Ah
IDAC0
ID3
ID2
ID1
ID0
DRDY
MODE
IMAG2
IMAG1
IMAG0
0Bh
IDAC1
I1DIR3
I1DIR2
I1DIR1
I1DIR0
I2DIR3
I2DIR2
I2DIR1
I2DIR0
0Ch
GPIOCFG
IOCFG7
IOCFG6
IOCFG5
IOCFG4
IOCFG3
IOCFG2
IOCFG1
IOCFG0
0Dh
GPIODIR
IODIR7
IODIR6
IODIR5
IODIR4
IODIR3
IODIR2
IODIR1
IODIR0
0Eh
GPIODAT
IODAT7
IODAT6
IODAT5
IODAT4
IODAT3
IODAT2
IODAT1
IODAT0
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SBAS426D – AUGUST 2008 – REVISED MARCH 2010
ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS
MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected
on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.
MUX0 - ADDRESS 00h
RESET VALUE = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BCS1
BCS0
MUX_SP2
MUX_SP1
MUX_SP0
MUX_SN2
MUX_SN1
MUX_SN0
Bits 7:6
BCS1:0
These bits select the magnitude of the sensor detect current source.
00 = Burnout current source off (default)
01 = Burnout current source on, 0.5mA
10 = Burnout current source on, 2mA
11 = Burnout current source on, 10mA
Bits 5:3
MUX_SP2:0
Positive input channel selection bits.
000 = AIN0 (default)
001 = AIN1
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
Bits 2:0
MUX_SN2:0
Negative input channel selection bits.
000 = AIN0
001 = AIN1 (default)
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
VBIAS—Bias Voltage Register
VBIAS - ADDRESS 01h
RESET VALUE = 00h
DEVICE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADS1248
VBIAS7
VBIAS6
VBIAS5
VBIAS4
VBIAS3
VBIAS2
VBIAS1
VBIAS0
ADS1247
0
0
0
0
VBIAS3
VBIAS2
VBIAS1
VBIAS0
Bits 7:0
VBIAS7:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input.
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).
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ADS1247
ADS1248
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
MUX1—Multiplexer Control Register 1
MUX1 - ADDRESS 02h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CLKSTAT
VREFCON1
VREFCON0
REFSELT1
REFSELT0
MUXCAL2
MUXCAL1
MUXCAL0
Bit 7
CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:5
VREFCON1:0
These bits control the internal voltage reference. These bits allow the reference to be turned on or
off completely, or allow the reference state to follow the state of the device. Note that the internal
reference is required for operation of the IDAC functions.
00 = Internal reference is always off (default)
01 = Internal reference is always on
10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the
device receives a shutdown opcode or the START pin is taken low
Bits 4:3
REFSELT1:0
These bits select the reference input for the ADC.
00 = REF0 input pair selected (default)
01 = REF1 input pair selected (ADS1248 only)
10 = Onboard reference selected
11 = Onboard reference selected and internally connected to REF0 input pair
Bits 2:0
MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).
000 = Normal operation (default)
001 = Offset measurement
010 = Gain measurement
011 = Temperature diode
100 = External REF1 measurement (ADS1248 only)
101 = External REF0 measurement
110 = AVDD measurement
111 = DVDD measurement
Table 25 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting
reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset
measurement.
Table 25. MUXCAL Settings
44
MUXCAL[2:0]
PGA GAIN SETTING
ADC INPUT
000
Set by SYS0 register
Normal operation
001
Set by SYS0 register
Inputs shorted to midsupply (AVDD + AVSS)/2
010
Forced to 1
VREFP – VREFN (full-scale)
011
Forced to 1
Temperature measurement diode
100
Forced to 1
(VREFP1 – VREFN1)/4
101
Forced to 1
(VREFP0 – VREFN0)/4
110
Forced to 1
(AVDD – AVSS)/4
111
Forced to 1
(DVDD – DVSS)/4
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
SYS0—System Control Register 0
SYS0 - ADDRESS 03h
RESET VALUE = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
PGA2
PGA1
PGA0
DOR3
DOR2
DOR1
DOR0
Bit 7
This bit must always be set to '0'
Bits 6:4
PGA2:0
These bits determine the gain of the PGA.
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
Bits 3:0
DOR3:0
These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the
highest data rate of 2000SPS.
0000 = 5SPS (default)
0001 = 10SPS
0010 = 20SPS
0011 = 40SPS
0100 = 80SPS
0101 = 160SPS
0110 = 320SPS
0111 = 640SPS
1000 = 1000SPS
1001 to 1111 = 2000SPS
OFC23:0
These bits make up the offset calibration coefficient register of the ADS1248.
OFC0—Offset Calibration Coefficient Register 0
OFC0 - ADDRESS 04h
RESET VALUE = 000000h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC7
OFC6
OFC5
OFC4
OFC3
OFC2
OFC1
OFC0
OFC1—Offset Calibration Coefficient Register 1
OFC1 - ADDRESS 05h
RESET VALUE = 000000h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC9
OFC8
OFC2—Offset Calibration Coefficient Register 2
OFC2 - ADDRESS 06h
RESET VALUE = 000000h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
FSC23:0
These bits make up the full-scale calibration coefficient register.
FSC0—Full-Scale Calibration Coefficient Register 0
RESET VALUE IS PGA DEPENDENT (1)
FSC0 - ADDRESS 07h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC1—Full-Scale Calibration Coefficient Register 1
RESET VALUE IS PGA DEPENDENT (1)
FSC1 - ADDRESS 08h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC2—Full-Scale Calibration Coefficient Register 2
RESET VALUE IS PGA DEPENDENT (1)
FSC2 - ADDRESS 09h
(1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
IDAC0—IDAC Control Register 0
IDAC0 - ADDRESS 0Ah
RESET VALUE = x0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ID3
ID2
ID1
ID0
DRDY MODE
IMAG2
IMAG1
IMAG0
Bits 7:4
ID3:0
Read-only, factory-programmed bits; used for revision identification.
Bit 3
DRDY MODE
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY
pin continues to indicate data ready, active low.
0 = DOUT/DRDY pin functions only as Data Out (default)
1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low
Bits 2:0
IMAG2:0
The ADS1247/8 have two programmable current source DACs that can be used for sensor
excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the
internal reference to be on.
000 = off (default)
001 = 50mA
010 = 100mA
011 = 250mA
100 = 500mA
101 = 750mA
110 = 1000mA
111 = 1500mA
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
IDAC1—IDAC Control Register 1
IDAC1 - ADDRESS 0Bh
RESET VALUE = FFh
DEVICE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADS1248
I1DIR3
I1DIR2
I1DIR1
I1DIR0
I2DIR3
I2DIR2
I2DIR1
I2DIR0
ADS1247
0
0
I1DIR1
I1DIR0
0
0
I2DIR1
I2DIR0
The two IDACs on the ADS1247/8 can be routed to either the IEXC1 and IEXC2 output pins or directly to the
analog inputs.
Bits 7:4
I1DIR3:0
These bits select the output pin for the first current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
Bits 3:0
I2DIR3:0
These bits select the output pin for the second current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
GPIOCFG—GPIO Configuration Register. The GPIO and analog pins are shared as follows:
GPIO0 shared with REFP0
GPIO1 shared with REFN0
GPIO2 shared with AIN2
GPIO3 shared with AIN3
GPIO4 shared with AIN4 (ADS1248)
GPIO5 shared with AIN5 (ADS1248)
GPIO6 shared with AIN6 (ADS1248)
GPIO7 shared with AIN7 (ADS1248)
GPIOCFG - ADDRESS 0Ch
RESET VALUE = 00h
DEVICE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADS1248
IOCFG7
IOCFG6
IOCFG5
IOCFG4
IOCFG3
IOCFG2
IOCFG1
IOCFG0
ADS1247
0
0
0
0
IOCFG3
IOCFG2
IOCFG1
IOCFG0
Bits 7:0
IOCFG7:0
These bits enable the GPIO because the GPIO pins are shared with the analog pins. Note that the
ADS1248 uses all the IOCFG bits, whereas the ADS1247 uses only bits 3:0.
0 = The pin is used as an analog input (default)
1 = The pin is used as a GPIO pin
GPIODIR—GPIO Direction Register
GPIODIR - ADDRESS 0Dh
RESET VALUE = 00h
DEVICE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADS1248
IODIR7
IODIR6
IODIR5
IODIR4
IODIR3
IODIR2
IODIR1
IODIR0
ADS1247
0
0
0
0
IODIR3
IODIR2
IODIR1
IODIR0
Bits 7:0
IODIR7:0
These bits control the direction of the GPIO when enabled by the IOCFG bits. Note that the
ADS1248 uses all the IODIR bits, whereas the ADS1247 uses only bits 3:0.
0 = The GPIO is an output (default)
1 = The GPIO is an input
GPIODAT—GPIO Data Register
GPIODAT - ADDRESS 0Eh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADS1248
IODAT7
IODAT6
IODAT5
IODAT4
IODAT3
IODAT2
IODAT1
IODAT0
ADS1247
0
0
0
0
IODAT3
IODAT2
IODAT1
IODAT0
Bits 7:0
48
RESET VALUE = 00h
DEVICE
IODAT7:0
If a GPIO pin is enabled in the GPIOCFG register and configured as an output in the GPIO
Direction register (GPIODIR), the value written to this register appears on the appropriate GPIO
pin. If a GPIO pin is configured as an input in GPIODIR, reading this register returns the value of
the digital I/O pins. Note that the ADS1248 uses all eight IODAT bits, while the ADS1247 uses only
bits 3:0.
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SPI COMMANDS
SPI COMMAND DEFINITIONS
The commands shown in Table 26 control the operation of the ADS1246/7/8. Some of the commands are
stand-alone commands (for example, RESET), whereas others require additional bytes (for example, WREG
requires command, count, and the data bytes).
Operands:
n = number of registers to be read or written (number of bytes – 1)
r = register (0 to 15)
x = don't care
Table 26. SPI Commands
COMMAND TYPE
System Control
Data Read
Read Register
Write Register
Calibration
COMMAND
DESCRIPTION
1st COMMAND BYTE
WAKEUP
Exit sleep mode
0000 000x (00h, 01h)
SLEEP
Enter sleep mode
0000 001x (02h, 03h)
SYNC
Synchronize the A/D conversion
0000 010x (04h, 05h)
RESET
Reset to power-up values
0000 011x (06h, 07h)
NOP
No operation
1111 1111 (FFh)
2nd COMMAND BYTE
0000-010x (04,05h)
RDATA
Read data once
0001 001x (12h, 13h)
RDATAC
Read data continuously
0001 010x (14h, 15h)
SDATAC
Stop reading data continuously
0001 011x (16h, 17h)
RREG
Read from register rrrr
0010 rrrr (2xh)
0000_nnnn
0000_nnnn
WREG
Write to register rrrr
0100 rrrr (4xh)
SYSOCAL
System offset calibration
0110 0000 (60h)
SYSGCAL
System gain calibration
0110 0001 (61h)
SELFOCAL
Self offset calibration
0110 0010 (62h)
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SYSTEM CONTROL COMMANDS
WAKEUP—Wake up from sleep mode that is set by the SLEEP command.
Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the
device wakes up on the rising edge of the eighth SCLK.
SLEEP—Set the device to sleep mode; can only be awakened by the WAKEUP command.
This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the
device completes the current conversion and then goes into sleep mode. Note that this command does not
automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for
each device for further details.
To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a
WAKEUP command followed by a SLEEP command.
Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.
DIN
SLEEP
WAKEUP
0000 001X
0000 000X
SCLK
Eighth SCLK
DRDY
Status
Normal Mode
Sleep Mode
Normal Mode
Finish Current Conversion
Start New Conversion
Figure 70. SLEEP and WAKEUP Commands Operation
SYNC—Synchronize DRDY.
This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices
connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices
simultaneously.
SYNC
DIN
0000 010X
0000 010X
SCLK
2 tOSC
Synchronization
Occurs Here
Figure 71. SYNC Command Operation
RESET—Reset the device to power-up state.
This command restores the registers to the respective power-up values. This command also resets the digital
filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET
command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the
wrong state, the device does not reset. The CS pin can be used to reset SPI interface first, and then a
RESET command can be issued to reset the device. The RESET command holds the registers and the
decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the
hardware reset. Therefore, SPI communication can be only be started 0.6ms after the RESET command is
issued, as shown in Figure 72.
Any SPI
Command
DIN
RESET
1
8
SCLK
0.6ms
Figure 72. SPI Communication After an SPI Reset
50
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DATA RETRIEVAL COMMANDS
RDATAC—Read data continuously.
The RDATAC command enables the automatic loading of a new conversion result into the output data
register. In this mode, the conversion result can be received once from the device after the DRDY signal
goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits
read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the
command takes effect on the next DRDY.
Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the
resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of
when the next DRDY falling edge occurs.
DRDY
RDATAC
DIN
NOP
0001 010X
24 Bits
DOUT
SCLK
1
8
1
24
Figure 73. Read Data Continuously
SDATAC—Stop reading data continuously.
The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not
automatically loaded into the output shift register when DRDY goes low, and register read operations can be
performed without interruption from new conversion results being loaded into the output shift register. Use
the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.
DRDY
SDATAC
DIN
0001 011X
Figure 74. Stop Reading Data Continuously
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RDATA—Read data once.
The RDATA command loads the most recent conversion result into the output register. After issuing this
command, the conversion result can be read out by sending 24 SCLKs, as shown in Figure 75. This
command also works in RDATAC mode.
When performing multiple reads of the conversion result, the RDATA command can be sent when the last
eight bits of the conversion result are being shifted out during the course of the first read operation by taking
advantage of the duplex communication nature of the SPI interface, as shown in Figure 76.
DRDY
RDATA
0001 001X
DIN
DOUT
NOP
NOP
NOP
MSB
Mid-Byte
LSB
SCLK
1
8
1
24
Figure 75. Read Data Once
1
2
7
8
9
10
23
24
1
2
23
24
SCLK
DOUT
D[23] D[22]
NOP
DIN
D[17] D[16] D[15] D[14]
NOP
NOP
D[1]
D[0]
RDATA
D[23] D[22]
NOP
D[1]
D[0]
NOP
DRDY
Figure 76. Using RDATA in Full-Duplex Mode
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USER REGISTER READ AND WRITE COMMANDS
RREG—Read from registers.
This command outputs the data from up to 16 registers, starting with the register address specified as part of
the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining
registers, the addresses wrap back to the beginning.
First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.
It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For
example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in
Figure 77. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send
NOP through the DIN when reading out the register data.
1st
2nd
Command Command
Byte
Byte
DIN
0010 0001 0000 0001
DOUT
VBIAS
MUX1
Data Byte
Data Byte
Figure 77. Read from Register
WREG—Write to registers.
This command writes to the registers, starting with the register specified as part of the instruction. The
number of registers that are written is one plus the value of the second byte.
First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.
Data Byte(s): data to be written to the registers.
DIN
0100 0010 0000 0001
MUX2
SYS0
1st
2nd
Command Command
Data
Byte
Data
Byte
Figure 78. Write to Register
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CALIBRATION COMMANDS
The ADS1246/7/8 provide system and offset calibration commands and a system gain calibration command.
SYSOCAL—Offset system calibration.
This command initiates a system offset calibration. For a system offset calibration, the input should be
externally set to zero. The OFC register is updated when this operation completes.
SYSGCAL—System gain calibration.
This command initiates the system gain calibration. For a system gain calibration, the input should be set to
full-scale. The FSC register is updated after this operation.
SELFOCAL—Self offset calibration.
This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the
calibration. The OFC register is updated after this operation.
Calibration
Starts
Calibration
Complete
tCAL
DRDY
Calibration
Command
DIN
SCLK
1
8
Figure 79. Calibration Command
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APPLICATION INFORMATION
SPI COMMUNICATION EXAMPLES
negative terminal of both sensors (that is, channels
AIN1 and AIN3). All these settings can be changed
by performing a block write operation on the first four
registers of the device. After the DRDY pin goes low,
the conversion result can be immediately retrieved by
sending in 16 SPI clock pulses because the device
defaults to RDATAC mode. As the conversion result
is being retrieved, the active input channels can be
switched to AIN2 and AIN3 by writing into the MUX0
register in a full-duplex manner, as shown in
Figure 80. The write operation is completed with an
additional eight SPI clock pulses. The time from the
write operation into the MUX0 register to the next
DRDY low transition is shown in Figure 80 and is
0.513ms in this case. After DRDY goes low, the
conversion result can be retrieved and the active
channel can be switched as before.
This section contains several examples of SPI
communication with the ADS1246/7/8, including the
power-up sequence.
Channel Multiplexing Example
This first example applies only to the ADS1247 and
ADS1248. It explains a method to use the device with
two sensors connected to two different analog
channels. Figure 80 shows the sequence of SPI
operations performed on the device. After power-up,
216 system clocks are required before communication
may be started. During the first 216 system clock
cycles, the devices are internally held in a reset state.
In this example, one of the sensors is connected to
channels AIN0 and AIN1 and the other sensor is
connected to channels AIN2 and AIN3. The ADC is
operated at a data rate of 2kSPS. The PGA gain is
set to 32 for both sensors. VBIAS is connected to the
Power-up sequence
16ms
ADC initial setup
Multiplexer change is channel 2
Data Retrieval for
Channel 2 Conversion
(1)
DVDD
START
RESET
CS
WREG
DIN
WREG
3 00 01 02 03
NOP
00 00
SCLK
Conversion result
for channel 2
Conversion result
for channel 1
DOUT
DRDY
tDRDY
Initial setting:
AIN0 is the positive channel,
AIN1 is the negative channel,
internal reference selected,
PGA gain = 32,
data rate = 2kSPS,
VBIAS is connected to the
negative pins AIN1 and AIN3.
0.513ms
for
MUX0
Write
AIN2 is the positive channel,
AIN3 is the negative channel.
(1) For fOSC = 4.096MHz.
Figure 80. SPI Communication Sequence for Channel Multiplexing
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Sleep Mode Example
This second example deals with performing one
conversion after power-up and then entering into the
power-saving sleep mode. In this example, a sensor
is connected to input channels AIN0 and AIN1.
Commands to set up the devices must occur at least
216 system clock cycles after powering up the
devices. The ADC operates at a data rate of 2kSPS.
The PGA gain is set to 32 for both sensors. VBIAS is
connected to the negative terminal of both the
sensors (that is, channel AIN1). All these settings can
Power-up sequence
16ms
be changed by performing a block write operation on
the first four registers of the device. After performing
the block write operation, the START pin can be
taken low. The device enters the power-saving sleep
mode as soon as DRDY goes low 0.575ms after
writing into the SYS0 register. The conversion result
can be retrieved even after the device enters sleep
mode by sending 16 SPI clock pulses.
ADC initial setup
(1)
ADC is put to sleep
after a single conversion.
Data are retrieved when
ADC is sleeping.
DVDD
START
RESET
CS
WREG
DIN
NOP
00 01 02 03
SCLK
Conversion result
for channel 1
DOUT
DRDY
Initial setting:
AIN0 is the positive channel,
AIN1 is the negative channel,
internal reference selected,
PGA gain = 32,
data rate = 2kSPS,
VBIAS is connected to the
negative pins, AIN1 and AIN3.
tDRDY
(0.575ms)
ADC enters
power-saving
sleep mode
(1) For fOSC = 4.096MHz.
Figure 81. SPI Communication Sequence for Entering Sleep Mode After a Conversion
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Hardware-Compensated, Three-Wire RTD
Measurement Example
be equal to the resistance of the PT-100 sensor at
+25°C (approximately 110Ω). The IDAC current is set
to 1.5mA. This setting results in a differential input
swing of ±14.7mV at the inputs of the ADC. The PGA
gain is set to 128. The full-scale input for the ADC is
±19.53mV. Fixing RBIAS at 833Ω fixes the reference at
2.5V and the input common-mode at approximately
2.7V, ensuring that the voltage at AIN0 is far away
from the IDAC compliance voltage.
Figure 82 is an application circuit to measure
temperatures in the range of 0°C to +50°C using a
PT-100 RTD and the ADS1247 or ADS1248 in a
three-wire, hardware-compensated topology. The two
onboard matched current DACs of the ADS1247/8
are ideally suited for implementing the three-wire
RTD topology. This circuit uses a ratiometric
approach, where the reference is derived from the
IDAC currents in order to achieve excellent noise
performance. The resistance of the PT-100 changes
from 100Ω at 0°C to 119.6Ω at +50°C. The
compensating resistor (RCOMP) has been chosen to
The maximum number of noise-free output codes for
this circuit in the 0°C to +50°C temperature range is
(2ENOB)(14.7mV)/19.53mV.
+5V
+3.3V
IN
TPS79333
0.1mF
EN
VOUT
NR
GND
AVDD
DVDD
IDAC1
1.5mA
RTD
RL(1)
15W
AIN0
RL(1)
15W
RCOMP(2)
110W AIN1
2.2mF
RESET
IDAC2
1.5mA
PGA
MSP430
or
other
Microprocessor
Modulator
Gain = 128
RL(1)
15W
VDD
SCLK
REFP0
DIN
(2)
RBIAS
833W
ADS1247/48
DOUT/DRDY
CS
REFN0
START
AVSS
(1)
RTD line resistances.
(2)
RBIAS and RCOMP should be as close to the ADC as possible.
DGND
CLK
GND
Figure 82. Three-Wire RTD Application with Hardware Compensation
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2009) to Revision D
Page
•
Updated Description section ................................................................................................................................................. 1
•
Added Analog Inputs, Full-scale input voltage maximum specification in Electrical Characteristics .................................... 4
•
Changed Analog Inputs, Absolute input current parameter of Electrical Characteristics ..................................................... 4
•
Added new footnote 1 to Electrical Characteristics .............................................................................................................. 4
•
Changed conditions of System Performance, Power-supply rejection parameter of Electricsl Characteristics ................... 4
•
Changed typical specification of Current Sources (IDACS), Initial mismatch parameter of Electrical Characteristics ........ 5
•
Changed typical specification of Current Sources (IDACS), Temperature drift parameter of Electrical Characteristics ...... 5
•
Changed Power Supply, AVDD current typical specification for 3.3V parameter in Electrical Characteristics .................... 5
•
Changed title of Table 6 ...................................................................................................................................................... 13
•
Changed title of Table 7 ...................................................................................................................................................... 14
•
Changed title of Table 9 ...................................................................................................................................................... 15
•
Updated Figure 5 ................................................................................................................................................................ 16
•
Updated Figure 6 ................................................................................................................................................................ 16
•
Added Figure 7, Noise Histogram Plot ............................................................................................................................... 16
•
Added Figure 8, Noise Histogram Plot ............................................................................................................................... 16
•
Updated Figure 9 ................................................................................................................................................................ 16
•
Added Figure 10, RMS Noise vs Input Signal .................................................................................................................... 16
•
Updated Figure 11 .............................................................................................................................................................. 17
•
Updated Figure 12 .............................................................................................................................................................. 17
•
Updated Figure 13 .............................................................................................................................................................. 17
•
Updated Figure 14 .............................................................................................................................................................. 17
•
Added Figure 15, Offset Drift vs Temperature .................................................................................................................... 17
•
Added Figure 16, Offset Drift vs Temperature .................................................................................................................... 17
•
Added Figure 17, Offset vs Temperature ........................................................................................................................... 18
•
Added Figure 18, Offset vs Temperature ........................................................................................................................... 18
•
Updated Figure 19 .............................................................................................................................................................. 18
•
Updated Figure 20 .............................................................................................................................................................. 18
•
Updated Figure 21 .............................................................................................................................................................. 18
•
Updated Figure 22 .............................................................................................................................................................. 18
•
Added Figure 23, Gain vs Temperature ............................................................................................................................. 19
•
Added Figure 24, Gain vs Temperature ............................................................................................................................. 19
•
Added Figure 25, Gain vs Temperature ............................................................................................................................. 19
•
Added Figure 26, Gain vs Temperature ............................................................................................................................. 19
•
Updated Figure 29 .............................................................................................................................................................. 20
•
Added Figure 31, Analog Current vs Temperature ............................................................................................................. 20
•
Added Figure 32, Digital Current vs Temperature .............................................................................................................. 20
•
Added Figure 42, Power-Supply Rejection vs Gain ........................................................................................................... 22
•
Added Figure 43, Internal VREF Initial Accuracy Histogram ................................................................................................ 22
•
Added Figure 44, IDAC Initial Accuracy Histogram ............................................................................................................ 22
•
Added Figure 45, IDAC Mismatch Histogram ..................................................................................................................... 22
•
Changed Table 11 .............................................................................................................................................................. 25
•
Updated Figure 55 .............................................................................................................................................................. 27
58
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426D – AUGUST 2008 – REVISED MARCH 2010
•
Updated Figure 56 .............................................................................................................................................................. 27
•
Revised VREFCOM description in Internal Voltage Reference section ............................................................................. 29
•
Changed fourth row entry of final output code column in Table 16 .................................................................................... 31
•
Added ADC Power-Up section ........................................................................................................................................... 32
•
Added Channel Cycling and Overload Recovery section ................................................................................................... 34
•
Changed first three rows of hardware reset columns in Table 20 ...................................................................................... 35
•
Revised Channel Multiplexing Example section ................................................................................................................. 55
•
Revised Sleep Mode Example section ............................................................................................................................... 56
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
Submit Documentation Feedback
59
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ADS1246IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
ADS1246IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
ADS1247IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
ADS1247IPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
ADS1248IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
ADS1248IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2010
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.6
1.6
8.0
12.0
Q1
ADS1246IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
ADS1247IPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
ADS1248IPWR
TSSOP
PW
28
2000
330.0
16.4
7.1
10.4
1.6
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1246IPWR
TSSOP
PW
16
2000
346.0
346.0
29.0
ADS1247IPWR
TSSOP
PW
20
2000
346.0
346.0
33.0
ADS1248IPWR
TSSOP
PW
28
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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