Maxim MAX116EAX 2x4-channel, simultaneous-sampling 12-bit adc Datasheet

19-1928; Rev 0; 1/01
KIT
ATION
EVALU
E
L
B
A
AVAIL
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
____________________________Features
The MAX115/MAX116 are high-speed, multichannel,
12-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 12-bit,
2µs, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference
input, and a bank of four simultaneous-sampling T/H
amplifiers that preserve the relative phase information
of the sampled inputs. The MAX115/MAX116 have two
multiplexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V. A fault condition on any channel will not damage the IC. Available input ranges are ±5V (MAX115)
and ±2.5V (MAX116).
The parallel interface’s data access and bus release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microprocessors. The MAX115/MAX116 conversion results can be
accessed without resorting to wait-states.
♦ Four Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (Eight Single-Ended
Inputs Total)
♦ 2µs Conversion Time per Channel
♦ Throughput: 390ksps (1 Channel)
218ksps (2 Channels)
152ksps (3 Channels)
116ksps (4 Channels)
♦ Input Range: ± 5V (MAX115)
± 2.5V (MAX116)
♦ Fault-Protected Input Multiplexer (±17V)
♦ Internal +2.5V or External Reference Operation
♦ Programmable On-Board Sequencer
♦ High-Speed Parallel DSP Interface
♦ Internal 10MHz Clock
________________________Applications
Multiphase Motor Control
Ordering Information
PART
Power-Grid Synchronization
TEMP. RANGE
MAX115CAX
Power-Factor Monitoring
Digital Signal Processing
MAX115EAX
MAX116CAX
Vibration and Waveform Analysis
MAX116EAX
PIN-PACKAGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
36 SSOP
36 SSOP
36 SSOP
36 SSOP
Typical Operating Circuit
Pin Configuration
TOP VIEW
CH2B 1
36 AGND
CH2A 2
35 CH3B
CH1B 3
34 CH3A
CH1A 4
33 CH4B
AVDD 5
32 CH4A
REFIN 6
MAX115
MAX116
31 AVSS
30 INT
REFOUT 7
AGND 8
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
29 CONVST
+5V
0.1µF
28 RD
D10 10
27 WR
0.1µF
D9 11
26 CS
-5V
D8 12
25 CLK
D7 13
24 A0
D6 14
23 A1
D5 15
22 D0/A2 (LSB)
D4 16
21 D1/A3
20 D2
DGND 18
19 D3
SSOP
MAX115
MAX116
AVDD
AGND
D11 (MSB) 9
DVDD 17
A0
A1
D0/A2
D1/A3
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
AVSS
REFIN
DVDD
+5V
0.1µF
0.1µF
REFOUT
DGND
4.7µF
CLK
CONVST INT
CS
RD
WR
16MHz
CONTROL INTERFACE
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX115/MAX116
________________General Description
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...........................................................-0.3V to 6V
AVSS to AGND ............................................................0.3V to -6V
DVDD to DGND ...........................................................-0.3V to 6V
AGND to DGND .......................................................-0.3V to 0.3V
CH_ _ to AGND....................................................................±17V
REFIN, REFOUT to AGND ..........................................-0.3V to 6V
Digital Inputs/Outputs to DGND ..............-0.3V to (DVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
36-Pin SSOP (derate 11.8mW/°C above +70°C) ..........941mW
Operating Temperature Ranges
MAX115_CAX/MAX116_CAX ...............................0°C to +70°C
MAX115_EAX/MAX116_EAX ............................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s)....................................300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
±1
LSB
0.6
±1
LSB
±5
±15
DC ACCURACY (Note 1)
Resolution
N
Integral Nonlinearity (Note 2)
INL
Differential Nonlinearity
DNL
All channels
MAX115
Bipolar Zero Error
MAX116
Bipolar Zero-Error Match
12
TA = +25°C
TA = TMIN to TMAX
±30
TA = +25°C
±5
TA = TMIN to TMAX
2
MAX115
180
MAX116
90
MAX115
Gain Error
MAX116
TA = +25°C
±5
TA = TMIN to TMAX
5
mV
TA = +25°C
±5
TA = TMIN to TMAX
mV
µV/°C
±15
±25
±10
mV
±18
Gain Error Match
2
Gain Error Tempco
±10
±18
Between all channels
Zero-Code Tempco
Bits
MAX115
120
MAX116
60
5
mV
µV/°C
DYNAMIC PERFORMANCE (fCLK = 16MHz, fIN = 10.06kHz) (Notes 1, 3)
Signal-to-Noise Ratio
SNR
(Note 4)
Total Harmonic Distortion
THD
(Notes 4, 5)
Spurious-Free Dynamic Range
SFDR
(Note 4)
Channel-to-Channel Isolation
2
(Note 6)
69
dB
-80
80
dB
dB
80
_______________________________________________________________________________________
dB
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range
VIN
Input Current
IIN
Input Capacitance
CIN
MAX115
±5
MAX116
±2.5
MAX115 (-5V to +5V range)
±625
MAX116 (-2.5V to +2.5V range)
±15
V
µA
16
pF
Small-Signal Bandwidth
10
MHz
Full-Power Bandwidth
TRACK/HOLD
Acquisition Time
tACQ
600
ns
1.3
MHz
Drop Rate
2
mV/ms
Aperture Delay
10
ns
Aperture Jitter
30
ps
Aperture-Delay Matching
500
ps
REFERENCE OUTPUT (Note 7)
Output Voltage
VREFOUT
TA = +25°C
2.462
2.5
2.532
V
External Load Regulation
0 < IREF < 1mA
0.5
mV/mA
REFOUT Tempco
(Note 8)
30
ppm/°C
External Capacitive Bypass
at REFIN
0.1
External Capacitive Bypass
at REFOUT
4.7
µF
22
µF
2.60
V
REFERENCE INPUT
Input Voltage Range
2.40
2.50
Input Current
±50
µA
Input Resistance (Note 9)
10
kΩ
Input Capacitance
10
pF
EXTERNAL CLOCK
External Clock Frequency
16
MHz
14.8
MHz
INTERNAL CLOCK
Internal Clock Frequency
5.6
10
DIGITAL INPUTS (CONVST, RD, WR, CS, CLK, A0–A3) (Note 1)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance
CIN
2.4
V
0.8
CONVST, RD, WR, CS, CLK
±1
A0–A3
±10
15
V
µA
pF
_______________________________________________________________________________________
3
MAX115/MAX116
ELECTRICAL CHARACTERISTICS (continued)
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V ±5%, AVSS = -5V ±5%, DVDD = +5V ±5%, VREFIN = +2.5V (external reference), AGND = DGND = 0, 4.7µF capacitor
from REFOUT to AGND, 0.1µF capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (D0–D11, INT)
Output High Voltage
VOH
IOUT = 1mA
Output Low Voltage
VOL
IOUT = -1.6mA
0.4
V
D0–D11
±10
µA
Three-State Leakage Current
4
Three-State Output
Capacitance
V
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
AVDD
4.75
5
5.25
V
Negative Supply Voltage
AVSS
-5.25
-5
-4.75
V
Digital Supply Voltage
DVDD
4.75
5
5.25
V
Positive Supply Current
IAVDD
17
25
mA
Negative Supply Current
IAVSS
-20
-15
Digital Supply Current
3
mA
6
mA
Shutdown Positive Current
1
µA
Shutdown Negative Current
-1
µA
Shutdown Digital Current
13
µA
Positive Supply Rejection
PSRR+
(Note 10)
±1
LSB
Negative Supply Rejection
PSRR-
(Note 10)
±1
LSB
Power Dissipation
(Note 11)
175
mW
TIMING CHARACTERISTICS
(See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C,
unless otherwise noted.)
PARAMETER
CONVST Pulse Width
SYMBOL
CONDITIONS
tCW
MIN
TYP
MAX
UNITS
30
ns
CS to WR Setup Time
tCWS
Guaranteed by design
0
ns
CS to WR Hold Time
tCWH
Guaranteed by design
0
ns
WR Low Pulse Width
tWR
30
ns
Address Setup Time
tAS
30
ns
Address Hold Time
tAH
0
RD to INT Delay
tID
25pF load
ns
55
ns
Delay Time Between Reads
tRD
45
ns
CS to RD Setup Time
tCRS
Guaranteed by design
0
ns
CS to RD Hold Time
tCRH
Guaranteed by design
0
ns
RD Low Pulse Width
tRD
Data-Access Time
tDA
25pF load (Note 12)
Bus-Relinquish Time
tDH
25pF load (Note 13)
4
30
5
_______________________________________________________________________________________
ns
40
ns
45
ns
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
(See Figure 4, AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0, TA = TMIN to TMAX, Typical values are at TA = +25°C,
unless otherwise noted.)
PARAMETER
Conversion Time
Conversion Rate
Startup Time
SYMBOL
tCONV
CONDITIONS
MIN
TYP
MAX
Mode 1, Channel 1
2
Mode 2, Channel 2
4
Mode 3, Channel 3
6
Mode 4, Channel 4
8
Mode 1, Channel 1
390
Mode 2, Channel 2
218
Mode 3, Channel 3
152
Mode 4, Channel 4
116
Exiting shutdown
20
UNITS
µs
ksps
ms
Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = ±5V (MAX115) or ±2.5V (MAX116).
Note 2: Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: CLK synchronized with CONVST.
Note 4: fIN = 10.06kHz, VIN = ±5V (MAX115) or ±2.5V (MAX116).
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digitized.
Note 7: AVDD = DVDD = +5V, AVSS = -5V, VIN = 0V (all channels).
Note 8: Temperature drift is defined as the change in output voltage from +25°C to TMIN or TMAX. It is calculated as
TC = [∆REFOUT/REFOUT] / ∆T.
Note 9: See Figure 2.
Note 10: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN = +2.5V (internal).
Note 11: Tested with all inputs connected to AGND. VREFIN = +2.5V (internal).
Note 12: The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit
of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 13: The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the
120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capacitance.
_______________________________________________________________________________________
5
MAX115/MAX116
TIMING CHARACTERISTICS (continued)
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1, 2
CH2B, CH2A
Channel 2 Multiplexed Inputs (single-ended)
3, 4
CH1B, CH1A
Channel 1 Multiplexed Inputs (single-ended)
5
AVDD
Analog Supply Voltage
6
REFIN
External reference input/internal reference output. Bypass with a 0.1µF capacitor to AGND.
7
REFOUT
8, 36
AGND
9–16
D11–D4
Data Bits. D11 = MSB.
17
DVDD
Digital Supply Voltage
18
DGND
Digital Ground
19, 20
D3, D2
Data Bits
21, 22
D1/A3, D0/A2
23, 24
A1, A0
25
CLK
26
CS
Chip-Select Input (active-low)
27
WR
Write Input (active-low)
28
RD
Read Input (active-low)
29
CONVST
30
INT
31
AVSS
32, 33
CH4A, CH4B
Channel 4 Multiplexed Inputs (single-ended)
34, 35
CH3A, CH3B
Channel 3 Multiplexed Inputs (single-ended)
Reference-Buffer output. Bypass with a 4.7µF capacitor to AGND.
Analog ground. Both pins must be connected to ground.
Bidirectional Data Bits/Address Bits
Address Bits
Clock Input (duty cycle must be 30% to 70%). Connect CLK to DVDD to activate internal clock.
Conversion-Start input. Rising edge initiates sampling and conversion sequence.
Interrupt output. Falling edge indicates the end of a conversion sequence.
Analog Supply Voltage
_______________Detailed Description
1.6mA
TO OUTPUT
PIN
1.6V
120pF
1.0mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
6
The MAX115/MAX116 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
12-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX115/MAX116 internal microsequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (Figure 2). The
MAX115/MAX116 can operate with either an external or
internal clock. For internal operation, connect CLK to
DVDD.
_______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
AGND
MAX115/MAX116
REFIN
REFOUT
BANDGAP REFERENCE
10kΩ
CH1A
A
CH1B
CH2A
B
A
B
MUX
T/H
2.50V
MUX
T/H
VREF
CH2B
MUX
COMP
CH3A
A
B
MUX
T/H
CH3B
12-BIT
DAC
CH4A
A
CH4B
B
MUX
SAR
T/H
VREF
A0
4x12
RAM
A1
D0/A2
AVDD
D1/A3
AGND
THREE-STATE
OUTPUT
DRIVERS
AVSS
D2
D3
D11 (MSB)
CONTROL LOGIC
10MHz
CLOCK
MAX115
MAX116
BUS INTERFACE
CLK
CONVST
INT
CS
RD
WR
DVDD
DGND
Figure 2. Functional Diagram
_______________________________________________________________________________________
7
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
HOLD
R1
BUFFER
CH_A
S1A
S2A
C HOLD
7pF
HOLD
R2
FROM MICROSEQUENCER
TRACK
TRACK
R3
C IN
S3A
MUX
R1
S1B
S2B
R2
CH_B
C IN
R3
S3B
REFOUT
DAC
MAX115
MAX116
MAX115: R1 = ∞, R2 = R3 = 5kΩ
MAX116: R1 = R2 = 5kΩ, R3 = ∞
SAR
Figure 3. Equivalent Input Circuit
The conversion timing and control sequences are
derived from either an internal clock or an external
clock, the CONVST signal, and the programmed mode.
The T/H amplifiers hold the input voltages at the
CONVST rising edge. Additional CONVST pulses are
ignored until the last conversion for the sample is complete. An on-board sequencer converts one to four
channels per CONVST pulse. In the default mode, one
T/H output (CH1A) is converted. An interrupt signal
(INT) is provided after the last conversion is complete.
Convert two to four channels by reprogramming the
MAX115/MAX116 through the bidirectional parallel
interface. Once programmed, the MAX115/MAX116
continues to convert the specified number of channels
per CONVST pulse until they are reprogrammed. The
channels are converted sequentially, beginning with
CH1. The INT signal always follows the end of the last
conversion in a conversion sequence. The ADC converts each assigned channel in 2µs and stores the
result in an internal 4 x 12-bit memory.
At the end of the last conversion, INT goes low and the
T/H amplifiers begin to track the inputs again. The data
can be accessed by applying successive pulses to the
RD pin. Successive reads access data words sequen8
tially. The memory is not random-access and data from
CH1 is always read first. After performing four consecutive reads or initiating a new conversion, the address
pointer selects CH1 again. Additional read pulses cycle
through the data words. CS can be held low during
successive reads.
Input Bandwidth
The T/H’s input tracking circuitry has a 10MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid highfrequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection
The MAX115’s input range is ±5V, and the MAX116’s
input range is ±2.5V. The input resistance for the
MAX115 is 10kΩ (typ), and the input resistance for the
MAX116 is 1MΩ (typ). An input protection structure
allows input voltages to ±17V without harming the IC.
This protection is also active in shutdown mode.
_______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
MAX115/MAX116
tCW
CONVST
tCONV
INT
tACQ
tID
tCWH
tCWS
CS
tCRS
tCRH
RD
tRD
t WR
t RD
WR
tDA
tDH
DATA
CH1
DATA IN
CH2
CH3
CH4
tAS
tAH
Figure 4. Timing Diagram
acquisition time between conversions. The analog input
appears as a 10kΩ resistor in parallel with a 16pF
capacitor for the MAX115 and as a 1MΩ resistor in parallel with a 16pF capacitor for the MAX116.
Between conversions, the buffer input is connected to
channel 1 of the selected track/hold bank. When a
channel is not selected, switches S1, S2, and S3 are
placed in hold mode to improve channel-to-channel
isolation.
CS
WR
A0
(LSB)
A1
Digital Interface
A2
A3
Figure 5. Programming a Four-Channel Conversion, Input Mux A
Track/Holds
The MAX115/MAX116 feature four simultaneous T/Hs.
Each T/H has two multiplexed inputs. A T-switch input
configuration provides excellent hold-mode isolation.
Allow 600ns acquisition time for 12-bit accuracy.
The T/H aperture delay is typically 10ns. The 500ps
aperture-delay mismatch between the T/Hs allows the
relative phase information of up to four different inputs
to be preserved. Figure 3 shows the equivalent input
circuit, illustrating the ADC’s sampling architecture.
Only one of four T/H stages with its two multiplexed
inputs (CH_A and CH_B) is shown. All switches are in
track configuration for channel A. An internal buffer
charges the hold capacitor to minimize the required
Input data (A0–A3) and output data (D0–D11) are multiplexed on a three-state bidirectional interface. This parallel I/O can easily be interfaced with a microprocessor
(µP) or DSP. CS, WR, and RD control the write and read
operations. CS is the standard chip-select signal, which
enables the controller to address the MAX115/MAX116
as an I/O port. When CS is high, it disables the WR and
RD inputs and forces the interface into a high-Z state.
Figure 4 details the interface timing.
Programming Modes
The MAX115/MAX116 have eight conversion modes
plus power-down, which are programmed through a
bidirectional parallel interface. At power-up, the devices
default to the Input Mux A/Single-Channel Conversion
mode. The user can select between two banks (mux
inputs A or mux inputs B) of four simultaneous-sampled
input channels, as illustrated in Figure 2. An internal
microsequencer can be programmed to convert one to
four channels of the selected bank per sample. For a
single-channel conversion, CH1 is digitized, and then
INT goes low to indicate completion of the conversion.
_______________________________________________________________________________________
9
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
Table 1. Modes of Operation
A3
A2
A1
A0
CONVERSION
TIME (µs)
MODE
0
0
0
0
2
Input Mux A/Single-Channel Conversion (default at power-up)
0
0
0
1
4
Input Mux A/Two-Channel Conversion
0
0
1
0
6
Input Mux A/Three-Channel Conversion
0
0
1
1
8
Input Mux A/Four-Channel Conversion
0
1
0
0
2
Input Mux B/Single-Channel Conversion
0
1
0
1
4
Input Mux B/Two-Channel Conversion
0
1
1
0
6
Input Mux B/Three-Channel Conversion
0
1
1
1
8
Input Mux B/Four-Channel Conversion
1
X
X
X
—
Power-Down
X = Don’t care
REFOUT
TO DAC
7
(2.5V)
4.7µF
AV = 1
REFIN
MAX115
MAX116
6
(2.5V)
0.1µF
10kΩ
2.5V
Figure 6. Internal Reference
For multichannel conversions, INT goes low after the last
channel has been digitized.
To input data into the MAX115/MAX116, pull CS low,
program the bidirectional pins A0–A3 (Table 1), and
pulse WR low. Data is latched into the devices on the
WR or CS rising edge. The ADC is now ready to convert.
Once programmed, the ADC continues operating in the
same mode until reprogrammed or until power is
removed. Figure 5 shows an example of programming a
four-channel conversion using Input Mux A.
10
Starting a Conversion
After programming the MAX115/MAX116 as outlined in
the Programming Modes section, pulse CONVST low to
initiate a conversion sequence. The analog inputs are
sampled at the CONVST rising edge. Do not start a
new conversion while the conversion is in progress.
Monitor the INT output. A falling edge indicates the end
of a conversion sequence.
Reading a Conversion
Digitized data from up to four channels is stored in
memory to be read out through the parallel interface.
After receiving an INT signal, the user can access up to
four conversion results by performing up to four read
operations.
With CS low, the conversion results from CH1_ are
accessed, and INT is reset high on the first RD falling
edge. On the RD rising edge, the internal address
pointer is advanced. If a single conversion is programmed, only one RD pulse is required. For multichannel conversions, up to four RD falling edges
sequentially access the data for channels 1 through 4.
For any number of channels converted, the address
pointer is reset to CH1_ after four RD pulses. The
address pointer also resets after receiving a CNVST
pulse. Do not perform a read operation during conversion; it will corrupt the conversion’s accuracy.
__________Applications Information
Clock
The MAX115/MAX116 have an internal 10MHz (typ)
clock, which is activated by connecting CLK to DVDD
(internal clock startup time is 165µs typ). The CLK input
also accepts an external clock with duty cycle between
30% and 70%.
______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
MAX115/MAX116
OUTPUT CODE
011 . . . 111
REFOUT
TO DAC
7
(2.5V)
011 . . . 110
4.7µF
000 . . . 010
000 . . . 001
AV = 1
000 . . . 000
REFIN
MAX115
MAX116
6
111 . . . 111
(2.5V)
OUT
111 . . . 110
111 . . . 101
MAX6325
10k
100 . . . 001
100 . . . 000
ZERO
- FS
2.5V
+FS - 1LSB
INPUT VOLTAGE (LSB)
MAX115: FS = 2 x VREFOUT, 1LSB = 4VREFOUT
4096
MAX116: FS = VREFOUT, 1LSB = 2VREFOUT
4096
Figure 7. External Reference
Figure 8. Bipolar Transfer Function
Internal and External Reference
The MAX115/MAX116 can be used with an internal or
external reference voltage. An external +2.5 reference
can be connected directly at REFIN. An internal buffer
with a gain of +1 provides +2.5V at REFOUT.
Internal Reference
The full-scale range with the internal reference is ±5V
for the MAX115 and ±2.5V for the MAX116. Bypass
REFIN with a 0.1µF capacitor to AGND, and bypass the
REFOUT pin with a 4.7µF (min) capacitor to AGND
(Figure 6). The maximum value to compensate the reference buffer is 22µF. Larger values are acceptable if
low-ESR capacitors are used.
External Reference
For operation over a wide temperature range, an external +2.5V reference with tighter specifications improves
accuracy. The MAX6325 is an excellent choice
to match the MAX115/MAX116 accuracy over the
commercial and extended temperature ranges with a
1ppm/°C (max) temperature drift. Connect an external
reference at REFIN as shown in Figure 7. The minimum
impedance is 7kΩ for DC currents in both normal operation and shutdown. Bypass REFOUT with a 4.7µF lowESR capacitor.
Power-On Reset
When power is first applied, the internal power-on reset
(POR) circuitry activates the MAX115/MAX116 with INT
= high, ready to convert. The default conversion mode
is Input Mux A/Single Channel Conversion. See the
Programming Modes section if other configurations are
desired.
After the power supplies have been stabilized, the reset
time is 5µs. No conversions should be performed
during this phase. At power-up, data-in memory is
undefined.
Software Power-Down
Software power-down is activated by setting bit A3 of
the control word high (Table 1). It is asserted after the
WR or CS rising edge, at which point the ADC immediately powers down to a low quiescent-current state.
IAVDD and IAVSS drop to less than 1µA (typ), and IDVDD
drops to 13µA (typ). The ADC circuitry and reference
buffer are turned off, but the digital interface and the
reference remain active for fast power-up recovery.
Wake up the MAX115/MAX116 by writing a control
word (A0–A3, Table 1). The bidirectional interface interprets a logic zero at A3 as the start signal, and powers
up in the mode selected by A0, A1, and A2. The reference buffer’s settling time and the bypass capacitor’s
value dominate the power-up delay. With the recommended 4.7µF at REFOUT, the power-up delay is typically 20ms.
Transfer Function
The MAX115/MAX116 have bipolar input ranges. Figure
8 shows the bipolar/output transfer function. Code transitions occur at successive-integer least significant bit
______________________________________________________________________________________
11
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
VCC
VCC
HC161
1/2 HC74
PRE
Q
D
Q
CLR
ENP
ENT
RD
LOAD
HC688
CLR
VCC
INT
A
B
(LSB) 0
P0
1
C
2
D
3
RCO
P1
P2
P3
P4
P5
P6
P7
EXTERNAL
CLOCK
VCC
P=Q
Q0
Q1
LATCH
CLOCK
(TO 16373 LATCH)
Q2
Q3
10kΩ
Q4
Q5
Q6
Q7
G
CH1
0
0
CH2
1
0
CH3
0
1
CH4
1
1
EXTERNAL
CLOCK
Figure 9. Output Demultiplexer Circuit
(LSB) values. Output coding is two-complement binary
with 1LSB = 2.44mV for the MAX115 and
1LSB = 1.22mV for the MAX116.
Output Demultiplexer
An output demultiplexer circuit is useful for isolating
data from one channel in a four-channel conversion
sequence. Figure 9’s circuit uses the external 16MHz
clock and the INT signal to generate four RD pulses
and a latch clock to save data from the desired channel. CS must be low during the four RD pulses. The
channel is selected with the binary coding of two
switches. A 16-bit 16373 latch simplifies layout.
12
Motor-Control Applications
Vector motor control requires monitoring of the individual phase currents. In their most basic application, the
MAX115/MAX116 simultaneously sample two currents
(CH1A and CH2A, Figure 10) and preserve the necessary relative phase information. Only two of the three
phase currents have to be digitized because the third
component can be mathematically derived with a coordinate transformation.
The circuit of Figure 10 shows a typical vector motorcontrol application using all available inputs of the
MAX115/MAX116. CH1A and CH2A are connected
to two isolated Hall-effect current sensors and are a
______________________________________________________________________________________
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
MAX115/MAX116
MAIN DC
RESOLVER/
ENCODER
AC
AC
MOTOR
MOTOR
12
CH1
MAX115
MAX116
12 BIT ADC +
MICROSEQUENCER
B
AUX
A
SIMULTANEOUS T/H
DSP
BUFFER
A
CH2
B
MAIN DC
R/E
VOLTAGE/POSITION
FEEDBACK
POWER
STAGE
CONTROLLER
CURRENT/TORQUE
FEEDBACK
EXTERNAL
SETPOINTS
A
CH3
B
A
CH4
B
TEMP
VELOCITY
FEEDBACK
µC
Figure 10. Vector Motor Control
part of the current (torque) feedback loop. The
MAX115/MAX116 digitize the currents and deliver raw
data to the following DSP and controller stages, where
the vector processing takes place. Sensorless vector
control uses a computer model for the motor and an
algorithm to split each output current into its magnetizing (stator current) and torque-producing (rotor current)
components.
If a two-to-three phase conversion is not practical,
three currents can be sampled simultaneously with the
addition of a third sensor (not shown). Optional voltage
(position) feedback can be derived by measuring two
phase voltages (CH3A, CH4A). Typically, an isolated
differential amplifier is used between the motor and the
MAX115/MAX116. Again, the third phase voltage can
be derived from the magnitude (phase voltage) and its
relative phase.
For optimum speed control and good load regulation
close to zero speed, additional velocity and position
feedback are derived from an encoder or resolver and
brought to the MAX115/MAX116 at CH4B. The addi-
tional channels can be used to evaluate slower analog
inputs, such as the main DC bus voltage (CH2B), temperature sensors (CH3B), or other analog inputs (AUX,
CH1B).
Power-Supply Bypassing
and Ground Management
For optimum system performance, use printed circuit
boards with separate analog and digital ground planes.
Wire-wrapped boards are not recommended. Connect
the two ground planes together at the low-impedance
power-supply source. For the best ground connection,
connect the DGND and AGND pins together and connect that point to the system analog ground plane to
avoid interference from other digital noise sources. If
DGND is connected to the system digital ground, digital noise may get through to the ADC’s analog portion.
The AGND pins must be connected directly to a lowimpedance ground plane. Extra impedance between
the pins and the ground plane increases crosstalk and
degrades INL.
______________________________________________________________________________________
13
Bypass AVDD and AVSS with 0.1µF ceramic capacitors
to AGND. Mount them with short leads close to the
device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Bypass
DVDD with a 0.1µF ceramic capacitor to DGND.
Chip Information
TRANSISTOR COUNT: 4116
SUBSTRATE CONNECTED TO AVSS
PROCESS: BiCMOS
________________________________________________________Package Information
SSOP.EPS
MAX115/MAX116
2x4-Channel, Simultaneous-Sampling
12-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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