AD AD8229HDZ 1 nv/hz low noise 210c instrumentation amplifier Datasheet

FEATURES
Down-hole instrumentation
Harsh environment data acquisition
Exhaust gas measurements
Vibration analysis
AD8229
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
Figure 1.
100
80
60
40
20
0
–20
–40
–60
–80
–100
–55 –35 –15
5
25
45
65
85 105 125 145 165 185 205 225
TEMPERATURE (°C)
09412-016
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
VOSI (µV)
Designed and guaranteed for 210°C operation
Low noise
1 nV/√Hz input noise
45 nV/√Hz output noise
High CMRR
126 dB CMRR (minimum), G = 100
80 dB CMRR (minimum) to 5 kHz, G = 1
Excellent ac specifications
15 MHz bandwidth (G = 1)
1.2 MHz bandwidth (G = 100)
22 V/μs slew rate
THD: −130 dBc (1 kHz, G = 1)
Versatile
±4 V to ±17 V dual supply
Gain set with single resistor (G = 1 to 1000)
Specified temperature range
−40°C to +210°C, SBDIP package
−40°C to +175°C, SOIC package
09412-001
Data Sheet
1 nV/√Hz Low Noise
210°C Instrumentation Amplifier
AD8229
Figure 2. Typical Input Offset vs. Temperature (G = 100)
GENERAL DESCRIPTION
The AD8229 is an ultralow noise instrumentation amplifier
designed for measuring small signals in the presence of large
common-mode voltages and high temperatures.
The AD8229 has been designed for high temperature operation.
The process is dielectrically isolated to avoid leakage currents at
high temperatures. The design architecture was chosen to
compensate for the low VBE voltages at high temperatures.
The AD8229 excels at measuring tiny signals. It delivers industry
leading 1 nV/√Hz input noise performance. The high CMRR of
the AD8229 prevents unwanted signals from corrupting the
acquisition. The CMRR increases as the gain increases, offering
high rejection when it is most needed.
bandwidth at high gain, for example, 1.2 MHz at G = 100. The
design includes circuitry to improve settling time after large
input voltage transients. The AD8229 was designed for excellent
distortion performance, allowing use in demanding applications
such as vibration analysis.
Gain is set from 1 to 1000 with a single resistor. A reference pin
allows the user to offset the output voltage. This feature can be
useful when interfacing with analog-to-digital converters.
For the most demanding applications, the AD8229 is available
in an 8-lead side-brazed ceramic dual in-line package (SBDIP).
For space-constrained applications, the AD8229 is available in
an 8-lead plastic standard small outline package (SOIC).
The AD8229 is one of the fastest instrumentation amplifiers
available. Its current feedback architecture provides high
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD8229
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Applications ....................................................................................... 1
Architecture ................................................................................ 17
Functional Block Diagram .............................................................. 1
Gain Selection ............................................................................. 17
General Description ......................................................................... 1
Reference Terminal .................................................................... 17
Revision History ............................................................................... 2
Input Voltage Range ................................................................... 18
Specifications..................................................................................... 3
Layout .......................................................................................... 18
Absolute Maximum Ratings ............................................................ 6
Input Bias Current Return Path ............................................... 19
Predicted Lifetime vs. Operating Temperature ........................ 6
Input Protection ......................................................................... 19
Thermal Resistance ...................................................................... 6
Radio Frequency Interference (RFI) ........................................ 19
ESD Caution .................................................................................. 6
Calculating the Noise of the Input Stage ................................. 20
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 21
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 21
REVISION HISTORY
2/12—Rev. A to Rev. B
Added 8-Lead SOIC ........................................................... Universal
Changes to Features Section and General Description Section...... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2, Thermal Resistance Section, and Table 3 ... 6
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
9/11—Rev. 0 to Rev. A
Changes to Features Section and General Description Section...... 1
Changes to Table 2 ............................................................................ 6
Added Predicted Lifetime vs. Operating Temperature Section and
Figure 3; Renumbered Sequentially .............................................. 6
Changes to Figure 18 and Figure 19............................................. 10
Changes to Figure 24 to Figure 28 ................................................ 11
Changes to Figure 29 and Figure 30............................................. 12
Changes to Figure 48 ...................................................................... 15
Changes to Figure 56 ...................................................................... 17
Changes to Power Supplies Section.............................................. 18
1/11—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD8229
SPECIFICATIONS
+VS = 15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 1.
Parameter
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance
G=1
Temperature Drift
G = 10
Temperature Drift
G = 100
Temperature Drift
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
VOLTAGE NOISE
Spectral Density 1: 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
Peak to Peak: 0.1 Hz to 10 Hz
G=1
G = 1000
CURRENT NOISE
Spectral Density: 1 kHz
Peak to Peak: 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
High Temperature
Input Offset Current
High Temperature
Test Conditions/Comments
Min
Typ
Max
Unit
VCM = ±10 V
86
134
dB
nV/V/°C
dB
nV/V/°C
dB
nV/V/°C
dB
80
90
90
90
dB
dB
dB
dB
TA = −40°C to +210°C
300
106
TA = −40°C to +210°C
30
126
TA = −40°C to +210°C
TA = −40°C to +210°C
VCM = ±10 V
3
VIN+, VIN− = 0 V
1
45
1.1
50
nV/√Hz
nV/√Hz
2
100
µV p-p
nV p-p
1.5
100
pA/√Hz
pA p-p
VOS = VOSI + VOSO/G
TA = −40°C to +210°C
0.1
TA = −40°C to +210°C
VS = ±5 V to ±15 V
TA = −40°C to +210°C
TA = −40°C to +210°C
TA = −40°C to +210°C
TA = −40°C to +210°C
3
100
1
1000
10
86
106
126
130
dB
dB
dB
dB
70
200
35
50
TA = 210°C
TA = 210°C
Rev. B | Page 3 of 24
µV
µV/°C
µV
µV/°C
nA
nA
nA
nA
AD8229
Parameter
DYNAMIC RESPONSE
Small Signal Bandwidth –3 dB
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G = 1 to 100
THD (FIRST FIVE HARMONICS)
G=1
G = 10
G = 100
G = 1000
THD + Noise
GAIN 2
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G = 1 to 1000
Gain vs. Temperature
G=1
G > 10
INPUT
Impedance (Pin to Ground) 3
Input Operating Voltage Range 4
Over Temperature
OUTPUT
Output Swing, RL = 2 kΩ
High Temperature, SBDIP package
High Temperature, SOIC package
Output Swing, RL = 10 kΩ
High Temperature, SBDIP package
High Temperature, SOIC package
Short-Circuit Current
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
15
4
1.2
0.15
MHz
MHz
MHz
MHz
0.75
0.65
0.85
5
µs
µs
µs
µs
0.9
0.9
1.2
7
µs
µs
µs
µs
22
V/µs
–130
–116
–113
–111
0.0005
dBc
dBc
dBc
dBc
%
10 V step
10 V step
f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p
f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p, G = 100
G = 1 + (6 kΩ/RG)
1
1000
V/V
0.03
0.3
0.3
0.3
%
%
%
%
VOUT = ±10 V
0.01
0.05
0.05
0.1
VOUT = −10 V to +10 V
RL = 10 kΩ
2
TA = −40°C to +210°C
TA = −40°C to +210°C
2
ppm
5
−100
ppm/°C
ppm/°C
−VS + 2.8
−VS + 2.8
+VS − 2.5
+VS − 2.5
GΩ||pF
V
V
−VS + 1.9
−VS + 1.1
−VS + 1.2
−VS + 1.8
−VS + 1.1
−VS + 1.2
+VS − 1.5
+VS − 1.1
+VS − 1.1
+VS − 1.2
+VS − 1.1
+VS − 1.1
1.5||3
VS = ±5 V to ±18 V for dual supplies
TA = −40°C to +210°C
TA = 210°C
TA = 175°C
TA = 210°C
TA = 175°C
35
Rev. B | Page 4 of 24
V
V
V
V
V
V
mA
Data Sheet
Parameter
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
POWER SUPPLY
Operating Range
Quiescent Current
High Temperature, SBDIP package
High Temperature, SOIC package
TEMPERATURE RANGE
For Specified Performance 5
SBDIP package
SOIC package
AD8229
Test Conditions/Comments
Min
Typ
Max
Unit
+VS
kΩ
µA
V
V/V
%
±17
7
12
11
V
mA
mA
mA
+210
+175
°C
°C
10
70
VIN+, VIN− = 0 V
−VS
1
0.01
±4
6.7
TA = 210°C
TA = 175°C
−40
−40
Total Voltage Noise = √(eni2 + (eno/G)2)+ eRG2). See the Theory of Operation section for more information.
These specifications do not include the tolerance of the external gain setting resistor, RG. For G>1, RG errors should be added to the specifications given in this table.
3
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4
Input voltage range of the AD8229 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See
the Input Voltage Range section for more details.
5
For the guaranteed operation time at the maximum specified temperature, refer to the Predicted Lifetime vs. Operating Temperature section.
1
2
Rev. B | Page 5 of 24
AD8229
Data Sheet
ABSOLUTE MAXIMUM RATINGS
PREDICTED LIFETIME VS. OPERATING
TEMPERATURE
Table 2.
Comprehensive reliability testing is performed on the AD8229.
Product lifetimes at extended operating temperature are obtained
using high temperature operating life (HTOL). Lifetimes are
predicted from the Arrhenius equation, taking into account
potential design and manufacturing failure mechanism assumptions. HTOL is performed to JEDEC JESD22-A108. A minimum
of three wafer fab and assembly lots are processed through
HTOL at the maximum operating temperature. Comprehensive
reliability testing is performed on all Analog Devices, Inc., high
temperature (HT) products.
±VS
±50 V/gain
±1 V
±VS
−65°C to +150°C
100k
−40°C to +210°C
−40°C to +175°C
245°C
200°C
4 kV
1.5 kV
200 V
For voltages beyond these limits, use input protection resistors. See the
Theory of Operation section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
10k
1k
100
10
1
120
130
140
150
160
170
180
190
200
210
OPERATING TEMPERATURE (°C)
09412-200
1
Rating
±17 V
Indefinite
±VS
PREDICTED LIFETIME (Hours)
Parameter
Supply Voltage
Output Short-Circuit Current Duration
Maximum Voltage at –IN, +IN1
Differential Input Voltage1
Gain ≤ 4
4 > Gain > 50
Gain ≥ 50
Maximum Voltage at REF
Storage Temperature Range
Specified Temperature Range
SBDIP
SOIC
Maximum Junction Temperature
SBDIP
SOIC
ESD
Human Body Model
Charge Device Model
Machine Model
Figure 3. Predicted Lifetime vs. Operating Temperature
Refer to the AD8229 Predicted Lifetime vs. Operating Temperature
document for the most up-to-date reliability data.
THERMAL RESISTANCE
θJA is specified for a device in free air using a 4-layer JEDEC
printed circuit board (PCB).
Table 3.
Package Type
8-Lead SBDIP
8-Lead SOIC
ESD CAUTION
Rev. B | Page 6 of 24
θJA
100
121
Unit
°C/W
°C/W
Data Sheet
AD8229
AD8229
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
09412-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input Terminal.
Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG).
Positive Input Terminal.
Negative Power Supply Terminal.
Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.
Output Terminal.
Positive Power Supply Terminal.
Rev. B | Page 7 of 24
AD8229
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15, VREF = 0, RL = 2 kΩ, unless otherwise noted.
60
N: 200
MEAN: 12.2
σ: 8.2
60
N: 201
MEAN: 4.0
σ: 0.7
50
50
40
30
20
20
10
10
0
–60
–40
–20
0
VOSI ±15V (µV)
20
40
60
0
Figure 5. Typical Distribution of Input Offset Voltage
4
6
IBIAS OFFSET (nA)
8
N: 200
MEAN: 10.9
σ: 3.7
120
30
100
25
80
HITS
HITS
2
Figure 8. Typical Distribution of Input Offset Current
N: 200
MEAN: 0.9
σ: 161.2
35
0
09412-007
HITS
30
09412-004
HITS
40
20
60
15
40
10
–400
–200
0
200
VOSO ±15V (µV)
400
600
800
0
–60
09412-005
0
–600
INVERTING
NONINVERTING
35
30
0
–20
20
40
60
CMRR G1 (µV/V)
Figure 6. Typical Distribution of Output Offset Voltage
40
–40
09412-008
20
5
Figure 9. Typical Distribution of Common Mode Rejection, G = 1
N: 200
MEAN: –6.1
σ: 6.7
35
N: 200
MEAN: –10.1
σ: 6.9
30
N: 198
MEAN: –9.1
σ: 9.9
25
HITS
20
20
15
15
10
10
0
–50
–40
–30
–20
–10
0
10
20
IBIAS (nA)
30
0
–60
–40
–20
0
20
NINV G ERROR G1 10K ±15V (µV/V)
Figure 7. Typical Distribution of Input Bias Current
Figure 10. Typical Distribution of Gain Error, G = 1
Rev. B | Page 8 of 24
09412-015
5
5
09412-006
HITS
25
Data Sheet
AD8229
3
3
25°C
210°C
G = 1, VS = ±5V
2
COMMON-MODE VOLTAGE (V)
1
0
–1
0
–1
–2
25°C
210°C
G = 100, VS = ±5V
–3
–2
–1
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
–4
–3
–2
–1
0
1
2
3
4
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±5 V; G = 100
10
10
G = 1, VS = ±12V
25°C
210°C
8
COMMON-MODE VOLTAGE (V)
6
4
2
0
–2
–4
–6
–8
6
4
2
0
–2
–4
–6
25°C
210°C
–8
G = 100, VS = ±12V
–8
–6
–4
–2
0
2
4
6
8
10
12
OUTPUT VOLTAGE (V)
–10
–12 –10
09412-010
–10
–12 –10
–8
–6
–4
–2
0
2
4
6
8
10
12
OUTPUT VOLTAGE (V)
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±12 V; G = 1
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±12 V; G = 100
14
14
12
25°C
210°C
G = 1, VS = ±15V
12
10
COMMON-MODE VOLTAGE (V)
10
8
6
4
2
0
–2
–4
–6
–8
8
6
4
2
0
–2
–4
–6
–8
–10
–10
–12
–12
–14
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE (V)
–14
–15
09412-011
COMMON-MODE VOLTAGE (V)
5
OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±5 V; G = 1
8
COMMON-MODE VOLTAGE (V)
–3
–5
09412-013
–4
09412-009
–3
–5
09412-012
–2
1
25°C
210°C
G = 100, VS = ±15V
–10
–5
0
5
10
15
OUTPUT VOLTAGE (V)
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±15 V; G = 1
Figure 16. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±15 V; G = 100
Rev. B | Page 9 of 24
09412-014
COMMON-MODE VOLTAGE (V)
2
Data Sheet
0
70
–5
60
–10
50
GAIN (dB)
–20
–25
12.60V
–30
30
10
0
–40
–10
–45
–20
–6
–4
–2
0
2
4
6
8
10
12
14
COMMON-MODE VOLTAGE (V)
GAIN = 10
20
–35
–50
–14 –12 –10 –8
GAIN = 100
40
–12.28V
GAIN = 1
–30
100
1k
CMRR (dB)
100
80
60
100M
BANDWIDTH
LIMITED
80
40
40
20
20
1
10
100
1k
10k
100k
1M
0
1
10
10k
100k
1M
Figure 21. CMRR vs. Frequency
160
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
140
1k
FREQUENCY (Hz)
Figure 18. Positive PSRR vs. Frequency
160
100
09412-018
60
09412-069
140
120
100
100
CMRR (dB)
120
80
60
BANDWIDTH
LIMITED
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
80
60
40
40
20
20
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
0
09412-070
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 19. Negative PSRR vs. Frequency
Figure 22. CMRR vs. Frequency, 1 kΩ Source Imbalance
Rev. B | Page 10 of 24
1M
09412-019
POSITIVE PSRR (dB)
100
FREQUENCY (Hz)
NEGATIVE PSRR (dB)
10M
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
140
120
0
1M
160
120
0
100k
Figure 20. Gain vs. Frequency
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
140
10k
FREQUENCY (Hz)
Figure 17. Input Bias Current vs. Common-Mode Voltage
160
VS = ±15V
GAIN = 1000
09412-017
–15
09412-068
INPUT BIAS CURRENT (nA)
AD8229
AD8229
12
20
10
15
8
10
6
4
0
2
–5
0
100
200
300
400
500
600
700
WARM-UP TIME (s)
–10
–55
09412-071
0
5
35
65
95
125
155
185
215
Figure 26. CMRR vs. Temperature, G = 1, Normalized at 25°C
10.0
200
–25
TEMPERATURE (°C)
Figure 23. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time
12
7.5
150
2.5
50
INPUT BIAS
CURRENT
0
0
–50
–2.5
–100
–5.0
–150
–7.5
SUPPLY CURRENT (mA)
5.0
INPUT OFFSET CURRENT (nA)
10
INPUT OFFSET
CURRENT
100
8
6
4
5
65
35
125
95
155
185
215
0
–55
TEMPERATURE (°C)
100
40
SHORT CIRCUIT CURRENT (mA)
50
–50
–100
–150
–200
–25
5
35
65
95
125
155
185
215
TEMPERATURE (°C)
65
95
125
155
185
215
215
ISHORT+
30
20
10
0
–10
–20
–30
ISHORT–
–40
09412-073
–250
–55
35
Figure 27. Supply Current vs. Temperature, G = 1
150
0
5
TEMPERATURE (°C)
Figure 24. Input Bias Current and Input Offset Current vs. Temperature
50
–25
09412-074
–10.0
–25
09412-072
–200
–55
09412-075
2
GAIN ERROR (µV/V)
INPUT BIAS CURRENT (nA)
5
09412-023
CMRR (µV/V)
CHANGE IN INPUT OFFSET VOLTAGE (µV)
Data Sheet
Figure 25. Gain Error vs. Temperature, G = 1, Normalized at 25°C
–50
–55
–25
5
35
65
95
125
155
185
TEMPERATURE (°C)
Figure 28. Short-Circuit Current vs. Temperature, G = 1
Rev. B | Page 11 of 24
AD8229
Data Sheet
+VS
30
–0.4
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+SR
25
SLEW RATE (V/μs)
–SR
20
15
10
5
–0.8
–1.2
–55°C
+125°C
–40°C
+150°C
+25°C
+210°C
+85°C
+225°C
+2.0
+1.6
+1.2
+0.8
5
35
65
95
125
155
185
–VS
09412-076
–25
215
TEMPERATURE (°C)
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±VS)
Figure 29. Slew Rate vs. Temperature, VS = ±15 V, G = 1
09412-029
+0.4
0
–55
Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
25
+VS
+SR
SLEW RATE (V/μs)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–0.4
–SR
20
15
10
5
–0.8
–1.2
–55°C
+125°C
–40°C
+150°C
+25°C
+210°C
+85°C
+225°C
+2.0
+1.6
+1.2
+0.8
–25
5
35
65
95
125
155
185
–VS
09412-077
0
–55
215
TEMPERATURE (°C)
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±VS)
Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
Figure 30. Slew Rate vs. Temperature, VS = ±5 V, G = 1
15
+VS
–55°C
+125°C
–0.5
–40°C
+150°C
+25°C
+210°C
VS = ±15V
+85°C
+225°C
–55°C
–40°C
+25°C
+85°C
+125°C
+150°C
+210°C
+225°C
10
OUTPUT VOLTAGE SWING (V)
–1.0
–1.5
–2.0
–2.5
+2.5
+2.0
+1.5
5
0
–5
–10
+1.0
–VS
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±VS)
18
–15
100
1k
10k
LOAD (Ω)
Figure 34. Output Voltage Swing vs. Load Resistance
Figure 31. Input Voltage Limit vs. Supply Voltage
Rev. B | Page 12 of 24
100k
09412-031
+1.5
09412-028
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
4
09412-030
+0.4
Data Sheet
AD8229
1000
+VS
VS = ±15V
–0.8
100
–1.2
GAIN = 1
NOISE (nV/√Hz)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–0.4
–1.6
–55°C
+125°C
–40°C
+150°C
+25°C
+210°C
+85°C
+225°C
+1.8
+1.6
+1.2
10
GAIN = 10
GAIN = 100
1
+0.8
GAIN = 1000
100μ
1m
0.1
09412-032
–VS
10μ
5m
OUTPUT CURRENT (A)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
09412-037
+0.4
Figure 38. Voltage Noise Spectral Density vs. Frequency
Figure 35. Output Voltage Swing vs. Output Current
10
GAIN = 1
8
GAIN = 1000, 100nV/DIV
NONLINEARITY (ppm/DIV)
6
4
2
GAIN = 1, 2μV/DIV
0
–2
–4
–8
1s/DIV
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
09412-083
–10
–10
09412-086
–6
Figure 36. Gain Nonlinearity, G = 1, RL = 10 kΩ
Figure 39. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
10
16
GAIN = 1000
15
8
14
13
12
NOISE (pA/√Hz)
4
2
0
–2
–4
11
10
9
8
7
6
5
–6
4
3
–8
–8
–6
–4
–2
0
2
4
6
8
OUTPUT VOLTAGE (V)
10
Figure 37. Gain Nonlinearity, G = 1000, RL = 10 kΩ
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 40. Current Noise Spectral Density vs. Frequency
Rev. B | Page 13 of 24
09412-087
2
–10
–10
09412-084
NONLINEARITY (ppm/DIV)
6
AD8229
Data Sheet
5V/DIV
640ns TO 0.01%
896ns TO 0.001%
1s/DIV
2µs/DIV
TIME (µs)
Figure 44. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,
VS = ±15 V
Figure 41. 1 Hz to 10 Hz Current Noise
30
G=1
G=1
VS = ±15V
25°C
210°C
175°C
225°C
20
50mV/DIV
OUTPUT VOLTAGE (V p-p)
25
09412-091
50pA/DIV
09412-088
0.002%/DIV
15
10
VS = ±5V
1k
10k
100k
1M
10M
FREQUENCY (Hz)
1μs/DIV
09412-089
0
100
09412-048
5
Figure 45. Small Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF
Figure 42. Large Signal Frequency Response
G = 10
20mV/DIV
5V/DIV
0.002%/DIV
2µs/DIV
TIME (µs)
09412-090
25°C
210°C
175°C
225°C
1μs/DIV
Figure 43. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step,
VS = ±15 V
Rev. B | Page 14 of 24
09412-049
750ns TO 0.01%
872ns TO 0.001%
Figure 46. Small Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
Data Sheet
AD8229
25°C
175°C
210°C
225°C
1400
G = 100
SETTLING TIME (ns)
1200
SETTLED TO 0.001%
800
SETTLED TO 0.01%
600
400
0
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 47. Small Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
Figure 50. Settling Time vs. Step Size, G = 1
1
NO LOAD
2kΩ LOAD
600Ω LOAD
G = 1, SECOND HARMONIC
VOUT = 10V p-p
0.1
0.01
0.001
0.0001
0.00001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 48. Small Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 51. Second Harmonic Distortion vs. Frequency, G = 1
1
1µs/DIV
09412-093
50mV/DIV
AMPLITUDE (Percentage of Fundamental)
G=1
NO LOAD
CL = 100pF
CL = 147pF
09412-096
09412-095
10µs/DIV
20mV/DIV
AMPLITUDE (Percentage of Fundamental)
G = 1000
NO LOAD
2kΩ LOAD
600Ω LOAD
G = 1, THIRD HARMONIC
VOUT = 10V p-p
0.1
0.01
0.001
0.0001
0.00001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 49. Small Signal Response with Various Capacitive Loads, G = 1,
RL = Infinity
Rev. B | Page 15 of 24
Figure 52. Third Harmonic Distortion vs. Frequency, G = 1
09412-097
25°C
175°C
210°C
225°C
09412-092
200
09412-094
2µs/DIV
20mV/DIV
1000
AD8229
AMPLITUDE (Percentage of Fundamental)
1
Data Sheet
NO LOAD
2kΩ LOAD
600Ω LOAD
1
VOUT = 10V p-p
RL ≥ 2kΩ
G = 1000, SECOND HARMONIC
VOUT = 10V p-p
0.1
0.1
0.01
THD (%)
0.01
GAIN = 100
0.001
GAIN = 1000
0.001
100
1k
10k
100k
FREQUENCY(Hz)
0.00001
10
Figure 53. Second Harmonic Distortion vs. Frequency, G = 1000
NO LOAD
2kΩ LOAD
600Ω LOAD
G = 1000, THIRD HARMONIC
VOUT = 10V p-p
0.1
0.01
0.001
0.0001
10
100
1k
10k
100k
FREQUENCY (Hz)
1k
FREQUENCY (Hz)
Figure 55. THD vs. Frequency
09412-099
AMPLITUDE (Percentage of Fundamental)
1
100
Figure 54. Third Harmonic Distortion vs. Frequency, G = 1000
Rev. B | Page 16 of 24
10k
100k
09412-100
0.0001
10
09412-098
0.0001 GAIN = 10
GAIN = 1
Data Sheet
AD8229
THEORY OF OPERATION
VB
I
I
IB
COMPENSATION
A1
IB
COMPENSATION
A2
C1
C2
R3
5kΩ
+VS
R4
5kΩ
NODE 1
+VS
R1
3kΩ
Q1
–IN
+VS
R2
3kΩ
+VS
+VS
OUTPUT
A3
NODE 2
Q2
R5
5kΩ
+VS
–VS
R6
5kΩ
REF
+IN
RG
RG–
–VS
RG+
–VS
–VS
09412-058
–VS
–VS
Figure 56. Simplified Schematic
ARCHITECTURE
Table 5. Gains Achieved Using 1% Resistors
The AD8229 is based on the classic 3-op-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes the
common-mode voltage and provides additional amplification.
Figure 56 shows a simplified schematic of the AD8229.
1% Standard Table Value of RG (Ω)
6.04 k
1.5 k
665
316
121
60.4
30.1
12.1
6.04
3.01
The first stage works as follows. To keep its two inputs matched,
Amplifier A1 must keep the collector of Q1 at a constant voltage. It
does this by forcing RG− to be a precise diode drop from –IN.
Similarly, A2 forces RG+ to be a constant diode drop from +IN.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows
through this resistance must also flow through the R1 and R2
resistors, creating a gained differential signal between the A2
and A1 outputs.
The second stage is a G = 1 difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage removes
the common-mode signal from the amplified differential signal.
The transfer function of the AD8229 is
where:
6 kΩ
Placing a resistor across the RG terminals sets the gain of the
AD8229, which can be calculated by referring to Table 5 or by
using the following gain equation:
6 kΩ
G −1
RG Power Dissipation
REFERENCE TERMINAL
RG
GAIN SELECTION
RG =
The AD8229 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8229’s specifications to determine the total gain accuracy
of the system. When the gain resistor is not used, gain error and
gain drift are minimal.
The AD8229 duplicates the differential voltage across its inputs
onto the RG resistor. The RG resistor size should be chosen to
handle the expected power dissipation.
VOUT = G × (VIN+ − VIN−) + VREF
G =1+
Calculated Gain
1.993
5.000
10.02
19.99
50.59
100.34
200.34
496.9
994.4
1994.355
The output voltage of the AD8229 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal must be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8229 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
Rev. B | Page 17 of 24
AD8229
Data Sheet
For best performance, source impedance to the REF terminal
should be kept well below 1 Ω. As shown in Figure 56, the
reference terminal, REF, is at one end of a 5 kΩ resistor.
Additional impedance at the REF terminal adds to this 5 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be calculated as follows:
2(5 kΩ + RREF)/(10 kΩ + RREF)
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INCORRECT
AD8229
REF
REF
V
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR over
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resistance
in the input path (for example, for input protection) should be
placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
CORRECT
AD8229
Common-Mode Rejection Ratio over Frequency
Power Supplies
V
+
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 18 and
Figure 19 for more information.
09412-059
OP1177
–
Figure 57. Driving the Reference Pin
INPUT VOLTAGE RANGE
Figure 11 through Figure 16 show the allowable common-mode
input voltage ranges for various output voltages and supply
voltages. The 3-op-amp architecture of the AD8229 applies gain
in the first stage before removing common-mode voltage with
the difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 56) experience a
combination of a gained signal, a common-mode signal, and a
diode drop. This combined signal can be limited by the voltage
supplies even when the individual input and output signals are
not limited.
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 59, a 10 μF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
+VS
0.1µF
10µF
+IN
RG
VOUT
AD8229
LOAD
REF
–IN
To ensure optimum performance of the AD8229 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8229 are arranged in a logical manner to aid in
this task.
0.1µF
–VS
10µF
09412-061
LAYOUT
Figure 59. Supply Decoupling, REF, and Output Referred to Local Ground
Reference Pin
8
+VS
RG 2
7
VOUT
RG 3
6
REF
+IN 4
5
–VS
AD8229
TOP VIEW
(Not to Scale)
The output voltage of the AD8229 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
09412-060
–IN 1
Figure 58. Pinout Diagram
Rev. B | Page 18 of 24
Data Sheet
AD8229
The input bias current of the AD8229 must have a return path to
ground. When using a floating source without a current return
path, such as a thermocouple, a current return path should be
created, as shown in Figure 60.
INCORRECT
place a small value resistor, such as a 33 Ω, between the diodes and
the AD8229.
+
VIN+
–
+VS
+VS
RPROTECT
+
VIN+
–
I
AD8229
–VS
+VS
SIMPLE METHOD
AD8229
REF
+
VIN–
–
–VS
VIN–
–
AD8229
33Ω
RPROTECT
+
AD8229
+VS
RPROTECT
+VS
I
CORRECT
+VS
33Ω
RPROTECT
–VS
–VS
LOW NOISE METHOD
09412-066
INPUT BIAS CURRENT RETURN PATH
Figure 61. Protection for Voltages Beyond the Rails
REF
Large Differential Input Voltage at High Gain
If large differential voltages at high gain are expected, use an
external resistor in series with each input to limit current during
overload conditions. The limiting resistor at each input can be
computed from
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
AD8229

| −1V
1  |V
RPROTECT ≥  DIFF
− RG 
2
I MAX

AD8229
REF
Noise-sensitive applications may require a lower protection
resistance. Low leakage diode clamps, such as the BAV199, can be
used across the inputs to shunt current away from the AD8229
inputs and therefore allow smaller protection resistor values.
REF
10MΩ
–VS
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+
VDIFF
+VS
C
C
AD8229
C
AD8229
RPROTECT
LOW NOISE METHOD
09412-062
IMAX
CAPACITIVELY COUPLED
Figure 60. Creating an Input Bias Current Return Path
INPUT PROTECTION
The inputs to the AD8229 should be kept within the ratings
stated in the Absolute Maximum Ratings section. If this cannot
be done, protection circuitry can be added in front of the AD8229
to limit the current into the inputs to a maximum current, IMAX.
Input Voltages Beyond the Rails
If voltages beyond the rails are expected, use an external resistor in
series with each input to limit current during overload conditions.
The limiting resistor at the input can be computed from
RPROTECT ≥
AD8229
–
Figure 62. Protection for Large Differential Voltages
–VS
CAPACITIVELY COUPLED
AD8229
SIMPLE METHOD
REF
R
–VS
+ I
VDIFF
RPROTECT
C
REF
I
–
R
1
fHIGH-PASS = 2πRC
RPROTECT
RPROTECT
09412-067
–VS
| VIN − VSUPPLY |
I MAX
Noise-sensitive applications may require a lower protection
resistance. Low leakage diode clamps, such as the BAV199, can be
used at the inputs to shunt current away from the AD8229 inputs
and therefore allow smaller protection resistor values. To ensure
current flows primarily through the external protection diodes,
The maximum current into the AD8229 inputs, IMAX, depends
on both time and temperature. At room temperature, the part
can withstand a current of 10 mA for at least a day. This time is
cumulative over the life of the part. At 210°C, limit current to
2 mA for the same period. The part can withstand 5 mA at
210°C for an hour, cumulative over the life of the part.
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 63. The filter
limits the input signal bandwidth, according to the following
relationship:
FilterFrequency DIFF =
FilterFrequency CM =
where CD ≥ 10 CC.
Rev. B | Page 19 of 24
1
2πR(2C D + C C )
1
2πRC C
AD8229
Data Sheet
+VS
Source Resistance Noise
0.1µF
Any sensor connected to the AD8229 has some output resistance.
There may also be resistance placed in series with inputs for
protection from either overvoltage or radio frequency interference.
This combined resistance is labeled R1 and R2 in Figure 64. Any
resistor, no matter how well made, has a minimum level of noise.
This noise is proportional to the square root of the resistor
value. At room temperature, the value is approximately equal
to 4 nV/√Hz × √(resistor value in kΩ).
10µF
CC
1nF
R
+IN
4.02kΩ
CD
10nF
VOUT
AD8229
RG
R
REF
–IN
4.02kΩ
CC
1nF
0.1µF
For example, assuming that the combined sensor and protection
resistance on the positive input is 4 kΩ, and on the negative
input is 1 kΩ, the total noise from the input resistance is
09412-063
10µF
–VS
Figure 63. RFI Suppression
( 4  4 ) 2  ( 4  1) 2 =
CD affects the difference signal, and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI. A
mismatch between R × CC at the positive input and R × CC at the
negative input degrades the CMRR of the AD8229. By using a
value of CD one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
Resistors add noise; therefore, the resistor and capacitor values
chosen depend on the desired tradeoff between noise, input
impedance at high frequencies, and RFI immunity. The resistors
used for the RFI filter can be the same as those used for input
protection.
Voltage Noise of the Instrumentation Amplifier
The voltage noise of the instrumentation amplifier is calculated
using three parameters: the part input noise, output noise, and
the RG resistor noise. It is calculated as follows:
Total Voltage Noise =
(Output Noise / G)2  ( Input Noise)2  (Noise of RG Resistor )2
For example, for a gain of 100, the gain resistor is 60.4 Ω. Therefore,
the voltage noise of the in-amp is
(45 / 100) 2  12  (4  0.0604 ) 2 = 1.5 nV/√Hz
CALCULATING THE NOISE OF THE INPUT STAGE
The total noise of the amplifier front end depends on much
more than the 1 nV/√Hz headline specification of this data
sheet. There are three main contributors: the source resistance,
the voltage noise of the instrumentation amplifier, and the
current noise of the instrumentation amplifier.
In the following calculations, noise is referred to the input
(RTI). In other words, everything is calculated as if it appeared
at the amplifier input. To calculate the noise referred to the
amplifier output (RTO), simply multiple the RTI noise by the
gain of the instrumentation amplifier.
SENSOR
R2
RG
Current Noise of the Instrumentation Amplifier
Current noise is calculated by multiplying the source resistance
by the current noise.
For example, if the R1 source resistance in Figure 64 is 4 kΩ,
and the R2 source resistance is 1 k Ω, the total effect from the
current noise is calculated as follows:
((4  1.5)2  (1  1.5)2 ) = 6.2 nV/√Hz
Total Noise Density Calculation
To determine the total noise of the in-amp, referred to input,
combine the source resistance noise, voltage noise, and current
noise contribution by the sum of squares method.
AD8229
09412-064
R1
64  16 = 8.9 nV/ Hz
For example, if the R1 source resistance in Figure 64 is 4 kΩ, the
R2 source resistance is 1 k Ω, and the gain of the in-amps is 100,
the total noise, referred to input, is
Figure 64. AD8229 with Source Resistance from Sensor and
Protection Resistors
8.9 2  1.52  6.2 2 ) = 11.0 nV/√Hz
Rev. B | Page 20 of 24
Data Sheet
AD8229
OUTLINE DIMENSIONS
0.528
0.520
0.512
8
5
0.298
0.290
0.282
1
0.320
0.310
0.300
4
INDEX
MARK
0.305
0.300
0.295
0.125
0.110
0.095
0.011
0.010
0.009
0.105
0.095
0.085
0.130 NOM
0.054
NOM
0.020
0.018
0.016
0.175 NOM
0.105
0.100
0.095
0.045
0.035
0.025
0.310
0.300
0.290
0.011
0.010
0.009
07-08-2010-B
SEATING
PLANE
0.032
NOM
Figure 65. 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-8-1)
Dimensions shown in inches
5.00 (0.1968)
4.80 (0.1890)
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 66. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
AD8229HDZ
AD8229HRZ
AD8229HRZ-R7
1
Temperature Range
−40°C to +210°C
−40°C to +175°C
−40°C to +175°C
Package Description
8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
Rev. B | Page 21 of 24
Package Option
D-8-1
R-8
R-8
AD8229
Data Sheet
NOTES
Rev. B | Page 22 of 24
Data Sheet
AD8229
NOTES
Rev. B | Page 23 of 24
AD8229
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09412-0-2/12(B)
Rev. B | Page 24 of 24