LTC2970/LTC2970-1 Dual I2C Power Supply Monitor and Margining Controller DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ The LTC®2970 is a dual power supply monitor and margining controller with an SMBus compatible I2C bus interface. A low-drift, on-chip reference and 14-bit ΔΣ A/D converter allow precise measurements of supply voltages, load currents or internal die temperature. Fault management allows ⎯A⎯L⎯E⎯R⎯T to be asserted for configurable over and under voltage fault conditions. Two voltage buffered, 8-bit IDACs allow highly accurate programming of DC/DC converter output voltages. The IDACs can be configured to automatically servo the power supplies to the desired voltages using the ADC. The LTC2970-1 adds a tracking feature that can be used to turn multiple power supplies on or off in a controlled manner. Less Than ±0.5% Total Unadjusted Error 14-Bit ΔΣ ADC with On-Chip Reference Dual, 8-Bit IDACs with 1x Voltage Buffers Linear, Voltage Servo Adjusts Supply Voltages by Ramping IDAC Outputs Up/Down I2C™ Bus Interface (SMBus Compatible) Extensive, User Configurable Fault Monitoring On-Chip Temperature Sensor Available in 24-Lead 4mm × 5mm QFN Package U APPLICATIO S ■ ■ ■ ■ Dual Power Supply Voltage Servo Monitoring Supply Voltage and Current Programmable Power Supplies Programmable Reference The bus address is set to 1 of 9 possible combinations by pin strapping the ASEL0 and ASEL1 pins. The LTC2970/ LTC2970-1 are packaged in the 24-lead, 4mm × 5mm QFN package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO Dual Power Supply Monitor and Controller (One of Two Channels Shown) ADC Total Unadjusted Error vs Temperature 8V TO 15V 0.50 15 PARTS MOUNTED ON PCB 0.1μF 12VIN IN VDD OUT 0.25 1/2 LTC2970 0.1μF ERROR (%) VIN GPIO_CFG I+ VIN0_BM I– VIN0_BP DC/DC CONVERTER RUN/SS GND FB SGND LOAD ALERT VOUT0 SCL VIN0_AP SDA IOUT0 VIN0_AM I2C BUS SMBUS COMPATIBLE ( GPIO_0 ) 0 –0.25 –0.50 –50 REF ADC VIN = 5V –25 0 50 25 TEMPERATURE (°C) 75 100 29701 TA01b GND ASEL0 ASEL1 0.1μF 29701 TA01 29701fc 1 LTC2970/LTC2970-1 U W W W ABSOLUTE AXI U RATI GS PIN CONFIGURATION (Notes 1 and 2) GPIO_CFG ASEL1 ASEL0 REF RGND TOP VIEW 24 23 22 21 20 VIN0_AP 1 19 SDA VIN0_AM 2 18 SCL VIN0_BP 3 17 ALERT 25 VIN0_BM 4 16 GPIO_0 VIN1_AP 5 15 GPIO_1 VIN1_AM 6 14 IOUT0 13 IOUT1 VOUT1 VOUT0 9 10 11 12 12VIN 8 VDD VIN1_BP 7 VIN1_BM Supply Voltages: VDD ......................................................... –0.3V to 6V 12VIN .................................................... –0.3V to 15V Digital Input/Output Voltages: ASEL0, ASEL1 ............................ –0.3V to VDD + 0.3V SDA, SCL, GPIO_CFG, ⎯A⎯L⎯E⎯R⎯T, GPIO_0, GPIO_1.......................... –0.3V to 6V Analog Voltages: VIN0_AP, VIN0_AM, VIN0_BP, VIN0_BM, VIN1_AP, VIN1_AM, VIN1_BP, VIN1_BM, VOUT0, VOUT1 .............. –0.3V to 6V IOUT0, IOUT1, REF......................... –0.3V to VDD + 0.3V RGND.................................................... –0.3V to 0.3V Operating Temperature Range: LTC2970C ................................................ 0°C to 70°C LTC2970I ............................................. –40°C to 85°C Storage Temperature Range...................– 65°C to 125°C Lead Temperature (Soldering, 10 sec) .................. 300°C UFD PACKAGE 24-LEAD (4mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2970CUFD#PBF LTC2970CUFD#TRPBF 2970 24-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C LTC2970CUFD-1#PBF LTC2970CUFD-1#TRPBF 29701 24-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C LTC2970IUFD#PBF LTC2970IUFD#TRPBF 2970 24-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C LTC2970IUFD-1#PBF LTC2970IUFD-1#TRPBF 29701 24-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 29701fc 2 LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VDD and REF pins floating unless otherwise indicated, CVDD = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.24 7.5 mA 3.7 5 mA 4.14 4.4 Power-Supply Characteristics IV12 12VIN Supply Current V12VIN = 12V, VDD Floating ● IDD VDD Supply Current VDD = 5V, V12VIN = VDD ● VLKO VDD Undervoltage Lockout VDD Ramping-Down, V12VIN = VDD ● 3.7 VDD Undervoltage Lockout Hysteresis VDD 118 Supply Input Operating Range Regulator Output Voltage 8V ≤ V12VIN ≤ 15V, –1mA ≤ IVDD ≤ 0 ● 4.5 ● 4.75 Regulator Output Voltage Temperature Coefficient V12VIN 4.95 V mV 5.75 V 5.25 V 10 ppm/°C Regulator Output Voltage Load Regulation –1mA ≤ IVDD ≤ 0 160 ppm/mA Regulator Line Regulation 8V ≤ V12VIN ≤ 15V, IVDD = 0mA 80 ppm/V Regulator Output Short-Circuit Current V12VIN = 12V, VDD = 0V ● –5 12VIN Supply Operating Range ● 8 –34 –63 mA 15 V Voltage Reference Characteristics VREF Reference Output Voltage 1.229 Reference Voltage Temperature Coefficient V 2 ● Reference Overdrive Voltage Input Range 1 ppm/°C 1.5 V ADC Characteristics N_ADC Resolution N_ADC = 8.192V/16384 500 TUE_ADC Total Unadjusted Error VIN = 3V, VIN = VINn_xP – VINn_xM (Note 3) ● INL_ADC Integral Nonlinearity (Note 4) ● DNL_ADC Differential Nonlinearity (Note 7) ● VIN_ADC Input Voltage Range ● 0 VOS_ADC Offset Error ● –1000 –4.5 Offset Error Drift GAIN_ADC Gain Error 2 –316 μV/LSB ±0.5 % 4.5 LSB ±0.5 LSB 6 V 1000 μV 0.19 Full-Scale VIN = 6V ● μV/°C ±0.4 % Gain Error Drift 3 TCONV_ADC Conversion Time 33.3 ms CIN_ADC Input Sampling Capacitance 3 pF FIN_ADC Input Sampling Frequency 61.4 kHz ILEAK_ADC Input Leakage Current 0V < VIN < 6V ● ppm/°C ±0.1 μA IDAC Output Current Characteristics N_IOUT Resolution (Guaranteed Monotonic) INL_IOUT Integral Nonlinearity VIOUTn < VDD – 1.5V ● 8 ±1 LSB DNL_IOUT Differential Nonlinearity VIOUTn < VDD – 1.5V ● ±1 LSB IFS-IOUT Full-Scale Output Current VIOUTn < VDD – 1.5V, DAC Code = 'hff ● –276 μA IDRIFT-IOUT Output Current Drift DAC Code = 'hff IOS-IOUT Offset Current DAC Code = 'h00 –236 Bits –255 32 ● ppm/°C ±0.1 μA 29701fc 3 LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, VDD and REF pins floating unless otherwise indicated, CVDD = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Buffered IDAC Output Characteristics INL_VOUT Integral Nonlinearity RIOUTn = 10kΩ, No Load on VOUTn (Note 5) ● ±1 LSB DNL_VOUT Differential Nonlinearity RIOUTn = 10kΩ, No Load on VOUTn (Note 5) ● ±1 LSB VOS-VOUT Offset Voltage VOS = VOUTn – VIOUTn, No Load on VOUTn ● Output Voltage Drift No Load on VOUTn VOUT Load Regulation 1.6 ±10 0.17 mV μV/°C 0.1V < VOUTn < VDD – 1.5V, IVOUTn Source = 1mA –57 ppm/mA 0.1V < VOUTn < VDD – 1.5V, IVOUTn Sink = 1mA 100 ppm/mA VOUTn High-Z, 0V ≤ VOUTn ≤ VDD ● Short-Circuit Current Low VOUTn Shorted to GND ● –50 mA Short-Circuit Current High VOUTn Shorted to VDD ● 50 mA Leakage Current 1 ±100 nA Soft Connect Comparator Characteristics (CMP0, CMP1) VOS Offset Voltage ±3 mV Temperature Sensor Characteristics TMP Gain 0.25 °C/LSB 12VIN Voltage Divider Characteristics GAIN_12VIN ● Gain 0.329 0.333 0.335 V/V Digital Inputs SCL, SDA, GPIO_CFG, GPIO_0, GPIO_1 VIH VIL Input High Threshold Voltage Input Low Threshold Voltage VHYST Input Hysteresis ILEAK Input Leakage Current CIN Input Capacitance SDA, SCL ● 2.1 V GPIO_CFG, GPIO_0, GIPO_1 ● 1.6 V SDA, SCL ● 1.5 GPIO_CFG, GPIO_0, GIPO_1 ● 1.0 V V 0.08 0V ≤ VIN ≤ 6V ● V ±1 10 μA pF Three State Inputs ASEL[1:0] VIH_ASEL Input High Threshold Voltage ● VIL_ASEL Input Low Threshold Voltage ● IIN,HL High, Low Input Current IIN,Z High Z Input Current ASEL[1:0] = 0, VDD VDD – 0.5 0.5 ● ● V V ±20 ±2 μA μA Open Drain Outputs SDA, GPIO_CFG, GPIO_0, GPIO_1, ⎯A⎯L⎯E⎯R⎯T VOL Output Low Voltage ISINK = 3mA ● 0.4 V IOH Input Leakage Current 0V ≤ VIN ≤ 6V ● ±1 μA 29701fc 4 LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz I2C Interface Timing Characteristics fSCL Serial Clock Frequency (Note 6) ● 10 tLOW Serial Clock Low Period (Note 6) ● 1.3 μs tHIGH Serial Clock High Period (Note 6) ● 0.6 μs tBUF Bus Free Time Between Stop and Start (Note 6) ● 1.3 μs tHD,STA Start Condition Hold Time (Note 6) ● 600 ns tSU,STA Start Condition Setup Time (Note 6) ● 600 ns tSU,STO Stop Condition Setup Time (Note 6) ● 600 ns tHD,DAT Data Hold Time (LTC2970 Receiving Data) (Note 6) Data Hold Time (LTC2970 Transmitting Data) ● 0 300 tSU,DAT Data Setup Time (LTC2970 Receiving Data) (Note 6) ● tSP Pulse Width of Spike Suppressed (Note 6) ● tSETUP_GPIO GPIO_0 and GPIO_1 Setup Time GPIO_0 and GPIO_1 input setup time prior to the 26th rising SCL of an IO() I2C read. These inputs must be valid and stable by this time to be returned in the IO() read result. (Note 6) ● tHOLD_GPIO GPIO_0 and GPIO_1 Hold Time GPIO_0 and GPIO_1 input hold time after the 26th rising SCL of an IO() I2C read. These inputs must be held until this amount of time has elapsed to be returned in the IO() read result. (Note 6) ● tOUT_GPIO GPIO_0 and GPIO_1 Output Time GPIO_0 and GPIO_1 output delay after the 35th rising SCL of an I2C write. These outputs will become high impedance or begin driving low by this time. (Note 6) ● 900 100 ns ns ns 98 ns 2.5 μs 2.5 μs 2.5 μs 39 ms Internal Timers tTIMEOUT_SMB Stuck BUS Timer The LTC2970 will release the I2C bus and terminate the current command if the command is not completed before this amount of time has elapsed. tSETUP_ADC ADC Channel Setup Time After selecting a new ADC channel, the LTC2970 will wait this amount of time to allow the analog input to settle before beginning an ADC conversion. 304 μs tTIMEOUT_ Tracking SYNC Failure Timer LTC2970-1 Only: The LTC2970-1 will abort a pending SYNC() command if a tracking command is not received before this amount of time has elapsed. 255 ms Tracking IDAC Disconnect Delay LTC2970-1 Only: After the tracking algorithm asserts CPIO_CFG low, the LTC2970-1 will delay disconnecting the IDACs from the power supply feedback nodes by this amount of time. Used while tracking power supplies on. 32 ms SYNC tHOLD_TRACK 24 32 29701fc 5 LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSETUP_TRACK Tracking IDAC Disconnect Delay LTC2970-1 Only: After the tracking algorithm asserts CPIO_CFG high, the LTC2970-1 will wait this amount of time before starting to decrement Chn_a_ delay_track[9:0]. Used while tracking power supplies off. 32 ms tDEC_TRACK LTC2970-1 Only: The LTC2970-1 changes Chn_a_delay_track[9:0] at this rate. 88 μs/LSB Tracking IDAC Decrement Rate Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: TUE (%) is defined as: % Gain Error + Note 4: Integral nonlinearity (INL) is defined as the deviation of a code from a straight line passing through the actual endpoints (0V and 6V) of the transfer curve. The deviation is measured from the center of the quantization band. Note 5: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 255 (full-scale). Note 6: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and clock risetime (tr) and falltime (tf) are: (20 + 0.1 • CB)(ns) < tr < 300ns and (20 + 0.1 • CB)(ns) < tf < 300ns. CB = capacitance of one bus line in pF. SCL and SDA external pull-up voltage, VIO, is 3V < VIO < 5.5V. Note 7: This specification is guaranteed by design. (INL • 500μV/LSB + VOS ) • 100 VIN TIMING DIAGRAM The I2C Bus Specification SDA tf tLOW tSU;DAT tr tf tHD;STA tSP tr tBUF SCL tHD;STA START CONDITION tHD;DAT tHIGH tSU;STA REPEATED START CONDITION tSU;STO STOP START CONDITION CONDITION 29701 TD 29701fc 6 LTC2970/LTC2970-1 U W TYPICAL PERFOR A CE CHARACTERISTICS ADC Total Unadjusted Error vs Temperature ADC INL BASED ON AVERAGE OF 15 PARTS 0.025 ASSEMBLED ON 1/8" THICK PCB 1V 0 ERROR (LSBs) ERROR (%) –0.025 1.8V –0.050 2.5V –0.075 3.3V –0.100 1.00 2.0 0.75 1.5 0.50 1.0 0.5 0 ADC VIN = 5V –0.125 ADC DNL 2.5 ERROR (LSBs) 0.050 –0.175 –50 0 25 50 TEMPERATURE (oC) 0 100 75 1 4 3 2 INPUT VOLTAGE (V) 5 –310 REJECTION (dB) –315 –320 –325 –330 –25 0 25 50 TEMPERATURE (oC) 75 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –60 –80 –90 –100 100 10 1000 FREQUENCY AT VIN (Hz) 1 10000 0 5000 10000 15000 20000 25000 30000 FREQUENCY AT VIN (Hz) 29701 G05 29701 G06 Voltage Buffered IDAC DNL Voltage Buffered IDAC INL 0.50 VIN = 0V 0.50 CHANNELS 0 AND 1 SHOWN RIOUT0 = RIOUT1 = 10k7 1,000,000 0.25 CHANNELS 0 AND 1 SHOWN RIOUT0 = RIOUT1 = 10k7 0.25 ERROR (LSBs) ERROR (LSBs) 100000 6 –40 –90 ADC Noise Histogram 100 5 –50 –80 29701 G04 1000 2 4 3 INPUT VOLTAGE (V) –70 –100 100 10,000 1 ADC Rejection vs Frequency at VIN –70 –335 –50 0 29701 G03 REJECTION (dB) –305 VOS (MV) –1.00 ADC Rejection vs Frequency at VIN ADC Zero Code Center Offset Voltage vs Temperature NUMBER OF READINGS 6 29701 G02 29701 G01 10,000,000 –0.25 –0.75 –1.0 –25 0 –0.50 –0.5 –0.150 0.25 0 –0.25 0 –0.25 10 1 –2 –1 0 1 OUTPUT CODE (LSBs) 2 29701 G07 –0.50 0 50 150 100 DAC CODE 200 250 29701 G08 –0.50 0 50 150 100 DAC CODE 200 250 29701 G09 29701fc 7 LTC2970/LTC2970-1 U W TYPICAL PERFOR A CE CHARACTERISTICS IDAC Output Current vs Temperature 257.4 1.620 IDAC CODE = 'hff RIOUT = 13kΩ 257.2 Voltage Buffered IDAC Load Regulation Sourcing 3.500 IDAC CODE = 'h00 25oC 1.615 257.0 256.8 256.6 3.498 OUTPUT VOLTAGE (V) OFFSET VOLTAGE (mV) OUTPUT CURRENT (μA) VOUTn Offset Voltage vs Temperature 1.610 1.605 1.600 1.595 256.2 –50 1.590 –50 75 0 25 50 TEMPERATURE (°C) 100 90oC –25 75 0 25 50 TEMPERATURE (oC) 100 VIOUTn = 3.5V –2 0 –6 –4 CURRENT (mA) –8 Voltage Buffered IDAC Transient Response to 1LSB DAC Code Change Voltage Buffered IDAC SoftConnect Transient Response 100k7 SERIES RESISTANCE ON VOUTn RIOUT = 10k7 CODE 'h80 100k7 SERIES RESISTANCE ON VOUTn RIOUT = 10k7 90oC 0.30 –10 29701 G12 29701 G11 Voltage Buffered IDAC Load Regulation Sinking VIOUT = 0.1V 3.494 3.490 29701 G10 0.35 3.496 3.492 256.4 –25 –45oC 0.20 –45oC 0.15 0.10 CODE 'h80 CODE 'h7f 10mV PER DIVISION 10mV PER DIVISION OUTPUT VOLTAGE (V) 25oC 0.25 HIGH-Z CONNECTED 0.05 0 0 2 4 6 10 8 CURRENT (mA) 5Ms PER DIVISION 1Ms PER DIVISION 29701 G13 Voltage Buffered IDAC Transient Response During Transition from On State to High-Z State Temperature Sensor Error vs Temperature 100k7 SERIES RESISTANCE ON VOUTn RIOUT = 10k7 VDD Regulator Output Voltage vs Temperature 1.5 4.945 1.0 4.944 VDD (V) CONNECTED 0 –0.5 10Ms PER DIVISION 29701 G16 4.942 4.941 4.940 –1.0 –1.5 –50 V12VIN = 12V IVDD = 0A 4.943 0.5 HIGH-Z ERROR (oC) 10mV PER DIVISION 29701 G15 29701 G14 4.939 –25 0 25 50 TEMPERATURE (oC) 75 100 29701 G17 4.938 –50 –25 50 25 0 TEMPERATURE (oC) 75 100 29701 G18 29701fc 8 LTC2970/LTC2970-1 U W TYPICAL PERFOR A CE CHARACTERISTICS 400 –100 300 –200 200 –25 NO LOAD ON VDD SHORT-CIRCUIT CURRENT (mA) 0 100 –300 –45°C –400 –500 0 25°C 90°C –700 –45°C –100 –200 –600 –800 VDD Regulator Short-Circuit Current vs Temperature VDD Regulator Line Regulation ΔVDD (ppm) ΔVDD (ppm) VDD Regulator Load Regulation 25°C –300 90°C V12VIN = 12V VDD = 0V –30 –35 –400 V12VIN = 12V 0 –1 –2 –3 CURRENT (mA) –4 –5 –500 8 9 10 29701 G19 10 12 V12VIN (V) 13 14 15 29701 G20 –40 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 29701 G21 U U U PI FU CTIO S VIN0_AP (Pin 1): Positive CH0_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be configured to servo IDAC0. VIN0_AM (Pin 2): Negative CH0_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be configured to servo IDAC0. VIN0_BP (Pin 3): Positive CH0_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only. VIN0_BM (Pin 4): Negative CH0_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only. VIN1_AP (Pin 5): Positive CH1_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be configured to servo IDAC1. VIN1_AM (Pin 6): Negative CH1_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be configured to servo IDAC1. VIN1_BP (Pin 7): Positive CH1_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only. VIN1_BM (Pin 8): Negative CH1_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only. VDD (Pin 9): VDD Power Supply, Voltage Monitor Input, and Internal 5V Regulator Output. The supply input range is 4.5V to 5.75V. The VDD pin voltage can be connected to the ADC through an internal mux. Bypass the VDD pin to device ground with a 100nF capacitor (CVDD). If no 5V input voltage supply is available, float the VDD pin and power the LTC2970 from the 12VIN pin. 12VIN (Pin 10): 12V Power Supply and Voltage Monitor Input. An internal regulator generates 5V from 12VIN. The input range for 12VIN is 8V to 15V. Bypass this pin with a 100nF capacitor. The regulator’s output is connected to the VDD pin. The 12VIN pin voltage can also be monitored by the ADC through a 3:1 attenuator and the internal mux. If no 12V supply input is available, tie the 12VIN to the VDD pin and operate from 4.5V to 5.75V. VOUT0 (Pin 11): CH0 Voltage Output. Buffered version of IDAC0 output voltage. 29701fc 9 LTC2970/LTC2970-1 U U U PI FU CTIO S VOUT1 (Pin 12): CH1 Voltage Output. Buffered version of IDAC1 output voltage. IOUT1 (Pin 13): IDAC1 Current Output. Connect a resistor between this pin and the point-of-load ground for channel 1. The IDAC sources between 0 and 255μA. IOUT0 (Pin 14): IDAC0 Current Output. Connect a resistor between this pin and the point-of-load ground for channel 0. The IDAC sources between 0 and 255μA. GPIO_1 (Pin 15): General Purpose Input or Open Drain Digital Output. GPIO_1 can be configured as the IDAC Fault or Faults output, a digital input, or an open-drain digital output. GPIO_0 (Pin 16): General Purpose Input or Open Drain Digital Output. GPIO_0 can be configured as the voltage monitor power-good or power-good bar output, a digital input, or a programmable open-drain output. Power good is the NOR of all instantaneous OV and UV faults; it does not include IDAC faults. ⎯ ⎯L⎯E⎯R⎯T (Pin 17): Open Drain Digital Output. Connect the A SMBALERT signal to this pin. ⎯A⎯L⎯E⎯R⎯T is asserted low when either IDAC0 or IDAC1 rails out (optional), or when one of the monitored voltages ventures outside its UV and OV thresholds (also optional). SDA (Pin 19): Serial Bus Data Input and Output. GPIO_CFG (Pin 20): GPIO Configuration Digital Input and Open Drain Output. Pulling GPIO_CFG high will cause the GPIO_0 and GPIO_1 open-drain outputs to automatically assert low after a power-on reset. If GPIO_CFG is pulled low, then GPIO_0 and GPIO_1 do not assert low after power-up. ASEL1 (Pin 21): Slave Address Select Bit 1. Tie this pin to the VDD pin, ground, or float in order to select the address location (see Table 2). ASEL0 (Pin 22): Slave Address Select Bit 0. Tie this pin to the VDD pin, ground, or float in order to select the address location (see Table 2). REF (Pin 23): Internal Reference Output or ADC Reference Overdrive Input. The voltage at this pin determines the full-scale input voltage of the delta-sigma ADC (VFULLSCALE = 6.65 • VREF , typically). An internal 3.5k resistor decouples the reference output from this pin. Bypass this pin to RGND with a 100nF capacitor (CREF). RGND (Pin 24): Reference Ground. Connect to device ground. GND (Pin 25): Device Ground. Must be soldered to ground. SCL (Pin 18): Serial Bus Clock Input. 29701fc 10 LTC2970/LTC2970-1 W BLOCK DIAGRA 5V REGULATOR VIN VOUT 12VIN 10 2R 0μA TO 255μA IDAC0 8 BITS R 14 IOUT0 VDD VDD 9 + 12VP CMP0 12VM VDDP GND 25 – + VDDM VBUF0 VDD 11 VOUT0 – TEMP SENSOR TSNSP UVLO POR TSNSM VIN0_AP 1 CH0_AP VIN0_AM 2 CH0_AM VIN0_BP 3 CH0_BP VIN0_BM 4 CH0_BM VIN1_AP 5 CH1_AP VIN1_AM 6 CH1_AM 0μA TO 255μA VIN1_BP VIN1_BM 7 8 + – IDAC1 8 BITS 13 IOUT1 14-BIT DELTA-SIGMA A/D + CMP1 ADC CLOCKS CH1_BP + 6.65X (TYP) CH1_BM VDD 12 VOUT1 VBUF1 – 3.5k 7:1 MUX – REFERENCE 1.229V (TYP) REF 23 RGND 24 20Ω ADC_Results MONITOR LIMITS SERVO TARGETS SCL 18 SDA 19 ASEL0 22 I2C BUS INTERFACE (400kHz, SMBUS COMPATIBLE) POR SERVO CONTROLLER GPIO_1 15 DAC SOFT CONNECT FUNCTION SERVO FUNCTION MONITOR FUNCTION MANAGE FAULT REPORTING WATCH DOG TRACKING CONTROL (LT2970-1) ALERT 17 GPIO_CFG 20 18 CLOCK GENERATION OSCILLATOR ASEL1 21 GPIO_0 16 RAM 7 REGISTERS I/O CONFIGURATION IDAC0 IDAC1 ADC MONITOR FAULT ENABLE INSTANTANEOUS FAULTS LATCHED FAULTS 2 POR 29701 BD 29701fc 11 LTC2970/LTC2970-1 U U TABLE OF CO TE TS (For Operations Sections) 1. LTC2970 Operation Overview .............................................................................................................................13 2. I2C Serial Digital Interface .................................................................................................................................14 3. Register Command Set.......................................................................................................................................15 4. Detailed I2C Command Register Descriptions ...................................................................................................16 5. Soft Connecting the LTC2970 to the Power Supply Feedback Node ..................................................................20 6. Hard Connecting the LTC2970 to the Power Supply Trim Pin ............................................................................20 7. Programming a Previously Connected IDAC ......................................................................................................21 8. Disconnecting the LTC2970 from the Power Supply Trim Pin ...........................................................................21 9. Tracking Power Supplies Overview (LTC2970-1 Only).......................................................................................21 10. Tracking Power Supplies On (LTC2970-1 Only) .................................................................................................21 11. Tracking Power Supplies Off (LTC2970-1 Only) .................................................................................................22 12. Continuous Power Supply Voltage Servo ...........................................................................................................23 13. One Time Power Supply Voltage Servo .............................................................................................................24 14. One Time Power Supply Voltage Servo with Repeat On Fault ..........................................................................24 15. Configuring ADC to Monitor Input Channels and Internal Temperature Sensor ................................................24 16. Generating and Monitoring Instantaneous Faults..............................................................................................25 17. Generating and Monitoring Latched Faults........................................................................................................26 18. General Purpose Input/Output Pins ....................................................................................................................27 19. Advanced Development Features .......................................................................................................................27 29701fc 12 LTC2970/LTC2970-1 U OPERATIO 1. LTC2970 Operation Overview The LTC2970 is designed to control and monitor two power supplies. The LTC2970’s superior accuracy allows it to precisely servo each supply’s output voltage over a wide range of operating conditions; increasing accuracy, reducing power requirements and component costs. Margining may be performed with equal ease and precision. The monitoring functions allow for increased reliability by alerting a system host about incipient failures before they occur. The seven channel ADC may also be used to monitor current, temperature, and the 5V or optional 12V supply. The LTC2970’s unique architecture and control algorithm have been especially tailored for power supply management. The soft connect feature allows the LTC2970 to begin controlling a power supply without perturbing its initial value. The delta-sigma ADC architecture was specifically chosen to average out power-supply noise and allow the LTC2970 to ignore fast transients. Unlike discrete time DACs, the LTC2970’s continuous time, voltage buffered IDAC is ideal for noise sensitive applications. The servo algorithm limits the IDAC step size to one LSB per iteration in order to minimize power supply transients. The point of load ground reference for the IDAC outputs minimize errors that would otherwise occur in a power system that experiences ground bounce. By selecting two resistor values, the user can choose the appropriate resolution while providing an important hardware range limit beyond which the supply may not be driven. The servo on fault option allows the LTC2970 to further reduce output voltage disturbances by only stepping the IDAC when the output voltage drifts outside of a user programmable window. The LTC2970 powers up in a high impedance state and will not interfere with default power supply operation. Similarly, powering down the LTC2970 will restore its high impedance state. All communication with the LTC2970 is performed over an industry standard I2C bus. The LTC2970 I2C interface also meets all SMBus setup times, hold times, and timeout requirements. The ALERT pin may be used to signal that one or more of the fourteen configurable fault limits have been reached. Each fault may be individually masked. The I2C interface supports word reads, word writes and the SMBus Alert Response Address protocol. Two general purpose IO pins may be used to provide additional fault information or user defined system control. Powering down the LTC2970 will not interfere with I2C operation. The LTC2970-1 enables power supply tracking and sequencing with the addition of a few external components. A special global address and synchronization command allow multiple LTC2970-1’s to track and sequence multiple pairs of power supplies. The LTC2970 can perform the following operations: • Accept all programming commands and report status over the I2C or SMBus bus. • Command each voltage buffered IDAC to connect to the corresponding power supply’s feedback node through an external resistor using the IDAC code that most closely approximates the feedback node’s regulation voltage (Soft Connect). • Command each voltage buffered IDAC output to connect to the corresponding power supply’s feedback node through an external resistor with a user-selected IDAC code (Hard Connect). • Change the code of a previously connected IDAC. • Disconnect each voltage buffered IDAC output from the power supply’s feedback node. • LTC2970-1 Only: Track two power supplies up or down. Multiple LTC2970-1’s can be configured to track simultaneously or in a sequence. 29701fc 13 LTC2970/LTC2970-1 U OPERATIO • Continuously servo one or both supplies to a programmed voltage. • Perform a one-time servo of one or both supplies to a programmed voltage and hold the servo codes in the controlling IDAC. • Perform a one time servo of one or both supplies to a programmed voltage and hold the code(s) in the controlling IDAC(s) until over/under voltage monitoring detects a fault, at which point a control bit may be used to allow the LTC2970 to servo back to the initial voltage target. • Select any combination of seven possible ADC channels to be monitored by the ADC. • Generate instantaneous faults based on user programmable over-voltage and under-voltage limits and fixed IDAC limits. The status of OR’d voltage limit faults and IDAC faults may be output over GPIO_0 and GPIO_1, respectively. • Enable instantaneous faults to set associated latched faults using the FAULT_EN register. The status of OR’d latched faults may be signalled using ALERT. • Configure the GPIO_0 and GPIO_1 pins to act as inputs or outputs. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC2970 I2C interface is SMBus compatible; it meets all SMBus setup times, hold times and timeout requirements. The LTC2970 is a receive-only (slave) device. The LTC2970 can signal the host through the SMBALERT protocol that it wants to talk by asserting ALERT low. The LTC2970 supports the three I2C protocols summarized in Table 1. Slave Address The LTC2970 can respond to one of nine 7-bit addresses. The two slave address select pins (ASEL1 and ASEL0) are programmed by the user and determine the slave address, as shown in Table 2. The LTC2970 also supports the ARA address and a global address that allows multiple LTC2970s to be programmed with the same data simultaneously, as shown in Table 3. Table 1. Supported I2C Command Types READ DATA WORD: S:ADR:W:A:CMD:A:Sr:ADR:R:A:DATA:A:DATA:NACK:P WRITE DATA WORD: S:ADR:W:A:CMD:A:DATA:A:DATA:A:P 2. I2C Serial Digital Interface The LTC2970 communicates with a host (master) using the 2-wire, I2C serial bus interface. The Timing Diagram shows the timing relationship of the signals on the bus. ALERT RESPONSE S:ARA:R:A:ADR:NACK:P: 29701fc 14 LTC2970/LTC2970-1 U OPERATIO Table 3. Special LTC2970 Addresses Table 2. LTC2970 Address Table ADDRESS[7:0] (R/W = 0) ADDRESS[7:1] ASEL1 ASEL0 8’hB8 7’h5C L L 8’hBA 7’h5D L F 8’hBC 7’h5E L H 8’hBE 7’h5F F L 8’hD6 7’h6B F F 8’hD8 7’h6C F H 8’hDA 7’h6D H L 8’hDC 7’h6E H F 8’hDE 7’h6F H H ADDRESS[7:0] ADDRESS[7:1] FUNCTION (R/W = 0) ARA 8’h18 7’h0C This is the standard Alert Response Address for all SMBus devices. This address is independent of the value of the ASEL1 and ASEL0 pins. Global 8’hB6 7’h5B This a global address to which all LTC2970s will respond. This address is independent of the value of the ASEL1 and ASEL0 pins. L: VASELn < VIL_ASEL F: ASELn Floating H: VASELn > VIH_ASEL 3. Register Command Set COMMAND FUNCTION DESCRIPTION R/W DATA LENGTH COMMAND BYTE VALUE FAULT() FAULT_EN() Instantaneous Fault Status For All Channels Read Only 16 Bits ‘h00 Enable For All Latched Faults and Servo On Fault Read/Write 16 Bits ‘h08 FAULT_LA_INDEX() Index to All Latched Faults Read Only 16 Bits ‘h10 FAULT_LA() Latched Fault Status For All Channels Read Only 16 Bits ‘h11 IO() IO Control and Status Register Read/Write 16 Bits ‘h17 ADC_MON() Control Register For Selecting ADC Channels to Monitor Read/Write 16 Bits ‘h18 *SYNC() Control Register For Synchronizing Tracking Across Multiple Devices Read/Write 16 Bits ‘h1F VDD_ADC() VDDIN ADC Conversion Result Register Read Only 16 Bits ‘h28 VDD_OV() VDDIN Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h29 VDD_UV() VDDIN Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h2A V12_ADC() 12VIN ADC Conversion Result Register Read Only 16 Bits ‘h38 V12_OV() 12VIN Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h39 V12_UV() 12VIN Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h3A CH0_A_ADC() CH0_A ADC Conversion Result Register Read Only 16 Bits ‘h40 CH0_A_OV() CH0_A Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h41 CH0_A_UV() CH0_A Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h42 CH0_A_SERVO() CH0_A Voltage Servo Control Register Read/Write 16 Bits ‘h43 CH0_A_IDAC() CH0_A IDAC Control Register Read/Write 16 Bits ‘h44 *CH0_A_IDAC_TRACK() CH0_A IDAC Track Final Value Register Read/Write 16 Bits ‘h45 *CH0_A_DELAY_TRACK() CH0_A IDAC Track Delay Register Read/Write 16 Bits ‘h46 CH0_B_ADC() CH0_B ADC Conversion Result Register Read Only 16 Bits ‘h48 CH0_B_OV() CH0_B Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h49 CH0_B_UV() CH0_B Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h4A CH1_A_ADC() CH1_A ADC Conversion Result Register Read Only 16 Bits ‘h50 CH1_A_OV() CH1_A Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h51 CH1_A_UV() CH1_A Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h52 29701fc 15 LTC2970/LTC2970-1 U OPERATIO 3. Register Command Set (Cont.) COMMAND FUNCTION DESCRIPTION R/W DATA LENGTH COMMAND BYTE VALUE CH1_A_SERVO() CH1_A Voltage Servo Control Register Read/Write 16 Bits ‘h53 CH1_A_IDAC() CH1_A IDAC Control Register Read/Write 16 Bits ‘h54 *CH1_A_IDAC_TRACK() CH1_A IDAC Track Control Register Read/Write 16 Bits ‘h55 *CH1_A_DELAY_TRACK() CH1_A IDAC Track Delay Register Read/Write 16 Bits ‘h56 CH1_B_ADC() CH1_B ADC Conversion Result Register Read Only 16 Bits ‘h58 CH1_B_OV() CH1_B Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h59 CH1_B_UV() CH1_B Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h5A TEMP_ADC() Temperature ADC Conversion Result Register Read/Write 16 Bits ‘h68 RESERVED() All other commands are reserved for future expansion and should not be written or read. Read/Write 16 Bits ‘hXX *LTC2970-1 Only. LTC2970 will not acknowledge these commands. 4. Detailed I2C Command Register Descriptions FAULT_EN: Fault Enabling Register – Read/Write FAULT: Instantaneous Fault Register – Read BIT(s) SYMBOL OPERATION BIT(s) b[0] Fault_en_ch0_a_ov b[1] Fault_en_ch0_a_uv 0 = The associated bit in the FAULT_LA register will always be 0. (default) SYMBOL b[0] Fault_ch0_a_ov b[1] Fault_ch0_a_uv b[2] Fault_ch0_a_idac b[3] Fault_ch0_b_ov b[4] Fault_ch0_b_uv b[5] Fault_ch1_a_ov b[6] Fault_ch1_a_uv b[7] Fault_ch1_a_idac b[8] Fault_ch1_b_ov b[9] Fault_ch1_b_uv b[10] Fault_vdd_ov b[11] Fault_vdd_uv b[12] b[13] OPERATION 0 = The associated channel is clear of instantaneous faults. b[2] Fault_en_ch0_a_idac 1 = The associated channel has an instantaneous fault. b[3] Fault_en_ch0_b_ov b[4] Fault_en_ch0_b_uv The reported faults are instantaneous and not latched. When used in conjunction with latched faults they may indicate faults that are transient in nature. b[5] Fault_en_ch1_a_ov b[6] Fault_en_ch1_a_uv b[7] Fault_en_ch1_a_idac b[8] Fault_en_ch1_b_ov b[9] Fault_en_ch1_b_uv b[10] Fault_en_vdd_ov b[11] Fault_en_vdd_uv b[12] Fault_en_v12_ov b[13] Fault_en_v12_uv b[14] Fault_en_ch0_a_servo b[15] Fault_en_ch1_a_servo Fault_v12_ov Fault_v12_uv b[15:14] Reserved Always Returns 0 1 = Instantaneous faults reported in the FAULT register will set associated bit in the FAULT_LA register. 0 = Do not re-servo CH0_A in response to instantaneous OV or UV fault. 1 = Repeat a one time servo of CH0_A in response to instantaneous OV or UV fault. CH0_A must have servo operation enabled with Ch0_a_idac_ servo_repeat set low, and Adc_mon_ ch0_a set high. 0 = Do not re-servo CH1_A in response to instantaneous OV or UV fault. 1 = Repeat a one time servo of CH1_A in response to instantaneous OV or UV fault. CH1_A must have servo operation enabled with Idac_ch1_a_ servo_repeat set low, and Adc_mon_ ch1_a set high. 29701fc 16 LTC2970/LTC2970-1 U OPERATIO 4. Detailed I2C Command Register Descriptions (Cont.) FAULT_INDEX: Latched Fault Index Register – Read BIT(s) SYMBOL OPERATION b[0] Fault_la_index 0 = All faults indicated by FAULT_LA are clear. IO: Input/Output Data and General Purpose Control Register – Read/Write unless specified otherwise. BIT(s) SYMBOL OPERATION b[1:0] Io_cfg_0[1:0] Io_cfg_0[1:0] is used to configure the function of the GPIO_0 pin and IO(Io_gpio_0). 00: Io_gpio_0 = GPIO_0 = Power_good. Power_ good asserts high if there are no instantaneous over-voltage or under-voltage faults. 1 = One or more faults indicated by FAULT_LA are set. 01: Io_gpio_0 = GPIO_0 = Power_good_bar. Power_good_bar is the complement of Power_good. This register allows a summary of all latched faults to be viewed in a single read without resetting latched faults. b[15:1] Reserved 10: GPIO_0 is a general-purpose open-drain output and mirrors the value written to Io_gpio_0 (default). Always Returns 0 11: GPIO_0 is a general-purpose digital input with Io_gpio_0 = GPIO_0 FAULT_LA: Latched Fault Register – Read BIT(s) SYMBOL OPERATION b[0] Fault_la_ch0_a_ov b[1] Fault_la_ch0_a_uv 0 = The associated channel is clear of faults. b[2] Fault_la_ch0_a_idac b[3] Fault_la_ch0_b_ov b[4] Fault_la_ch0_b_uv b[5] Fault_la_ch1_a_ov b[6] Fault_la_ch1_a_uv b[7] Fault_la_ch1_a_idac b[8] Fault_la_ch1_b_ov b[9] Fault_la_ch1_b_uv b[10] Fault_la_vdd_ov b[11] Fault_la_vdd_uv b[12] Fault_la_v12_ov b[13] Fault_la_v12_uv b[15:14] Reserved b[3:2] Io_cfg_1[1:0] 00: Io_gpio_1 = GPIO_1 = Idac_fault. Idac_fault asserts if either IDAC value is faulted (Chn_idac[7:0] = 8’h00 or 8’hff) 1 = The associated channel has faulted and is enabled. The latched faults are set and held when the associated channel's instantaneous fault has occured with faults enabled. Clearing the enable bit for the associated channel in FAULT_EN will immediately clear its corresponding latched fault bit. All latched channel faults are cleared when this register is read. They may be set again if the instantaneous fault condition and fault_en have not changed. Io_cfg_1[1:0] is used to configure the function of the GPIO_1 pin and IO(Io_gpio_1). 01: Io_gpio_1 = GPIO_1 = Idac_fault_bar. Idac_fault_bar is the complement of Idac_fault. 10 = GPIO_1 is a general-purpose opendrain output and mirrors the value written to Io_gpio_1 (default). 11 = GPIO_1 is a general-purpose digital input with Io_gpio_1 = GPIO_1 b[4] Io_gpio_0 See Io_cfg_0. If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_0 is cleared and the GPIO_0 open-drain output will assert low. b[5] Io_gpio_1 See Io_cfg_1. If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_1 is cleared and the GPIO_1 open-drain output will assert low. b[6] Io_alertb Mirrors the value of the ALERT pin. Read only. b[7] Io_alertb_enb Always Returns 0 1 = ALERT pin never asserts (default). 0 = ALERT pin asserts low when one or more FAULT_LA bits are set. b[8] Io_i2c_adc_ wen 1 = Special test mode that inhibits ADC from writing to ADC result register and allows user to update registers over the I2C serial interface. 0 = Normal operation (default). b[9] Io_gpio_cfg Read only. GPIO_CFG digital input and opendrain output. Reading this bit returns the current state of the GPIO_CFG pin voltage. b[10] Io_track_start Writing a 1 to this bit will start tracking all enabled channels. Returns a 1 when tracking is pending (LTC2970-1). Reserved on LTC2970 and always returns 0. b[15:11] Reserved Always Returns 0 29701fc 17 LTC2970/LTC2970-1 U OPERATIO 4. Detailed I2C Command Register Descriptions (Cont.) ADC_MON: ADC Monitoring Mux Control Register – Read/Write VDD_ADC, V12_ADC, CH0_A_ADC, CH0_B_ADC, CH1_A_ADC, CH1_B_ADC, and TEMP_ADC: ADC Conversion Result Registers – Read Only Unless Specified Otherwise BIT(s) SYMBOL OPERATION b[14:0] Vdd_adc[14:0] Measured data from ADC conversion. 0 = ADC will not convert associated channel. (Default) V12_adc[14:0] 1 = ADC will continuously convert associated channel. Ch0_b_adc[14:0] Ch1_a_adc[14:0] 'h4000 corresponds to negative fullscale input voltage. 'h0000 corresponds to 0V. 'h3fff corresponds to full-scale input voltage. Ch1_b_adc[14:0] 2’s complement format, b[14] = sign. Temp_adc[14:0] Read/Write when Io_i2c_adc_wen = 1. BIT(s) SYMBOL OPERATION b[0] Adc_mon_vdd b[1] Adc_mon_v12 b[2] Adc_mon_ch0_a b[3] Adc_mon_ch0_b b[4] Adc_mon_ch1_a b[5] Adc_mon_ch1_b b[6] Adc_mon_temp b[15:7] Reserved Ch0_a_adc[14:0] Default value is undefined. Always Returns 0 b[15] Vdd_adc_new V12_adc_new SYNC: Tracking Synchronization Control Register – Read/Write LTC2970-1 Only BIT(s) SYMBOL OPERATION b[0] Sync_track Write 0 = Do not synchronize. Ch0_a_adc_new Ch0_b_adc_new 1 = The LTC2970-1 is synchronized for tracking. Use of the global address will allow the synchronization status of multiple LTC2970-1s to be verified in a single read; since a one can only be returned if all LTC2970-1s are synchronized. The IO_track_start command may then be issued with the same global address to begin synchronized tracking across multiple ICs. b[15:1] Reserved Always Returns 0 0 = Previously read data. (Default) Ch1_a_adc_new Ch1_b_adc_new Temp_adc_new 1 = Synchronize all tracking enabled registers to the same starting point. Read 0 = The LTC2970-1 is not synchronized for tracking (default). 1 = The ADC has updated the associated result register since the last time the data was read. VDD_OV, V12_OV, CH0_A_OV, CH0_B_OV, CH1_A_OV, CH1_B_ OV: Over Voltage Limit Registers – Read/Write BIT(s) SYMBOL OPERATION b[14:0] Vdd_ov[14:0] ADC over-voltage threshold limit. V12_ov[14:0] Ch1_a_ov[14:0] The associated instantaneous over voltage fault is asserted if the channel’s ADC result is greater than this limit. Code 'h3fff disables OV threshold detect feature for that channel. Ch1_b_ov[14:0] 2’s complement format, b[14] = sign. Ch0_a_ov[14:0] Ch0_b_ov[14:0] Default value is undefined. b[15] Reserved Always Returns 0 VDD_UV, V12_UV, CH0_A_UV, CH0_B_UV, CH1_A_UV, CH1_B_ UV: Under Voltage Limit Registers – Read/Write BIT(s) SYMBOL OPERATION b[14:0] Vdd_uv[14:0] ADC under-voltage threshold limit. V12_uv[14:0] Ch1_a_uv[14:0] The associated instantaneous under voltage fault is asserted if the channel’s ADC result is greater than this limit. Code 'h4000 disables UV threshold detect feature for that channel. Ch1_b_uv[14:0] 2’s complement format, b[14] = sign. Ch0_a_uv[14:0] Ch0_b_uv[14:0] Default value is undefined. b[15] Reserved Always Returns 0 29701fc 18 LTC2970/LTC2970-1 U OPERATIO 4. Detailed I2C Command Register Descriptions (Cont.) b[10] Ch0_a_idac_pol 0 = Use this setting when increasing VOUTn causes (VINn_AP-VINn_AM) to decrease. Inverting configuration common to DC/DC converters with external feedback networks. Ch1_a_idac_pol CH0_A_SERVO, CH1_A_SERVO: Voltage Servo Control Registers – Read/Write BIT(s) SYMBOL OPERATION b[14:0] Ch0_a_servo[14:0] During servo operation Ch1_a_servo[14:0] Chn_a_idac[7:0] output current is stepped to force Chn_a_adc[14:0] code to equal target code stored in Chn_a_servo[14:0]. 2’s complement format, b[14] = sign 1 = Use this setting when increasing VOUTn causes (VINn_AP-VINn_AM) to increase. Non-inverting configuration common to DC/DC converters with trim pins. b[11] Ch1_a_idac_servo_repeat Default value is undefined. b[15] Ch0_a_servo_en 0 = Chn_a servo disabled (default). Ch1_a_servo_en 1 = Chn_a servo enabled. CH0_A_IDAC, CH1_A_IDAC: IDAC Control/Data Registers – Read/Write BIT(s) SYMBOL OPERATION b[7:0] Ch0_a_idac[7:0] Chn_a IDAC data value. Ch1_a_idac[7:0] b[8] 0 = During servo operation, servo Chn_a until the measured result is stable and matches the target code. 1 = During servo operation, continuously servo Chn_a to the target code. b[15:12] Reserved Always Returns 0 CH0_A_IDAC_TRACK and CH1_A_IDAC_TRACK: IDAC Tracking data and control registers – Read/Write LTC2970-1 Only Ch0_a_idac_en 0 = VOUTn output tri-stated. BIT(s) SYMBOL OPERATION Ch1_a_idac_en 1 = VOUTn output enabled. b[7:0] Ch0_a_idac_ track[7:0] Final target value for of Chn_a_ idac[7:0]. During tracking, Chn_a_ idac[7:0] is incremented/decremented by 1 until it is equal to this value. There are two ways to enable VOUTn. 1) When Chn_a_idac_en is set high with Chn_a_idac_con low, the LTC2970 will perform a soft connect. During a soft connect, the VOUTn voltage buffer output will not be connected to the VOUTn pin until the internal algorithm has servo’d the voltage at the IDACn pin to match the VOUTn pin voltage. Resolution is one Chn_a_idac LSB. 2) When Chn_a_idac_en is enabled with Chn_a_idac_con high, the LTC2970 will perform a hard connect. The VOUTn voltage buffer will be immediately connected to the VOUTn pin. b[9] Ch0_a_idac_servo_repeat Ch0_a_idac_con Ch1_a_idac_con Ch1_a_idac_ track[7:0] b[8] Ch0_a_idac_track_en 0 = inhibit tracking of Chn_a_idac[7:0]. b[15:9] Reserved Ch1_a_idac_track_en 1 = enable tracking of Chn_a_idac[7:0] Always Returns 0 CH0_A_DELAY_TRACK and CH1_A_DELAY_TRACK: IDAC Tracking delay register – Read/Write LTC2970-1 Only BIT(s) SYMBOL OPERATION b[9:0] Ch0_a_delay_track[9:0] Ch1_a_delay_track[9:0] Delay used to synchronize or offset tracking events. Reserved Always Returns 0 b[1510] 0 = VOUTn is not enabled or has been enabled but is not yet connected to the output of the CHn voltage buffer. (Default) 1 = VOUTn is enabled and has been connected to the output of the CHn voltage buffer. See Chn_a_idac_en for additional information. 29701fc 19 LTC2970/LTC2970-1 U OPERATIO 5. Soft Connecting the LTC2970 to the Power Supply Feedback Node The soft connect feature allows the LTC2970 to connect to the power supply’s feedback node with minimal disturbance to the supply’s output voltage. This is accomplished by comparing the buffered voltage of IOUTn to the voltage at VOUTn and incrementing or decrementing Chn_a_idac[7:0] until the comparator output (COMPn) changes. The value of Chn_a_idac[7:0] when the comparator transitions is the appropriate value for a soft connect. The voltage buffer output is only connected to VOUTn if the IDAC reaches this soft connect value without generating an instantaneous IDAC fault (Fault_chn_a_idac). Soft-Connect Procedure: Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing VOUTn causes differential voltage (VINn_AP – VINn_AM) to increase. When properly programmed, lowering the value in Chn_ a_idac[7:0] will always cause the output of the controlled power supply to decrease. Ensure that the channel’s IDAC is not currently enabled for connection, i.e., the Chn_a_idac_en bit must be 0. Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 0, Chn_a_idac_en = 1, and Chn_a_idac[7:0] = 0x80. The value programmed into Chn_a_idac[7:0] is ignored and Chn_a_idac[7:0] is initially set to 8’h80. The LTC2970 will now ramp Chn_a_idac[7:0] while monitoring the output of the soft connect comparator. If the soft connect comparator trips, the LTC2970 will connect the output of VBUFn to VOUTn and set Chn_a_idac_con high. If the soft connect comparator does not trip before the IDAC value reaches ‘h00 or ‘hFF, then the soft connection will fail, an IDAC fault will be indicated (Fault_chn_a_idac), and Chn_a_idac_con will remain low. Soft-Connect Rules: When both channels are requesting a soft connect, channel 0 has priority. Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect on that channel or the previously issued soft connect failed with an IDAC fault (Fault_chn_a_idac = 1). Recall that the Chn_a_idac_en bit must initially have been set to 0. LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change the Chn_a_idac_pol bit if there is a pending tracking operation. 6. Hard Connecting the LTC2970 to the Power Supply Trim Pin The hard connect feature allows the LTC2970 to bypass the soft connect algorithm and connect directly to the power supply’s feedback node using the value programmed into Chn_a_idac[7:0]. This feature is useful for systems that have calculated or measured an acceptable voltage at which to connect the IDAC’s buffered voltage VBUFn to VOUTn. Hard Connect Procedure: Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing VOUTn causes (VINn_AP – VINn_AP) to increase. When properly programmed, lowering the value in the IDAC will always cause the output of the controlled power supply to decrease. Determine the value for Chn_a_idac[7:0]. The values ‘h00 or ‘hff are allowed, but they will trip the IDAC’s fault bit (Fault_chn_a_idac = 1). When the IDAC is already connected, the value Chn_a_ idac[7:0] and Chn_a_idac_pol will be programmed into the IDAC provided all other conditions are met. See “Programming a Previously Connected Current DAC” for details Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 1, Chn_a_idac_en = 1, and Chn_a_idac[7:0]. Hard Connect Rules: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect on that channel or the previously issued 29701fc 20 LTC2970/LTC2970-1 U OPERATIO soft connect failed with an IDAC fault (Fault_chn_a_idac = 1). Recall that a new hard connection requires the previous value of Chn_a_idac_en = 0. LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_ idac_con or Chn_a_idac[7:0] if there is a pending tracking operation. 7. Programming a Previously Connected IDAC 8. Disconnecting the LTC2970 from the Power Supply Trim Pin VOUTn can be placed in a high impedance state simply by clearing the Chn_a_idac_en bit. In order to minimize the resulting disturbance to the power supply voltage, the IDAC code should not be changed from its current value when clearing the Chn_a_idac_en bit. This is not an issue if the channel’s associated servo_en bit is high. Disconnect Procedure: Update CHn_IDAC() with Chn_a_idac_en set low. The LTC2970 will immediately disconnect the buffered IOUTn from VOUTn. The LTC2970 IDAC’s may be programmed after they have been connected with a soft connect or a hard connect provided a servo operation is not enabled on the associated channel. Disconnect Rules: Procedure: Determine the value for Chn_a_idac[7:0]. The values ‘h00 or ‘hff are allowed, but will trip the IDAC’s fault bit (Fault_chn_a_idac = 1). LTC2970-1 Only: Chn_a_idac_en may not be changed if the feedback node connection is configured for tracking. Tracking is enabled when GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. Verify that the IDAC is already connected, and that Chn_a_idac_con is high. 9. Tracking Power Supplies Overview (LTC2970-1 Only) Ensure that servo mode is not enabled for the channel being programmed. Chn_a_servo_en must be low. This requirement prevents the user from interfering with a previously requested servo operation. The LTC2970-1 tracking feature allows the I2C interface to initiate a controlled power up or power down of two or more supplies (Figure 2 shows a typical LTC2970-1 application circuit). Multiple LTC2970-1’s with different addresses may be simultaneously programmed using the LTC2970 group address and the SYNC() command. Tracking is enabled when GPIO_CFG is pulled high and either GPIO_0 or GPIO_1 are high. Update the CHn_A_IDAC() register with Chn_a_idac_pol, Chn_a_idac_con = 1, Chn_a_idac_en = 1, and Chn_a_ idac[7:0]. Note: Care should be taken to preserve the current value of the Chn_a_idac_pol bit, since the LTC2970 does not prevent the user from changing this value when writing to the IDAC control registers. Rules: Setting Chn_a_idac_con to zero will not disconnect the DAC unless Chn_a_idac_en is also set low. All Hard Connect rules apply. Clearing Chn_a_idac_con with Chn_a_idac_en high will not disconnect the IDAC. Only setting Chn_a_idac_en low will clear Chn_a_idac_con. 10. Tracking Power Supplies On (LTC2970-1 Only) The LTC2970-1 tracking feature allows the I2C to initiate a controlled power up of two or more supplies. Procedure: This procedure describes all the steps necessary to track up two or more power supplies. Steps that require I2C interaction are prefixed with the required I2C command function. Power-up the LTC2970-1 with GPIO_CFG pulled high. 29701fc 21 LTC2970/LTC2970-1 U OPERATIO This causes open-drain outputs GPIO_1 and GPIO_0 to automatically pull the power supplies’ run/soft-start pins to ground. CHn_A_IDAC(): Hard connect Chn_a_idac[7:0] with a value that forces the power supplies off when GPIO_CFG = 1. Verify that Chn_a_idac_pol is at the appropriate value. CHn_A_IDAC_TRACK(): Set Chn_a_idac_track_en = 1, and set the Chn_a_idac_track[7:0] target value to the code that causes VOUTn to most closely approximate the corresponding power supply’s feedback node voltage when it is in regulation. CHn_A_DELAY_TRACK(): Set the value by which the incrementing of IDACn should be delayed with respect to the start of tracking event. This controls whether the power supplies track up coincidentally or sequentially. IO(): Release the run/soft-start pins by programming io_gpio_n = 1. This will enable the power supplies without allowing their outputs to move since these are held low by Chn_a_idac[7:0]. Wait until power supplies have had sufficient time to start running before starting tracking. SYNC(): Optional command that allows multiple LTC29701’s to be synchronized for tracking. Writing Sync_track = 1 will allow the LTC2970-1 to finish its current ADC conversion before having it wait to receive io_track_start = 1. The LTC2970-1 will timeout this wait command after tTIMEOUT_SYNC. Reading back Sync_track = 1 using the global address will ensure all LTC2970-1’s are synchronized before proceeding with the tracking operation. IO(): Set Io_track_start = 1 and keep the run/soft-start pins enabled. Use the global I2C address to simultaneously track up power supplies across multiple LTC2970-1’s. LTC2970-1 response: For each tracking enabled channel, the LTC2970-1 will decrement the CHn_A_delay_track counter at a rate of tDEC_TRACK. As soon as a channel’s tracking counter reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the final value of Chn_a_idac_track[7:0] is reached, at which point Chn_a_idac_track_en is de-asserted. When the final value is reached for all channels, GPIO_CFG is asserted low. After a time delay of tHOLD_TRACK, Chn_a_idac_en is de-asserted. Power-Up Tracking Rules: Tracking cannot begin if Chn_a_idac_con is not connected. This condition is met when the previous procedure is followed. Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(Io_track_start) is asserted until tracking is complete or whenever tracking is pending, i.e., GPIO_CFG pulled high with either GPIO_0 or GPIO_1 asserted pulled high. 11. Tracking Power Supplies Off (LTC2970-1 Only) The LTC2970-1 tracking feature allows the I2C to initiate a controlled power down of two or more supplies. Procedure: This procedure describes all steps necessary to track down two or more power supplies. Steps that require I2C interaction are prefixed with the required I2C command function. CHn_IDAC(): Disable the IDAC’s for each tracking enabled channel (Chn_a_idac_en = 0). Ensure Chn_a_idac_pol is at the appropriate value. CHn_IDAC_TRACK(): Select the channels to be tracked by setting Chn_a_idac_track_en = 1, and set the target value for each Chn_a_idac_track[7:0] to that which forces the supply off. CHn_A_DELAY_TRACK(): Set the value by which the decrementing of that channel’s DAC should be delayed with respect to the start of the tracking event. This controls whether the supplies track down coincidentally or sequentially. SYNC(): Optional command that allows multiple LTC29701’s to be synchronized for tracking. Writing Sync_track = 1 will allow the LTC2970-1 to finish its current ADC conversion before having it wait to receive io_track_start = 1. The LTC2970-1 will timeout this wait command after tTIMEOUT_SYNC. Reading back Sync_track = 1 using the global address will ensure all LTC2970’s are synchronized before proceeding with the tracking operation. IO(): Set Io_track_start = 1. Use the global I2C address to simultaneously track down power supplies across multiple LTC2970’s. 29701fc 22 LTC2970/LTC2970-1 U OPERATIO LTC2970-1 response: Each tracking enabled channel is soft connected. The GPIO_CFG pin is released allowing it to be pulled high. The LTC2970-1 waits tSETUP_TRACK to allow GPIO_CFG to settle. For each tracking enabled channel, the Chn_a_delay_track counter is decremented at a rate of tDEC_TRACK. As soon as a channel’s tracking counter reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the final value of Chn_a_idac_track[7:0] is reached. The tracking enable bit is then cleared for both channels (Chn_a_idac_track_en = 0). IO(): The I2C interface may then be used to set GPIO_1 and GPIO_0 low, disabling the power supplies. Power Down Tracking Rules: Power down tracking requests will be ignored until the user has disabled the IDAC’s by setting Chn_a_idac_en = 0 for each tracking enabled channel. Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(IO_track_start) is asserted until tracking is complete and whenever tracking range is configured; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high). Determine the target servo voltage, Chn_a_servo[14:0]. Update CHn_A_SERVO() with Chn_a_servo_en = 1, and Chn_a_servo[14:0]. Update CHn_A_IDAC() with Chn_a_idac_servo_repeat = 1. This step may be skipped if Chn_a_idac_servo_repeat was set high during the soft or hard connect procedure. LTC2970 response: The LTC2970 will continuously increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. Whenever the CHn_A_SERVO() register is updated an internal flag is cleared indicating that a successful servo has not been completed. This internal flag, Chn_a_servo_done, initially causes the ADC to operate in an accelerated 12-bit mode. Once the channel reaches the servo target, the ADC switches back to 14-bit mode for two conversions before asserting Chn_a_servo_done high. In continuous voltage servo mode the Chn_a_servo_done flags allow the initial servo target to be reached quickly. During this time, ADC conversions for all non-servo channels are temporarily inhibited. Rules: 12. Continuous Power Supply Voltage Servo The continuous voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value. The voltage of the external supply is monitored over Chn_A_ADC and compared to a target value stored in Chn_a_servo. After each conversion, Chn_A_IDAC is incremented by 1, decremented by 1, or held; whichever brings or keeps the measured voltage closer to the targeted servo value. Procedure: Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be asserted high. The servo channel’s IDAC must be enabled before Chn_A_servo_en can be set high. The IDAC associated with the servo channel must be enabled. If Chn_a_idac_en is low the servo enable bit Chn_a_servo_en is always forced low. The IDAC associated with the servo channel must be connected (Chn_a_idac_con = 1). An IDAC fault may be generated during a continuous servo operation. The LTC2970 will report the fault and continue trying to servo that channel. LTC2970-1 Only: There must be no pending tracking commands. A pending tracking command will clear Chn_a_servo_en. LTC2970-1 Only: The tracking range must not be enabled; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high). An enabled tracking range will clear Chn_a_servo_en low. 29701fc 23 LTC2970/LTC2970-1 U OPERATIO 13. One Time Power Supply Voltage Servo Procedure: The one time voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value and then stop updating the IDAC once the target value has been reached. Follow procedure outlined for “One Time Power Supply Voltage Servo”. Procedure: Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be deasserted low. The servo channel’s IDAC must be enabled before Chn_a_servo_en may be set high. Update CHn_A_IDAC() with Chn_a_idac_servo_repeat = 0. This step may be skipped if Chn_a_idac_servo_repeat was cleared low during the soft or hard connect procedure. Update FAULT_EN() with Fault_en_chn_a_servo = 0. This prevents the LTC2970 from reinitiating a servo after an over-voltage or under-voltage fault. Determine the target servo voltage, Chn_a_servo[14:0]. Update CHn_A_SERVO() register with Chn_a_servo_en = 1, and Chn_a_servo[14:0]. LTC2970 response: The LTC2970 will increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. The servo procedure will end when the internal Chn_a_servo_ done flag is set (see “Continuous Power Supply Voltage Servo”). At this point the IDAC is either programmed to the appropriate servo value or faulted. Rules: All “Continuous Power Supply Voltage Servo” rules apply. 14. One Time Power Supply Voltage Servo with Repeat On Fault The LTC2970 one time voltage servo feature may be modified to allow the LTC2970 to perform an additional power supply servo operation after an under-voltage or over-voltage fault is detected on the servo channel. Update FAULT_EN() with Fault_en_chn_a_servo = 1. Enable detection of the appropriate instantaneous faults for all servo channels; see “Generating and Monitoring Instantaneous Faults”. LTC2970 response: Any time an instantaneous undervoltage or over-voltage fault is detected on the servo channel (Fault_ov_a_chn or Fault_uv_a_chn), the internal Chn_a_servo_done flag for that channel is cleared, and the LTC2970 will perform a complete one time servo. This allows the LTC2970 to precisely restore the power supply to the target servo value, after it has drifted beyond a user defined operating window. Rules: All “Continuous Power Supply Voltage Servo” rules apply. During a permanent under-voltage or over-voltage fault the LTC2970 will continuously try to correct the faulted channel, after each failed attempt all other channels that need monitoring by the ADC will be serviced. 15. Configuring ADC to Monitor Input Channels and Internal Temperature Sensor The LTC2970 is able to perform ADC conversions on any combination of seven different input channels. A channel is converted if its associated ADC_MON() bit is set high. Refer to Table 7 for details. Procedure: Update ADC_MON() with the control bit of each channel that is to be monitored set high. LTC2970 response: All enabled channels will be sequentially converted. The result of the most recent conversion may be read from the ADC result register. Each time a conversion is completed the new data bit associated with the result register is asserted high. The new data bit is 29701fc 24 LTC2970/LTC2970-1 U OPERATIO Table 7. LTC2970 ADC Conversion and Fault Limit Registers INPUT CHANNEL ADC_MON() CONTROL BIT ADC RESULT REGISTER (2s COMPLEMENT) OV FAULT REGISTER (2s COMPLEMENT) UV FAULT REGISTER (2s COMPLEMENT) TEMPERATURE Adc_mon_temp Temp_adc[14:0] - - VIN1_BP-VIN1_BM Adc_mon_b_ch1 Ch1_b_adc[14:0] Ch1_b_ov[14:0] Ch1_b_uv[14:0] VIN1_AP-VIN1_AM Adc_mon_a_ch1 Ch1_a_adc[14:0] Ch1_a_ov[14:0] Ch1_a_uv[14:0] VIN0_BP-VIN0_BM Adc_mon_b_ch0 Ch0_b_adc[14:0] Ch0_b_ov[14:0] Ch0_b_uv[14:0] VIN0_AP-VIN0_AM Adc_mon_a_ch0 Ch0_a_adc[14:0] Ch0_a_ov[14:0] Ch0_a_uv[14:0] 12VIN Adc_mon_v12 V12_adc[14:0] V12_ov[14:0] V12_uv[14:0] VDD Adc_mon_vdd Vdd_adc[14:0] Vdd_ov[14:0] Vdd_uv[14:0] reset each time the result register is read. This provides a simple mechanism for supervisory software to determine if a new conversion has been completed since data was last read. Rules: The LTC2970 assigns priority to ADC conversions of CH1_A_ADC and CH0_A_ADC when these channels are in their initial fast servo mode. The IO() register control bit Io_i2c_adc_wen must be low in order for ADC conversions to be performed. 16. Generating and Monitoring Instantaneous Faults The LTC2970 supports fourteen different types of instantaneous faults. These faults together with the conditions that trigger them are defined in Table 8. There are six under-voltage faults, six over-voltage faults and two IDAC limit faults. The FAULT() command may be used to read the status of all instantaneous fault bits. The IO() command may be used to configure GPIO_0 and GPIO_1 to view voltage limit and IDAC faults respectively. The state of GPIO_0 and GPIO_1 may be read using IO(). LTC2970-1 Only: ADC conversions are suspended during any pending tracking requests. Table 8. LTC2970 Fault Reporting Bits and Conditions CONDITION THAT GENERATES AN INSTANTANEOUS FAULT FAULT() FAULT_EN() FAULT_LA() INSTANTANEOUS FAULT REPORTING ENABLE FOR LATCHED FAULT REPORTING LATCHED FAULT REPORTING V12_adc[14:0] < V12_uv[14:0] Fault_v12_uv Fault_en_v12_uv Fault_la_v12_uv V12_adc[14:0] > V12_ov[14:0] Fault_v12_ov Fault_en_v12_ov Fault_la_v12_ov Vdd_adc[14:0] < Vdd_uv[14:0] Fault_vdd_uv Fault_en_vdd_uv Fault_la_vdd_uv Vdd_adc[14:0] > Vdd_ov[14:0] Fault_vdd_ov Fault_en_vdd_ov Fault_la_vdd_ov Ch1_b_adc[14:0] < Ch1_b_uv[14:0] Fault_ch1_b_uv Fault_en_ch1_b_uv Fault_la_ch1_b_uv Ch1_b_adc[14:0] > Ch1_b_ov[14:0] Fault_ch1_b_ov Fault_en_ch1_b_ov Fault_la_ch1_b_ov Idac_a_ch1[7:0] = 8’ff or 8’h00 Fault_ch1_a_idac Fault_en_ch1_a_idac Fault_la_ch1_a_idac Ch1_a_adc[14:0] < Ch1_a_uv[14:0] Fault_ch1_a_uv Fault_en_ch1_a_uv Fault_la_ch1_a_uv Ch1_a_adc[14:0] > Ch1_a_ov[14:0] Fault_ch1_a_ov Fault_en_ch1_a_ov Fault_la_ch1_a_ov Ch0_b_adc[14:0] < Ch0_b_uv[14:0] Fault_ch0_b_uv Fault_en_ch0_b_uv Fault_la_ch0_b_uv Ch0_b_adc[14:0] > Ch0_b_ov[14:0] Fault_ch0_b_ov Fault_en_ch0_b_ov Fault_la_ch0_b_ov Idac_a_ch0[7:0] = 8’ff or 8’h00 Fault_ch0_a_idac Fault_en_ch0_a_idac Fault_la_ch0_a_idac Ch0_a_adc[14:0] < Ch0_a_uv[14:0] Fault_ch0_a_uv Fault_en_ch0_a_uv Fault_la_ch0_a_uv Ch0_a_adc[14:0] > Ch0_a_ov[14:0] Fault_ch0_a_ov Fault_en_ch0_a_ov Fault_la_ch0_a_ov 29701fc 25 LTC2970/LTC2970-1 U OPERATIO Procedure: Update the over-voltage limit register with the value above which the ADC result should generate an over-voltage fault. Instantaneous over-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is greater than the over-voltage limit. They are cleared if the ADC result is less than or equal to the over-voltage limit. Setting the over-voltage limit to 14’h3fff inhibits instantaneous faults for the associated channel. Update the under-voltage limit register with the value below which the ADC result should generate an under-voltage fault. Instantaneous under-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is less than the under-voltage limit. They are cleared if the ADC result is greater than or equal to the under-voltage limit. Setting the over-voltage limit to 14’h4000 inhibits instantaneous faults for the associated channel. Update ADC_MON() control bits to allow ADC conversions on all channels that are to be monitored for over and under voltage limits. Instantaneous IDAC faults are polled after all ADC conversions are completed and set when the associated IDAC registers are at ‘h00 of ‘hff. Read FAULT() to view the value of all instantaneous faults. The IO(Io_cfg_0) command may be used to configure the GPIO_0 pin to output the internal Power_good flag. Power_good is asserted high if there are no instantaneous over-voltage or under-voltage faults. IO() may be used to read the value of Power_good through io_gpio_0. The IO(Io_cfg_1) command may be used to configure the GPIO_1 pin to output the internal Idac_fault flag. Idac_fault is asserted high if either IDAC value is faulted. IO() may be used to read the value of Idac_fault through io_gpio_1. Rules: The over-voltage and under-voltage limits must be initialized; they do not have a default value. All over-voltage limits, under-voltage limits and ADC results use 2’s complement notation with bit position [14] of register [14:0] being used for the sign. Instantaneous Ch0_a and Ch1_a faults may be used to trigger a servo on fault event. Over-voltage and under-voltage faults require that the associated ADC_MON control bit be asserted high for instantaneous fault detection to be updated. 17. Generating and Monitoring Latched Faults The LTC2970 is able to selectively latch instantaneous faults in the latched fault register FAULT_LA. Each instantaneous fault has an associated latched fault bit in FAULT_LA and a fault enable bit in FAULT_EN; (see Table 8) for details. When an instantaneous fault enable bit is high, any event that sets the instantaneous fault will simultaneously set the latched fault. The latched fault will remain set even if conditions permit the instantaneous fault to be cleared. The latched faults are immediately cleared whenever the associated fault enable bit is cleared. All latched faults are also cleared when the latched fault register is read over FAULT_LA(). The FAULT_INDEX() command may be read to determine if any latched faults are asserted. Reading FAULT_INDEX() does not clear latched faults. The ALERT output may also be configured to view whether any latched faults are asserted. Procedure: Follow procedure for generating instantaneous faults. Write FAULT_EN() to enable any combination of latched faults. Read FAULT_INDEX() to determine if any latched faults are asserted without clearing latched faults. Read FAULT_LA() to monitor all latched faults. Reading FAULT_LA() will clear all latched faults. These will remain clear until the next time the LTC2970 polls and sets an associated instantaneous fault. Setting IO(Io_alert_enb) low will cause ALERT to be asserted low whenever any one of the fourteen latched faults is asserted high. The value of the ALERT pin may also be read through IO(Alertb). 29701fc 26 LTC2970/LTC2970-1 U OPERATIO Rules: Rules: See “Generating and Monitoring Instantaneous Faults”. The power on reset configurations for GPIO_0 and GPIO_1 are output pins with a value equal to the complement of the GPIO_CFG level. 18. General Purpose Input/Output Pins The GPIO_0 and GPIO_1 may be used to: (1) monitor instantaneous faults (see “Generating and Monitoring Instantaneous faults”); (2) control switcher run/start pins during tracking (see “Tracking Power Supplies Overview”); or (3) provide general purpose input/output pins. Procedure: To program GPIO_n as an open drain output set Io_cfg_n = 2’b10. The value written to lo_gpio_n will be output over GPIO_n. To program GPIO_n as an input set Io_cfg_n = 2’b11. The value of GPIO_n may now be read through lo_gpio_n. 19. Advanced Development Features The internal ADC may be disabled with the ADC result registers accepting written I2C data. This feature allows faults to be generated for diagnostic purposes, without having to generate an actual overvoltage or undervoltage event. Procedure: Set IO(Io_i2c_adc_wen) high to enable ADC result register writes and disable internal ADC updates. Rules: Io_i2c_adc_wen must be clear for normal operation. U W U U APPLICATIO S I FOR ATIO Margining DC/DC Converters with External Feedback Resistors 8V TO 15V 0.1μF VIN R50 Figure 1 shows a typical application circuit for margining a power supply with an external feedback network. The VIN0_AP and VIN0_AM differential inputs sense the load voltage directly, and differential inputs VIN0_BP and VIN0_BM are connected across load current sense resistor R50. A correction voltage is developed at the IOUT0 pin by sourcing IDAC0’s current into resistor R40. R40 is Kelvin connected to the point-of-load GND in order to isolate VIOUT0 from ground bounce due to load current changes. VIOUT0 is replicated at VOUT0 by an on-chip, unity-gain voltage buffer. VOUT0 is then connected to the feedback node of the power supply through resistor R30. The feedback node can be isolated from the DAC’s correction voltage by placing the VOUT0 pin in high-impedance mode. Since the GPIO_CFG pin is pulled-up to VDD, the LTC2970’s GPIO_0 pin will automatically hold the power supply’s RUN/SS pin low after power-up until the I2C interface releases it. VIN IN VDD OUT 1/2 LTC2970 0.1μF GPIO_CFG I+ VIN0_BM I– VIN0_BP DC/DC CONVERTER R30 R20 RUN/SS FB R10 GND SGND ALERT VOUT0 SCL VIN0_AP SDA I2C BUS + LOAD VDC0 – IOUT0 GPIO_0 R40 VIN0_AM REF GND ASEL0 ASEL1 0.1μF 29701 F01 Figure 1. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors 29701fc 27 LTC2970/LTC2970-1 U U W U APPLICATIO S I FOR ATIO ⎛ R20 ⎞ VDC0,NOM = VFB • ⎜ 1+ + I • R20 ⎝ R10 ⎟⎠ FB 4-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors The following 4-step procedure should be used to quickly calculate the resistor values shown for the Typical Application Circuit shown in Figure 1. R20 • R30 (R40 • 236μA − VFB0 − 10mV ) VDC0,MIN ≤ VDC0,NOM − 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC0,NOM, and solve for R10. VDC0,NOM is the desired output voltage of the DC/DC converter when the LTC2970’s VOUT0 pin is in a high impedance state. VFB0 is the voltage at the converter’s feedback node when the loop is in regulation, and IFB0 is the feedback node’s input current. R10 = R20 • VFB0 VDC,NOM − IFB0 • R20 − VFB0 (1) 2. Solve for the maximum value of R30 that yields the maximum required DC/DC converter output voltage VDC0,max. When VOUT0 is at 0V, the output of the DC/DC converter is at its maximum voltage. Note that the 10mV term corresponds to the maximum offset voltage of the IDAC 1X voltage buffer. R30 ≤ R20 • ( VFB − 10mV ) VDC,MAX − VDC,NOM (2) 3. Solve for the minimum value of R40 that’s needed to yield the minimum required DC/DC converter output voltage VDC0,MIN. (4) VDC0,MAX ≥ VDC0,NOM + (5) R20 • ( VFB0 − 10mV ) R30 The margining resolution is bounded by: R20 • R40 • 276μA volts/DAC LSB VRES ≤ R30 256 (7) Margining DC/DC Converters with a TRIM Pin Figure 2 illustrates a typical application circuit for margining the output voltage of a DC/DC converter with a TRIM Pin. The LTC2970’s VOUT0 pin connects directly to the TRIM pin through resistor R30 and the IOUT0 pin is terminated at the converter's point-of-load ground throught R40. Resistors R30 and R40 give this application circuit two degrees of freedom so that the margin-up and margindown percentages can be specified independently. Following power-up, the LTC2970's VOUT0 pin defaults to a high-impedance state. If the soft-connect feature is used, 8V TO 15V 0.1μF 12VIN VIN VDD VO+ 1/2 LTC2970 The DC/DC converter output voltage will be a minimum when IDAC0 is at its full-scale current. In order to guarantee that R40 is large enough, assume that IDAC0’s full-scale current is at the datasheet minimum of 236μA. (6) 0.1μF GPIO_CFG R30 VOUT0 TRIM DC/DC CONVERTER VIN0_AP ALERT SCL I2C BUS SDA VSENSE+ + R40 ≥ ( ) R30 + V + 10mV R20 FB (3) 236μA VDC,NOM − VDC,MIN • 4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution. ON/OFF LOAD VDC0 – VSENSE– VO– IOUT0 GPIO_0 R40 VIN0_AM REF GND ASEL0 ASEL1 0.1μF 29701 F02 Figure 2. LTC2970 Application Circuit for DC/DC Converters with a TRIM Pin 29701fc 28 LTC2970/LTC2970-1 U W U U APPLICATIO S I FOR ATIO the LTC2970 will automatically find the IDAC code that most closely approximates the TRIM pin's open-circuit voltage before enabling VOUT0. Note: The relationship between VTRIM and the converter's output is typically non-inverting, so be sure to set the LTC2970's CH0_a_idac_pol bit to 1 in order to allow the voltage servo feature to function properly. DC/DC converters with a TRIM pin are usually margined high or low by connecting an external resistor between the TRIM pin and either the VSENSE+ or VSENSE– pin. The relationships between these resistors and the Δ% change in the output voltage of the DC/DC converter are typically expressed as: RTRIM _ DOWN = RTRIM • 50 − RTRIM ΔDOWN % (8) RTRIM _UP = ⎡ RTRIM • VDC • (100 + ΔUP %) RT RIM • 50 ⎤ − RTRIM ⎥ − ⎢ ΔUP % 2 • VREF • ΔUP % ⎣ ⎦ (9) Tracking with the LTC2970-1 A typical LTC2970-1 tracking application circuit is shown in Figure 3 (the sequence of events for tracking are described in sections 9 and 10 of the Operation section). The GPIO_0 and GPIO_1 pins are tied directly to their respective DC/DC converter RUN/SS pins. Since GPIO_CFG is pulled-up to VDD, the LTC2970-1 will automatically hold off the DC/DC converters after power-up by asserting open drain outputs GPIO_0 and GPIO_1 low. N-channel FETs Q10/11 and diodes D10/11 form unidirectional range switches around resistors R30A/31A while GPIO_CFG is high. These range switches allow the LTC2970-1’s VOUT0 and VOUT1 pins to drive the converter outputs all the way to/from ground through resistors R30B/31B. When GPIO_CFG pulls low, N-channel FETs Q10 and Q11 will turn off. R30A/31A and R30B/31B then combine in series for normal margin operation. The 100k/0.1μF low-pass filter in series with the gates of Q10/11 minimizes charge injection into the feedback nodes of the DC/DC converters when GPIO_CFG pulls low. 8V TO 15V where RTRIM is the resistance looking into the TRIM pin, VREF is the TRIM pin's opern-circuit output voltage and VDC is the DC/DC converter's nominal output voltage. ΔUP% and ΔDOWN% denote the percentage change in the converter's output voltage when margining up or down respectively. 0.1μF 12VIN VDD 10k Q10, Q11: 2N7002 D10, D11: MMBD4448V *SOME DETAILS OMITTED FOR CLARITY 0.1μF GPIO_CFG 100k GPIO_0 RUN/SS D10 LTC2970-1 VIN IN DC/DC CONVERTER Q10 VOUT0 2-Step Resistor Selection Procedure for DC/DC Converters with a TRIM Pin R30B ALERT I2C BUS The following two-step procedure should be used to calculate values for resistors R30 and R40 shown in Figure 2. R10 SCL IOUT0 SDA 0.1μF RUN/SS D11 Q11 R31B R11 (10) GND VDC1 OUT FB R31A R21 IOUT1 R41 29701 F03 2. Solve for R40: ⎛ ΔUP % ⎞ VREF • R40 ≥ ⎜ 1 + ΔDOWN % ⎟⎠ 236μ A ⎝ VIN IN DC/DC CONVERTER VOUT1 ⎛ 50 − ΔDOWN % ⎞ R30 ≤ RTRIM • ⎜ ⎝ ΔDOWN % ⎟⎠ R20 R40 GPIO_1 1. Solve for R30: VDC0 OUT FB R30A Figure 3. LTC2970-1 Tracking Application Circuit (11) 29701fc 29 LTC2970/LTC2970-1 U U W U APPLICATIO S I FOR ATIO 7-Step Procedure for Calculating Tracking Application Circuit Resistor Values, Counter Delay Values, and Terminal IDAC Codes The following 7-step procedure should be used to calculate the resistor values, tracking counter delays, and terminal IDAC codes for the Tracking Application Circuit shown in Figure 3. 1. Assume a value for R20 and solve for R21. VDCn,NOM is the output voltage of the DC/DC converter when the LTC2970’s VOUTn pin is in a high impedance state. VDC1,NOM R21= R20 • (12) VDC0,NOM Due to the forward drop of diodes D10 and D11 (0.8V max), the minimum value for R40 = R41 from expression (14) may result in small or even negative values of R30 and R31 in Step 4. If this is the case, assume a minimum allowable value for R3nB, and use the following expression to calculate the minimum value R40 = R41: R40 = R41≥ (15) ⎛ R3nB R3nB ⎞ VFBn • ⎜ 1+ + + 0.8 V + 10mV ⎝ R1n R2n ⎟⎠ 236μA Note: Use the channel whose parameters yield the maximum value for R40 = R41. 4. Solve for R30B and R31B. 2. Solve for R10 and R11. R1n = R2n (13) ⎛ VDCn,NOM ⎞ − 1⎟ ⎜⎝ V ⎠ FBn Solve for the upper limits of R30B and R31B and then determine which resistor value constrains the maximum value of the other resistor using Equation 17. R3nB ≤ (R4n • 236μA − VFBn − 0.8V − 10mV ) 3. Solve for R40 and R41. For simplicity, this procedure assumes that R40 = R41. VDCn,MAX and VDCn,MIN are the maximum and minimum converter output margin voltages, respectively. The value of R40 = R41 is constrained by: R40 = R41≥ ( ( ) ) R30B R31B = R20 R21 (16) (17) 5. Solve for R30A and R31A. (14) ⎛ VDCn,NOM − VDCn,MIN ⎞ + 1⎟ + 10mV VFBn • ⎜ ⎜⎝ VDCn,MAX − VDCn,NOM ⎟⎠ 236μA 1 ⎞ ⎛ 1 VFBn • ⎜ + ⎝ R1n R2n ⎟⎠ R30A and R31A are constrained by: R3nA ≤ (18) R2n ⎛ R2n ⎞ ⎛ VDCn,MAX − VDCn,NOM ⎞ ⎜⎝ 1+ R1n ⎟⎠ • ⎜ ⎟ VDCn,NOM ⎝ ⎠ − R3nB 29701fc 30 LTC2970/LTC2970-1 U W U U APPLICATIO S I FOR ATIO 6. Solve for Channel 1’s tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK(). CH1_ A _ DELAY _ TRACK() = R31B VDC1,NOM′ − VDC0,NOM′ • R21 (counts) 1μA / count • R41 ( ) (19) From Equation 2: R30 ≤ Note: VDCn,NOMʹ is based on the final values of R2n and R1n. If the result for CH1_A_DELAY_TRACK() is less than 0, apply the unsigned result to the CH0_A_DELAY_TRACK() register. 7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0]. Chn _ a _ idac _ track[7 : 0] = VFBn 255 − (LSB’s) 1μA / LSB • R4n 2. Solve for the value of R30 that yields the maximum required DC/DC converter output voltage VDC0,MAX (20) Note: This formula assumes that the Chn_a_idac_pol bit is set to 0. Margining Application Circuit Design Example R20 • ( VFB − 10mV ) = VDC,MAX − VDC,NOM 10.0kΩ • ( 0.8 V − 10mV ) = 7, 861Ω 3.63V − 2.625V Let R30 = 7.68kΩ. 3. Solve for the value of R40 that’s needed to yield the minimum required DC/DC converter output voltage VDC0,MIN. From Equation 3: R40 ≥ +V ( VDC,NOM − VDC,MIN ) • RR30 20 FB = 236μA .96kΩ + 0.8 V (2.625V − 1.62V ) • 710 kΩ = 6, 780Ω 236μA Consider the LTC2970 application circuit shown in Figure 1. Channel 0 is a DC/DC converter whose output needs to be varied between 3.63V and 1.62V. VFB0 = 0.8V and assume that IFB0 = 0A. Let R40 = 6.81kΩ. 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC0,NOM, and solve for R10. From Equations 4, 5, and 6: Let VDC0,NOM = 2.625V (the average of 3.63V and 1.62V) and assume that R20 = 10kΩ. From Equation 1: R10 = R20 • VFB0 = VDC,NOM − IFB0 • R20 − VFB0 10kΩ • 0.8 V = 4, 384Ω 2.625V − 0.8 V Let R10 = 4.37kΩ (the nearest E192 series resistor value). 4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution. ⎛ R20 ⎞ VDC0,NOM = VFB • ⎜ 1+ + I • R20 = ⎝ R10 ⎟⎠ FB 10kΩ ⎞ ⎛ 0.8 V • ⎜ 1+ = 2.631V ⎝ 4.37kΩ ⎟⎠ VDC0,MIN < VDC0,NOM − R20 • ( 236μA • R40 − VFB0 ) R30 10kΩ • 7.68kΩ (236μA • 6.81kΩ − 0.8V − 10mV ) = 1.59V → VDC0,MIN < 2.631V − 29701fc 31 LTC2970/LTC2970-1 U W U U APPLICATIO S I FOR ATIO VDC0,MAX > VDC0,NOM + R20 • ( VFB0 − 10mV ) R30 10kΩ • 7.68kΩ (0.8V − 10mV ) = 3.660V → VDC0,MAX > 2.631V + From Equation 7, the margining resolution will be less than: R20 • R40 • 276μA R 30 VRES < = 256 10kΩ • 6.65kΩ • 276μA 7.68kΩ = 9.33mV/LSB 256 Margining DC/DC Converter with TRIM Pin Design Example The output voltage of the DC/DC converter in Figure 2 needs to be margined ±10% about its nominal value. Assume that RTRIM = 10.22kΩ and VREF = 1.225V. Tracking Application Circuit Design Example Consider the LTC2970-1 application circuit shown in Figure 3. Channel 0 is a 1.8V DC/DC converter while channel 1 is a 2.5V switching power supply. Both converters have a feedback node voltage of 0.8V and need to track on and off coincidentally. In addition, a margin range of +5% and –10% is required for each supply. 1. Assume a value for R20 and solve for R21. Let R20 = 5,970Ω. From Equation 12: VDC1,NOM R21= R20 • VDC0,NOM = 5, 970Ω • 2.5V = 8, 292Ω 1.8 V Let R21 = 8,250Ω (the nearest E192 Series resistor value). 2. Solve for R10 and R11. From Equation 13: R10 = R20 = ⎛ VDC0,NOM ⎞ − 1⎟ ⎜⎝ V ⎠ FB0 5, 970Ω = 4, 776Ω ⎛ 1.8 V ⎞ ⎜⎝ 0.8 V − 1⎟⎠ 1. Solve for R30 using Equation 10: ⎛ 50 − ΔDOWN % ⎞ R30 ≤ RTRIM • ⎜ % ⎟⎠ ⎝ Δ DOWN ⎛ 50 − 1 0 ⎞ = 10 . 22kΩ • ⎜ = 40, 880Ω ⎝ 10 ⎟⎠ R11= R21 ⎛ VDC1,NOM ⎞ − 1⎟ ⎜⎝ V ⎠ = FB1 8, 250Ω = 3, 882Ω ⎛ 2.5V ⎞ ⎜⎝ 0.8 V − 1⎟⎠ Let R10 = 4,750Ω and R11 = 3,880Ω. 3. Solve for R40 and R41. Let R30 = 39.2kΩ. 2. Solve for R40 using Equations 11: ⎛ ΔUP % ⎞ VREF • R40 ≥ ⎜ 1 + ΔDOWN % ⎟⎠ 236μ A ⎝ ⎛ 10 ⎞ 1 . 225V = ⎜ 1+ ⎟ • = 10, 381Ω ⎝ 10 ⎠ 236μ A Let R40 = 10.5kΩ. Assume that R40 = R41. R40 = R41≥ ( ( ) ) ⎛ VDCn,NOM − VDCn,MIN ⎞ VFBn • ⎜ + 1⎟ + 10mV ⎜⎝ VDCn,MAX − VDCn,NOM ⎟⎠ = 236μA ⎛ (1− 0.9) ⎞ 0.8 V • ⎜ + 1 + 10mV ⎝ (1.05 − 1) ⎟⎠ = 10, 212Ω 236μA Let R40 = R41 = 10.5kΩ 29701fc 32 LTC2970/LTC2970-1 U W U U APPLICATIO S I FOR ATIO 4. Solve for R30B and R31B. (R40 • 236μA − VFB0 − 0.8V − 10mV ) = R30B ≤ 1 ⎞ ⎛ 1 + VFB0 • ⎜ ⎝ R10 R20 ⎟⎠ (10.5kΩ • 236μA − 0.8 V − 0.8 V − 10mV) = 2, 870Ω 1 1 ⎞ ⎛ + 0.8 V • ⎜ ⎝ 4, 750Ω 5, 970Ω ⎟⎠ R31B ≤ (R41• 236μA − VFB1 − 0.8V − 10mV ) = 1 ⎞ ⎛ 1 VFB1 • ⎜ + ⎝ R11 R21⎟⎠ (10.5kΩ • 236μA − 0.8 V − 0.8 V − 10mV) = 2, 863Ω 1 1 ⎞ ⎛ + 0.8 V • ⎜ ⎝ 3, 880Ω 8, 250Ω ⎟⎠ For coincident tracking to occur Equation 17 also must be satisfied: R30B R31B = R20 R21 → R30B = → R31B = R21 ⎛ R21⎞ ⎛ VDC1,MAX − VDC1,NOM ⎞ ⎜⎝ 1+ R11⎟⎠ • ⎜ ⎟ VDC1,NOM ⎝ ⎠ − R31B = 8, 250Ω − 2, 890Ω = 49, 888Ω ⎛ 8, 250Ω ⎞ ⎛ 1.05 − 1⎞ ⎜⎝ 1+ 3, 880Ω ⎟⎠ • ⎜⎝ 1 ⎟⎠ Let R30A = 49.9kΩ and R31A = 48.7kΩ. 6. Solve for Channel 1’s tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK(). First, recalculate the values of VDCn,NOM based on the final values of R1n and R2n: ⎛ R20 ⎞ + I • R20 = VDC0,NOM′ = VFB • ⎜ 1+ ⎝ R10 ⎟⎠ FB ⎛ 5, 970Ω ⎞ + 0 = 1.805V 0.8 V • ⎜ 1+ ⎝ 4, 750Ω ⎟⎠ ⎛ 8, 250Ω ⎞ VDC1,NOM′ = 0.8 V • ⎜ 1+ + 0 = 2.501V ⎝ 3, 880Ω ⎟⎠ R31B 2, 863Ω • R20 = • 5, 970Ω = 2, 078Ω R21 8, 250Ω R30B 2, 870Ω • R21= • 8, 250Ω = 3, 957Ω R20 5, 970Ω Let R30B = 2,100Ω and R31B = 2,890Ω. 5. Solve for R30A and R31A. Referring to Equation 18: R30 A ≤ R31A ≤ R20 − R30B = ⎛ R20 ⎞ ⎛ VDC0,MAX − VDC0,NOM ⎞ ⎜⎝ 1+ R10 ⎟⎠ • ⎜ ⎟ VDC0,NOM ⎝ ⎠ 5, 970Ω − 2,100Ω = 50, 806Ω ⎛ 5, 970Ω ⎞ ⎛ 1.05 − 1⎞ ⎜⎝ 1+ 4, 750Ω ⎟⎠ • ⎜⎝ 1 ⎟⎠ Next, apply Equation 19: CH1_ A _ DELAY _ TRACK() = R31B VDC1,NOM′ − VDC0,NOM′ • R21 = 1μA / count • R41 Ω (2.501V − 1.805V ) • 82,,890 250Ω = 23 counts 1μA / count • 10.5kΩ ( ) 7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0]. Ch0 _ a _ idac[7 : 0] = Ch1_ a _ idac[7 : 0] = 0.8 V 255 − = 179 1μA / LSB • 10.5kΩ 29701fc 33 LTC2970/LTC2970-1 U U W U APPLICATIO S I FOR ATIO drop across resistor RSENSE. Since the VDD pin voltage is monitored by the LTC2970, its tolerance can be accounted for when calculating the point of load voltage. Transistor Q1 allows the IOUT0 pin to force current into the converter’s feedback node without forward biasing the LTC2970’s IOUT0 body diode. Note that IOUT0’s output current defaults to 128μA after the LTC2970 comes out of power-on reset. 2.7 2.4 VDC1 2.1 VOLTS 1.8 VDC0 1.5 1.2 0.9 0.6 0.3 0 29701 F04 5ms/DIV 15-Bit Programmable Power Supply Application Circuit Figure 4. Tracking Design Example DC/DC Converter Output Waveforms Figure 4 shows the DC/DC converter output voltages for this design example tracking-up and tracking-down. Temperature Sensor Conversion The LTC2970's internal temperature sensor output is proportional to absolute temperature (PTAT). In order to convert the ADC reading to degress Celsius, apply the following formula: result (°C) = ADC_temp_sensor_reading − 273.15 4 (21) Negative Power Supply Application Circuit Figure 5 shows the LTC2970 controlling a negative power supply. The R30/R40 resistor divider translates the point of load voltage to the LTC2970’s VIN0_A inputs while the VIN0_B inputs monitor the converter’s input current I • R Figure 6 illustrates how both servo channels of the LTC2970 can be configured to adjust a single DC/DC converter over a 15-bit dynamic range. R30 and R31 are sized to force 1 bit of overlap between the coarse (channel 0) and fine (channel 1) servo loops. One coarse servo iteration should be performed first on channel 0 with IDAC1 programmed to mid-scale, and then channel 1 can be programmed to servo to the desired voltage. Programmable Reference Application Circuit Figure 7 shows a LTC2970 configured as a programmable reference that can span a 0V to 3.5V range with a resolution of 100μV and an absolute accuracy of less than ±0.5%. The two IDAC’s are paralleled by terminating IDAC1’s output resistor in the VOUT0 output and taking the output of the composite DAC from VOUT1. IDAC0 should servo once with IDAC1 set to mid-scale, and then IDAC1 can servo once, continuously, or trigger on drift to the desired target voltage. 8V TO 15V 8V TO 15V 0.1μF 0.1μF R20 0.1μF 12VIN VDD 12VIN VIN VIN0_AP IN OUT R10 R30 RUN/SS FB 0.1μF 29701 F05 R31 ≥ R30 • 128 R41 = R40 LOAD ( ) ( IOUT0 R41 SCL I2C BUS SDA GPIO_0 R40 VIN0_AM GND SGND ALERT IOUT1 LOAD R10 GND ASEL0 ASEL1 VEE VIN0_AP VIN1_AP REF R20 R10 VOUT0 R31 R20 OUT FB DC/DC CONVERTER SDA VIN0_BM IOUT0 VIN I2C BUS SCL Q1 TP0610K DC/DC CONVERTER GPIO_CFG VOUT1 ALERT RSENSE 0.1μF LTC2970 CLOAD 1/2 LTC2970 VIN0_BP GND VDD + VIN0_AM REF VIN1_AM GND ASEL0 ASEL1 0.1μF ) VOUT = VDD – 1 + R30 • VIN0_AP – VIN0_AM R40 29701 F06 Figure 5. Negative Power Supply Application Circuit Figure 6. Programmable Power Supply Application Circuit 29701fc 34 LTC2970/LTC2970-1 U PACKAGE DESCRIPTIO UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696) 2.65 ± 0.10 (2 SIDES) R = 0.115 TYP 23 24 0.75 ± 0.05 4.00 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP 0.70 ±0.05 0.40 ± 0.05 PIN 1 TOP MARK (NOTE 6) 4.50 ± 0.05 1 3.10 ± 0.05 2 2.65 ± 0.05 (2 SIDES) 5.00 ± 0.10 (2 SIDES) 0.25 ±0.05 0.50 BSC 3.65 ± 0.05 (2 SIDES) 4.10 ± 0.05 5.50 ± 0.05 3.65 ± 0.10 (2 SIDES) (UFD24) QFN 0505 0.200 REF PACKAGE OUTLINE 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE U TYPICAL APPLICATIO 8V TO 15V 0.1μF 12VIN VDD LTC2970 0.1μF VIN1_AP VIN1_AM VIN0_AP VIN0_AM VOUT1 I2C BUS SCL SDA IOUT1 22μF + VOUT – ALERT 100Ω VOUT0 10Ω IOUT0 12.7k REF GND ASEL0 ASEL1 0.1μF 29701 F07 Figure 7. Programmable Reference Application Circuit 29701fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2970/LTC2970-1 U TYPICAL APPLICATIO 8V TO 15V 10 R50 VIN IN 0.1μF 12VIN VDD OUT 9 10k 4 I+ 3 I– DC/DC CONVERTER 0 11 1 R30 GPIO_CFG VIN0_BM 0.1μF 20 VIN0_BP VOUT0 VIN0_AP R20 RUN/SS FB LOAD R10 14 IOUT0 R40 PGND SGND 2 VIN0_AM ALERT SCL 16 SDA GPIO_0 17 18 19 I2C BUS SMBUS COMPATIBLE ( ) LTC2970 R51 VIN IN OUT 8 I+ 7 I– 12 DC/DC CONVERTER 1 5 R31 VIN1_BM VIN1_BP VOUT1 VIN1_AP R21 RUN/SS FB LOAD R11 PGND SGND 13 IOUT1 R41 6 VIN1_AM REF 23 0.1μF 15 RGND GPIO_1 24 GND ASEL0 ASEL1 25 22 21 29701 TA01 Figure 8. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2920-1/LTC2920-2 Single/Dual Power Supply Margining Controllers Symmetric/Asymmetric High and Low Voltage Margining LTC2921/LTC2922 Power Supply Trackers with Input Monitors 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches LTC2923 Power Supply Tracking Controller Up to 3 Supplies LTC2924 Quad Power Supply Sequencer Voltage Monitoring and Sequence Error Detection and Reporting LTC2925 Multiple Power Supply Tracking Controller Power Good Timer, Remote Sense Switch LTC2926 MOSFET Controller Power Supply Tracker Up to 3 Modules LTC2927 Single Power Supply Tracker Point of Load Applications 29701fc 36 Linear Technology Corporation 0308 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006