MICREL SY10E175JCTR

9-BIT LATCH
WITH PARITY
FEATURES
DESCRIPTION
9-bit latch
Extended 100E VEE range of –4.2V to –5.5V
Parity detection/generation
800ps max. D to Output
Reset
Internal 75KΩ input pull-down resistors
Fully compatible with Motorola MC10E/100E175
Available in 28-pin PLCC package
The SY10/100E175 are 9-bit latches. They also feature
a tenth latched output (ODDPAR) which is formed as the
odd parity of the nine data inputs (ODDPAR is HIGH if
an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by
using D8 as the parity-type select (L = even parity, H =
odd parity) and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a
logical high and makes the latch transparent when placed
at a logic low level.
Q
Q0
Q8
Q7
VCCO
D
D6
D7
D0
D8
VCCO
PIN CONFIGURATION
BLOCK DIAGRAM
EN
R
25 24 23 22 21 20 19
Q
Q8
EN
Q6
D4
27
17
Q5
D3
VEE
28
16
15
VCC
Q4
LEN
MR
D2
2
TOP VIEW
PLCC
J28-1
1
3
4
R
5
D
Q
6
7
8
9
14
Q3
13
VCCO
12
Q2
10 11
VCCO
Q1
D
18
D0
D8
26
VCCO
ODDPAR
Q0
bits
1–7
D5
D1
■
■
■
■
■
■
■
■
SY10E175
SY100E175
ODDPAR
EN
PIN NAMES
R
LEN
Pin
MR
Function
D0 – D8
Data Inputs
LEN
Latch Enable
MR
Master Reset
Q0 – Q8
Data Outputs
ODDPAR
Parity Output
VCCO
VCC to Output
Rev.: C
1
Amendment: /1
Issue Date: February, 1998
SY10E175
SY100E175
Micrel
TRUTH TABLE
D
LEN
MR
Q
ODDPAR
H
L
L
H
H if odd no. of Dn HIGH
H if odd no. of Dn HIGH
L
L
L
L
X
H
L
Q0
X
X
H
L
Q0
L
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
IIH
Input HIGH Current
IEE
Power Supply Current
10E
100E
TA = +25°C
TA = +85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
mA
—
—
—
110
110
132
132
—
—
110
110
132
132
—
—
110
127
132
152
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
TA = +25°C
TA = +85°C
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
tPLH
tPHL
Propagation Delay to Output
D to Q
D to ODDPAR
LEN to Q
LEN to ODDPAR
MR to Q (tPHL)
MR to ODDPAR (tPHL)
450
850
525
525
525
525
600
1150
700
700
700
700
800
1450
900
900
900
900
450
850
525
525
525
525
600
1150
700
700
700
700
800
1450
900
900
900
900
450
850
525
525
525
525
600
1150
700
700
700
700
800
1450
900
900
900
900
tS
Set-up Time
D (Q)
D (ODDPAR)
275
900
100
700
—
—
275
900
—
—
—
—
275
900
—
—
—
—
Hold Time
D (Q)
D (ODDPAR)
175
–300
–100
–700
—
—
175
–300
—
—
—
—
175
–300
—
—
—
—
tRR
Reset Recovery Time
850
600
—
850
600
—
850
600
—
tskew
Within-Device Skew
LEN, MR
D to Q
D to ODDPAR
—
—
—
75
75
200
—
—
—
—
—
—
75
75
200
—
—
—
—
—
—
75
75
200
—
—
—
300
500
800
300
500
800
300
500
800
tH
tr
tf
Rise/Fall Times
20–80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
Unit
Condition
ps
—
ps
—
ps
—
ps
—
ps
1
ps
—
PRODUCT ORDERING CODE
Ordering
Code
2
Package
Type
Operating
Range
SY10E175JC
J28-1
Commercial
SY10E175JCTR
J28-1
Commercial
SY100E175JC
J28-1
Commercial
SY100E175JCTR
J28-1
Commercial
SY10E175
SY100E175
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
3
SY10E175
SY100E175
Micrel
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4