NCP729 200 mA Ultra-Low Noise Very-Low Iq, High PSRR, LDO Linear Voltage Regulator http://onsemi.com The NCP729 is a 200 mA LDO suitable to provide clean analog power supply rails for noise sensitive applications. This device features Ultra−Low Noise performance, High Power Supply Rejection Ratio and Very good transient response characteristics. Very Low Dropout and Very Low Quiescent Current makes this LDO an attractive choice for wide range of battery powered, portable products. Current Limit and Thermal Shutdown provide protection during failure conditions. NCP729 is available in 1.06 mm x 1.06 mm Chip Scale Package and it is stable with small 1 mF Ceramic capacitors. DEVICE MARKING INFORMATION Features • • • • • • • • • • • • Operating Input Voltage Range: 2.0 V to 5.5 V Fixed Voltage Options Available: 0.8 V to 3.5 V Very Low Quiescent Current: Max. 50 mA over Temperature Ultra Low Noise: 10 mVRMS from 100 Hz to 100 kHz Very Low Dropout: 86 mV Typical at 200 mA ±2% Accuracy over Full Load, Line and Temperature Variations High PSRR: 72 dB at 1 kHz Thermal Shutdown and Current Limit Protections Stable with a 1 mF Ceramic Output Capacitor Available in 1.06 mm x 1.06 mm 4−bump CSP Package Active Output Discharge for Fast Turn−Off These are Pb−free Devices IN CIN OFF ON XXX YWW XXX = Specific Device Code Y = Year WW = Work Week PIN CONNECTIONS EN IN A1 A2 B1 B2 (Top View) PDAs, Tablets, GPS, Smartphones Wireless Handsets, Wireless LAN, Bluetooth, Zigbee Portable Medical Equipment Other Battery Powered Applications VIN A1 GND OUT Typical Applications • • • • 4 BUMP CSP FC SUFFIX CASE 568AD EN NCP729 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. VOUT OUT COUT GND 1 mF Ceramic Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 2 1 Publication Order Number: NCP729/D NCP729 IN ENABLE LOGIC EN THERMAL SHUTDOWN UVLO BANDGAP REFERENCE MOSFET DRIVER WITH CURRENT LIMIT OUT AUTO LOW POWER MODE ACTIVE DISCHARGE EN EEPROM GND Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. 4−bump CSP Pin Name Description B2 OUT Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to ground to assure stability. B1 GND Power supply ground. Soldered to large copper plane allows for better heat dissipation. A1 EN Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode. A2 IN Input pin. A small capacitor is needed from this pin to ground to assure stability. Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VIN −0.3 V to 6 V V Output Voltage VOUT −0.3 V to VIN + 0.3 V V Enable Input VEN −0.3 V to VIN + 0.3 V V Output Short Circuit Duration tSC ∞ s TJ(MAX) 150 °C TSTG −55 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Input Voltage (Note 1) Maximum Junction Temperature Storage Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. http://onsemi.com 2 NCP729 Table 3. THERMAL CHARACTERISTICS Rating Symbol Thermal Characteristics, 4−bump CSP package Thermal Resistance, Junction−to−Air (Note 3) Thermal Resistance, Junction−to−Air (Note 4) Value RqJA Unit °C/W 90 157 3. Specified according to JEDEC 51.7 4−Layer Board. 4. Single component mounted on 4−Layer Board, 480 mm2, Top Layer thickness: 1 oz, Cu Area: 100 mm2. Table 4. ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VIN = VOUT(NOM) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, CIN = COUT = 1 mF unless otherwise noted. Typical values are at TJ = +25°C. (Note 5) Test Conditions Parameter Operating Input Voltage Symbol Min VIN Typ Max Unit 2.0 5.5 V −2 +2 % Output Voltage Accuracy VOUT + 0.3 V ≤ VIN ≤ 5.5 V 0 mA ≤ IOUT ≤ 200 mA VOUT Line Regulation VOUT + 0.3 V ≤ VIN ≤ 5.5 V RegLINE 150 mV/V Load Regulation IOUT = 0 mA to 200 mA RegLOAD 2 mV/mA Dropout Voltage (Note 6) VDO = VIN – (VOUT(NOM) – 100 mV) IOUT = 200 mA VDO 170 100 90 80 80 70 65 220 140 130 120 120 110 100 mV Quiescent Current IOUT = 0 mA IQ 35 50 mA Ground Current IOUT = 200 mA IGND 255 155 300 200 mA Disable Current VEN = 0 V IDIS 0.3 1 mA Output Current Limit VOUT = VOUT(NOM) – 100 mV IOUT 250 400 530 mA Output Short Circuit Current VOUT = 0 V ISC 250 400 530 mA EN Pin Threshold Voltage High Threshold Low Threshold VEN Voltage increasing VEN Voltage decreasing VEN_HI VEN_LO 0.9 EN Pin Input Current VEN = 5.5 V IEN 100 Turn−on Time VOUT = 0 V to 98% VOUT(NOM), after assertion of the EN tON 150 ms Power Supply Rejection Ratio VIN = 3.8 V, VOUT = 3.3 V VPP = 100 mV IOUT = 200 mA PSRR 74 72 56 dB Output Noise Voltage VOUT = 1.8 V, IOUT = 200 mA f = 100 Hz to 100 kHz VN 10 mVrms Line Transient VOUT + 0.3 V ≤ VIN ≤ VOUT + 1.3 V or VOUT + 0.3 V ≤ VIN ≤ VOUT + 1.3 V in 1 ms ±20 mV Load Transient IOUT = 1 mA to 200 mA or IOUT = 200 mA to 1 mA in 1 ms DVOUT ±80 mV Undervoltage Lock−out VIN rising from 0 V to 5.5 V UVLO Thermal Shutdown Temperature Temperature increasing from TJ = +25°C TSD Thermal Shutdown Hysteresis Temperature falling from TSD TSDH VOUT = 1.8 V VOUT = 2.5 V VOUT = 2.6 V VOUT = 2.8 V VOUT = 2.85 V VOUT = 3.0 V VOUT = 3.3 V VOUT < 1.8 V VOUT ≥ 1.8 V V f = 100 Hz f = 1 kHz f = 10 kHz 0.4 1.3 1.6 500 1.9 165 − 20 nA V °C − °C 5. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 6. Characterized when VOUT falls 100 mV below the regulated voltage at VIN = VOUT(NOM) + 0.3 V. http://onsemi.com 3 NCP729 10 VIN = 2.0 V, VOUT = 0.8 V, CIN = COUT = 1 mF, TA = 25°C 1 IOUT = 10 mA 0.1 IOUT = 1 mA IOUT = 200 mA 0.01 0.001 10 100 1K 10 K 100 K 1M 1K 10 K 100 K 1M PSRR (dB) VIN = 2.3 V, VOUT = 1.8 V, CIN = none, COUT = 1 mF, TA = 25°C 100 IOUT = 100 mA 10 K 100 K 1M IOUT = 10 mA 60 50 40 VIN = 3.3 V, VOUT = 2.8 V, CIN = none, COUT = 1 mF, TA = 25°C 30 20 IOUT = 200 mA 1K 10 M IOUT = 1 mA 70 10 0 10 M 10 100 IOUT = 100 mA IOUT = 200 mA 1K 10 K 100 K 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. PSRR, VOUT = 1.8 V, COUT = 1 mF Figure 6. PSRR, VOUT = 2.8 V, COUT = 1 mF 90 10 M 90 IOUT = 1 mA 80 70 60 50 40 30 20 10 10 100 IOUT = 100 mA 10 K 100 K 1M 60 50 40 VIN = 3.8 V, VOUT = 3.3 V, CIN = none, COUT = 4.7 mF, TA = 25°C 30 20 IOUT = 200 mA 1K IOUT = 10 mA 70 IOUT = 10 mA VIN = 3.8 V, VOUT = 3.3 V, CIN = none, COUT = 1 mF, TA = 25°C IOUT = 1 mA 80 PSRR (dB) PSRR (dB) 100 80 40 0 10 90 50 10 IOUT = 200 mA 0.01 Figure 4. Output Voltage Noise, VOUT = 3.3 V, COUT = 1 mF 60 0 IOUT = 1 mA Figure 3. Output Voltage Noise, VOUT = 0.8 V, COUT = 1 mF IOUT = 10 mA 10 IOUT = 10 mA 0.1 FREQUENCY (Hz) 70 20 VIN = 3.6 V, VOUT = 3.3 V, CIN = COUT = 1 mF, TA = 25°C 1 0.001 10 M IOUT = 1 mA 30 10 FREQUENCY (Hz) 80 PSRR (dB) OUTPUT VOLTAGE NOISE (mV/rtHz) OUTPUT VOLTAGE NOISE (mV/rtHz) TYPICAL CHARACTERISTICS 10 10 M 0 10 100 IOUT = 100 mA IOUT = 200 mA 1K 10 K 100 K 1M 10 M FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. PSRR, VOUT = 3.3 V, COUT = 1 mF Figure 8. PSRR, VOUT = 3.3 V, COUT = 4.7 mF http://onsemi.com 4 NCP729 200 CIN = 1 mF, COUT = 1 mF, VOUT = 0.8 V, VIN = 2.0 V TA = 25°C TA = −40°C QUIESCENT CURRENT (mA) 50 0.01 0.1 1 10 100 40 TA = 125°C 120 TA = 25°C 100 TA = −40°C 80 60 40 0.001 0.01 0.1 1 10 100 OUTPUT CURRENT (mA) Figure 9. Ground Current vs. Output Current, VOUT = 0.8 V Figure 10. Ground Current vs. Output Current, VOUT = 3.3 V 50 TA = 125°C TA = 25°C 30 TA = −40°C 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 40 TA = 125°C 35 TA = 25°C 30 TA = −40°C 25 20 15 10 5.5 CIN = 1 mF, COUT = 1 mF, VOUT(NOM) = 3.3 V, IOUT = 0 mA 45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 11. Quiescent Current vs. Input Voltage, VOUT = 0.8 V Figure 12. Quiescent Current vs. Input Voltage, VOUT = 3.3 V 220 180 160 TA = 125°C TA = 25°C 140 120 TA = −40°C 100 80 60 40 0 25 50 5.5 120 CIN = 1 mF, COUT = 1 mF, VOUT(NOM) = 1.8 V 200 1000 OUTPUT CURRENT (mA) 35 20 0 160 140 20 0 1000 CIN = 1 mF, COUT = 1 mF, VOUT(NOM) = 0.8 V, IOUT = 0 mA 45 20 DROPOUT VOLTAGE (mV) GROUND CURRENT (mA) TA = 125°C 0.001 CIN = 1 mF, COUT = 1 mF, VOUT = 3.3 V, VIN = 3.6 V 180 QUIESCENT CURRENT (mA) 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 DROPOUT VOLTAGE (mV) GROUND CURRENT (mA) TYPICAL CHARACTERISTICS 75 100 125 150 175 100 TA = 125°C 90 TA = 25°C 80 TA = −40°C 70 60 50 40 200 CIN = 1 mF, COUT = 1 mF, VOUT(NOM) = 2.8 V 110 0 25 50 75 100 125 150 175 200 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 13. Dropout Voltage vs. Output Current, VOUT = 1.8 V Figure 14. Dropout Voltage vs. Output Current, VOUT = 2.8 V http://onsemi.com 5 NCP729 TYPICAL CHARACTERISTICS 0.820 CIN = 1 mF, COUT = 1 mF, VOUT(NOM) = 3.3 V 110 100 0.815 90 TA = 125°C 80 TA = 25°C 70 60 TA = −40°C OUTPUT VOLTAGE (V) DROPOUT VOLTAGE (mV) 120 50 40 0 25 50 75 100 125 150 175 VIN = 5.5 V 0.800 VIN = 2.0 V 0.795 0.790 0.780 −40 −20 200 1.820 0 20 40 60 80 100 120 140 OUTPUT CURRENT (mA) JUNCTION TEMPERATURE (°C) Figure 15. Dropout Voltage vs. Output Current, VOUT = 3.3 V Figure 16. Output Voltage vs. Temperature, VOUT = 0.8 V 3.340 VOUT = 1.8 V, COUT = CIN = 1 mF, IOUT = 10 mA 3.330 1.810 VIN = 5.5 V 1.800 VIN = 2.1 V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.830 1.790 1.780 3.320 VOUT = 3.3 V, COUT = CIN = 1 mF, IOUT = 10 mA 3.310 VIN = 5.5 V 3.300 VIN = 3.6 V 3.290 3.280 3.270 1.770 1.760 −40 −20 0 20 40 60 80 100 3.260 −40 −20 120 140 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 17. Output Voltage vs. Temperature, VOUT = 1.8 V Figure 18. Output Voltage vs. Temperature, VOUT = 3.3 V 3 OUTPUT VOLTAGE DEVIATION (mV) OUTPUT VOLTAGE DEVIATION (mV) 0.805 0.785 1.840 2 0.810 VOUT = 0.8 V, COUT = CIN = 1 mF, IOUT = 10 mA VIN = 2.0 V or VOUT(NOM) + 0.3 V, COUT = CIN = 1 mF, IOUT = 0 mA to 200 mA 1 0 VOUT = 0.8 V −1 VOUT = 3.3 V −2 −3 −40 −20 0 20 40 60 80 100 120 140 6 5 VIN = 2.0 V or VOUT(NOM) + 0.3 V to 5.5 V, COUT = CIN = 1 mF, IOUT = 10 mA 4 3 VOUT = 0.8 V 2 1 0 −40 −20 VOUT = 3.3 V 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 19. Load Regulation vs. Temperature Figure 20. Line Regulation vs. Temperature http://onsemi.com 6 NCP729 TYPICAL CHARACTERISTICS 550 500 VIN = 2.0 V or VOUT(NOM) + 0.3 V, COUT = CIN = 1 mF, VOUT = VOUT(NOM) − 100 mV 450 SHORT CIRCUIT CURRENT (mA) OUTPUT CURRENT LIMIT (mA) 550 VOUT(NOM) = 3.3 V 400 VOUT(NOM) = 0.8 V 350 300 −40 −20 0 20 40 60 80 100 120 VOUT(NOM) = 3.3 V 400 VOUT(NOM) = 0.8 V 350 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (°C) Figure 21. Output Current Limit vs. Temperature Figure 22. Short Circuit Current vs. Temperature 0.14 ENABLE INPUT CURRENT (mA) VIN = 5.5 V, COUT = CIN = 1 mF, VEN = 0 V VOUT(NOM) = 3.3 V 0.6 0.4 VOUT(NOM) = 0.8 V 0.2 0 20 40 60 80 100 120 0.12 TA = 125°C 0.10 TA = 25°C 0.08 TA = −40°C 0.06 VIN = 3.6 V, VOUT(NOM) = 3.3 V, COUT = CIN = 1 mF, IOUT = 10 mA 0.04 0.02 0 140 0 1 2 3 4 5 6 JUNCTION TEMPERATURE (°C) ENABLE VOLTAGE (V) Figure 23. Shutdown Current vs. Temperature Figure 24. Enable Input Current vs. Enable Voltage 1.2 2.0 VIN = 3.6 V, VOUT = 3.3 V, COUT = CIN = 1 mF, IOUT = 10 mA 1.0 0.8 UVLO THRESHOLD (V) SHUTDOWN CURRENT (mA) 450 JUNCTION TEMPERATURE (°C) 0 −40 −20 ENABLE THRESHOLD (V) 500 300 −40 −20 140 1.0 0.8 VIN = 2.0 V or VOUT(NOM) + 0.3 V, COUT = CIN = 1 mF, VOUT = 0 V (Shorted to GND) VEN Rising 0.6 VEN Falling 0.4 0.2 0 −40 −20 0 20 40 60 80 100 120 1.8 VIN Rising 1.6 VIN Falling 1.4 1.2 VEN = VIN, VOUT = 3.3 V, COUT = CIN = 1 mF, IOUT = 10 mA 1.0 −40 −20 140 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) Figure 25. Enable Threshold vs. Temperature Figure 26. UVLO Threshold vs. Temperature http://onsemi.com 7 NCP729 VIN = 3.3 V VOUT(NOM) = 2.8 V CIN = COUT = 1 mF IOUT = 1 mA TA = 25°C 0V 0V IINRUSH 0V VEN 0V IINRUSH 0 mA 100 ms/DIV Figure 27. Turn−On Response, VOUT = 2.8 V Figure 28. Turn−On Response, VOUT = 1.8 V VIN = 3.3 V VOUT(NOM) = 2.8 V CIN = COUT = 1 mF IOUT = 1 mA TA = 25°C VIN = 2.3 V VOUT(NOM) = 1.8 V CIN = COUT = 1 mF IOUT = 1 mA TA = 25°C VOUT 500 mV/DIV 1 V/DIV 0V 0V VEN 1 V/DIV 0V VEN 0V 2 ms/DIV 2 ms/DIV Figure 29. Turn−Off Response, VOUT = 2.8 V Figure 30. Turn−Off Response, VOUT = 1.8 V 100 mV/DIV VOUT = 2.8 V VIN = 3.3 V VOUT(NOM) = 2.8 V CIN = COUT = 1 mF IOUT = 1 mA ... 200 mA DIOUT/Dt = 200 mA/1 ms TA = 25°C 200 mA/DIV 1 V/DIV VOUT 100 ms/DIV VOUT 100 mV/DIV VIN = 2.3 V VOUT(NOM) = 1.8 V CIN = COUT = 1 mF IOUT = 1 mA TA = 25°C IOUT = 200 mA IOUT = 1 mA VIN = 2.3 V VOUT(NOM) = 1.8 V CIN = COUT = 1 mF IOUT = 1 mA ... 200 mA DIOUT/Dt = 200 mA/1 ms TA = 25°C VOUT = 1.8 V IOUT = 200 mA IOUT = 1 mA 50 ms/DIV 50 ms/DIV Figure 31. Load Transient Response, VOUT = 2.8 V, IOUT = 1 mA to 200 mA Figure 32. Load Transient Response, VOUT = 1.8 V, IOUT = 1 mA to 200 mA http://onsemi.com 8 200 mA/DIV 1 V/DIV VEN 0 mA 200 mA/DIV 500 mV/DIV VOUT 200 mA/DIV 1 V/DIV 1 V/DIV TYPICAL CHARACTERISTICS NCP729 100 mV/DIV VIN = 3.3 V VOUT(NOM) = 2.8 V CIN = COUT = 1 mF IOUT = 10 mA ... 200 mA DIOUT/Dt = 200 mA/1 ms TA = 25°C VOUT = 2.8 V VIN = 2.3 V VOUT(NOM) = 1.8 V CIN = COUT = 1 mF IOUT = 10 mA ... 200 mA DIOUT/Dt = 200 mA/1 ms TA = 25°C 200 mA/DIV 200 mA/DIV 100 mV/DIV TYPICAL CHARACTERISTICS IOUT = 200 mA IOUT = 10 mA IOUT = 200 mA IOUT = 10 mA 20 ms/DIV 20 ms/DIV Figure 33. Load Transient Response, VOUT = 2.8 V, IOUT = 10 mA to 200 mA VIN = 2.3 V VOUT(NOM) = 1.8 V CIN = COUT = 1 mF VOUT = 1.8 V to 0 V TA = 25°C VOUT = 1.8 V 500 mV/DIV 1 V/DIV 0V 300 mA/DIV ISHORT 1 mA 0V ISHORT 1 mA 100 ms/DIV Figure 36. Short−Circuit Response, VOUT = 1.8 V 500 mV/DIV 200 ms/DIV Figure 35. Short−Circuit Response, VOUT = 2.8 V VIN = 4.3 V VIN = 3.3 V VIN = 3.3 V VIN = 2.3 V 40 mV/DIV 300 mA/DIV 500 mV/DIV 40 mV/DIV Figure 34. Load Transient Response, VOUT = 1.8 V, IOUT = 10 mA to 200 mA VIN = 3.3 V VOUT(NOM) = 2.8 V CIN = COUT = 1 mF VOUT = 2.8 V to 0 V TA = 25°C VOUT = 2.8 V VOUT = 1.8 V VOUT = 2.8 V VIN = 3.3 V to 4.3 V DVIN/Dt = 1 V/1 ms VOUT(NOM) = 2.8 V COUT = 1 mF IOUT = 10 mA VOUT = 1.8 V VIN = 2.3 V to 3.3 V DVIN/Dt = 1 V/1 ms VOUT(NOM) = 1.8 V COUT = 1 mF IOUT = 10 mA 200 ms/DIV 200 ms/DIV Figure 37. Line Transient Response, VOUT = 2.8 V Figure 38. Line Transient Response, VOUT = 1.8 V http://onsemi.com 9 NCP729 TYPICAL CHARACTERISTICS 10 Unstable Operation Region ESR (W) 1 VOUT = 0.8 V VOUT = 3.3 V 0.1 Stable Operation Region 0.01 VIN = VOUT(NOM) + 0.3 V or 2 V, COUT = CIN = 1 mF, TA = 25°C 0.001 0 20 40 60 80 100 120 140 160 180 200 IOUT, OUTPUT CURRENT (mA) Figure 39. ESR vs. Output Current http://onsemi.com 10 NCP729 APPLICATIONS INFORMATION General The NCP729 is a high performance 200 mA Very Low Dropout Linear Regulator. This device delivers excellent noise and dynamic performance. It features typical quiescent current of 35 mA at no−load, ultra−low noise of 10 mVRMS and high PSRR of 72 dB at 1 kHz. Such excellent dynamic parameters and small package size make the device an ideal choice for powering the precision analog and noise sensitive circuitry in portable applications. NCP729 requires very small voltage headroom for correct operation. The dropout for 3.3 V voltage option is only 68 mV (typ.) A logic EN input provides ON/OFF control of the output voltage. When the EN is low the device consumes as low as typ. 300 nA from the IN pin. The device is fully protected in case of output overload, output short circuit condition and overheating, assuring a very robust design. Part Number Description C0402C105K8PACTU 1 mF Ceramic ±10%, 10 V, 0402, X5R C1005X5R1A105K -||- GRM155R61A105KE15D -||- 0402ZD105KAT2A -||- MCCA000571 1 mF Ceramic ±10%, 50 V, 1206, X7R ECJ−0EB0J475M 4.7 mF Ceramic ±20%, 6.3 V, 0402, X5R No−load Operation The regulator remains stable and regulates the output voltage properly within the ±2% tolerance limits with no external load applied to the output. Input Capacitor (CIN) Enable Operation It is recommended to connect a minimum of 1 mF Ceramic X5R or X7R capacitor close to the IN pin of the device. This capacitor will provide a low impedance path for unwanted AC signals or noise modulated onto constant input voltage. There is no requirement for the min./max. ESR of the input capacitor but it is recommended to use ceramic capacitors for their low ESR and ESL. A good input capacitor will limit the influence of input trace inductance and power source resistance during sudden load current changes. Larger input capacitor may be necessary if fast and large line/load transients are encountered in the application. The NCP729 uses the EN pin to enable, disable its output and to deactivate, activate the active output discharge function. If the EN pin voltage is <0.4 V the device is guaranteed to be disabled. The pass transistor is turned−off and the active discharge transistor is active so that the output voltage VOUT is pulled to GND through a 1 kW resistor. In the disable state the device consumes as low as typ. 300 nA from the VIN. If the EN pin voltage > 0.9 V the device is guaranteed to be enabled. The output voltage is regulated at the nominal value and the active discharge transistor is turned−off. The EN pin has internal pull−down current source with typ. value of 110 nA which assures that the device is turned−off when the EN pin is not connected. A build in 2 mV of hysteresis in the EN prevents from periodic on/off oscillations that can occur due to noise. In the case where the EN function isn’t required the EN pin should be tied directly to IN. Output Capacitor (COUT) The NCP729 is designed to operate with a small 1.0 mF ceramic capacitor on the output. To assure proper operation it is recommended to use min. 1.0 mF capacitor with the initial tolerance of ±10%, made of X7R or X5R dielectric material types. NCP729 is internally compensated so there is no requirement for the minimum value of Equivalent Series Resistance (ESR) for the COUT but the maximum value of ESR should be less than 500 mW. Larger output capacitors could be used to improve the load transient response or high frequency PSRR. This part is not designed to work with tantalum or electrolytic capacitors on the output due to their large ESR and ESL. The equivalent series resistance of tantalum capacitors is also strongly dependent on the temperature, increasing at low temperatures. The tantalum capacitors are generally more costly than ceramic capacitors. The table below lists examples of suitable output capacitors: Undervoltage Lockout The internal UVLO circuitry assures that the device becomes disabled when the VIN falls below typ. 1.5 V. When the VIN voltage ramps−up the NCP729 becomes enabled for VIN ≥ 1.6 V. The 100 mV hysteresis prevents from on/off oscillations that can occur due to noise on VIN line. Reverse Current The PMOS pass transistor has an inherent body diode which will be forward biased in the case that VOUT > VIN. Due to this fact in cases where the extended reverse current condition is anticipated the device may require additional external protection. http://onsemi.com 11 NCP729 Output Current Limit Load Regulation Output Current is internally limited within the IC to a typical 400 mA. The NCP729 will source this amount of current measured with the output voltage 100 mV lower than the nominal VOUT. The short circuit current flowing to the IN pin when the Output Voltage is directly shorted to ground will be just slightly above 400 mA – typ. 410 mA. The current limit and short circuit were verified to work properly and to secure the part from the damage up to VIN = 5.5 V at TA = 25°C. There is no limitation for the short circuit duration. The NCP729 features excellent load regulation of typical 200 mV in the 0 mA to 200 mA range. Due to this fact at large load currents the major contributors to the output voltage shift will be the junction temperature increase and the PCB trace resistance. Line Regulation The IC features very good line regulation of typical 150 mV/V measured for the input voltage change from VIN = VOUT + 0.3 V to 5.5 V. Power Supply Rejection Ratio Thermal Shutdown The NCP729 features very good Power Supply Rejection ratio. If desired the PSRR at higher frequencies in the range 100 kHz – 10 MHz can be tuned by the selection of COUT capacitor and proper PCB layout. Additional Ferrite Bead Input filter will further improve the PSRR. When the die temperature exceeds the Thermal Shutdown threshold (TSD – 165°C typical), Thermal Shutdown event is detected and the device is disabled. The IC will remain in this state until the die temperature decreases below the Thermal Shutdown Reset threshold (TSDU − 140°C typical). Once the IC temperature falls below the 140°C the LDO is enabled. The thermal shutdown feature provides protection from a catastrophic device failure due to accidental overheating. This protection is not intended to be used as a substitute for proper heat sinking. Output Noise The IC is designed for ultra−low noise output voltage. Figures 3 and 4 illustrate the noise performance for different VOUT, IOUT, COUT. Generally the noise performance in the indicated frequency range improves with increasing output current. Power Dissipation PCB Layout Recommendations As power dissipated in the NCP729 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. For reliable operation junction temperature should be limited to +125°C. The maximum power dissipation the IC can handle is given by: P D(MAX) + ƪ125 * T Aƫ q JA To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors close to the device pins and make the PCB traces wide. VOUT, VIN and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance for noise pickup. In order to minimize the solution size use 0402 capacitors. Larger copper area connected to the pins will improve the device thermal resistance. The actual power dissipation can be calculated by the formula given in Equation 2. (eq. 1) The power dissipated by the NCP729 for given application conditions can be calculated from the following equations: P D [ V INǒI GND@I OUTǓ ) I OUTǒV IN * V OUTǓ (eq. 2) Table 5. ORDERING INFORMATION Device Voltage Option Marking NCP729FC08T2G 0.8 V 7AA NCP729FC18T2G 1.8 V 7AB NCP729FC25T2G 2.5 V 7AG NCP729FC26T2G 2.6 V 7AC NCP729FC28T2G 2.8 V 7AD NCP729FC285T2G 2.85 V 7AE NCP729FC30T2G 3.0 V 7AH NCP729FC33T2G 3.3 V 7AF Package Shipping † CSP4 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCP729 PACKAGE DIMENSIONS CSP4, 1.06x1.06 CASE 568AD ISSUE A ÈÈ ÈÈ D PIN A1 REFERENCE 2X A B E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A A1 b D E e 0.10 C 2X 0.10 C TOP VIEW 0.10 C A 4X 0.05 C A1 SIDE VIEW NOTE 3 MILLIMETERS MIN MAX −−− 0.70 0.21 0.26 0.30 0.34 1.06 BSC 1.06 BSC 0.50 BSC RECOMMENDED SOLDERING FOOTPRINT* C SEATING PLANE A1 PACKAGE OUTLINE e/2 4X 0.05 C A B 0.03 C e b e 0.50 PITCH B A 1 2 e/2 4X 0.50 0.275 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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