TI MSP430X261X Mixed signal microcontroller Datasheet

MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
-- Active Mode: 365 μA at 1 MHz, 2.2 V
-- Standby Mode (VLO): 0.5 μA
-- Off Mode (RAM Retention): 0.1 μA
Wake-Up From Standby Mode in Less
Than 1 μs
16-Bit RISC Architecture,
62.5-nsInstruction Cycle Time
Three-Channel Internal DMA
12-Bit Analog-to-Digital (A/D) Converter
With Internal Reference, Sample-and-Hold,
and Autoscan Feature
Dual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
On-Chip Comparator
Four Universal Serial Communication
Interfaces (USCIs)
-- USCI_A0 and USCI_A1
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- USCI_B0 and USCI_B1
-- I2Ct
-- Synchronous SPI
D Supply Voltage Supervisor/Monitor With
D
D
D
D
D
D
†
Programmable Level Detection
Brownout Detector
Bootstrap Loader
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Family Members Include:
-- MSP430F2416:
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2417:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2418:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2419:
120KB+256B Flash Memory, 4KB RAM
-- MSP430F2616:
92KB+256B Flash Memory, 4KB RAM
-- MSP430F2617:
92KB+256B Flash Memory, 8KB RAM
-- MSP430F2618:
116KB+256B Flash Memory, 8KB RAM
-- MSP430F2619:
120KB+256B Flash Memory, 4KB RAM
Available in 80-Pin Quad Flat Pack (QFP)
and 64-Pin QFP (See Available Options)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide,
Literature Number SLAU144
The MSP430F241x devices are identical to the MSP430F261x
devices, with the exception that the DAC12 modules and the DMA
controller are not implemented.
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active
mode in less than 1 μs.
The MSP430F261x/241x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI)
modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x devices,
with the exception that the DAC12 and the DMA modules are not implemented.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a registered trademark of Philips Incorporated.
Copyright © 2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
AVAILABLE OPTIONS
TA
--40°C to 105°C
2
PACKAGED DEVICES
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN LQFP (PM)
MSP430F2416TPN
MSP430F2417TPN
MSP430F2418TPN
MSP430F2419TPN
MSP430F2616TPN
MSP430F2617TPN
MSP430F2618TPN
MSP430F2619TPN
MSP430F2416TPM
MSP430F2417TPM
MSP430F2418TPM
MSP430F2419TPM
MSP430F2616TPM
MSP430F2617TPM
MSP430F2618TPM
MSP430F2619TPM
POST OFFICE BOX 655303
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
pin designation, MSP430F241x, 80-pin package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
1
2
60
59
P7.6
P7.5
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
3
4
5
6
58
57
56
55
P7.4
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
VeREF+
VREF-/VeREF-
7
8
9
10
11
54
53
52
51
50
P7.0
DVSS2
DVCC2
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
12
13
14
15
49
48
47
46
P5.5/SMCLK
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
16
45
17
18
19
44
43
42
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P2.0/ACLK/CA2
20
41
P4.5/TB5
80-pin
PN PACKAGE
(TOP VIEW)
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
pin designation, MSP430F241x, 64-pin package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
XIN
XOUT
VeREF+
VREF-/VeREF-
1
2
3
4
5
6
7
8
9
10
11
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
12
13
14
15
16
P6.6/A6
P6.7/A7/SVSIN
VREF+
64-pin
PM PACKAGE
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
37
36
35
34
33
P4.1/TB1
P4.0/TB0
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
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P5.2/UCB1SOMI/UCB1SCL
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P3.7/UCA1RXD/UCA1SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
P7.7
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P8.7/XT2IN
P8.6/XT2OUT
pin designation, MSP430F261x, 80-pin package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
P6.3/A3
P6.4/A4
1
2
3
60
59
58
P7.6
P7.5
P7.4
P6.5/A5/DAC1
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
4
5
6
57
56
55
P7.3
P7.2
P7.1
VREF+
XIN
XOUT
7
8
9
54
53
52
P7.0
DVSS2
DVCC2
51
50
49
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
80-pin
PN PACKAGE
(TOP VIEW)
VeREF+/DAC0
VREF-/VeREFP1.0/TACLK/CAOUT
10
11
12
P1.1/TA0
P1.2/TA1
P1.3/TA2
13
14
15
48
47
46
P5.4/MCLK
P5.3/UCB1CLK/UCA1STE
P5.2/UCB1SOMI/UCB1SCL
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
16
45
17
18
44
43
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P4.7/TBCLK
P1.7/TA2
P2.0/ACLK/CA2
19
20
42
41
P4.6/TB6
P4.5/TB5
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/DMAE0/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
POST OFFICE BOX 655303
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5
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
XT2OUT
TDO/TDI
XT2IN
TDI/TCLK
TMS
TCK
RST/NMI
P6.0/A0
P6.1/A1
P6.2/A2
AVSS
DVSS1
AVCC
pin designation, MSP430F261x, 64-pin package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DV CC1
1
48
P6.3/A3
2
47
P5.3/UCB1CLK/UCA1STE
P6.4/A4
3
46
P5.2/UCB1SOMI/UCB1SCL
P6.5/A5/DAC1
P6.6/A6/DAC0
4
5
45
44
P5.1/UCB1SIMO/UCB1SDA
P5.0/UCB1STE/UCA1CLK
P6.7/A7/DAC1/SVSIN
6
43
P4.7/TBCLK
VREF+
7
42
P4.6/TB6
XIN
8
41
P4.5/TB5
40
39
P4.4/TB4
P4.3/TB3
XOUT
VeREF+/DAC0
9
10
64-pin
PM PACKAGE
(TOP VIEW)
VREF-/VeREF-
11
38
P4.2/TB2
P1.0/TACLK/CAOUT
12
37
P4.1/TB1
P1.1/TA0
13
36
P4.0/TB0
P1.2/TA1
14
35
P3.7/UCA1RXD/UCA1SOMI
P1.3/TA2
P1.4/SMCLK
15
16
34
33
P3.6/UCA1TXD/UCA1SIMO
P3.5/UCA0RXD/UCA0SOMI
POST OFFICE BOX 655303
P3.4/UCA0TXD/UCA0SIMO
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.0/UCB0STE/UCA0CLK
P2.7/TA0/CA7
P2.6/ADC12CLK/DMAE0/CA6
P2.5/ROSC/CA5
P2.4/CA1/TA2
P2.3/CA0/TA1
P2.2/CAOUT/TA0/CA4
P2.1/TAINCLK/CA3
P2.0/ACLK/CA2
P1.7/TA2
P1.6/TA1
P1.5/TA0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
6
P5.4/MCLK
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
functional block diagram, MSP430F241x, 80-pin package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS1/2
Flash
RAM
120kB
116kB
92kB
92kB
4kB
8kB
8kB
4kB
AVCC
AVSS
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
ADC12
12-Bit
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
8
Channels
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
4x8 I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
Timer_B7
Watchdog
WDT+
MPY,
MPYS,
MAC,
MACS
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
functional block diagram, MSP430F241x, 64-pin package
XIN/ XOUT/
XT2IN XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS
Flash
RAM
120kB
116kB
92kB
92kB
4kB
8kB
8kB
4kB
AVCC
AVSS
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
ADC12
12-Bit
2x8 I/O
Interrupt
capability
8
Channels
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
POST OFFICE BOX 655303
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7
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
functional block diagram, MSP430F261x, 80-pin package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
Flash
DVSS1/2
AVCC
RAM
120kB
116kB
92kB
92kB
56kB
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
Ports
P1/P2
Ports
P3/P4
P5/P6
2x8 I/O
Interrupt
capability
4x8 I/O
P7.x/P8.x
2x8/
1x16
Ports
P7/P8
2x8/1x16
I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MAB
MDB
Brownout
Protection
Emulation
JTAG
Interface
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
SVS,
SVM
DMA
Controller
Timer_B7
Watchdog
WDT+
3
Channels
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
functional block diagram, MSP430F261x, 64-pin package
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
DVSS
Flash
AVCC
RAM
120kB
116kB
92kB
92kB
56kB
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS
DAC12
12-Bit
2
Channels
Voltage
Out
Ports
P1/P2
2x8 I/O
Interrupt
capability
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Emulation
Brownout
Protection
JTAG
Interface
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
RST/NMI
8
P3.x/P4.x
P5.x/P6.x
2x8
4x8
P1.x/P2.x
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Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions
TERMINAL
NO.
NAME
†
I/O
DESCRIPTION
64
PIN
80
PIN
AVCC
64
80
Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AVSS
62
78
Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DVCC1
1
1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
63
79
Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2
52
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2
53
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/
CAOUT
12
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input/Comparator_A output
P1.1/TA0
13
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2
20
20
I/O
General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/
CA3
21
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/
TA0/CA4
22
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL
receive/Comparator_A input
P2.3/CA0/TA1
23
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2
24
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc/CA5
25
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
frequency/Comparator_A input
P2.6/ADC12CLK/
DMAE0†/CA6
26
26
I/O
General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel 0 external
trigger/Comparator_A input
P2.7/TA0/CA7
27
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/Comparator_A input
P3.0/UCB0STE/
UCA0CLK
28
28
I/O
General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0 clock input/output
P3.1/UCB0SIMO/
UCB0SDA
29
29
I/O
General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
P3.2/UCB0SOMI/
UCB0SCL
30
30
I/O
General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.3/UCB0CLK/
UCA0STE
31
31
I/O
General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/UCA0TXD/
UCA0SIMO
32
32
I/O
General-purpose digital I/O pin/USCIA transmit data output in UART mode, slave data in/master out
in SPI mode
P3.5/UCA0RXD/
UCA0SOMI
33
33
I/O
General-purpose digital I/O pin/USCI A0 receive data input in UART mode, slave data out/master
in in SPI mode
P3.6/UCA1TXD/
UCA1SIMO
34
34
I/O
General-purpose digital I/O pin/USCI A1 transmit data output in UART mode, slave data in/master
out in SPI mode
P3.7/UCA1RXD/
UCA1SOMI
35
35
I/O
General-purpose digital I/O pin/USCIA1 receive data input in UART mode, slave data out/master
in in SPI mode
MSP430F261x devices only
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9
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
NAME
DESCRIPTION
80
PIN
P4.0/TB0
36
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1
37
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2
38
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3
39
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4
40
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5
41
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6
42
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK
43
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/UCB1STE/
UCA1CLK
44
44
I/O
General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1 clock input/output
P5.1/UCB1SIMO/
UCB1SDA
45
45
I/O
General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode, SDA I2C data in I2C mode
P5.2/UCB1SOMI/
UCB1SCL
46
46
I/O
General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode, SCL I2C clock in I2C mode
P5.3/UCB1CLK/
UCA1STE
47
47
I/O
General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave transmit enable
P5.4/MCLK
48
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT
51
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -- Timer_B
TB0 to TB6/SVS comparator output
P6.0/A0
59
75
I/O
General-purpose digital I/O pin/analog input A0 – 12-bit ADC
P6.1/A1
60
76
I/O
General-purpose digital I/O pin/analog input A1 – 12-bit ADC
P6.2/A2
61
77
I/O
General-purpose digital I/O pin/analog input A2 – 12-bit ADC
P6.3/A3
2
2
I/O
General-purpose digital I/O pin/analog input A3 – 12-bit ADC
P6.4/A4
3
3
I/O
General-purpose digital I/O pin/analog input A4 – 12-bit ADC
P6.5/A5/DAC1†
4
4
I/O
General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1 output
P6.6/A6/DAC0†
5
5
I/O
General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0 output
6
6
I/O
General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1 output/SVS input
P7.0
54
I/O
General-purpose digital I/O pin
P7.1
55
I/O
General-purpose digital I/O pin
P7.2
56
I/O
General-purpose digital I/O pin
P7.3
57
I/O
General-purpose digital I/O pin
P7.4
58
I/O
General-purpose digital I/O pin
P7.5
59
I/O
General-purpose digital I/O pin
P7.6
60
I/O
General-purpose digital I/O pin
P7.7
61
I/O
General-purpose digital I/O pin
P8.0
62
I/O
General-purpose digital I/O pin
P8.1
63
I/O
General-purpose digital I/O pin
P8.2
64
I/O
General-purpose digital I/O pin
P8.3
65
I/O
General-purpose digital I/O pin
P6.7/A7/DAC1†/
SVSIN
†
I/O
64
PIN
MSP430F261x devices only
10
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Terminal Functions (Continued)
TERMINAL
NO.
NAME
†
64
PIN
80
PIN
I/O
DESCRIPTION
P8.4
66
I/O
General-purpose digital I/O pin
P8.5
67
I/O
General-purpose digital I/O pin
P8.6/XT2OUT
68
O
General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
P8.7/XT2IN
69
I
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only standard crystals can be
connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
XT2IN
53
I
Input port for crystal oscillator XT2
RST/NMI
58
74
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
TCK
57
73
I
Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.
TDI/TCLK
55
71
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
70
I/O
TMS
56
72
I
Test mode select. TMS is used as an input port for device programming and test.
VeREF+/DAC0†
10
10
I
Input for an external reference voltage/DAC12.0 output
VREF+
7
7
O
Output of positive terminal of the reference voltage in the ADC12
VREF-- /VeREF--
11
11
I
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
XIN
8
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
9
O
Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
Test data output port. TDO/TDI data output or programming data input terminal.
MSP430F261x devices only
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11
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g., CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
Indexed
Symbolic (PC relative)
Absolute
Indirect
Indirect
autoincrement
Immediate
NOTE: S = source
12
S D
D
D
D
D
D
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
MOV EDE,TONI
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
MOV &MEM,&TCDAT
M(MEM) ----> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ----> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ----> R11
R10 + 2----> R10
D
MOV #X,TONI
MOV #45,TONI
D = destination
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#45
----> M(TONI)
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
--
All clocks are active.
D Low-power mode 0 (LPM0)
--
CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
D Low-power mode 1 (LPM1)
--
CPU is disabled.
ACLK and SMCLK remain active. MCLK is disabled.
DCO’s dc-generator is disabled if DCO not used in active mode.
D Low-power mode 2 (LPM2)
--
CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator remains enabled.
ACLK remains active.
D Low-power mode 3 (LPM3)
--
CPU is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
ACLK remains active.
D Low-power mode 4 (LPM4)
--
CPU is disabled.
ACLK is disabled.
MCLK and SMCLK are disabled.
DCO’s dc-generator is disabled.
Crystal oscillator is stopped.
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0x0FFFF to 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
Power-up
External Reset
Watchdog
Flash Key Violation
PC out of range (see Note 1)
PORIFG
WDTIFG
RSTIFG
KEYV (see Note 2)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0x0FFFE
31, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (see Notes 2 and 6)
(Non)maskable
(Non)maskable
(Non)maskable
0x0FFFC
30
Timer_B7
TBCCR0 CCIFG
(see Note 3)
Maskable
0x0FFFA
29
Timer_B7
TBCCR1 to TBCCR6 CCIFGs, TBIFG
(see Notes 2 and 3)
Maskable
0x0FFF8
28
Comparator_A+
CAIFG
Maskable
0x0FFF6
27
Watchdog timer+
WDTIFG
Maskable
0x0FFF4
26
Timer_A3
TACCR0 CCIFG (see Note 3)
Maskable
0x0FFF2
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Notes 2 and 3)
Maskable
0x0FFF0
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 2 and 4)
Maskable
0x0FFEE
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 4)
Maskable
0x0FFEC
22
ADC12
ADC12IFG (see Notes 2 and 3)
Maskable
0x0FFEA
21
0x0FFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (see Notes 2 and 3)
Maskable
0x0FFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7 (see Notes 2 and 3)
Maskable
0x0FFE4
18
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
UCA1RXIFG, UCB1RXIFG
(see Notes 2 and 4)
Maskable
0x0FFE2
17
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG
(see Notes 2 and 5)
Maskable
0x0FFE0
16
DMA
DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 2 and 3)
Maskable
0x0FFDE
15
DAC12
DAC12_0IFG, DAC12_1IFG
(see Notes 2 and 3)
Maskable
0x0FFDC
14
Reserved (see Notes 7 and 8)
Reserved
0x0FFDA to
0 0FFC0
0x0FFC0
13 to 0,
0
l
lowest
t
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x00000 to 0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
14
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
special function registers
Most interrupt enable bits are collected in the lowest address space. Special-function register bits not allocated
to a functional purpose are not physically present in the device. This arrangement provides simple software
access.
interrupt enable 1 and 2
Address
7
6
00h
5
4
ACCVIE
rw--0
3
2
1
0
NMIIE
OFIE
WDTIE
rw--0
rw--0
rw--0
Interrupt Enable Register 1
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE
Oscillator-fault-interrupt enable
NMIIE
Nonmaskable-interrupt enable
ACCVIE
Flash memory access violation interrupt enable
Address
7
6
5
4
01h
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw--0
rw--0
rw--0
rw--0
Interrupt Enable Register 2
UCA0RXIE
USCI_A0 receive-interrupt enable
UCA0TXIE
USCI_A0 transmit-interrupt enable
UCB0RXIE
USCI_B0 receive-interrupt enable
UCB0TXIE
USCI_B0 transmit-interrupt enable
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw--0
rw--(0)
rw--(1)
rw--1
rw--(0)
Interrupt Flag Register 1
WDTIFG
Set on watchdog timer overflow or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG
Flag set on oscillator fault7
PORIFG
Power--on interrupt flag. Set on VCC power up.
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power up.
NMIIFG
Set via RST/NMI pin
Address
7
6
5
4
03h
3
2
1
0
UCB0TX
IFG
UCB0RX
IFG
UCA0TX
IFG
UCA0RX
IFG
rw--1
rw--0
rw--1
rw--0
Interrupt Flag Register 2
UCA0RXIFG
USCI_A0 receive-interrupt flag
UCA0TXIFG
USCI_A0 transmit-interrupt flag
UCB0RXIFG
USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
L e g en d
16
rw :
rw -0 ,1 :
rw -(0,1)
B it c an b e rea d a n d w ritten .
B it c an b e rea d a n d w ritten . It is R eset o r S et b y P U C .
B it c an b e rea d a n d w ritten . It is R eset o r S et b y P O R .
S F R b it is n o t p rese n t in d e vic e .
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MSP430x241x, MSP430x261x
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memory organization
MSP430F2416
MSP430F2616
MSP430F2417
MSP430F2617
Size
Flash
Flash
92KB
0x0FFFF -- 0x0FFC0
0x18FFF -- 0x02100
92KB
0x0FFFF -- 0x0FFC0
0x19FFF -- 0x03100
RAM (total)
Size
Extended
Size
Mirrored
Size
4kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x018FF -- 0x01100
8kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
Memory
Main: interrupt vector
Main: code memory
Information memory
Size
Flash
256 Byte
0x010FF -- 0x01000
256 Byte
0x010FF -- 0x01000
Boot memory
Size
ROM
1KB
0x00FFF -- 0x00C00
1KB
0x00FFF -- 0x00C00
Size
2KB
0x009FF -- 0x00200
2KB
0x009FF -- 0x00200
16-bit
8-bit
8-bit SFR
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
MSP430F2618
MSP430F2418
MSP430F2619
MSP430F2419
Size
Flash
Flash
116KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x03100
120KB
0x0FFFF -- 0x0FFC0
0x1FFFF -- 0x02100
RAM (total)
Size
Extended
Size
Mirrored
Size
8kB
0x030FF -- 0x01100
6kB
0x030FF -- 0x01900
2kB
0x018FF -- 0x01100
4kB
0x020FF -- 0x01100
2kB
0x020FF -- 0x01900
2kB
0x018FF -- 0x01100
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
Memory
Main: interrupt vector
Main: code memory
Information memory
Size
Flash
256 Byte
0x010FF -- 0x01000
256 Byte
0x010FF -- 0x01000
Boot memory
Size
ROM
1KB
0x00FFF -- 0x00C00
1KB
0x00FFF -- 0x00C00
Size
2KB
0x009FF -- 0x00200
2KB
0x009FF -- 0x00200
16-bit
8-bit
8-bit SFR
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
0x001FF -- 0x00100
0x000FF -- 0x00010
0x0000F -- 0x00000
RAM (mirrored at
0x18FF to 0x01100)
Peripherals
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL Function
PM, RTD Package Pins
Data Transmit
13 - P1.1
Data Receive
22 - P2.2
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
D Flash content integrity check with marginal read modes
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x241x and MSP43x261x family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 μs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or a very
low-power LF oscillator
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
18
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
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calibration data stored in information memory segment A
Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.
TAGS USED BY THE ADC CALIBRATION TAGS
NAME
ADDRESS
VALUE
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration
TAG_ADC12_1
0x10DA
0x10
ADC12_1 calibration tag
--
0xFE
Identifier for empty memory areas
TAG_EMPTY
DESCRIPTION
LABELS USED BY THE ADC CALIBRATION TAGS
LABEL
CONDITION AT CALIBRATION / DESCRIPTION
SIZE
ADDRESS OFFSET
CAL_ADC_25T85
INCHx = 0x1010; REF2_5 = 1, TA = 85°C
word
0x000E
CAL_ADC_25T30
INCHx = 0x1010; REF2_5 = 1, TA = 30°C
word
0x000C
CAL_ADC_25VREF_FACTOR
REF2_5 = 1, TA = 30°C
word
0x000A
CAL_ADC_15T85
INCHx = 0x1010; REF2_5 = 0, TA = 85°C
word
0x0008
CAL_ADC_15T30
INCHx = 0x1010; REF2_5 = 0, TA = 30°C
word
0x0006
REF2_5 = 0, TA = 30°C
word
0x0004
CAL_ADC_OFFSET
External VREF = 1.5 V, fADC12CLK = 5 MHz
word
0x0002
CAL_ADC_GAIN_FACTOR
CAL_ADC_15VREF_FACTOR
External VREF = 1.5 V, fADC12CLK = 5 MHz
word
0x0000
CAL_BC1_1MHz
--
byte
0x0007
CAL_DCO_1MHz
--
byte
0x0006
CAL_BC1_8MHz
--
byte
0x0005
CAL_DCO_8MHz
--
byte
0x0004
CAL_BC1_12MHz
--
byte
0x0003
CAL_DCO_12MHz
--
byte
0x0002
CAL_BC1_16MHz
--
byte
0x0001
CAL_DCO_16MHz
--
byte
0x0000
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until
VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
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digital I/O
There are up to eight 8-bit I/O ports implemented—ports P1 through P8:
D
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
Ports P7/P8 can be accessed word wise.
watchdog timer+ (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin) or I2C, and asynchronous combination protocols such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.
The USCI B module provides support for SPI (3 pin or 4 pin) and I2C.
20
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timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
22 - P2.2
TA0
CCI0B
14 - P1.2
DVSS
GND
DVCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
13 - P1.1
CCR0
TA0
17 - P1.5
27 - P2.7
14 - P1.2
18 - P1.6
CCR1
TA1
23 - P2.3
ADC12 (internal)
DAC12_0 (internal)
DAC12_1 (internal)
15 - P1.3
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
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CCR2
• DALLAS, TEXAS 75265
TA2
19 - P1.7
24 - P2.4
21
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS†
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
43 - P4.7
TBCLK
TBCLK
MODULE OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
36 - P4.0
TB0
CCI0B
ADC12 (internal)
DVSS
GND
37 - P4.1
37 - P4.1
DVCC
VCC
TB1
CCI1A
CCR0
TB0
37 - P4.1
ADC12 (internal)
TB1
CCI1B
DVSS
GND
DVCC
VCC
38 - P4.2
TB2
CCI2A
38 - P4.2
38 - P4.2
TB2
CCI2B
DAC_0(internal)
DVSS
GND
DVCC
VCC
TB3
CCI3A
39 - P4.3
39 - P4.3
TB3
CCI3B
DVSS
GND
DVCC
VCC
40 - P4.4
TB4
CCI4A
40 - P4.4
TB4
CCI4B
DVSS
GND
41 - P4.5
41 - P4.5
42 - P4.6
22
MODULE
BLOCK
DVCC
VCC
TB5
CCI5A
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
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CCR1
CCR2
TB1
TB2
DAC_1(internal)
39 - P4.3
CCR3
TB3
40 - P4.4
CCR4
TB4
41 - P4.5
CCR5
TB5
42 - P4.6
CCR6
• DALLAS, TEXAS 75265
TB6
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8-bit or 12-bit mode
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
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MSP430x241x, MSP430x261x
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peripheral file map
PERIPHERAL FILE MAP
DMA†
DAC12†
ADC12
†
24
DMA channel 2 transfer size
DMA2SZ
0x01F2
DMA channel 2 destination address
DMA2DA
0x01EE
DMA channel 2 source address
DMA2SA
0x01EA
DMA channel 2 control
DMA2CTL
0x01E8
DMA channel 1 transfer size
DMA1SZ
0x01E6
DMA channel 1 destination address
DMA1DA
0x01E2
DMA channel 1 source address
DMA1SA
0x01DE
DMA channel 1 control
DMA1CTL
0x01DC
DMA channel 0 transfer size
DMA0SZ
0x01DA
DMA channel 0 destination address
DMA0DA
0x01D6
DMA channel 0 source address
DMA0SA
0x01D2
DMA channel 0 control
DMA0CTL
0x01D0
DMA module interrupt vector word
DMAIV
0x0126
DMA module control 1
DMACTL1
0x0124
DMA module control 0
DMACTL0
0x0122
DAC12_1 data
DAC12_1DAT
0x01CA
DAC12_1 control
DAC12_1CTL
0x01C2
DAC12_0 data
DAC12_0DAT
0x01C8
DAC12_0 control
DAC12_0CTL
0x01C0
Interrupt-vector-word register
ADC12IV
0x01A8
Inerrupt-enable register
ADC12IE
0x01A6
Inerrupt-flag register
ADC12IFG
0x01A4
Control register 1
ADC12CTL1
0x01A2
Control register 0
ADC12CTL0
0x01A0
Conversion memory 15
ADC12MEM15
0x015E
Conversion memory 14
ADC12MEM14
0x015C
Conversion memory 13
ADC12MEM13
0x015A
Conversion memory 12
ADC12MEM12
0x0158
Conversion memory 11
ADC12MEM11
0x0156
Conversion memory 10
ADC12MEM10
0x0154
Conversion memory 9
ADC12MEM9
0x0152
Conversion memory 8
ADC12MEM8
0x0150
Conversion memory 7
ADC12MEM7
0x014E
Conversion memory 6
ADC12MEM6
0x014C
Conversion memory 5
ADC12MEM5
0x014A
Conversion memory 4
ADC12MEM4
0x0148
Conversion memory 3
ADC12MEM3
0x0146
Conversion memory 2
ADC12MEM2
0x0144
Conversion memory 1
ADC12MEM1
0x0142
Conversion memory 0
ADC12MEM0
0x0140
MSP430F261x devices only
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
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PERIPHERAL FILE MAP (CONTINUED)
ADC12
(continued)
Timer_B7
_
Timer_A3
_
ADC memory-control register15
ADC12MCTL15
0x008F
ADC memory-control register14
ADC12MCTL14
0x008E
ADC memory-control register13
ADC12MCTL13
0x008D
ADC memory-control register12
ADC12MCTL12
0x008C
ADC memory-control register11
ADC12MCTL11
0x008B
ADC memory-control register10
ADC12MCTL10
0x008A
ADC memory-control register9
ADC12MCTL9
0x0089
ADC memory-control register8
ADC12MCTL8
0x0088
ADC memory-control register7
ADC12MCTL7
0x0087
ADC memory-control register6
ADC12MCTL6
0x0086
ADC memory-control register5
ADC12MCTL5
0x0085
ADC memory-control register4
ADC12MCTL4
0x0084
ADC memory-control register3
ADC12MCTL3
0x0083
ADC memory-control register2
ADC12MCTL2
0x0082
ADC memory-control register1
ADC12MCTL1
0x0081
ADC memory-control register0
ADC12MCTL0
0x0080
Capture/compare register 6
TBCCR6
0x019E
Capture/compare register 5
TBCCR5
0x019C
Capture/compare register 4
TBCCR4
0x019A
Capture/compare register 3
TBCCR3
0x0198
Capture/compare register 2
TBCCR2
0x0196
Capture/compare register 1
TBCCR1
0x0194
Capture/compare register 0
TBCCR0
0x0192
Timer_B register
TBR
0x0190
Capture/compare control 6
TBCCTL6
0x018E
Capture/compare control 5
TBCCTL5
0x018C
Capture/compare control 4
TBCCTL4
0x018A
Capture/compare control 3
TBCCTL3
0x0188
Capture/compare control 2
TBCCTL2
0x0186
Capture/compare control 1
TBCCTL1
0x0184
Capture/compare control 0
TBCCTL0
0x0182
Timer_B control
TBCTL
0x0180
Timer_B interrupt vector
TBIV
0x011E
Capture/compare register 2
TACCR2
0x0176
Capture/compare register 1
TACCR1
0x0174
Capture/compare register 0
TACCR0
0x0172
Timer_A register
TAR
0x0170
Reserved
0x016E
Reserved
0x016C
Reserved
0x016A
Reserved
0x0168
Capture/compare control 2
TACCTL2
0x0166
Capture/compare control 1
TACCTL1
0x0164
Capture/compare control 0
TACCTL0
0x0162
Timer_A control
TACTL
0x0160
Timer_A interrupt vector
TAIV
0x012E
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Hardware
Multiplier
Sum extend
SUMEXT
0x013E
Result high word
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
OP2
0x0138
Multiply signed +accumulate/operand1
MACS
0x0136
Multiply+accumulate/operand1
MAC
0x0134
Multiply signed/operand1
MPYS
0x0132
Multiply unsigned/operand1
MPY
0x0130
Flash control 4
FCTL4
0x01BE
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
Watchdog
Watchdog Timer control
WDTCTL
0x0120
USCI A0/B0
/
USCI A0 auto baud rate control
UCA0ABCTL
0x005D
USCI A0 transmit buffer
UCA0TXBUF
0x0067
USCI A0 receive buffer
UCA0RXBUF
0x0066
USCI A0 status
UCA0STAT
0x0065
USCI A0 modulation control
UCA0MCTL
0x0064
USCI A0 baud rate control 1
UCA0BR1
0x0063
USCI A0 baud rate control 0
UCA0BR0
0x0062
USCI A0 control 1
UCA0CTL1
0x0061
USCI A0 control 0
UCA0CTL0
0x0060
USCI A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI A0 IrDA transmit control
UCA0IRTCLT
0x005E
USCI B0 transmit buffer
UCB0TXBUF
0x006F
USCI B0 receive buffer
UCB0RXBUF
0x006E
USCI B0 status
UCB0STAT
0x006D
USCI B0 I2C Interrupt enable
UCB0CIE
0x006C
USCI B0 baud rate control 1
UCB0BR1
0x006B
USCI B0 baud rate control 0
UCB0BR0
0x006A
USCI B0 control 1
UCB0CTL1
0x0069
USCI B0 control 0
UCB0CTL0
0x0068
USCI B0 I2C slave address
UCB0SA
0x011A
USCI B0 I2C own address
UCB0OA
0x0118
USCI A1 auto baud rate control
UCA1ABCTL
0x00CD
USCI A1 transmit buffer
UCA1TXBUF
0x00D7
USCI A1 receive buffer
UCA1RXBUF
0x00D6
USCI A1 status
UCA1STAT
0x00D5
USCI A1 modulation control
UCA1MCTL
0x00D4
USCI A1 baud rate control 1
UCA1BR1
0x00D3
USCI A1 baud rate control 0
UCA1BR0
0x00D2
USCI A1 control 1
UCA1CTL1
0x00D1
USCI A1 control 0
UCA1CTL0
0x00D0
USCI A1 IrDA receive control
UCA1IRRCTL
0x00CF
USCI A1 IrDA transmit control
UCA1IRTCLT
0x00CE
Flash
USCI A1/B1
/
26
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MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
USCI A1/B1
/
(continued)
USCI B1 transmit buffer
UCB1TXBUF
0x00DF
USCI B1 receive buffer
UCB1RXBUF
0x00DE
USCI B1 status
UCB1STAT
0x00DD
USCI B1 I2C Interrupt enable
UCB1CIE
0x00DC
USCI B1 baud rate control 1
UCB1BR1
0x00DB
USCI B1 baud rate control 0
UCB1BR0
0x00DA
USCI B1 control 1
UCB1CTL1
0x00D9
USCI B1 control 0
UCB1CTL0
0x00D8
USCI B1 I2C slave address
UCB1SA
0x017E
USCI B1 I2C own address
UCB1OA
0x017C
USCI A1/B1 interrupt enable
UC1IE
0x0006
USCI A1/B1 interrupt flag
UC1IFG
0x0007
Comparator_A port disable
CAPD
0x005B
Comparator_A control2
CACTL2
0x005A
Comparator_A control1
CACTL1
0x0059
Basic clock system control3
BCSCTL3
0x0053
Basic clock system control2
BCSCTL2
0x0058
Basic clock system control1
BCSCTL1
0x0057
DCO clock frequency control
DCOCTL
0x0056
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
0x0055
Port PA†
Port PA resistor enable
PAREN
0x0014
Port PA selection
PASEL
0x003E
Port PA direction
PADIR
0x003C
Port PA output
PAOUT
0x003A
Port PA input
PAIN
0x0038
Port P8 resistor enable
P8REN
0x0015
Port P8 selection
P8SEL
0x003F
Port P8 direction
P8DIR
0x003D
Port P8 output
P8OUT
0x003B
Port P8 input
P8IN
0x0039
Port P7 resistor enable
P7REN
0x0014
Port P7 selection
P7SEL
0x003E
Port P7 direction
P7DIR
0x003C
Port P7 output
P7OUT
0x003A
Port P7 input
P7IN
0x0038
Port P6 resistor enable
P6REN
0x0013
Port P6 selection
P6SEL
0x0037
Port P6 direction
P6DIR
0x0036
Port P6 output
P6OUT
0x0035
Port P6 input
P6IN
0x0034
Port P5 resistor enable
P5REN
0x0012
Port P5 selection
P5SEL
0x0033
Port P5 direction
P5DIR
0x0032
Port P5 output
P5OUT
0x0031
Port P5 input
P5IN
0x0030
Comparator_A+
p
_
Basic Clock
Port
P8†
Port P7†
Port P6
Port P5
†
80-pin devices only
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
PERIPHERAL FILE MAP (CONTINUED)
Port P4
Port P3
Port P2
Port P1
Special
p
Functions
28
Port P4 selection
P4SEL
0x001F
Port P4 resistor enable
P4REN
0x0011
Port P4 direction
P4DIR
0x001E
Port P4 output
P4OUT
0x001D
Port P4 input
P4IN
0x001C
Port P3 resistor enable
P3REN
0x0010
Port P3 selection
P3SEL
0x001B
Port P3 direction
P3DIR
0x001A
Port P3 output
P3OUT
0x0019
Port P3 input
P3IN
0x0018
Port P2 resistor enable
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
Port P2 interrupt enable
P2IE
0x002D
Port P2 interrupt-edge select
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P2 input
P2IN
0x0028
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
Port P1 interrupt enable
P1IE
0x0025
Port P1 interrupt-edge select
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
P1OUT
0x0021
Port P1 input
P1IN
0x0020
SFR interrupt flag2
IFG2
0x0003
SFR interrupt flag1
IFG1
0x0002
SFR interrupt enable2
IE2
0x0001
SFR interrupt enable1
IE1
0x0000
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature: Unprogrammed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Programmed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification, with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
MAX
Supply voltage during program execution, VCC
PARAMETER
AVCC = DVCC = VCC (see Note 1)
1.8
3.6
V
Supply voltage during flash memory programming, VCC
AVCC = DVCC = VCC (see Note 1)
2.2
3.6
V
Supply voltage, VSS
AVSS = DVSS = VSS
0.0
0.0
V
I version
--40
85
T version
--40
105
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
4.15
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
dc
16
Operating free-air
free air temperature,
temperature TA
Processor frequency fSYSYTEM (maximum MCLK frequency)
(see Notes 2 and 3 and Figure 1)
UNIT
°C
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power-up.
2. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
System Frequency --MHz
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
Active mode (AM)
current (1 MHz)
Active mode (AM)
current (1 MHz)
Active mode (AM)
current (4 kHz)
TEST CONDITIONS
TA
TYP
MAX
365
395
375
420
515
560
525
595
330
370
340
390
460
495
470
520
2.1
9
105_C
15
31
--40_C to 85_C
3
11
19
32
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32,768
32 768 Hz,
Hz
Program executes from flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 0,
0 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 0
--40_C to 85_C
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32,768
32 768 Hz,
Hz
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 0,
0 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 0
--40_C to 85_C
fMCLK = fSMCLK =
fACLK = 32,768 Hz/8 = 4,096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
--40_C to 85_C
105_C
--40_C to 85_C
105_C
105_C
--40_C to 85_C
105_C
VCC
22V
2.2
3V
22V
2.2
3V
MIN
UNIT
μA
μA
22V
2.2
μA
3V
105_C
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
--40_C to 85_C
67
86
22V
2.2
fACLK = 0 Hz,
Hz
105_C
80
99
Active mode (AM) Program executes in flash,
IAM,100kHz
μA
RSELx = 0, DCOx = 0,
current (100 kHz)
--40_C to 85_C
84
107
CPUOFF = 0,
0 SCG0 = 0
0, SCG1 = 0,
0
3V
105_C
99
128
OSCOFF = 1
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
typical characteristics -- active mode supply current (into DVCC + AVCC)
7.0
10.0
6.0
Active Mode Current -- mA
9.0
Active Mode Current -- mA
TA = 85 °C
fDCO = 16 MHz
8.0
fDCO = 12 MHz
7.0
6.0
5.0
fDCO = 8 MHz
4.0
3.0
2.0
0.0
1.5
2.0
2.5
3.0
5.0
4.0
VCC = 3 V
TA = 85 °C
3.0
TA = 25 °C
2.0
VCC = 2.2 V
1.0
fDCO = 1 MHz
1.0
TA = 25 °C
3.5
4.0
0.0
0.0
VCC -- Supply Voltage -- V
Figure 2. Active Mode Current vs VCC, TA = 25°C
POST OFFICE BOX 655303
4.0
8.0
12.0
16.0
fDCO -- DCO Frequency -- MHz
Figure 3. Active Mode Current vs DCO Frequency
• DALLAS, TEXAS 75265
31
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0, 1MHz
ILPM0,
100kHz
ILPM2
ILPM3,LFXT1
Low-power mode 0
(LPM0) current,
current
see Note 3
Low-power mode 0
(LPM0) current,
current
see Note 3
Low-power mode 2
(LPM2) current,
current
see Note 4
Low-power mode 3
(LPM3) current,
current
see Note 4
TEST CONDITIONS
TA
TYP
MAX
68
83
83
98
87
105
100
125
37
49
50
62
40
55
57
73
23
33
35
46
25
36
40
55
--40°C
0.8
1.2
25°C
1
1.3
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
MHz
fACLK = 32,768 Hz,
CALBC1 1MHZ
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 0
--40_C to 85_C
fMCLK = 0MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz
kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz,
fACLK = 32,768
32 768 Hz
Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 1,
1
OSCOFF = 0
--40_C to 85_C
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
105_C
--40_C to 85_C
105_C
105_C
--40_C to 85_C
105_C
--40_C to 85_C
105_C
--40_C to 85_C
105_C
85°C
ILPM3,VLO
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
22V
2.2
3V
22V
2.2
3V
22V
2.2
3V
22V
2.2
MIN
4.6
7
105°C
14
24
--40°C
0.9
1.3
1.1
1.5
25°C
85°C
Low-power mode 3
((LPM3)) current,
see N
Note
t 4
VCC
3V
5.5
8
105°C
17
30
--40°C
0.4
1.0
25°C
0.5
1.0
4.3
6.5
85°C
22V
2.2
105°C
14
24
--40°C
0.6
1.2
0.6
1.2
25°C
85°C
105°C
3V
5
7.5
16.5
29.5
UNIT
μA
μA
μA
μA
μA
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a micro crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
3. Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK.
4. Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply current into VCC excluding external current (see Notes 1 and 2) (continued)
PARAMETER
ILPM4
ILPM4
Low-power mode 4
(LPM4) current,
see Note 3
Low-power mode 4
(LPM4) current,
see Note 3
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
VCC
TYP
MAX
0.1
0.5
0.1
0.5
4
6
105°C
13
23
--40°C
0.2
0.5
25°C
0.2
0.5
4.7
7
14
24
--40°C
25°C
85°C
22V
2.2
85°C
3V
105°C
MIN
UNIT
μA
A
μA
A
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a micro crystal CC4V--T1A SMD crystal with a load capacitance of 9 pf. The internal and external
load capacitance is chosen to closely match the required 9 pf.
3. Current for Brownout included.
ILPM4 -- Low--power mode current -- uA
typical characteristics -- LPM4 current
16.0
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
Vcc = 3.6V
7.0
Vcc = 3.0V
6.0
5.0
Vcc = 2.2V
4.0
3.0
2.0
1.0
Vcc = 1.8V
0.0
--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- °C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Schmitt-trigger inputs -- ports P1 through P8, RST/NMI, JTAG, XIN, and XT2IN (see Note 4)
PARAMETER
VIT+
VIT--
TEST CONDITIONS
Positive-going
Positive
going input threshold voltage
Negative-going
Negative
going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ -- VIT-- )
RPull
Pullup/pulldown resistor
Pullup: VIN = VSS,
Pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
TYP
MAX
0.45 VCC
0.75 VCC
2.2 V
1.0
1.65
3V
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.2
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
35
50
5
UNIT
V
V
V
kΩ
pF
NOTE 4: XIN and XT2IN in bypass mode only.
inputs -- ports P1 and P2
PARAMETER
tint
TEST CONDITIONS
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger pulse width to
set the interrupt flag (see Note)
VCC
2.2 V/3 V
MIN
MAX
20
UNIT
ns
NOTE: The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter
than t(int).
leakage current -- ports P1 through P8 (see Note 1 and 2)
PARAMETER
Ilkg (Px.x)
TEST CONDITIONS
High-impedance leakage current
see Notes 1 and 2
VCC
2.2 V/3 V
MIN
MAX
UNIT
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pull--up/pull--down resistor is
disabled..
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
standard inputs -- RST/NMI
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VIL
Low-level input voltage
2.2 V/3 V
VSS
VSS+0.6
V
VIH
High-level input voltage
2.2 V/3 V
0.8×VCC
VCC
V
UNIT
outputs -- ports P1 through P8
PARAMETER
TEST CONDITIONS
VCC
IOH(max) = --1.5 mA (see Note 2)
VOH
22V
2.2
IOH(max) = --6 mA (see Note 2)
High level output voltage
High-level
IOH(max) = --1.5 mA (see Note 2)
3V
IOH(max) = --6 mA (see Note 2)
IOL(max) = 1.5 mA (see Note 2)
VOL
22V
2.2
IOL(max) = 6 mA (see Note 2)
Low level output voltage
Low-level
IOL(max) = 1.5 mA (see Note 2)
3V
IOL(max) = 6 mA (see Note 2)
NOTES: 1. The maximum total current,
voltage drop specified.
2. The maximum total current,
voltage drop specified.
MIN
MAX
VCC --0.25
VCC
VCC --0.6
VCC
VCC --0.25
VCC
VCC --0.6
VCC
VSS
VSS+0.25
VSS
VSS+0.6
VSS
VSS+0.25
VSS
VSS+0.6
V
V
IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
output frequency -- ports P1 through P8
PARAMETER
VCC
MIN
fPx.y
Port output frequency
with load
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ
(see Notes 1 and 2)
2.2 V
DC
10
3.0 V
DC
12
fPort_CLK
Clock output frequency
P2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
DC
12
3.3 V
DC
16
t(Xdc)
Duty cycle of output
frequency
q
y
TEST CONDITIONS
TYP
MAX
P5.6/ACLK, CL = 20 pF, LF mode
30
50
70
P5.6/ACLK, CL = 20 pF, XT1 mode
40
50
60
P5.4/MCLK, CL = 20 pF, XT1 mode
40
P5.4/MCLK, CL = 20 pF, DCO
50% -- 15 ns
P1.4/SMCLK, CL = 20 pF, XT2 mode
P1.4/SMCLK, CL = 20 pF, DCO
UNIT
MHz
MHz
%
60
50%
50% + 15 ns
40
60
50% -- 15 ns
50% + 15 ns
%
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
VCC = 2.2 V
P4.5
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
50.0
I OL -- Typical Low-Level Output Current -- mA
I OL -- Typical Low-Level Output Current -- mA
25.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
of one pin
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
of one pin
VCC = 3 V
P4.5
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
VOL -- Low-Level Output Voltage -- V
I OH -- Typical High-Level Output Current -- mA
I OH -- Typical High-Level Output Current -- mA
2.5
3.0
3.5
0.0
VCC = 2.2 V
P4.5
--5.0
--10.0
--15.0
TA = 85°C
TA = 25°C
1.0
1.5
2.0
2.5
VOH -- High-Level Output Voltage -- V
VCC = 3 V
P4.5
--10.0
--20.0
--30.0
TA = 85°C
--40.0
--50.0
0.0
TA = 25°C
0.5
1.0
1.5
Figure 8
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH -- High-Level Output Voltage -- V
Figure 7
36
2.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
0.0
0.5
1.5
Figure 6
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
of one pin
--25.0
0.0
1.0
VOL -- Low-Level Output Voltage -- V
Figure 5
--20.0
TA = 25°C
40.0
• DALLAS, TEXAS 75265
3.5
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
operating voltage
dVCC/dt ± 3 V/s
0.7 ¢ V(B_IT--)
V
V(B_IT--)
negative going VCC reset threshold voltage
dVCC/dt ± 3 V/s
1.71
V
Vhys(B_IT--)
VCC reset threshold hysteresis
dVCC/dt ± 3 V/s
210
mV
td(BOR)
BOR reset release delay time
2000
μs
treset
Pulse length at RST/NMI pin to accept a reset
70
2.2 V / 3 V
2
130
μs
NOTES: 1. The current consumption of the brownout module is included in the ICC current consumption data. The voltage level
V(B_IT--) + Vhys(B_IT--) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO
settings must not be changed until VCC ≥ VCC(MIN), where VCC(min) is the minimum supply voltage for the desired operating
frequency.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(Start)
1
0
td(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- μs
1 ns
tpw -- Pulse Width -- μs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw -- Pulse Width -- μs
tpw -- Pulse Width -- μs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SVS (supply voltage supervisor/monitor)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 12)
5
MAX
150
dVCC/dt ≤ 30 V/ms
2000
td(SVSon)
SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0‡
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 12)
20
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 12)
VLD = 2 to 14
Vhys(SVS_IT--)
hys(SVS IT--)
VCC/dt ≤ 3 V/s (see Figure 12), External voltage applied
on A7
VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13)
V(SVS_IT--)
(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13),
External voltage applied on A7
ICC(SVS)
(see Note 1)
TYP
VLD = 15
70
120
μs
150
μs
12
μs
1.7
V
210
mV
V(SVS_IT--) ×
0.004
V(SVS_IT--) ×
0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61†
VLD = 13
3.24
3.5
3.76†
VLD = 14
3.43
3.7†
3.99†
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V/3 V
UNIT
V
mV
V
μA
†
The recommended operating voltage range is limited to 3.6 V.
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
typical characteristics
AVCC
V(SVS_IT--)
V(SVSstart)
Software sets VLD >0:
SVS is active
Vhys(SVS_IT--)
Vhys(B_IT--)
V(B_IT--)
VCC(start)
Brownout
Brownout
Region
Brownout
Region
1
0
SVS out
td(BOR)
1
0
td(SVSon)
Set POR
1
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT--)
td(SVSR)
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)
VCC(min) -- V
1.5
Triangular Drop
1
1 ns
1 ns
VCC
0.5
t pw
3V
0
1
10
100
1000
tpw -- Pulse Width -- μs
VCC(min)
tf = tr
tf
tr
t -- Pulse Width -- μs
Figure 13. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1)
MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1)
DCO frequency
PARAMETER
Vcc
Supply voltage range
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
UNIT
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
1.55
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
ratio
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
Duty cycle
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
%
41
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
--1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
calibrated DCO frequencies -- tolerance over temperature 0°C to 85°C
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over temperature
PARAMETER
0°C to 85°C
3V
--2.5
±0.5
+2.5
%
8-MHz tolerance over temperature
0°C to 85°C
3V
--2.5
±1.0
+2.5
%
12-MHz tolerance over temperature
0°C to 85°C
3V
--2.5
±1.0
+2.5
%
16-MHz tolerance over temperature
0°C to 85°C
%
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
42
1-MHz
1
MHz calibration value
8-MHz
8
MHz calibration value
12-MHz
12
MHz calibration value
16 MHz calibration value
16-MHz
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHz,
CALBC1 1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5ms
BCSCTL1 = CALBC1_8MHz,
CALBC1 8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
0°C
0
C to 85°C
85 C
0°C
0
C to 85°C
85 C
BCSCTL1 = CALBC1_12MHz,
CALBC1 12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
0°C
0
C to 85°C
85 C
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
CALDCO 16MHz
Gating time: 2 ms
0°C to 85°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3V
--3.0
±2.0
+3.0
2.2 V
0.970
1
1.030
3V
0.975
1
1.025
3.6 V
0.970
1
1.030
2.2 V
7.760
8
8.400
3V
7.800
8
8.200
3.6 V
7.600
8
8.240
2.2 V
11.64
12
12.36
3V
11.64
12
12.36
3.6 V
11.64
12
12.36
3V
15.52
16
16.48
3.6 V
15.00
16
16.48
MHz
MHz
MHz
MHz
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
--3
±2
+3
%
1.8 V to 3.6 V
--3
±2
+3
%
25°C
2.2 V to 3.6 V
--3
±2
+3
%
25°C
3.0 V to 3.6 V
--6
±2
+3
%
25°C
1.8 V to 3.6 V
0.970
1
1.030
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.760
8
8.240
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
25°C
3.0 V to 3.6 V
15.00
16
16.48
MHz
MIN
TYP
MAX
calibrated DCO frequencies -- overall tolerance
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance overall
--40°C to 105°C
1.8 V to 3.6 V
--5
±2
+5
%
8-MHz tolerance overall
--40°C to 105°C
1.8 V to 3.6 V
--5
±2
+5
%
12-MHz tolerance overall
--40°C to 105°C
2.2 V to 3.6 V
--5
±2
+5
%
--6
±3
+6
%
16-MHz tolerance overall
UNIT
--40°C to 105°C
3 V to 3.6 V
--40°C to 105°C
1.8 V to 3.6 V
0.950
1
1.050
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5ms
--40°C to 105°C
1.8 V to 3.6 V
7.600
8
8.400
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5ms
--40°C to 105°C
2.2 V to 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
--40°C to 105°C
3 V to 3.6 V
15.00
16
17.00
MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 1-MHz DCO frequency
1.02
Frequency -- MHz
1.01
TA = 105 °C
1.00
TA = 85 °C
TA = 25 °C
0.99
TA = --40 °C
0.98
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 14. Calibrated 1-MHz Frequency vs VCC
typical characteristics -- calibrated 8-MHz DCO frequency
8.20
TA = 105 °C
8.15
Frequency -- MHz
8.10
8.05
8.00
TA = 85 °C
TA = 25 °C
7.95
TA = --40 °C
7.90
7.85
7.80
1.5
2.0
2.5
3.0
VCC -- Supply Voltage -- V
3.5
4.0
Figure 15. Calibrated 8-MHz Frequency vs VCC
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated 12-MHz DCO frequency
12.2
Frequency -- MHz
12.1
TA = --40 °C
TA = 25 °C
12.0
TA = 85 °C
11.9
TA = 105 °C
11.8
11.7
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 16. Calibrated 12-MHz Frequency vs VCC
typical characteristics -- calibrated 16-MHz DCO frequency
16.1
16.0
Frequency -- MHz
TA = --40 °C
15.9
TA = 25 °C
TA = 85 °C
15.8
TA = 105 °C
15.7
15.6
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 17. Calibrated 16-MHz Frequency vs VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from low-power modes (LPM3/LPM4)
PARAMETER
tDCO,LPM3/4
tCPU,LPM3/4
TEST CONDITIONS
DCO clock wake-up
wake up time from LPM3/4
(see Note 1)
VCC
MIN
TYP
MAX
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHz,
DCOCTL = CALDCO_8MHz
2.2 V/3 V
1.5
BCSCTL1= CALBC1_12MHz,
DCOCTL = CALDCO_12MHz
2.2 V/3 V
1
BCSCTL1= CALBC1_16MHz,
DCOCTL = CALDCO_16MHz
3V
1
UNIT
μs
s
CPU wake-up time from LPM3/4
(see Note 2)
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
DCO Wake Time -- us
10.00
1.00
0.10
0.10
RSELx = 0...11
RSELx = 12...15
1.00
10.00
DCO Frequency -- MHz
Figure 18. Clock Wake-Up Time From LPM3 vs DCO Frequency
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO with external resistor ROSC (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
TYP
2.2 V
1.8
3V
1.95
UNIT
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1
1, RSELx = 4,
4 DCOx = 3,
3 MODx = 0,
0 TA = 25°C
MHz
Dt
Temperature drift
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
NOTE 1: ROSC = 100 kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
typical characteristics -- DCO with external resistor ROSC
10.00
DCO Frequency -- MHz
DCO Frequency -- MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
1.00
0.10
RSELx = 4
0.01
10.00
10000.00
ROSC -- External Resistor -- kOhm
10000.00
Figure 20. DCO Frequency vs ROSC,
VCC = 3.0 V, TA = 25°C
2.50
2.50
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
--25.0
0.0
25.0
50.0
75.0
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
ROSC = 1M
0.25
2.25
DCO Frequency -- MHz
2.25
DCO Frequency -- MHz
1000.00
ROSC -- External Resistor -- kOhm
Figure 19. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
0.00
--50.0
100.00
ROSC = 1M
0.25
100.0
0.00
1.5
Figure 21. DCO Frequency vs Temperature,
VCC = 3.0 V
POST OFFICE BOX 655303
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
TA -- Temperature -- °C
Figure 22. DCO Frequency vs VCC,
TA = 25°C
• DALLAS, TEXAS 75265
47
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0/1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic
level square wave input
frequency, LF mode
XTS = 0, LFXT1Sx = 3, XCAPx = 0
1.8 V to 3.6 V
Oscillation allowance for
LF crystals
OALF
Integrated effective load
capacitance LF mode
capacitance,
(see Note 1)
CL,eff
MIN
TYP
MAX
32,768
10,000
32,768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF
200
UNIT
Hz
50,000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle
LF mode
XTS = 0, Measured at P1.4/ACLK,
fLFXT1,LF = 32,768 Hz
fFault,LF
Oscillator fault
frequency, LF mode
(see Note 3)
XTS = 0, LFXT1Sx = 3, XCAPx = 0
(see Note 2)
2.2 V/3 V
30
2.2 V/3 V
10
50
pF
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
5. Applies only if using an external logic-level clock source. Not applicable when using a crystal or resonator.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
TA
--40°C to 85°C
fVLO
VLO frequency
dfVLO/dT
VLO frequency
temperature drift
See Note NO TAG1
dfVLO/dVCC
VLO frequency supply
voltage drift
See Note 2
105°C
VCC
2 2 V/3 V
2.2
2.2 V/3 V
25°C
1.8V -- 3.6V
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
0.5
%/°C
4
%/V
NOTES: 1. Calculated using the box method:
I version: (MAX(--40_C to 85_C) -- MIN(--40_C to 85_C))/MIN(--40_C to 85_C)/(85_C -- (--40_C))
T version: (MAX(--40_C to 105_C) -- MIN(--40_C to 105_C))/MIN(--40_C to 105_C)/(105_C -- (--40_C))
2. Calculated using the box method: (MAX(1.8 V to 3.6V) -- MIN(1.8V to 3.6V))/MIN(1.8 V to 3.6V)/(3.6 V -- 1.8 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
XTS = 1, LFXT1Sx = 0, XCAPx = 0
1.8 V to 3.6 V
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1, XCAPx = 0
1.8 V to 3.6 V
1
4
MHz
LFXT1 oscillator
ill t crystal
t l frequency,
f
HF mode 2
1.8 V to 3.6 V
2
10
fLFXT1,HF2
XTS = 1, LFXT1Sx = 2, XCAPx = 0
2.2 V to 3.6 V
2
12
LFXT1 oscillator logic level
square-wave
square
wave input frequency,
HF mode
fLFXT1,HF,logic
Oscillation allowance for HF
crystals
(see Figure 23 and Figure 24)
OAHF
Integrated effective load
capacitance, HF mode
(see Note 1)
CL,eff
Duty cycle
16
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0,
LFXT1Sx = 0, fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
2700
XTS = 1, XCAPx = 0,
LFXT1Sx = 1, fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
800
XTS = 1, XCAPx = 0,
LFXT1Sx = 2, fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
XTS = 1, XCAPx = 0 (see Note 2)
HF mode
Oscillator fault frequency, HF mode
(see Note 4)
fFault,HF
3 V to 3.6 V
XTS = 1, LFXT1Sx = 3, XCAPx = 0
2
1.8 V to 3.6 V
2.2 V/3 V
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
fLFXT1,HF = 16 MHz
2.2 V/3 V
40
XTS = 1, LFXT1Sx = 3, XCAPx = 0
(see Note 3)
2.2 V/3 V
30
40
50
MHz
Ω
1
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
fLFXT1,HF = 10 MHz
MHz
pF
60
%
50
60
300
kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
50
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1)
Oscillation Allowance -- Ohms
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
Figure 23. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
1500.0
XT Oscillator Supply Current -- uA
1400.0
1300.0
LFXT1Sx = 3
1200.0
1100.0
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
0.0
0.0
LFXT1Sx = 1
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 24. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, XT2 (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fXT2
XT2 oscillator crystal frequency,
mode 0
XT2Sx = 0
1.8 V to 3.6 V
0.4
1
MHz
fXT2
XT2 oscillator crystal frequency,
mode 1
XT2Sx = 1
1.8 V to 3.6 V
1
4
MHz
XT2 oscillator
ill t crystal
t l frequency,
f
mode 2
1.8 V to 3.6 V
2
10
fXT2
XT2Sx = 2
2.2 V to 3.6 V
2
12
XT2 oscillator
ill t logic
l i level
l
l
square-wave input frequency
fXT2
Oscillation allowance
(see Figure 23 and Figure 24)
OA
Integrated effective load
capacitance, HF mode
(see Note 1)
CL,eff
3 V to 3.6 V
XT2Sx = 3
16
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XT2Sx = 0, fXT2 = 1 MHz,
CL,eff = 15 pF
2700
XT2Sx = 1, fXT2 = 4 MHz,
CL,eff = 15 pF
800
XT2Sx = 2, fXT1,HF = 16 MHz,
CL,eff = 15 pF
300
See Note 2
Duty cycle
Measured at P1.4/SMCLK,
fXT2 = 16 MHz
Oscillator fault frequency, HF mode
(see Note 4)
XT2Sx = 3, (see Note 3)
pF
40
50
60
40
50
60
2 2 V/3 V
2.2
2.2 V/3 V
MHz
Ω
1
Measured at P1.4/SMCLK,
fXT2 = 10 MHz
fFault
2
1.8 V to 3.6 V
MHz
%
30
300
kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
52
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- XT2 oscillator
Oscillation Allowance -- Ohms
100000.00
10000.00
1000.00
XT2Sx = 3
100.00
XT2Sx = 2
XT2Sx = 1
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
XT Oscillator Supply Current -- uA
Figure 25. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
1600.0
1500.0
1400.0
1300.0
1200.0
1100.0
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
0.0
XT2Sx = 3
XT2Sx = 2
XT2Sx = 1
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 26. XT2 Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer A clock frequency
Timer_A
Internal: SMCLK, ACLK,
External: TACLK,
TACLK INCLK
INCLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A, capture timing
TA0, TA1, TA2
VCC
MIN
MAX
2.2 V
10
3.3 V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer_B
PARAMETER
TEST CONDITIONS
fTB
Timer B clock frequency
Timer_B
Internal: SMCLK, ACLK,
External: TBCLK
TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B, capture timing
TB0, TB1, TB2
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
MIN
MAX
2.2 V
10
3.3 V
16
2.2 V/3 V
20
UNIT
MHz
ns
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time
(see Note 1)
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V /3 V
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
600
ns
3V
50
100
600
ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 27 and Figure 28)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
TEST CONDITIONS
VCC
MIN
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid;
CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
1
with t LO∕HI ≥ max(t VALID,MO(USCI) + t SU,SI(Slave), t SU,MI(USCI) + t VALID,SO(Slave)).
2t LO∕HI
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
NOTE 2: f UCxCLK =
USCI (SPI slave mode) (see Figure 29 and Figure 30)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time,
STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time,
Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time,
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time,
STE high to SOMI high impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input
inp t data setup
set p time
tHD,SI
SIMO inp
inputt data hold time
tVALID,SO
SOMI o
output
tp t data valid
alid time
UCLK edge to SOMI valid;
CL = 20 pF
50
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
1
with t LO∕HI ≥ max(t VALID,MO(Master) + t SU,SI(USCI), t SU,MI(Master) + t VALID,SO(USCI))
2t LO∕HI
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
NOTE 3: f UCxCLK =
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 27. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 28. SPI Master Mode, CKPH = 1
56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
tHD,MI
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 29. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 30. SPI Slave Mode, CKPH = 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 31)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V/3 V
fSCL ≤ 100 kHz
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) Start
tSU,STA
Set p time for a repeated Start
Setup
tHD,DAT
Data hold time
2.2 V/3 V
0
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for Stop
2.2 V/3 V
4.0
μs
tSP
Pulse width of spikes suppressed by input filter
2.2 V
50
150
600
3V
50
100
600
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2 2 V/3 V
2.2
0
MAX
2 2 V/3 V
2.2
4.7
SDA
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 31. I2C Mode Timing
58
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
μs
s
0.6
tSU,STA tHD,STA
1/fSCL
μs
s
0.6
ns
ns
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
I(DD)
CAON = 1,
1 CARSEL = 0
0, CAREF = 0
I(Refladder/Refdiode)
CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
1/2/3 no load at P2.3/CA0/TA1
P2 3/CA0/TA1
and P2.4/CA1/TA2
V(IC)
CAON =1
2.2 V/3 V
0
PCA0 = 1, CARSEL = 1, CAREF = 1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
PCA0 = 1, CARSEL = 1, CAREF = 2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
V(Ref025)
V(Ref050)
Common-mode input voltage
Voltage @ 0.25 V
V
CC
node
CC
Voltage @ 0.5V
V
CC
node
CC
VCC --1
UNIT
μA
μA
V
V(RefVT)
See Figure 35 and Figure 36
PCA0 = 1, CARSEL = 1, CAREF = 3,
no load at P2.3/CA0/TA1
P2 3/CA0/TA1 and
P2.4/CA1/TA2, TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
--30
30
mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
TA = 25
25°C,
C, Overdrive 10 mV,
Without filter: CAF = 0
2.2 V
80
165
300
3V
70
120
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF = 1
2.2 V
1.4
1.9
2.8
3V
0.9
1.5
2.2
t(response)
Response time, low-to-high
low to high and
high-to-low (see Note 3)
mV
ns
μs
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled
(CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0V
0
VCC
1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 μs
Figure 32. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-400 mV
t(response)
V+
Figure 33. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
--
IOUT = 10μA
Comparator_A+
CASHORT = 1
Figure 34. Comparator_A+ Short Resistance Test Condition
60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator A+
650
650
VCC = 2.2 V
V(REFVT) -- Reference Volts --mV
600
Typical
550
500
450
400
--45
--25
--5
15
35
55
75
600
Typical
550
500
450
400
--45
95
--25
--5
15
35
55
75
95
TA -- Free-Air Temperature -- °C
TA -- Free-Air Temperature -- °C
Figure 36. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 35. V(RefVT) vs Temperature, VCC = 3 V
100.00
Short Resistance -- kΩ
V(REFVT) -- Reference Volts --mV
VCC = 3 V
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
10.00
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC -- Normalized Input Voltage -- V/V
Figure 37. Short Resistance vs VIN/VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
61
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
(see Note 2)
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x = 1, 0 ≤ x ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
fADC12CLK = 5 MHz, ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
IREF+
Operating
p
g supply
pp y current
i
into
AVCC terminal
i l
(see Note 4)
fADC12CLK = 5 MHz, ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5 MHz, ADC12ON = 0,
REFON = 1, REF2_5V = 0
CI †
Input capacitance
Only one terminal can be selected at one time,
P6.x/Ax
RI†
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC
VCC
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
0.8
3V
0.8
1.0
3V
0.5
0.7
2.2 V
0.5
0.7
3V
0.5
0.7
2.2 V
3V
mA
mA
A
40
pF
2000
Ω
†
Lmits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VeREF+ > VREF-- /VeREF-- (see Note 2)
1.4
VAVCC
V
Negative external
reference voltage input
VeREF+ > VREF-- /VeREF-- (see Note 3)
0
1.2
V
(VeREF+ -- VREF--/VeREF-- )
Differential external
reference voltage input
VeREF+ > VREF-- /VeREF-- (see Note 4)
1.4
VAVCC
V
IVeREF+
Static input current
0V ≤VeREF+ ≤ VAVCC
2.2 V/3 V
±1
μA
IVREF--/VeREF--
Static input current
0V ≤ VeREF-- ≤ VAVCC
2.2 V/3 V
±1
μA
VeREF+
Positive external
reference voltage input
VREF-- /VeREF--
VCC
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
62
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC built-in reference
PARAMETER
VREF+
AVCC(min)
IVREF+
IL(VREF)+ †
Positive built-in
reference voltage
output
AVCC minimum
voltage, positive
built-in
built
in reference
active
TEST CONDITIONS
VCC
REF2_5V = 1 (2.5 V)
IVREF+max ≤ IVREF+≤ IVREF+min
3V
REF2_5V = 0 (1.5 V)
IVREF+max ≤ IVREF+≤ IVREF+min
2.2 V/3 V
2.2 V/3 V
MIN
TYP
--40°C to 85°C
2.4
2.5
2.6
105°C
2.37
2.5
2.64
--40°C to 85°C
1.44
1.5
1.56
105°C
1.42
1.5
1.57
REF2_5V = 0,
IVREF+max ≤ IVREF+≤ IVREF+min
2.2
REF2_5V = 1,
--0.5mA ≤ IVREF+≤ IVREF+min
2.8
REF2_5V = 1,
--1mA ≤ IVREF+≤ IVREF+min
2.9
Load current out of
VREF+ terminal
Load-current
regulation VREF+
regulation,
terminal
TA
IVREF+ = 500 μA +/-- 100 μA
Analog input voltage ~0.75
0 75 V,
V
REF2_5V = 0
MAX
0.01
--0.5
3V
0.01
--1
2.2 V
±2
3V
±2
IVREF+ = 500 μA ± 100 μA
Analog input voltage ~1.25 V,
REF2_5V = 1
3V
±2
3V
20
Load current
regulation VREF+
terminal
IVREF+ = 100 μA → 900 μA,
CVREF+= 5 μF,
F at ~0.5
0 5 VREF+,
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at pin
VREF+ (see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V/3 V
TREF+†
Temperature
coefficient of
built-in reference
IVREF+ is a constant in the range
of 0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
tREFON†
Settle time of
internal reference
voltage (see
Figure 38 and Note
2)
IVREF+ = 0.5 mA, CVREF+ = 10 μF,
VREF+ = 1.5 V, VAVCC = 2.2 V
5
V
V
2.2 V
IDL(VREF) +‡
UNIT
10
mA
LSB
ns
μF
±100
17
ppm/°C
ms
†
Limits characterized
Limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use
two capacitors between pins VREF+ and AVSS and VREF-- /VeREF-- and AVSS: 10 μF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
‡
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- ADC12
CVREF+
100 μF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in μF
10 μF
1 μF
0
1 ms
10 ms
100 ms
tREFON
Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
64
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
From
Power
Supply
DVCC
+
-10 μ F
100 nF
AVCC
+
-10 μ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
10 μ F
MSP430F261x
MSP430F241x
100 nF
VREF --/VeREF--
+
-10 μ F
AVSS
VREF+ or VeREF+
+
--
Apply
External
Reference
DVSS
100 nF
Figure 39. Supply Voltage and Reference Voltage Design VREF--/VeREF-- External Supply
From
Power
Supply
DVCC
+
-10 μ F
100 nF
AVCC
+
-Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
10 μ F
100 nF
AVSS
MSP430F261x
MSP430F241x
VREF+ or VeREF+
+
-10 μ F
DVSS
100 nF
Reference Is Internally
Switched to AVSS
VREF-- /VeREF--
Figure 40. Supply Voltage and Reference Voltage Design VREF--/VeREF-- = AVSS, Internally Connected
POST OFFICE BOX 655303
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65
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit ADC timing parameters
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
Internal ADC12 oscillator
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12
linearity parameters
2.2V/3 V
0.45
5
6.3
MHz
ADC12DIV = 0,
fADC12CLK = fADC12OSC
2.2 V/ 3 V
3.7
5
6.3
MHz
CVREF+ ≥ 5 μF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V/ 3 V
2.06
tCONVERT
Conversion time
tADC12ON‡
Turn-on settling time of
the ADC
See Note 1
tSample‡
Sampling time
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] x CI;(see Note 2)
External fADC12CLK from ACLK, MCLK
or SMCLK, ADC12SSEL ≠ 0
3.51
μs
s
13 × ADC12DIV
× 1/fADC12CLK
100
3V
1220
2.2 V
1400
ns
ns
†
Limits characterized
Limits verified by design
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
‡
12-bit ADC linearity parameters
PARAMETER
TEST CONDITIONS
VCC
EI
Integral linearit
linearity error
1.4 V ≤ (VeREF+ -- VREF-- /VeREF-- ) min ≤ 1.6 V
1.6 V < (VeREF+ -- VREF-- /VeREF-- ) min ≤ VAVCC
ED
Differential linearity error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
EO
Offset error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
2.2 V/3 V
EG
Gain error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted error
(VeREF+ -- VREF-- /VeREF-- )min ≤ (VeREF+ -- VREF-- /VeREF-- ),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
66
POST OFFICE BOX 655303
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2 2 V/3 V
2.2
MIN
TYP
MAX
±2
±1.7
UNIT
LSB
±1
LSB
±2
±4
LSB
2.2 V/3 V
±1.1
±2
LSB
2.2 V/3 V
±2
±5
LSB
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC temperature sensor and built-in VMID
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
ISENSOR
Operating supply current into
AVCC terminal (see Note 1)
REFON = 0, INCH = 0Ah,
ADC12ON = 1, TA = 25_C
2.2 V
40
120
3V
60
160
VSENSOR†
See Note 2
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
986
3V
986
2.2 V
3.55
3V
3.55
TCSENSOR†
ADC12ON = 1
1, INCH = 0Ah
2.2 V
30
3V
30
UNIT
μA
A
mV
mV/°C
tSENSOR(sample)†
Sample time required if channel
10 is selected (see Note 3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at channel 11
(see Note 4)
ADC12ON = 1
1, INCH = 0Bh
VMID
AVCC divider
di ider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
2.2 V
1.1
1.1±0.04
3V
1.5
1.50±0.04
tVMID(sample)
Sample time required if channel
11 is selected (see Note 5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
μs
s
2.2 V
NA
3V
NA
μA
A
V
ns
† Limits characterized
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or if (ADC12ON = 1, INCH = 0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
4. No additional current is needed. The VMID is used during sampling.
5. The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
POST OFFICE BOX 655303
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
12-bit DAC supply specifications
PARAMETER
AVCC
IDD
PSRR
Analog supply voltage
Supply current, single
DAC channel
(see Notes 1 and 2)
Power-supply rejection
ratio
(see Notes 3 and 4)
TEST CONDITIONS
VCC
TA
AVCC = DVCC,
AVSS = DVSS = 0 V
MIN
TYP
2.20
MAX
UNIT
3.60
V
--40°C to 85°C
50
110
105°C
69
150
2.2V/3V
50
130
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2V/3V
200
440
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC
2.2V/3V
700
1500
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0x0800
2 2V/3V
2.2V/3V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = x00800 ,
VeREF+ = VREF+ = AVCC
μA
DAC12_xDAT = 800h, VREF = 1.5 V,
∆AVCC = 100mV
DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V,
∆AVCC = 100mV
2.2V
70
dB
3V
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20 × log{∆AVCC/∆VDAC12_xOUT}
4. VREF is applied externally. The internal reference is not used.
68
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC linearity specifications (see Figure 41)
PARAMETER
TEST CONDITIONS
Resolution
INL
DNL
VCC
MIN
12-bit monotonic
Integral nonlinearit
nonlinearity (see Note 1)
Differential nonlinearity
(see Note 1)
Offset voltage without calibration
(see Notes 1 and 2)
EO
Offset voltage with calibration
(see Notes 1 and 2)
dE(O)/dT
Offset error temperature
coefficient (see Note 1)
EG
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
tOffset_Cal
Offset Cal
Time for
Ti
f offset
ff t calibration
lib ti
(see Note 3)
TYP
MAX
12
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
VREF = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2 V
VREF = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
UNIT
bits
±2.0
20
±8.0
80
LSB
±0.4
04
±1.0
10
LSB
±21
21
mV
±2.5
25
2.2 V/3 V
VREF = 1.5 V
2.2 V
VREF = 2.5 V
3V
30
μV/C
±3.50
3 50
2.2 V/3 V
ppm of
FSR/°C
10
DAC12AMPx = 2
% FSR
100
DAC12AMPx = 3, 5
32
2.2 V/3 V
DAC12AMPx = 4, 6, 7
ms
6
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may affect accuracy and is not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Ideal transfer
function
Gain Error
DAC Code
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics -- 12-bit DAC, linearity specifications
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
INL -- Integral Nonlinearity Error -- LSB
4
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
--1
--2
--3
--4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL -- Differential Nonlinearity Error -- LSB
2.0
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
--0.5
--1.0
--1.5
--2.0
0
512
1024
1536
2048
2560
DAC12_xDAT -- Digital Code
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3072
3584
4095
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC output specifications
PARAMETER
TEST CONDITIONS
VCC
MIN
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
VO
Output voltage range
(see Note 1 and Figure 44)
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh,
DAC12IR = 1, DAC12AMPx = 7
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Max DAC12 load
capacitance
IL(DAC12)
Ma DAC12 load current
Max
c rrent
0
0.005
AVCC --0.05
AVCC
0
0.1
AVCC --0.13
AVCC
100
2.2V
--0.5
+0.5
3V
--1.0
+1.0
RLoad= 3 kΩ, VO/P(DAC12) = 0 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RO/P(DAC12)
RLoad= 3 kΩ, VO/P(DAC12) = AVCC,
DAC12AMPx = 7,
DAC12_xDAT = 0FFFh
UNIT
V
2.2 V/3 V
Output resistance
(see Figure 44)
MAX
2 2 V/3 V
2.2
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR =
1, DAC12AMPx = 7
CL(DAC12)
TYP
2.2 V/3 V
RLoad= 3 kΩ,
0.3 V < VO/P(DAC12) < AVCC -- 0.3 V,
DAC12AMPx = 7
150
250
150
250
1
4
pF
mA
Ω
NOTE 1: Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
ILoad
Max
RLoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC --0.3V
VOUT
AV CC
Figure 44. DAC12_x Output Resistance Tests
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MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC reference input specifications
PARAMETER
TEST CONDITIONS
Reference input voltage
range
VeREF+
VCC
DAC12IR = 0, (see Notes 1 and 2)
MIN
2 2 V/3 V
2.2
DAC12IR = 1, (see Notes 3 and 4)
DAC12_0 IR = DAC12_1 IR = 0
NOTES: 1.
2.
3.
4.
5.
Reference input
p
resistance
i
MAX
AVCC/3
AVCC+0.2
AVcc
AVcc+0.2
20
DAC12_0 IR = 1, DAC12_1 IR = 0
Ri(VREF+),
Ri(VeREF+)
TYP
DAC12_0 IR = 0, DAC12_1 IR = 1
2.2 V/3 V
UNIT
V
MΩ
40
48
56
20
24
28
kΩ
DAC12_0 IR = DAC12_1 IR = 1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC -- VE(O)] / [3*(1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC -- VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC dynamic specifications, Vref = VCC, DAC12IR = 1 (see Figure 45 and Figure 46)
PARAMETER
tON
tS(FS)
tS(C-C)
SR
DAC12 on-time
TEST CONDITIONS
DAC12_xDAT
_
= 800h,,
ErrorV(O) < ±0.5 LSB
(see Note 1 and
Figure 45)
Settling
S
ttli time,
ti
full scale
DAC12_xDAT
DAC12
DAT =
80h→ F7Fh→ 80h
Settling
S
ttli time,
ti
code to code
DAC12_xDAT
DAC12
xDAT =
3F8h→
3F8h 408h→
408h 3F8h
BF8h→ C08h→ BF8h
Slew rate
DAC12_xDAT
DAC12
DAT =
80h→ F7Fh→ 80h
Glitch
Glit
h energy,
full scale
DAC12_xDAT
DAC12
DAT =
80h→ F7Fh→ 80h
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V/3
/ V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
DAC12AMPx = 3, 5
2.2 V/3 V
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
TYP
MAX
60
120
15
30
6
12
100
200
40
80
15
30
DAC12AMPx = 3, 5
2
2.2 V/3 V
DAC12AMPx = 4, 6, 7
DAC12AMPx = 3, 5
2.2 V/3 V
DAC12AMPx = 4, 6, 7
0.05
0.12
0.35
0.7
1.5
2.7
DAC12AMPx = 2
2.2 V/3 V
DAC12AMPx = 4, 6, 7
150
30
Conversion 1
ILoad
Glitch
Energy
Conversion 2
AV CC
+/-- 1/2 LSB
CLoad = 100pF
tsettleLH
Figure 45. Settling Time and Glitch Energy Testing
72
Conversion 3
+/-- 1/2 LSB
2
RO/P(DAC12.x)
POST OFFICE BOX 655303
μs
V/μs
600
DAC12AMPx = 3, 5
VOUT
μs
1
DAC12AMPx = 2
RLoad = 3 kΩ
μs
μ
5
NOTES: 1. RLoad and CLoad are connected to AVSS (not AVCC/2) in Figure 45.
2. Slew rate applies to output voltage steps ≥ 200 mV.
DAC Output
UNIT
• DALLAS, TEXAS 75265
tsettleHL
nV-ss
nV
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 46. Slew Rate Testing
12-bit DAC, dynamic specifications (continued) (TA = 25°C, unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW --3dB
3-dB bandwidth,
VDC = 1.5V, VAC = 0.1 VPP
(see Figure 47)
Channel to channel crosstalk
Channel-to-channel
(see Note 1 and Figure 48)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 80h<-->F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz, Duty cycle = 50%
MAX
UNIT
40
180
2.2 V/3 V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h<-->F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz, Duty cycle = 50%
TYP
kHz
550
--80
2 2 V/3 V
2.2
dB
--80
NOTE 1: RLOAD = 3 kΩ, CLOAD = 100 pF
Ve REF+
ILoad
DAC12_x
RLoad = 3 kΩ
AV CC
2
DACx
AC
CLoad = 100pF
DC
Figure 47. Test Conditions for 3-dB Bandwidth Specification
ILoad
DAC12_0
AV CC
DAC12_xDAT 080h
2
DAC0
ILoad
AV CC
7F7h
080h
V DAC12_xOUT
2
DAC1
080h
V DAC12_yOUT
RLoad
DAC12_1
7F7h
V OUT
CLoad= 100pF
VREF+
e
RLoad
fToggle
CLoad= 100pF
Figure 48. Crosstalk Test Conditions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
73
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.2 V/ 3.6 V
3
5
mA
IERASE
Supply current from DVCC during erase
2.2 V/ 3.6 V
3
7
mA
tCPT
Cumulative program time
See Note 1
2.2 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
See Note 2
2.2 V/ 3.6 V
200
104
Program/Erase endurance
ms
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See Note 3
100
35
years
tFTG
tBlock, 0
Block program time for first byte or word
See Note 3
30
tFTG
tBlock, 1-63
Block program time for each additional byte or word
See Note 3
21
tFTG
tBlock, End
Block program end-sequence wait time
See Note 3
6
tFTG
tMass Erase
Mass erase time (see Note 4)
See Note 3
10593
tFTG
tSeg Erase
Segment erase time
See Note 3
4819
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/fFTG,max = 5297 × 1/476 kHz). To
achieve the required cumulative mass erase time, the Flash Controller’s mass erase operation can be repeated until this time is met.
A worst case minimum of 19 cycles is required.
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
4. To erase the complete code area, the mass erase must be performed once with a dummy address in the range of the lower 64-kB
flash addresses and once with the dummy address in the upper 64-kB flash addresses.
RAM
PARAMETER
VRAMh
TEST CONDITIONS
See Note 1
CPU halted
MIN
1.6
MAX
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
74
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
JTAG interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
See Note 1
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
See Note 2
VCC
MIN
TYP
MAX
2.2 V
0
5
3V
0
10
2.2 V/ 3 V
25
60
90
MIN
MAX
UNIT
MHz
kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER
TEST CONDITIONS
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse blow (F versions)
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TA = 25°C
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
76
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P1 (P1.0 to P1.7) pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK
/
X
0
FUNCTION
P1.0 (I/O)
Timer_A3.TACLK
CAOUT
P1.1/TA0
/
P1.2/TA1
/
P1.3/TA2
/
1
2
3
P1.4/SMCLK
/
4
P1.5/TA0
/
5
P1.7/TA2
/
6
7
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
P1.1 (I/O)
P1.2 (I/O)
P1.3 (I/O)
P1.4 (I/O)
SMCLK
P1.6/TA1
/
CONTROL BITS / SIGNALS
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA2
1
1
P1.5 (I/O)
P1.6 (I/O)
P1.7 (I/O)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
77
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2 pin schematic: P2.0 to P2.4, P2.6, and P2.7, input/output with Schmitt trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
D
Module X IN
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
78
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0/CA6
P2.7/TA0/CA7
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions
PIN NAME (P2.X)
(P2 X)
P2.0/ACLK/CA2
/
/
P2.1/TAINCLK/CA3
/
/
P2.2/CAOUT/TA0/
/
/
/
CA4
P2.3/CA0/TA1
/
/
P2.4/CA1/TA2
/
/
P2.6/ADC12CLK/
/
/
DMAE0/CA6
P2.7/TA0/CA7
/
/
X
0
1
2
3
4
6
7
CONTROL BITS / SIGNALS
FUNCTION
CAPD.x
P2DIR.x
P2SEL.x
P2.0 (I/O)
0
I: 0; O: 1
0
ACLK
0
1
1
CA2
1
X
X
P2.1 (I/O)
0
I: 0; O: 1
0
Timer_A3.INCLK
0
0
1
DVSS
0
1
1
CA3
1
X
X
P2.2 (I/O)
0
I: 0; O: 1
0
CAOUT
0
1
1
TA0
0
0
1
CA4
1
X
X
P2.3 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA1
0
1
1
CA0
1
X
X
P2.4 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA2
0
1
X
CA1
1
X
1
P2.6 (I/O)
0
I: 0; O: 1
0
ADC12CLK
0
1
1
DMAE0
0
0
1
CA6
1
X
X
P2.7 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA0
0
1
1
CA7
1
X
X
NOTE: X: Don’t care
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
79
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P2 pin schematic: P2.5, input/output with Schmitt trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2IFG.5
P2SEL.5
Interrupt
Edge Select
P2IES.5
Port P2.5 pin functions
PIN NAME (P2.X)
(P2 X)
P2.5/R
/ OSC//CA5
X
5
FUNCTION
CONTROL BITS / SIGNALS
CAPD
DCOR
P2DIR.5
P2.5 (I/O)
0
0
I: 0; O: 1
0
ROSC (see Note 2)
0
1
X
X
DVSS
0
0
1
1
CA5
1 or selected
0
X
X
NOTES: 1. X: Don’t care
2. If Rosc is used it is connected to an external resistor.
80
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2SEL.5
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P3 pin schematic: P3.0 to P3.7, input/output with Schmitt trigger
Pad Logic
P3REN.x
P3DIR.x
0
Module
direction
P3OUT.x
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
0
Module X OUT
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.0 to P3.7 pin functions
PIN NAME (P3.X)
(P3 X)
X
P3.0/UCB0STE/
/
/
UCA0CLK
0
P3.1/UCB0SIMO/
/
/
UCB0SDA
1
P3.2/UCB0SOMI/
/
/
UCB0SCL
2
P3.3/UCB0CLK/
/
/
UCA0STE
3
P3.4/UCA0TXD/
/
/
UCA0SIMO
4
P3.5/UCA0RXD/
/
/
UCA0SOMI
5
P3.6/UCA1TXD/
/
/
UCA1SIMO
6
P3.7/UCA1RXD/
/
/
UCA1SOMI
7
NOTES: 1.
2.
3.
4.
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK (see Note 2 and 4)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (see Note 2 and 3)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (see Note 2 and 3)
P3.3 (I/O)
UCB0CLK/UCA0STE (see Note 2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (see Note 2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (see Note 2)
P3.6 (I/O)
UCA1TXD/UCA1SIMO (see Note 2)
P3.7 (I/O)
UCA1RXD/UCA1SOMI (see Note 2)
CONTROL BITS / SIGNALS
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X: Don’t care
The pin direction is controlled by the USCI module.
In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI A0/B0 will
be forced to 3-wire SPI mode if 4-wire SPI mode is selected.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
81
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Port P4.0 to P4.7 pin functions
PIN NAME (P4.X)
(P4 X)
P4.0/TB0
/
P4.1/TB1
/
P4.2/TB2
/
P4.3/TB3
/
P4.4/TB4
/
X
0
1
2
3
4
FUNCTION
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B7.CCI0A and Timer_B7.CCI0B
0
1
Timer_B7.TB0
1
1
P4.0 (I/O)
P4.1 (I/O)
I: 0; O: 1
0
Timer_B7.CCI1A and Timer_B7.CCI1B
0
1
Timer_B7.TB1
1
1
P4.2 (I/O)
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB2
1
1
P4.3 (I/O)
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3
1
1
I: 0; O: 1
0
0
1
P4.4 (I/O)
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
P4.5/TB5
/
5
P4.5 (I/O)
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5
P4.6/TB6
/
6
P4.6 (I/O)
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6
P4.7/TBCLK
/
7
P4.7 (I/O)
Timer_B7.TBCLK
82
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
1
1
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P5 pin schematic: P5.0 to P5.7, input/output with Schmitt trigger
Pad Logic
P5REN.x
P5DIR.x
0
Module
Direction
1
P5OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5SEL.x
P5IN.x
EN
Module X IN
D
Port P5.0 to P5.7 pin functions
PIN NAME (P5.X)
(P5 X)
X
P5.0/UCB1STE/
/
/
UCA1CLK
0
P5.1/UCB1SIMO/
/
/
UCB1SDA
1
P5.2/UCB1SOMI/
/
/
UCB1SCL
2
P5.3/UCB1CLK/
/
/
UCA1STE
3
P5.4/MCLK
/
4
P5.5/SMCLK
/
5
FUNCTION
P5.0 (I/O)
UCB1STE/UCA1CLK (see Note 2 and 4)
P5.1 (I/O)
UCB1SIMO/UCB1SDA (see Note 2 and 3)
P5.2 (I/O)
UCB1SOMI/UCB1SCL (see Note 2 and 3)
P5.3 (I/O)
UCB1CLK/UCA1STE (see Note 2)
P5.0 (I/O)
MCLK
6
NOTES: 1.
2.
3.
4.
7
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
1
1
0
1
1
I: 0; O: 1
0
1
1
P5.7 (I/O)
I: 0; O: 1
0
TBOUTH
0
1
SVSOUT
1
1
P5.2 (I/O)
ACLK
P5.7/TBOUTH/
/
/
SVSOUT
P5DIR.x
I: 0; O: 1
P5.1 (I/O)
SMCLK
P5.6/ACLK
/
CONTROL BITS / SIGNALS
X: Don’t care
The pin direction is controlled by the USCI module.
In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A1/B1 will
be forced to 3-wire SPI mode if 4-wire SPI mode is selected.
POST OFFICE BOX 655303
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83
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.0 to P6.4, input/output with Schmitt trigger
Pad Logic
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Port P6.0 to P6.4 pin functions
PIN NAME (P6.X)
(P6 X)
P6.0/A0
/
X
0
FUNCTION
P6.0 (I/O)
A0 (see Note 2)
P6.1/A1
/
1
P6.2/A2
/
2
P6.3/A3
/
3
P6.1 (I/O)
A1 (see Note 2)
P6.2 (I/O)
A2 (see Note 2)
P6.3 (I/O)
A3 (see Note 2)
P6.4/A4
/
4
P6.4 (I/O)
A4 (see Note 2)
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
84
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.5 and P6.6, input/output with Schmitt trigger
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
P6DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.x
DVSS
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Port P6.5 to P6.6 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
P6.5/A5/DAC1†
/ /
†
X
5
FUNCTION
P6.5 (I/O)
6
P6SEL.x
CAPD.x or
DAC12AMP > 0
I: 0; O: 1
0
0
DVSS
1
1
0
A5 (see Note 2)
X
X
1
DAC1 (DA12OPS= 1, see Note 3)
P6.6/A6/DAC0†
/ /
†
P6DIR.x
X
X
1
I: 0; O: 1
0
0
DVSS
1
1
0
A6 (see Note 2)
X
X
1
DAC0 (DA12OPS= 0, see Note 3)
X
X
1
P6.6 (I/O)
†
MSP430F261x devices only
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
POST OFFICE BOX 655303
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85
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P6 pin schematic: P6.7, input/output with Schmitt trigger
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
P6DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P6OUT.7
DVSS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
Module X IN
D
Port P6.7 pin functions
PIN NAME (P6.X)
(P6 X)
P6.7/A7/DAC1†/
/ /
†/
SVSIN†
X
7
FUNCTION
P6.7 (I/O)
P6DIR.x
P6SEL.x
I: 0; O: 1
0
DVSS
1
1
A7 (see Note 2)
X
X
DAC1 (DA12OPS= 0, see Note 3)
X
X
SVSIN (VLD = 15)
X
X
NOTES: 1. X: Don’t care
2. The ADC12 channel Ax is connected to AVss internally if not selected.
3. The DAC outputs are floating if not selected.
† MSP430F261x devices only
86
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P7 pin schematic: P7.0 to P7.7, input/output with Schmitt trigger†
Pad Logic
P7REN.x
P7DIR.x
0
0
1
P7OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P7.x
P7SEL.x
P7IN.x
EN
Module X IN
D
Port P7.0 to P7.7 pin functions†
PIN NAME (P7.X)
(P7 X)
P7.0
X
0
FUNCTION
P7.0 (I/O)
Input
P7.1
1
P7.2
2
P7.3
3
P7.1 (I/O)
Input
P7.2 (I/O)
Input
P7.3 (I/O)
Input
P7.4
4
P7.4 (I/O)
Input
P7.5
5
P7.6
6
P7.5 (I/O)
Input
P7.6 (I/O)
Input
P7.7
7
P7.7 (I/O)
Input
†
CONTROL BITS / SIGNALS
P7DIR.x
P7SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin devices only
POST OFFICE BOX 655303
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87
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.0 to P8.5, input/output with Schmitt trigger†
Pad Logic
P8REN.x
P8DIR.x
0
0
1
P8OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
Module X IN
D
Port P8.0 to P8.5 pin functions†
PIN NAME (P8.X)
(P8 X)
P8.0
X
0
FUNCTION
P8.0 (I/O)
Input
P8.1
1
P8.2
2
P8.3
3
P8.1 (I/O)
Input
P8.2 (I/O)
Input
P8.3 (I/O)
Input
P8.4
4
P8.4 (I/O)
Input
P8.5
5
P8.5 (I/O)
Input
†
80-pin devices only
88
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.6, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
0
XT2CLK
From
P8.7/XIN
1
P8.7/XIN
XT2 off
Pad Logic
P8SEL.7
P8REN.6
P8DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.6
DVSS
P8.6/XOUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
Module X IN
D
Port P8.6 pin functions†
PIN NAME (P8.X)
(P8 X)
P8.6/XOUT
/
†
X
6
FUNCTION
CONTROL BITS / SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XOUT (default)
0
1
DVSS
1
1
P8.6 (I/O)
80-pin devices only
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
89
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Port P8 pin schematic: P8.7, input/output with Schmitt trigger†
BCSCTL3.XT2Sx = 11
P8.6/XOUT
XT2 off
0
XT2CLK
1
P8SEL.6
Pad Logic
P8REN.7
0
P8DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.7
DVSS
P8.7/XIN
Bus
Keeper
EN
P8SEL.7
P8IN.7
EN
Module X IN
D
Port P8.7 pin functions†
PIN NAME (P8.X)
(P8 X)
P8.7/XIN
/
†
X
7
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XIN (default)
0
1
VSS
1
1
P8.7 (I/O)
80-pin devices only
90
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
and
DVCC
Emulation
Module
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
91
MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 49). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 49. Fuse Check Mode Current
92
POST OFFICE BOX 655303
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MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541A -- JUNE 2007 -- REVISED OCTOBER 2007
Data Sheet Revision History
LITERATURE
NUMBER
SLAS541
SLAS541A
SUMMARY
Product Preview release.
Production Data release.
Corrected the format and the content shown on the first page.
Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list.
Corrected the port schematics.
Corrected “calibration data” section (page 20). Typos and formatting corrected.
Added figure “typical characteristics -- LPM4 current” (page 33).
POST OFFICE BOX 655303
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93
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2416TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2416TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2417TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2418TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2419TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2616TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2617TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPM
ACTIVE
LQFP
PM
64
160
CU NIPDAU
Level-3-260C-168 HR
Addendum-Page 1
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2618TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2618TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2619TPNR
ACTIVE
LQFP
PN
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
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1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
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amplifier.ti.com
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logic.ti.com
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microcontroller.ti.com
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