AD DAC312HP 12-bit high speed multiplying d/a converter Datasheet

a
12-Bit High Speed Multiplying
D/A Converter
DAC312
FEATURES
Differential Nonlinearity: 61/2 LSB
Nonlinearity: 0.05%
Fast Settling Time: 250 ns
High Compliance: –5 V to +10 V
Differential Outputs: 0 to 4 mA
Guaranteed Monotonicity: 12 Bits
Low Full-Scale Tempco: 10 ppm/8C
Circuit Interface to TTL, CMOS, ECL, PMOS/NMOS
Low Power Consumption: 225 mW
Industry Standard AM6012 Pinout
Available In Die Form
PIN CONNECTIONS
20-Pin Hermetic DIP (R-Suffix),
20-Pin Plastic DIP (P-Suffix),
20-Pin SOL (S-Suffix)
GENERAL DESCRIPTION
The DAC312 series of 12-bit multiplying digital-to-analog converters provide high speed with guaranteed performance to
0.012% differential nonlinearity over the full commercial operating temperature range.
The DAC312 combines a 9-bit master D/A converter with a
3-bit (MSBs) segment generator to form an accurate 12-bit D/A
converter at low cost. This technique guarantees a very uniform
step size (up to ± 1/2 LSB from the ideal), monotonicity to
12-bits and integral nonlinearity to 0.05% at its differential current outputs. In order to provide the same performance with a
12-bit R-2R ladder design, an integral nonlinearity over temperature of 1/2 LSB (0.012%) would be required.
The 250 ns settling time with low glitch energy and low power
consumption are achieved by careful attention to the circuit design and stringent process controls. Direct interface with all
popular logic families is achieved through the logic threshold
terminal.
High compliance and low drift characteristics (as low as
10 ppm/°C) are also features of the DAC312 along with an excellent power supply rejection ratio of ± .001% FS/%∆V. Operating over a power supply range of +5/–11 V to ± 18 V the
device consumes 225 mW at the lower supply voltages with an
absolute maximum dissipation of 375 mW at the higher supply
levels.
With their guaranteed specifications, single chip reliability and
low cost, the DAC312 device makes excellent building blocks
for A/D converters, data acquisition systems, video display drivers, programmable test equipment and other applications where
low power consumption and complete input/output versatility
are required.
FUNCTIONAL BLOCK DIAGRAM
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
DAC312–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Resolution
Monotonicity
Differential Nonlinearity
DNL
Nonlinearity
INL
Full-Scale Current
IFS
Full-Scale Tempco
TCI FS
Output Voltage Compliance
VOC
Full-Scale Symmetry
Zero-Scale Current
Settling Time
IFSS
IZS
tS
Propagation Delay–All Bits
tPLH
tPHL
Output Resistance
Output Capacitance
Logic Input
Levels “0”
Levels “1”
Logic Input Current
Logic Input Swing
Reference Bias Current
Reference Input
Slew Rate
Power Supply Sensitivity
RO
COUT
Power Supply Current
Power Dissipation
Conditions
DAC312E
Typ
Max
Min
Min
12
12
Deviation from Ideal
Step Size 2
Deviation from Ideal
Straight Line1
VREF = 10 V
R14 = R15 = 10 kΩ2
DNL Specification Guaranteed over Compliance Range
|IFS|–|IFS|
dl/dt
PSSI FS+
R14(eq) = 800 Ω, CC = 0 pF1
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
VOUT = 0 V
VOUT = 0 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
V+
V–
I+
I–
I+
I–
Pd
3.967
Units
12
12
Bits
Bits
± 0.0250 %FS
±1
LSB
± 0.05
%FS
± 0.0250
±1
± 0.05
4.031
± 20
± 0.002
3.935 3.999
± 10
± 0.001
4.063
± 40
± 0.004
3.935 3.999
± 80
± 0.008
4.063
mA
ppm/°C
%FS/°C
+10
±1
0.10
–5
± 0.4
+10
±2
0.10
–5
± 0.4
± 0.4
+10
±2
0.10
V
µA
µA
250
25
25
500
50
50
250
25
25
500
50
50
250
25
25
500
50
50
ns
ns
ns
>10
20
0.8
>10
20
0.8
2
–0.5
4
8
± 0.0005
40
+18
–2
2
–5
0
–0.5
4
8
± 0.001
± 0.0005
± 0.00025 ± 0.001
18
–10.8
3.3
7
–13.9
–18
3.9
7
–13.9
–18
225
305
267
375
4.5
–18
MΩ
pF
0.8
2
–5
0
TYPICAL ELECTRICAL CHARACTERISTICS
DAC312H
Typ
Max
3.999
±5
± 0.005
–5
4.5
–18
Min
12
12
>10
20
VLC = GND
VLC = GND
VIN = –5 to +18 V
DAC312F
Typ
Max
± 0.0125
± 0.5
± 0.05
To ± 1/2 LSB, All Bits
Switched ON or OFF1
All Bits Switched 50% Point
Logic Swing to 50% Point
Output1
VIL
VIH
IIN
VIS
I15
PSSIFS–
Power Supply Range
(@ VS = 615 V, IREF = 1.0 mA, 08C ≤ TA ≤ +708C for DAC312E and –408C ≤ TA ≤ +858C
for DAC312F, DAC312H, unless otherwise noted. Output characteristics refer
to both IOUT and IOUT.)
40
+18
–2
–5
0
–0.5
4
8
± 0.001
± 0.0005
± 0.00025 ± 0.001
18
–10.8
3.3
7
–13.9
–18
3.9
7
–13.9
–18
225
305
267
375
4.5
–18
40
+18
–2
V
V
µA
V
µA
mA/µs
± 0.001
%FS/%∆V
± 0.00025 ± 0.001
18
–10.8
3.3
7
–13 9
–18
3.9
7
–13.9
–18
225
305
267
375
%FS/%∆V
V
V
mA
mA
mA
mA
mW
mW
@ 258C; VS = 615 V, and IREF = 1.0 mA, unless otherwise noted. Output
characteristics refer to both IOUT and IOUT.
Parameter
Symbol
Reference Input
Slew Rate
dl/dt
Propagation Delay
tPLH, tPHL
Settling Time
tS
Full-Scale
DAC312N
Typical
DAC312G
Typical
Units
8
8
mA/µs
Any Bit
25
25
ns
To ± 1/2 LSB, All
Bits Switched ON
or OFF.
250
250
ns
± 10
± 10
ppm/°C
Conditions
TCIFS
–2–
REV. C
DAC312
ELECTRICAL CHARACTERISTICS
@ VS = 615 V, IREF = 1.0 mA, 08C ≤ TA ≤ 708C for DAC312E and –408C ≤ TA ≤ +858C for
DAC312F, DAC312H, unless otherwise noted. Output characteristics refer to both IOUT and IOUT. Continued
Symbol
Conditions
Logic Input
Levels “0”
VIL
VLC = GND
Logic Input
Levels “1”
VIH
VLC = GND
Logic Input
Current
IIN
VIN = –5 V to +18 V
Logic Input
Swing
VIS
–5
Reference Bias
Current
I15
0
–0.5
4
8
Reference Input
Slew Rate
dl/dt
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
Power Supply
Range
V+
V–
Power Supply
Current
I+
I–
I+
I–
Power
Dissipation
Pd
R14(eq) = 800 Ω
CC = 0 pF (Note 1)
Min
DAC312E
Typ
Max
Parameter
0.8
2
2
Max
Units
0.8
V
2
V
40
+18
–5
–2
0
–0.5
4
8
+18
–5
–2
0
–0.5
4
8
40
µA
+18
V
–2
µA
mA/µs
± 0.0005 ± 0.001
± 0.0005 ± 0.001
± 0.0005 ± 0.001 %FS/%∆V
± 0.00025 ± 0.001
± 0.00025 ± 0.001
± 0.00025 ± 0.001 %FS/%∆V
4.5
–18
18
–10.8
4.5
–18
18
–10.8
4.5
–18
18
–10.8
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
3.3
–13.9
3.9
–13.9
7
–18
7
–18
3.3
–13.9
3.9
–13.9
7
–18
7
–18
3.3
–13.9
3.9
–13.9
7
–18
7
–18
V+ = +5 V, V– = –15 V
V+ = +15 V, V– = –15 V
225
267
305
375
225
267
305
375
225
267
305
375
NOTES
1
Guaranteed by design.
2
TA = +25°C for DAC312H grade only.
Specifications subject to change without notice.
REV. C
DAC312H
Min Typ
0.8
40
V+ = +13.5 V to +16.5 V,
V– = –15 V
V– = –13.5 V to –16.5 V,
V+ = +15 V
VOUT = 0 V
DAC312F
Min Typ
Max
–3–
V
mA
mW
DAC312
WAFER TEST LIMITS @ V = 615 V, I
S
REF =
1.0 mA, TA = 258C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.
DAC312N
Limit
DAC312G
Limit
Units
Resolution
12
12
Bits min
Monotonicity
12
12
Bits min
Parameter
Symbol
Conditions
± 0.05
± 0.05
%FS max
Full-Scale Current
Change <1/2 LSB
+10
–5
+10
–5
V max
V min
VREF = 10.000 V
R14, R15 = 10.000 kΩ
4.031
3.967
4.063
3.935
mA max
mA min
±1
±2
µA max
Nonlinearity
Output Voltage
Compliance
Voc
Full-Scale
Current
Full-Scale Symmetry
IFSS
Zero-Scale Current
IZS
0.1
0.1
µA max
Differential
Nonlinearity
DNL
Deviation from
Ideal Step Size
± 0.012
± 1/2
± 0.025
±1
%FS max
Bits (LSB) max
Logic Input Levels “0”
VIL
VLC = GND
0.8
0.8
V max
VLC = GND
Logic Input Levels “1”
VIH
2
2
V min
Logic Input Swing
VIS
+18
–5
+18
–5
V max
V min
Reference Bias
Current
I15
–2
–2
µA max
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
V+ = +13.5 V to +16.5 V, V– = –15 V
V– = –13.5 V to –16.5 V, V+ = +15 V
± 0.001
± 0.001
± 0.001
± 0.001
%/%max
Power Supply
Current
I+
I–
VS = +15 V
IREF ≤ 1.0 mA
7
–18
7
–18
mA max
Power
Dissipation
PD
VS = +15 V
IREF ≤ 1.0 mA
375
375
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
DICE CHARACTERISTICS
1. B1 (MSB)
2. B2
3. B3
4. B4
5. B5
6. B6
7. B7
8. B8
9. B9
10. B10
11. B11
12. B12 (LSB)
13. VLC/AGND
14. VREF(+)
15. VREF(–)
16. COMP
17. V–
18. IO
19. IO
20. V+
DIE SIZE 0.141 × 0.096 inch, 13,536 sq. mils (3.58 × 2.44 mm, 8.74 sq. mm)
–4–
REV. C
DAC312
ABSOLUTE MAXIMUM RATINGS 1
Operating Temperature
DAC312E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
DAC312F, DAC312H . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature (Tj) . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . . . . 300°C
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +18 V
Analog Current Outputs . . . . . . . . . . . . . . . . . . . . –8 V to +12 V
Reference Inputs V14, V15 . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage (V 14, V15) . . . . . . . . . . ± 18 V
Reference Input Current (I 14) . . . . . . . . . . . . . . . . . . . . . 1.25 mA
Package Type
uJA2
uJC
Units
20-Pin Hermetic DIP (R)
20-Pin Plastic DIP (P)
20-Pin SOL (S)
76
69
88
11
27
25
°C/W
°C/W
°C/W
ORDERING GUIDE1
Model
DNL
Temperature
Range
Package
Description
Package
Option
DAC312ER2
DAC312FR
DAC312BR/883
DAC312HP
DAC312HS
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
Cerdip-20
Cerdip-20
Cerdip-20
Plastic DIP-20
SOL-20
Q-20
Q-20
Q-20
N-20
R-20
NOTES
1
Burn-in is available on commercial and industrial temperature range parts in
cerdip, plastic DIP, and TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part
number. Consult factory for 883 data sheet.
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for cerdip and P-DIP packages; θJA is specified for device soldered to
printed circuit board for SOL package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC312 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–5–
WARNING!
ESD SENSITIVE DEVICE
DAC312
TYPICAL PERFORMANCE CHARACTERISTICS
Output Current vs. Output Voltage
(Output Voltage Compliance)
Reference Amplifier Common-Mode
Range
Output Compliance vs. Temperature
Power Supply Current vs. Power
Supply Voltage
Power Supply Current vs.
Temperature
True and Complementary Output
Operation
Reference Amplifier Small-Signal
Frequency Response
Reference Amplifier Large-Signal
Frequency Response
–6–
Gain Accuracy vs. Reference Current
REV. C
DAC312
BASIC CONNECTIONS
Positive Low Impedance Output Operation
Negative Low Impedance Output Operation
Basic Negative Reference Operation
REV. C
Accommodating Bipolar References
Recommended Full-Scale Adjustment Circuit
Basic Positive Reference Operation
Pulsed Reference Operation
–7–
DAC312
BASIC CONNECTIONS
Interfacing with Various Logic Families
Bipolar Offset (True Zero)
Code Format
Output Scale
MSB
LSB IO
IO
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (mA) (mA) VOUT
Offset Binary;
True Zero Output.
Positive Full-Scale
Positive Full-Scale –LSB
+LSB
Zero-Scale
–LSB
Negative Full-Scale +LSB
Negative Full-Scale
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
3.999
3.998
2.001
2.000
1.999
0.001
0.000
0.000
0.001
1.998
1.999
2.000
3.998
3.999
9.9951
9.9902
0.0049
0.000
–0.0049
–9.9951
–10.000
2s Complement;
True Zero Output
MSB Complemented
(Need Inverter at B1).
Positive Full-Scale
Positive Full-Scale –LSB
+1 LSB
Zero-Scale
–1 LSB
Negative Full-Scale +LSB
Negative Full-Scale
0
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
3.999
3.998
2.001
2.000
1.999
0.001
0.000
0.000
0.001
1.998
1.999
2.000
3.998
3.999
9.9951
9.9902
0.0049
0.000
–0.0049
–9.9951
–10.000
–8–
REV. C
DAC312
BASIC CONNECTIONS
Basic Unipolar Operation
Code Format
Output Scale
MSB
LSB IO
IO
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (mA) (mA) VOUT
Straight Binary;
Unipolar with True
Input Code, True
Zero Output.
Positive Full-Scale
Positive Full-Scale –LSB
LSB
Zero-Scale
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
3.999
3.998
0.001
0.000
0.000
0.001
3.998
3.999
9.9976
9.9951
0.0024
0.0000
Complementary Binary;
Unipolar with
Complementary Input
Code, True Zero Output.
Positive Full-Scale
Positive full-Scale –LSB
LSB
Zero-Scale
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0.000
0.001
3.998
3.999
3.999
3.998
0.001
0.000
9.9976
9.9951
0.0024
0.0000
MSB
LSB IO
IO
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 (mA) (mA)
VOUT
Straight Offset Binary;
Positive Full-Scale
Symmetrical about Zero, Positive Full-Scale –LSB
No True Zero Output.
(+) Zero-Scale
(–) Zero-Scale
Negative Full-Scale –LSB
Negative Full-Scale
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999
3.998
2.000
1.999
0.001
0.000
0.00
0.001
1.999
2.000
3.998
3.999
9.9976
9.9927
0.0024
–0.0024
–9.9927
–9.9976
1s Complement;
Symmetrical about Zero,
No True Zero Output.
MSB Complemented
(Need Inverter at B1).
0
0
0
1
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999
3.998
2.000
1.999
0.001
0.000
0.000
0.001
1.999
2.000
3.998
3.999
9.9976
9.9927
0.0024
–0.0024
–9.9927
–9.9976
Symmetrical Offset Operation
Code Format
REV. C
Output Scale
Positive Full-Scale
Positive Full-Scale –LSB
(+) Zero-Scale
(–) Zero-Scale
Negative Full-Scale –LSB
Negative Full-Scale
–9–
DAC312
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SETUP
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
The DAC312 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary
from nearly zero to +1.0 mA. The full range output current is a
linear function of the reference current and is given by:
AC reference applications will require the reference amplifier to
be compensated using a capacitor from pin 16 to V–. The value
of this capacitor depends on the impedance presented to pin 14
for R14 values of 1.0 Ω, 2.5 Ω and 5.0 kΩ, minimum values of
CC are 5 pF, 10 pF, and 25 pF. Larger values of R14 require
proportionately increased values of CC for proper phase margin.
IFR =
4095
× 4 × (IREF) = 3.999 IREF,
4096
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(–) at pin 15. Reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. This negative reference connection has the advantage of a very high impedance presented at pin 15. The voltage at pin 14 is equal to and tracks the voltage at pin 15 due to
the high gain of the internal reference amplifier. R15 (nominally
equal to R14) is used to cancel bias current errors.
Bipolar references may be accommodated by offsetting VREF or
pin 15. The negative common-mode range of the reference amplifier is given by: VCM– = V– plus (IREF × 3 kΩ) plus 1.23 V.
The positive common-mode range is V+ less 1.8 V.
For fastest response to a pulse, low values of R14 enabling small
CC values should be used. If pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated
which will decrease overall bandwidth and slew rate. For R14 =
1 kΩ and CC = 5 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from IREF = 0 to IREF = 1 mA in 250 ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 1 mA)
occurs in 62.5 ns when the equivalent impedance at pin 14 is
800 Ω and CC = 0. This yields a reference slew rate of 8 mA/µs
which is relatively independent of RIN and VIN values.
LOGIC INPUTS
When a dc reference is used, a reference bypass capacitor is recommended. A 5.0 V TTL logic supply is not recommended as a
reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed
to ground with a 0.1 µF capacitor.
For most applications the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full scale
trimming may be accomplished by adjusting the value of R14,
or by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T.C. effects
is shown in the Recommended Full-Scale Adjustment circuit.
The reference amplifier must be compensated by using a capacitor from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see section entitled “Reference Amplifier Compensation for
Multiplying Applications.”
MULTIPLYING OPERATION
The DAC312 provides excellent multiplying performance with
an extremely linear relationship between IFS and IREF over a
range of 1 mA to 1 µA. Monotonic operation is maintained over
a typical range of IREF from 100 µA to 1.0 mA. Although some
degradation of gain accuracy will be realized at reduced values
of IREF. (See Gain Accuracy vs. Reference Current).
The DAC312 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made possible by the large input swing capability, 40 µA logic input current, and completely adjustable logic threshold voltage. For V–
= –15 V, the logic inputs may swing between –5 V and +10 V.
This enables direct interface with +15 V CMOS logic, even
when the DAC312 is powered from a +5 V supply. Minimum
input logic swing and minimum logic threshold voltage are given
by: V– plus (IREF × 3 kΩ) plus 1.8 V. The logic threshold may
be adjusted over a wide range by placing an appropriate voltage
at the logic threshold control pin (pin 13, VLC). The appropriate
graph shows the relationship between VLC and VTH over the
temperature range, with VTH nominally 1.4 above VLC. For
TTL interface, simply ground pin 13. When interfacing ECL,
an IREF ≤ 1 mA is recommended. For interfacing other logic
families, see block titled “Interfacing With Various Logic Families”. For general setup of the logic control circuit, it should be
noted that pin 13 will sink 7 mA typical; external circuitry
should be designed to accommodate this current.
–10–
REV. C
DAC312
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFR. Current appears at the true output when a
“1” is applied to each logic input. As the binary count increases,
the sink current at pin 18 increases proportionally, in the fashion of a “positive logic” D/A converter. When a “0” is applied to
any input bit, that current is turned off at pin 18 and turned on
at pin 19. A decreasing logic count increases IO as in a negative
or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required it must still
be connected to ground or to a point capable of sourcing IFR; do
not leave an unused output pin open.
Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance
is 25 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in
other balanced applications such as driving center-tapped coils
and transformers.
POWER SUPPLIES
The DAC312 operates over a wide range of power supply voltages from a total supply of 20 V to 36 V. When operating with
V– supplies of –10 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with IREF = 1 mA is not recommended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to insure turn-on of the internal bias network.
Symmetrical supplies are not required, as the DAC312 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artificial ground may be used to insure logic swings, etc. remain between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC312 are guaranteed to apply over the entire rated operating
temperature range. Full-scale output current drift is tight, typically ± 10 ppm/°C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB.
full-scale drift. Settling times of the DAC312 decrease approximately 10% at –55°C; at +125°C an increase of about 15% is
typical.
SETTLING TIME
The DAC312 is capable of extremely fast settling times; typically 250 ns at IREF = 1.0 mA. Judicious circuit design and careful board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 25 ns for each of the 12 bits.
Settling time to within 1/2 LSB of the LSB is therefore 25 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 250 ns, thus determining the overall settling time
of 250 ns. Settling to 10-bit accuracy requires about 90 ns to
130 ns. The output capacitance of the DAC312 including the
package is approximately 20 pF; therefore, the output RC time
constant dominates settling time if RL > 500 Ω.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 0.5 mA, with gradual increases
for lower IREF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
Measurement of the settling time requires the ability to accurately resolve ± 1/2 LSB of current, which is ± 500 nA for 4 mA
FSR. In order to assure the measurement is of the actual settling
time and not the RC time of the output network, the resistive
termination on the output of the DAC must be 500 Ω or less.
This does, however, place certain limitations on the testing apparatus. At IREF values of less than 0.5 mA, it is difficult to prevent RC damping of the output and maintain adequate
sensitivity. Because the DAC312 has 8 equal current sources for
the 3 most significant bits, the major carry occurs at the code
change of 000111111111 to 111000000000. The worst case settling time occurs at the zero to full-scale transition and it requires 9.2 time constants for the DAC output to settle to within
± 1/2 LSB (0.0125%) of its final value.
The DAC312 switching transients or “glitches” are on the order
of 500 mV-ns. This is most evident when switching through the
major carry and may be further reduced by adding small capacitive loads at the output with a minor sacrifice in transition speeds.
Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors at the supply pins provide full transient protection.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
REV. C
–11–
DAC312
DIFFERENTIAL VS. INTEGRAL NONLINEARITY
Integral nonlinearity, for the purposes of the discussion, refers
to the “straightness”of the line drawn through the individual response points of a data converter. Differential nonlinearity, on
the other hand, refers to the deviation of the spacing of the adjacent points from a 1 LSB ideal spacing. Both may be expressed
as either a percentage of full-scale output or as fractional LSBs
or both. The following figures define the manner in which these
parameters are specified. The left figure shows a portion of the
transfer curve of a DAC with 1/2 LSB INL and the (implied)
DNL spec of 1 LSB. Below this is a graphic representation of
the way this would appear on a CRT, for example, if the D/A
converter output were to be applied to the Y input of a CRT as
shown in the application schematic titled “CRT Display Drive.”
On the right is a portion of the transfer curve of a DAC specified for 2 LSB INL with 1/2 LSB DNL specified and the
graphic display below it.
One of the characteristics of an R-2R DAC in standard form is
that any transition which causes a zero LSB change (i.e., the
same output for two different codes) will exhibit the same output each time that transition occurs. The same holds true for
transitions causing a 2 LSB change. These two problem transitions are allowable for the standard definition of monotonicity
and also allow the device to be specified very tightly for INL.
The major problem arising from this error type is in A/D converter implementations. Inputs producing the same output are
now represented by ambiguous output codes for an identical input. Also, 2 LSB gaps can cause large errors at those input levels (assuming 1/2 LSB quantizing levels). It can be seen from
the two figures that the DNL specified D/A converter will yield
much finer grained data than the INL specified part, thus improving the ability of the A/D to resolve changes in the analog
input.
DIFFERENTIAL LINEARITY COMPARISON
D/A Converter with ± 1/2 LSB INL, ± 1 LSB DNL
D/A Converter with ± 2 LSB INL, ± 1/2 LSB DNL
Video Deflection by DACs
Video Deflection by DACs
ENLARGED “POSITIONAL” OUTPUTS
ENLARGED “POSITIONAL” OUTPUTS
–12–
REV. C
DAC312
DESCRIPTION OF OPERATION
The DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
The three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is connected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the IO line, while all
higher order resistors (R6 through R8) are summed into the IO
line. The R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the IO or IO lines depending on the bits selected. In the figure, the code selected is: 100 110000000. Therefore, 2 mA (4 ×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into IO giving an IO of 2.375 mA. IO has a current
of 1.625 mA with this code. As the three MSB’s are incremented, each successively higher code adds 0.5 mA to IO and subtracts 0.5 mA from IO, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. This configuration guarantees monotonicity.
Expanded Transfer Characteristic Segment (001 010 011)
Simplified Schematic
REV. C
–13–
000000000
12-Bit Fast A/D Converter
Outline Dimensions
Dimension shown in inches and (mm).
20-Lead Plastic DIP (N-20)
20-Lead Cerdip (Q-20)
PRINTED IN U.S.A.
20-Lead Wide Body SOL (R-20)
–14–