Intersil ISL78215AUZ Improved industry standard single-ended current mode pwm controller Datasheet

ISL78215
Features
The ISL78215 family of adjustable frequency, low power,
pulse width modulating (PWM) current mode controllers
is designed for a wide range of power conversion
applications including boost, flyback, and isolated output
configurations. Peak current mode control effectively
handles power transients and provides inherent
overcurrent protection.
• 1A MOSFET Gate Driver
This advanced BiCMOS design is pin compatible with the
industry standard 384x family of controllers and offers
significantly improved performance. Features include low
operating current, 60µA start-up current, adjustable
operating frequency to 2MHz, and high peak current
drive capability with 20ns rise and fall times.
• 20ns Rise and Fall Times with 1nF Output Load
The ISL78215 is fully TS16949 compliant and tested to
AEC-Q100 specifications.
• Tight Tolerance Current Limit Threshold
• 60µA Start-up Current, 100µA Maximum
• 25ns Propagation Delay Current Sense to Output
• Fast Transient Response with Peak Current Mode
Control
• Adjustable Switching Frequency to 2MHz
• Trimmed Timing Capacitor Discharge Current for
Accurate Deadtime/Maximum Duty Cycle Control
• High Bandwidth Error Amplifier
• Tight Tolerance Voltage Reference Over Line, Load,
and Temperature
• Pb-Free (RoHS Compliant)
• TS16949 Compliant
• AEC-Q100 Tested
Applications*(see page 10)
• Automotive Power
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
• PC Power Supplies
• Isolated Buck and Flyback Regulators
• Boost Regulators
Pin Configuration
ISL78215
(8 LD MSOP)
TOP VIEW
COMP 1
August 16, 2010
FN7673.0
1
8 VREF
FB 2
7 VDD
CS 3
6 OUT
RTCT 4
5 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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ISL78215
Improved Industry Standard Single-Ended Current
Mode PWM Controller
ISL78215
Pin Description
PIN
SYMBOL
1
COMP
COMP is the output of the error amplifier and the input of the PWM comparator. The
control loop frequency compensation network is connected between the COMP and FB
pins.
DESCRIPTION
2
FB
The output voltage feedback is connected to the inverting input of the error amplifier
through this pin. The non-inverting input of the error amplifier is internally tied to a
reference voltage.
3
CS
This is the current sense input to the PWM comparator. The range of the input signal is
nominally 0V to 1.0V and has an internal offset of 100mV.
4
RTCT
This is the oscillator timing control pin. The operational frequency and maximum duty
cycle are set by connecting a resistor, RT, between VREF and this pin and a timing
capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a
programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time,
tD, the switching frequency, f, and the maximum duty cycle, Dmax, can be calculated
from Equations 1, 2, 3 and 4:
t
C
t
≈ 0.583 • RT • CT
(EQ. 1)
0.0083 • RT – 4.3
≈ – RT • CT • ln ⎛ ----------------------------------------------⎞
⎝ 0.0083 • RT – 2.4⎠
(EQ. 2)
D
f = 1 ⁄ (tC + tD)
D = t
C
(EQ. 3)
•f
(EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required
for a given frequency.
5
GND
GND is the power and small signal reference ground for all functions.
6
OUT
This is the drive output to the power switching device. It is a high current output capable
of driving the gate of a power MOSFET with peak currents of 1.0A.
7
VDD
VDD is the power connection for the device. The total supply current will depend on the
load applied to OUT. Total IDD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f, and the MOSFET gate
charge, Qg, the average output current can be calculated in Equation 5:
I OUT = Qg × f
(EQ. 5)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the
VDD and GND pins as possible.
8
VREF
The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating
temperature. Bypass to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL78215AUZ
78215
-40 to +105
8 Ld MSOP
M8.118
ISL78215AUZ-T (Note 1)
78215
-40 to +105
8 Ld MSOP
M8.118
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78215. For more information on MSL please
see techbrief TB363.
2
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August 16, 2010
Functional Block Diagram
VREF
5.00V
VDD
UVLO
COMPARATOR
ENABLE
VDD OK
+
-
VREF
VREF FAULT
-
3
VREF
UV COMPARATOR
4.65V 4.80V
GND
A
2.5V
+
-
+
BG +
-
BG
A = 0.5
PWM
COMPARATOR
+
-
CS
ERROR
AMPLIFIER
2R
+
-
FB
+
-
1.1V
CLAMP
ISL78215
100mV
ISL78215
Q
R
T
Q
COMP
OUT
VREF
S Q
R Q
2.6V
0.7V
ON
OSCILLATOR
COMPARATOR
+
RTCT
FN7673.0
August 16, 2010
8.4mA
ON
CLOCK
RESET
DOMINANT
Typical Application - 48V Input Dual
Output Flyback
CR5
+3.3V
T1
R21
VIN+
R3
C21
+C15
+ C16
+1.8V
C4
CR4
4
C2
C17
CR2
C5
C22
+
+
C20
C19
RETURN
CR6
R1
36V TO 75V
C1
R16
C6
C3
R17
R18
R19
U2
Q1
C14
R22
VIN-
U3
R27
C13
R15
R20
U4
R26
COMP
CS
FB
VREF
VDD
OUT
RTCT
GND
ISL78215
R6
R10
CR1
Q3
C12
VR1
C8
R13
C11
ISL78215
R4
FN7673.0
August 16, 2010
Typical Application - Boost Converter
R8
C10
CR1
L1
VIN+
+VOUT
+
C2
C3
5
R4
Q1
RETURN
R5
ISL78215
C9
C1
R1
R2
U1
COMP
CS
C4
RTCT
ISL78215
FB
R7
VREF
VIN+
VDD
OUT
GND
R3
C7
VIN-
C5
C6
C8
R6
FN7673.0
August 16, 2010
ISL78215
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUT . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
ESD Rating
Human Body Model (Tested per JESD22-A11) . . . . . 2500V
Machine Model (Tested per JESD22-C101) . . . . . . . . . 75V
Charged Device Model (Tested per JESD22-A115) . . 1500V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
MSOP Package (Notes 4, 5) . . . . . .
170
60
Maximum Junction Temperature . . . . . . . . -55°C to +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . -40°C to +105°C
Supply Voltage Range (Typical, Note 6). . . . . . . .7.5V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block
Diagram” on page 3 and “Typical Application” schematics on page 4 and 5. VDD = 15V
(Note 10), Rt = 10kΩ, Ct = 3.3nF, TA = -40 to +105°C, Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to
+105°C.
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
START Threshold
6.5
7.0
7.5
V
STOP Threshold
6.1
6.6
6.9
V
-
0.4
-
V
-
60
100
µA
PARAMETER
TEST CONDITIONS
UNDERVOLTAGE LOCKOUT
Hysteresis
Start-up Current, IDD
VDD < START Threshold
Operating Current, IDD
(Note 8)
-
3.3
4.0
mA
Operating Supply Current, ID
Includes 1nF GATE loading
-
4.1
5.5
mA
4.925
5.000
5.050
V
-
5
-
mV
Fault Voltage
4.40
4.65
4.85
V
VREF Good Voltage
REFERENCE VOLTAGE
Overall Accuracy
Over line (VDD = 12V to 18V),
load, temperature
Long Term Stability
TA = +125°C, 1000 hours
(Note 9)
4.60
4.80
VREF - 0.05
V
Hysteresis
50
165
250
mV
Current Limit, Sourcing
-20
-
-
mA
5
-
-
mA
-1.0
-
1.0
µA
Current Limit, Sinking
CURRENT SENSE
VCS = 1V
Input Bias Current
CS Offset Voltage
VCS = 0V (Note 9)
95
100
105
mV
COMP to PWM Comparator Offset
Voltage
VCS = 0V (Note 9)
0.80
1.15
1.30
V
0.91
0.97
1.03
V
2.5
3.0
3.5
V/V
Input Signal, Maximum
Gain, ACS = ΔVCOMP/ΔVCS
0 < VCS < 910mV, VFB = 0V
(Note 9)
6
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ISL78215
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. Refer to “Functional Block
Diagram” on page 3 and “Typical Application” schematics on page 4 and 5. VDD = 15V
(Note 10), Rt = 10kΩ, Ct = 3.3nF, TA = -40 to +105°C, Typical values are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to
+105°C. (Continued)
TEST CONDITIONS
CS to OUT Delay
(Note 9)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
-
25
40
ns
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 9)
60
90
-
dB
Unity Gain Bandwidth
(Note 9)
3.5
5
-
MHz
2.475
2.514
2.55
V
-1.0
-0.2
1.0
µA
Reference Voltage
VFB = VCOMP
FB Input Bias Current
VFB = 0V
COMP Sink Current
VCOMP = 1.5V, VFB = 2.7V
1.0
-
-
mA
COMP Source Current
VCOMP = 1.5V, VFB = 2.3V
-0.4
-
-
mA
COMP VOH
VFB = 2.3V
4.80
-
VREF
V
COMP VOL
VFB = 2.7V
0.4
-
1.0
V
PSRR
Frequency = 120Hz, VDD = 12V
to 18V (Note 9)
60
80
-
dB
Initial, TJ = +25°C
49
52
55
kHz
OSCILLATOR
Frequency Accuracy
Frequency Variation with VDD
T = +25°C (f18V - f12V)/f12V
-
0.2
1.0
%
Temperature Stability
(Note 9)
-
-
5
%
Amplitude, Peak-to-Peak
-
1.9
-
V
RTCT Discharge Voltage
-
0.7
-
V
7.2
8.4
9.5
mA
Discharge Current
RTCT = 2.0V
OUTPUT
Gate VOH
VDD to OUT, IOUT = -200mA
-
1.0
2.0
V
Gate VOL
OUT to GND, IOUT = 200mA
-
1.0
2.0
V
Peak Output Current
COUT = 1nF (Note 9)
-
1.0
-
A
Rise Time
COUT = 1nF (Note 9)
-
20
40
ns
Fall Time
COUT = 1nF (Note 9)
-
20
40
ns
Maximum Duty Cycle
47
48
Minimum Duty Cycle
-
-
PWM
%
0
%
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
9. Limits established by characterization and are not production tested.
10. Adjust VDD above the start threshold and then lower to 15V.
7
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August 16, 2010
ISL78215
Typical Performance Curves
1.001
1.01
NORMALIZED VREF
NORMALIZED FREQUENCY
1.02
1.00
0.99
0.98
0.97
-40
-10
20
50
80
1.000
0.999
0.998
0.997
0.996
0.995
-40 -25 -10 5
110
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
103
1.002
FREQUENCY (kHz)
NORMALIZED EA REFERENCE
FIGURE 1. FREQUENCY vs TEMPERATURE
20 35 50 65 80 95 110
TEMPERATURE (°C)
TEMPERATURE (°C)
1.000
0.998
0.996
0.994
-40 -25 -10 5 20 35 50 65 80 95 110
TEMPERATURE (°C)
FIGURE 3. EA REFERENCE vs TEMPERATURE
Functional Description
Features
220pF
330pF
470pF
1.0nF
10
1
10
2.2nF
3.3nF
4.7nF
20
30
40
50
60
70
The ISL78215 controllers have a sawtooth oscillator with
a programmable frequency range to 2MHz, which can be
programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the
resistor and capacitance required for a given frequency.)
90 100
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES
GIVEN
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated in Figure 5, clamps the voltage on COMP.
VREF
COMP
Oscillator
80
RT (kΩ)
ISL78215
The ISL78215 current mode PWMs make an ideal choice
for low-cost flyback and forward topology applications.
With its greatly improved performance over industry
standard parts, it is the obvious choice for new designs
or existing designs which require updating.
100pF
100
GND
FIGURE 5. SOFT-START
8
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August 16, 2010
ISL78215
Gate Drive
RTCT
VREF
CS
Slope Compensation
For applications where the maximum duty cycle is less
than 50%, slope compensation may be used to improve
noise immunity, particularly at lighter loads. The amount
of slope compensation required for noise immunity is
determined empirically, but is generally about 10% of the
full scale current feedback signal. For applications where
the duty cycle is greater than 50%, slope compensation
is required to prevent instability. The minimum amount
of slope compensation required corresponds to 1/2 the
inductor downslope. Adding excessive slope
compensation, however, results in a control loop that
behaves more as a voltage mode controller than as a
current mode controller.
CS SIGNAL (V)
ISL78215
The ISL78215 is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of
the MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Slope compensation may be added to the CS signal
shown in Figure 7.
DOWNSLOPE
CURRENT SENSE SIGNAL
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When
a Fault is detected, OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of
the device. A good ground plane must be employed. A
unique section of the ground plane must be designated
for high di/dt currents associated with the output stage.
VDD should be bypassed directly to GND with good high
frequency capacitors.
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
9
FN7673.0
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ISL78215
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
8/16/10
FN7673.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL78215
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
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patent or patent rights of Intersil or its subsidiaries.
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10
FN7673.0
August 16, 2010
ISL78215
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
11
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN7673.0
August 16, 2010
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