IDT IDT74SSTV16857PAG 14-bit registered buffer with sstl i/o Datasheet

IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
IDT74SSTV16857
14-BIT REGISTERED
BUFFER WITH SSTL I/O
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
2.3V to 2.7V Operation
SSTL_2 Class II style data inputs/outputs
Differential CLK input
RESET control compatible with LVCMOS levels
Flow-through architecture for optimum PCB design
Drive up to equivalent of 14 SDRAM loads
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V
VDD and supports low standby operation. All data inputs and outputs are
SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
APPLICATIONS:
• Ideally suited for DIMM DDR registered applications
FUNCTIONAL BLOCK DIAGRAM
RESET
CK
34
38
39
CK
V REF
D1
35
48
1D
1
C1
Q1
R
TO 13 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2003
1
c
2003 Integrated Device Technology, Inc.
DSC-5737/5
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
VDD or VDDQ Supply Voltage Range
Q1
1
48
(2)
Max.
Unit
–0.5 to 3.6
V
D1
VI
Input Voltage Range
–0.5 to VDD +0.5
V
VO(3)
Output Voltage Range
–0.5 to VDDQ +0.5
V
Q2
2
47
D2
GND
3
46
GND
VDDQ
4
45
VDD
Q3
5
44
D3
Q4
6
43
D4
Q5
7
42
D5
GND
8
41
D6
VDDQ
9
40
D7
Q6
10
39
CLK
Q7
11
38
CLK
VDDQ
12
37
VDD
GND
13
36
GND
Q8
14
35
VREF
Q9
15
34
RESET
VDDQ
16
33
D8
GND
17
32
D9
Q10
18
31
D10
Q11
19
30
D11
Q12
20
29
D12
VDDQ
21
28
VDD
GND
22
27
GND
Q13
23
26
D13
Q14
24
25
D14
IIK
Input Clamp Current, VI < 0
–50
mA
IOK
Output Clamp Current,
±50
mA
±50
mA
±100
mA
–65 to +150
°C
VO < 0 or VO > VDDQ
IO
Continuous Output Current,
VO = 0 to VDDQ
VDD
Continuous Current through each
VDD, VDDQ or GND
TSTG
Storage Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) VO = VDDQ
FUNCTION TABLE(1)
Input
TSSOP
TOP VIEW
RESET
CLK
CLK
D
Q Outputs
H
↑
↓
L
L
H
↑
↓
H
H
H
L or H
L or H
X
Q(2)
L
X
X
X
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Q = Output level before the indicated steady-state conditions were established.
2
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V
Symbol
VIK
Parameter
Test Conditions
Control Inputs
VDD = 2.3V, II = −18mA
Min.
VDD = 2.3V to 2.7V, IOH = -100µA
VOH
VDD = 2.3V, IOH = -16mA
VOL
II
IDD
IDDD
Typ.
Max.
Unit
—
—
–1.2
V
VDD – 0.2
—
—
V
1.95
—
—
VDD = 2.3V to 2.7V, IOL = 100µA
—
—
0.2
VDD = 2.3V, IOL = 16mA
—
—
0.35
All Inputs
VDD = 2.7V, VI = VDD or GND
—
—
±5
µA
Static Standby
IO = 0, VDD = 2.7V, RESET = GND
—
—
0.01
mA
Static Operating
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC)
—
—
—
Dynamic Operating (Clock Only)
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
—
—
—
CLK and CLK Switching 50% Duty Cycle.
µA/Clock
MHz
Dynamic Operating
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
(Per Each Data Input)
CLK and CLK Switching 50% Duty Cycle. One Data Input
rOH
Output HIGH
VDD = 2.3V to 2.7V, IOH = -20mA
rOL
Output LOW
rO(∆)
| rOH- rOL| each separate bit
Data Inputs
CLK and CLK
RESET
—
—
—
µA/Clock
MHz/Data
Switching at Half Clock Frequency, 50% Duty Cycle.
CI
V
Input
Ω
7
—
20
VDD = 2.3V to 2.7V, IOH = 20mA
7
—
20
Ω
VDD = 2.5V, TA = 25°C, IOH = -20mA
—
—
4
Ω
VDD = 2.5V, VI = VREF ± 310mV
2.5
—
3.5
VICR = 1.25V, VI (PP) = 360mV
2.5
—
3.5
VI = VDD or GND
—
—
—
pF
OPERATING CHARACTERISTICS, TA = 25ºC(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
VDDQ
—
2.7
V
VDDQ
Output Supply Voltage
2.3
2.5
2.7
V
VREF
Reference Voltage (VREF= VDDQ/2)
1.15
1.25
1.35
V
V TT
Termination Voltage
VREF– 40mV
VREF
VREF+ 40mV
V
0
—
VDD
V
VI
Input Voltage
VIH
AC High-Level Input Voltage
Data Inputs
VREF+ 310mV
—
—
V
VIL
AC Low-Level Input Voltage
Data Inputs
—
—
VREF– 310mV
V
VIH
DC High-Level Input Voltage
Data Inputs
VREF+ 150mV
—
—
V
VIL
DC Low-Level Input Voltage
Data Inputs
—
—
VREF– 150mV
V
VIH
High-Level Input Voltage
RESET
1.7
—
—
V
VIL
Low-Level Input Voltage
RESET
—
—
0.7
V
VICR
Common-Mode Input Range
CLK, CLK
0.97
—
1.53
V
VI (PP)
Peak-to-Peak Input Voltage
CLK, CLK
360
—
—
mV
IOH
High-Level Output Current
—
—
– 20
mA
IOL
Low-Level Output Current
—
—
20
TA
Operating Free-Air Temperature
– 40
—
+85
NOTE:
1.
The RESET input of the device must be held at VDD or GND to ensure proper device operation.
3
°C
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
VDD = 2.5V ± 0.2V
Symbol
Parameter
Min.
Max.
Unit
Clock Frequency
—
200
MHz
tw
Pulse Duration, CLK, CLK HIGH or LOW
2.5
—
ns
tACT
Differential Inputs Active Time
—
22
ns
tINACT
Differential Inputs Inactive Time(2)
—
22
ns
0.75
—
ns
0.9
—
ns
CLOCK
tSU
Setup Time, Fast Slew Rate
(1)
(3, 5)
Data Before CLK↑, CLK↓
Setup Time, Slow Slew Rate(4, 5)
tN
Hold Time, Fast Slew Rate
(3,5)
Data Before CLK↑, CLK ↓
Hold Time, Slow Slew Rate(2,5)
0.75
—
ns
0.9
—
ns
NOTES:
1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.
3. For data signal input slew rate is ≥1V/ns.
4. For data signal input slew rate is ≥0.5V/ns and <1V/ns.
5. CLK, CLK signal input slew rates are ≥1V/ns.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
VDD = 2.5V ± 0.2V
Symbol
fMAX
tPD
tPHL
Parameter
Min
200
1.1
—
CLK and CLK to Q
RESET to Q
4
Max.
—
2.8
5
Unit
MHz
ns
ns
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V ± 0.2V)
V TT
R L = 50 Ω
From Output
Under Test
Test Point
C L = 30 pF
(see note 1)
Load Circuit
LVCMOS
RESE T
Input
V DD
V D D /2
V D D /2
t IN AC T
Timing
Input
0V
t AC T
V IC R
V IC R
t PLH
V I(P P)
t PH L
V OH
ID D
90%
10%
Output
V TT
V TT
V OL
(see note 2)
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESE T
Input
V IH
V D D /2
V IL
t PH L
tW
V OH
V IH
Input
Output
V R EF
VREF
V OL
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Pulse Duration
Timing
Input
V IC R
t SU
V TT
V IL
V I(PP )
tN
V IH
Input
V RE F
V RE F
V IL
Voltage Waveforms - Setup and Hold Times
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tPD.
5
IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
XX
SSTV
Family
Temp. Range
XXXX
XX
Device Type Package
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
PA
PAG
Thin Shrink Small Outline Package
TSSOP - Green
857
14-Bit Registered Buffer with SSTL I/O
16
Double-Density
74
–40°C to +85°C
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
6
for Tech Support:
[email protected]
(408) 654-6459
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