AKM AK4675EG Stereo codec with mic/rcv/hp/spk-amp Datasheet

[AK4675]
AK4675
Stereo CODEC with MIC/RCV/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4675 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier, cap-less
Headphone-Amplifier and stereo audio class-D Speaker-Amplifier. The AK4675 features dual PCM I/F in
addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth I/F. The
Speaker-Amplifier includes ALC (Automatic Level Control) circuit what is able to stabilize each output
sound levels. The AK4675 is available in an 83pin BGA, utilizing less board space than competitive
offerings.
FEATURES
1. Recording Function (Stereo CODEC)
• 4 Stereo Input Selector x 2ch
• 4 Stereo Inputs (Single-ended) or 2 Stereo Input (Full-differential)
• MIC Amplifier: +30dB ∼ −12dB, 3dB step
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 5-band Programmable Notch Filter
• Audio Interface Format: 16bit MSB justified, I2S, DSP Mode
2. Playback Function (Stereo CODEC)
• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• 5-band EQ
• Stereo Line Output
• Mono Receiver-Amp
- BTL Output
- Output Power: 30mW@32Ω (AVDD=3.3V)
• Stereo Cap-less Headphone Amplifier
- Mono / Stereo Mode
- Output Power: 64mW x 2ch @ 16Ω, SVDDA=3.3V, THD+N = –40dB
- THD+N: -58dB @ 16Ω, Po=30mW, SVDDA=3.3V
- Output Noise Level: 24μVrms
- Outputs Volume: +12dB to –50dB, 2dB Step
- Pop Noise Free at Power-ON/OFF and Mute
• Class-D Speaker Amplifier
- BTL output
- Output Power: 1.6W @ 8Ω, SVDDA=5.0V
0.8W @ 8Ω, SVDDA=3.6V
- THD+N: –65dB @8Ω, Po=0.25W, SVDDA=3.6V
- Output Noise Level: 71μVrms
- ALC (Automatic Level Control) Circuit
- Pop Noise Free at Power-ON/OFF and Mute
- External filter-less
- Short Protection circuit
• Thermal Shutdown / Short protection circuit
• Analog Mixing: 4 Stereo Input
• Audio Interface Format: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP
Mode
3. Dual PCM I/F for Baseband & Bluetooth Interface
MS0963-E-00
2008/05
-1-
[AK4675]
• Sample Rate Converter (Up sample: up to x6: Down sample: down to x1/6)
• Sample Rate: 8kHz
• Digital Volume
• Audio Interface Format:
- 16bit Linear, 8bit A-law, 8bit μ-law
- Short/Long Frame, I2S, MSB justified
4. 10bit SAR ADC
• 3 Input Selectors
5. Power Management
6. Master Clock:
(1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz,
24MHz, 26MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Sampling Rate: 256fs, 384fs, 512fs, 768fs or 1024fs (MCKI pin)
7. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
8. Sampling Rate (Stereo CODEC):
• PLL Slave Mode (LRCK pin): 8kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 8kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
8kHz ∼ 48kHz (256fs, 384fs), 8kHz ∼ 26kHz (512fs, 768fs),
8kHz ∼ 13kHz (1024fs)
9. μP I/F: I2C Bus (Ver 1.0, 400kHz High Speed Mode)
10. Master/Slave mode
11. Ta = –30 ∼ 85°C
12. Power Supply:
• Analog1: 2.2 ∼ 3.6V
• Analog2: 2.6 ∼ 3.6V
• Digital I/F: 1.6 ∼ 3.6V
• Speaker Amp: 3.0 ∼ 5.5V
13. Package: 83pin BGA (5.5mm x 5.5mm, 0.5mm pitch)
MS0963-E-00
2008/05
-2-
[AK4675]
■ Block Diagram (CODEC Block)
AVDD
VSS1
SAIN1 SAIN2 SAIN3
VCOM
SAVDD
VSS3
DVDD
VSS4
TEST
GPO1
GPO2
PMSAD
MDT
MPWR
PMMP
MPWR
TEST5
A/D
MIC Power
Supply
Control
Register
MIC-Amp
PMADL or PMADR
RIN1/IN1−
A/D
LIN2/IN2
External
MIC
TEST4
PMMICL
LIN1/IN1+
Internal
MIC
TEST6
PDN
HPF
PMMICR
PFSEL=0
PMADL
or
PMADR
RIN2/IN2
LIN3/IN3
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
RIN3/IN3
LIN4/IN4
PMLO1
LOUT1/RCP
PMLOOPR
PMLOOPL
PMAINR4
PMAINL4
PMAINR2
PMAINR3
PMAINL3
PMAINL2
PMAINL1
PMAINR1
RIN4/IN4
HPF
LPF
BICK
Stereo
Separation
5-band
Notch
ALC
LRCK
Audio
I/F
PMDAL
or
PMDAR
PMDAL or PMDAR or
SVOLA
M DATT 5-band
I SMUTE EQ
X
S
E
L
MCKI
MCKO
PMRO1
ROUT1/RC
N
PMPLL
PLL
PMLO2S
PMPCM
LOUT2S
Stereo Line Out
SDTO
SDTI
MIX
D/A
Stereo Line Out
or
Mono Receiver
SCL
SDA
VCOCBT
PLLBT
PMSRA
PMRO2S
ROUT2S
VCOC
SRC-A
BICKA
SVOLB
PMSRB
PCM
I/F A
PMLO3
SRC-B
LOUT3/LOP
Stereo Line Out
DATT-C
ROUT3/LON
BVOL
PVDD
VSS2
TVDD2
SDTOA
SDTIA
DATT-B
PMRO3
SYNCA
PCM
I/F B
BICKB
SYNCB
SDTOB
SDTIB
TVDD3
Figure 1. Block Diagram (CODEC Block)
MS0963-E-00
2008/05
-3-
[AK4675]
■ Block Diagram (HP/SPK-Amp Block)
AVDDA
VSS1A
TEST3
TEST2
SVDDA
PMSP
SPIN
ALCA
SPP
SPN
VSS2A
PMMHL
PMHPL
PMV1
Mixing
LIN1A
Vol
RIN1A
Vol
Selector
VOL
HPL
VOL
HPR
Mixing
Selector
PMHPR
PMMHR
VCOMA
MCKIA
VCOMA
PMVCMA
Int Osc or Ext Clock
PMOSC
TVDDA
PMCP
R1
SDA
SCL
Serial I/F
PDNA
R2
VBATIN
VBATO
Charge
Pump
CP
CN
PVDDA VSS3A PVEE
Figure 2. Block Diagram (HP/SPK-Amp Block)
MS0963-E-00
2008/05
-4-
[AK4675]
■ Ordering Guide
−30 ∼ +85°C
83pin BGA (0.5mm pitch)
Evaluation board for AK4675
AK4675EG
AKD4675
■ Pin Layout
10
9
8
7
AK4675
6
Top View
5
4
3
2
1
A
10
TEST
9
AVDD
8
VSS1
7
VBATIN
6
5
4
3
LOUT1
/RCP
RIN3
/IN3−
LIN2
/IN2+
LIN1
/IN1+
HPR
ROUT1
/RCN
ROUT3
/LON
LOUT3
/LOP
LIN4
/IN4+
RIN2
/IN2−
SAIN3
B
C
D
E
F
G
H
J
K
VCOM
VCOC
HPL
PVDDA
VSS3A
CP
SDTIA
GPO2
VBATO
VCOCBT
PVEE
SDTOA
SYNCA
CN
PDNA
BICKA
VCOMA
RIN4
/IN4−
PVDD
VSS2
TVDD2
TVDDA
VSS4
MCKIA
TEST6
DVDD
SDA
MCKO
NC
SCL
SAIN2
MCKI
TEST5
BICK
SAIN1
LRCK
PDN
VSS1A
LIN3
/IN3+
RIN1A
Top View
RIN1
/IN1−
SAVDD
SDTOB
SDTO
BICKB
NC
TEST3
AVDDA
2
LIN1A
MPWR
ROUT2S
NC
VSS3
SPN
SYNCB
SDTIB
TEST4
SPIN
1
MDT
LOUT2S
NC
SVDDA
VSS2A
TVDD3
SPP
TEST2
SDTI
GPO1
A
B
C
D
E
F
G
H
J
K
MS0963-E-00
2008/05
-5-
[AK4675]
PIN/FUNCTION
No.
A1
B2
B4
C5
C4
D3
E2
F1
E3
G2
G3
H2
J1
K1
Pin Name
MDT
MPWR
SAIN3
SAIN2
SAIN1
SAVDD
VSS3
TVDD3
SDTOB
SYNCB
BICKB
SDTIB
SDTI
GPO1
I/O
I
O
I
I
I
O
I/O
I/O
I
I
O
J2
TEST4
O
F3
SDTO
O
J4
PDN
I
H4
H5
H6
LRCK
MCKI
MCKO
I/O
I
O
H7
TEST6
I
K5
BICK
I/O
J5
TEST5
I
K6
J8
J7
K7
K10
SCL
VSS4
DVDD
SDA
GPO2
I
I/O
O
Function
MIC Detection Pin (Internal pull down by typ. 500kΩ)
MIC Power Supply Pin
10bit SAR ADC Analog Input 3 Pin
10bit SAR ADC Analog Input 2 Pin
10bit SAR ADC Analog Input 1 Pin
10bit SAR ADC Power Supply Pin
2.2V ~ 3.6V
Ground 3 Pin for CODEC
Digital I/O Power Supply 3 Pin for CODEC
1.6V ~ 3.6V
Serial Data Output B Pin
Sync Signal B Pin
Serial Data Clock B Pin
Serial Data Input B Pin
Audio Serial Data Input Pin
General Purpose Output 1 Pin
TEST Pin
This pin must be open.
Audio Serial Data Output Pin
CODEC Power-Down Mode Pin
“H”: Power-up
“L”: Power-down, reset and initializes the control registers for CODEC. “L” time
of 150ns or more after power-up is needed to reset the AK4675.
Input / Output Channel Clock Pin
External Master Clock Input Pin
Master Clock Output Pin
Test Pin
Connect to DVDD.
Audio Serial Data Clock Pin
TEST Pin
This pin must be connected to VSS4.
Control Data Clock Input Pin
Ground 4 Pin for CODEC
Digital Power Supply Pin for CODEC
1.6V ~ 3.6V
Control Data Input/Output Pin
General Purpose Output 2 Pin
MS0963-E-00
2008/05
-6-
[AK4675]
No.
J10
K9
G9
F9
G8
F8
E8
Pin Name
SDTIA
BICKA
SYNCA
SDTOA
TVDD2
VSS2
PVDD
I/O
I
I/O
I/O
O
-
D9
VCOCBT
O
D10
VCOC
O
C10
VCOM
O
A10
TEST
-
A9
A8
AVDD
VSS1
ROUT1
RCN
LOUT1
RCP
ROUT3
LON
LOUT3
LOP
RIN4
IN4−
LIN4
IN4+
RIN3
IN3−
LIN3
IN3+
RIN2
IN2−
LIN2
IN2+
RIN1
IN1−
LIN1
IN1+
ROUT2S
LOUT2S
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
B9
A6
B8
B7
D8
B6
A5
C7
B5
A4
B3
A3
C2
B1
Function
Serial Data Input A Pin
Serial Data Clock A Pin
Sync Signal A Pin
Serial Data Output A Pin
Digital I/O Power Supply 2 Pin for CODEC
1.6V ~ 3.6V
Ground 2 Pin for CODEC
PLLBT Power Supply Pin
2.2V ~ 3.6V
Output Pin for Loop Filter of PLLBT Circuit
This pin must be connected to VSS2 pin with one resistor and capacitor in series.
Output Pin for Loop Filter of PLL Circuit
This pin must be connected to VSS1 pin with one resistor and capacitor in series.
Common Voltage Output Pin, 0.5 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Test Pin
This pin must be open.
Analog Power Supply Pin for CODEC
2.2V ~ 3.6V
Ground 1 Pin for CODEC
Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output)
Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output)
Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Rch Stereo Line Output 2 Pin
Lch Stereo Line Output 2 Pin
MS0963-E-00
2008/05
-7-
[AK4675]
No.
Pin Name
I/O
Function
Test 2 Pin
This pin must be open.
No Connect Pin
H3 NC
No internal bonding. This pin must be opened or connected to the ground.
HP/SPK-Amp Analog Power Supply Pin
2.6V ~ 3.6V
K3 AVDDA
HP/SPK-Amp Ground 1 Pin
K4 VSS1A
HP/SPK-Amp Digital Interface Power Supply Pin
1.6V ~ 3.6V
H8 TVDDA
This pin must be connected to DVDD.
No Connect Pin
J6 NC
No internal bonding. This pin must be opened or connected to the ground.
HP/SPK-Amp External Clock Input Pin (Internal Pull-down pin to VSS1A: typ.
I
K8 MCKIA
100kΩ)
HP/SPK-Amp Power-Down Mode Pin
“H”: Power-up
I
J9 PDNA
“L”: Power-down, reset and initializes the control registers for HP/SPK-Amp. “L”
time of 150ns or more after power-up is needed to reset the AK4675.
O
H10 CP
Positive Charge Pump Capacitor Terminal Pin
I
H9 CN
Negative Charge Pump Capacitor Terminal Pin
F10 PVDDA
Charge Pump Circuit Positive Power Supply Pin
2.6V ~ 3.6V
G10 VSS3A
HP/SPK-Amp Ground 3 Pin
O
E9 PVEE
Charge Pump Circuit Negative Voltage Output Pin
O
E10 HPL
Lch Headphone-Amp Output Pin
O
B10 HPR
Rch Headphone-Amp Output Pin
I
Battery Monitor Input Pin
A7 VBATIN
O
Battery Monitor Output Pin
C9 VBATO
O
HP/SPK-Amp Analog Common Voltage Output Pin
C8 VCOMA
RIN1A
I
Rch
HP-Amp Input Pin
C6
I
Lch HP-Amp Input Pin
A2 LIN1A
No Connect Pin
D2 NC
No internal bonding. This pin must be opened or connected to the ground.
No Connect Pin
C1 NC
No internal bonding. This pin must be opened or connected to the ground.
Speaker-Amp Power Supply Pin
3.0V ~ 5.5V
D1 SVDDA
HP/SPK-Amp Ground 2 Pin
E1 VSS2A
O
Positive Speaker-Amp Output Pin
G1 SPP
O
Negative Speaker-Amp Output Pin
F2 SPN
TEST Pin
J3 TEST3
This pin must be open.
I
K2 SPIN
Speaker-Amp Input Pin
Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+,
RIN3/IN3−, LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3, LIN1A, RIN1A, SPIN, VBATIN) must not be left
floating. I/O pins except the SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICK) must be processed
appropriately as shown in “Master Mode/Slave Mode” and “PCM I/F Master Mode/Slave Mode”. The PDA pin
should be pulled-up externally and connected to (DVDD+0.3)V or less.
H1
TEST2
-
MS0963-E-00
2008/05
-8-
[AK4675]
■ Handling of Unused Pins
The unused I/O pins must be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR, MDT, VCOC, ROUT3/LON, LOUT3/LOP,
ROUT2S, LOUT2S, ROUT1/RCN, LOUT1/RCP,
RIN4/IN4−, LIN4/IN4+, RIN3/IN3−, LIN3/IN3+,
RIN2/IN2−, LIN2/IN2+, RIN1/IN1−, LIN1/IN1+,
VCOCBT, SAIN1, SAIN2, SAIN3, HPL, HPR, SPIN,
SPP, SPN, LIN1A, RIN1A, VBATIN, VBATO, TEST2
MCKO, SDTOA, SDTOB, GPO1, GPO2, BICKA,
SYNCA, BICKB, SYNCB
Setting
These pins msut be open.
These pins must be open.
These pins must be connected to
VSS4.
These pins must be connected to
VSS1A.
MCKI, , SDTIA, SDTIB
MCKIA
MS0963-E-00
2008/05
-9-
[AK4675]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Note 2, Note 3)
Parameter
Symbol
Min
Power Supplies:
CODEC Analog
AVDD
−0.3
(Note 4)
PLLBT
PVDD
−0.3
10bit SAR ADC
SAVDD
−0.3
CODEC Digital
DVDD
−0.3
CODEC Digital I/O 2
TVDD2
−0.3
CODEC Digital I/O 3
TVDD3
−0.3
HP/SPK-Amp Analog
AVDDA
−0.3
HP/SPK-Amp Digital I/F
TVDDA
−0.3
Speaker-Amp & Headphone-Amp SVDDA
−0.3
Charge Pump
PVDDA
−0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage 1 (Note 5)
VINA1
−0.3
Analog Input Voltage 2 (Note 6)
VINA2
−0.3
Analog Input Voltage 3 (Note 7)
VINA3
−0.3
Analog Input Voltage 4 (Note 8)
VINA4
−0.3
Digital Input Voltage 1 (Note 9)
VIND1
−0.3
Digital Input Voltage 2 (Note 10)
VIND2
−0.3
Digital Input Voltage 3 (Note 11)
VIND3
−0.3
Digital Input Voltage 4 (Note 12)
VIND4
−0.3
Ambient Temperature (powered applied)
Ta
−30
Storage Temperature
Tstg
−65
Maximum Power Dissipation Ta=85ºC (Note 14)
Pd1
(Note 13)
Pd2
Ta=70ºC (Note 15)
max
4.0
4.0
4.0
4.0
4.0
4.0
6.0
6.0
6.0
4.0
±10
AVDD+0.3
SAVDD+0.3
(AVDDA+0.3) or 6.0
6.0
DVDD+0.3
TVDD2+0.3
TVDD3+0.3
(TVDDA+0.3) or 6.0
85
150
0.91
1.18
Units
V
V
V
V
V
V
V
V
V
V
mA
V
V
V
V
V
V
V
V
°C
°C
W
W
Note 2. All voltages with respect to ground.
Note 3. VSS1, VSS2, VSS3, VSS4, VSS1A, VSS2A and VSS3A must be connected to the same analog
ground plane.
Note 4. TVDDA should be connected to DVDD.
Note 5. RIN4/IN4−, LIN4/IN4+, RIN3/IN3−, LIN3/IN3+, RIN2/IN2−, LIN2/IN2+, RIN1/IN1−, LIN1/IN1+ pins
Note 6. SAIN1, SAIN2, SAIN3 pins
Note 7. LIN1A, RIN1A, SPIN pins. The maximum value is smaller value between (AVDDA+0.3)V and 6.0V.
Note 8. VBATIN pin
Note 9. PDN, SCL, SDA, SDTI, LRCK, BICK, MCKI pins
Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage.
Note 10. BICKA, SYNCA, SDTIA pins
Note 11. BICKB, SYNCB, SDTIB pins
Note 12. PDNA, MCKIA pins. The maximum value is smaller value between (AVDDA+0.3)V and 6.0V.
Note 13. In case that the PCB wiring density is 300%. This power is the AK4675 internal dissipation that does not include
power of externally connected speaker and headphone.
Note 14. When Ta=85°C, the HP-Amp power must be under 30mW@16Ω and SPK-Amp power must be 1.0W@8Ω.
Note 15. When Ta=70°C, the HP-Amp power must be under 30mW@16Ω and SPK-Amp power must be 1.6W@8Ω.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS0963-E-00
2008/05
- 10 -
[AK4675]
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Note 2)
Parameter
Symbol
min
Power Supplies CODEC Analog
AVDD
2.2
(Note 16) PLLBT
PVDD
2.2
10bit SAR ADC
SAVDD
2.2
CODEC Digital
DVDD
1.6
CODEC Digital I/O 2
TVDD2
1.6
CODEC Digital I/O 3
TVDD3
1.6
HP/SPK-Amp Analog
AVDDA
2.6
HP/SPK-Amp Digital I/F
TVDDA
1.6
Speaker-Amp & Headphone-Amp
SVDDA
3.0
Charge Pump
PVDDA
2.6
Difference 1
AVDD−PVDD
−0.1
Difference 2
PVDDA–AVDDA
−0.3
Difference 3
SVDDA–AVDDA
−0.3
Difference 4
DVDD–TVDDA
−0.3
typ
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.6
3.3
0
0
0
max
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
5.5
3.6
+0.1
+0.3
+0.3
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note 2. All voltages with respect to ground.
Note 16. TVDDA must be connected to DVDD. The power-up sequence between AVDD, PVDD, SAVDD, DVDD,
TVDD2, TVDD3, AVDDA, TVDDA, SVDDA and PVDDA is not critical. However, the PDN and PDNA pin
must be held to “L” until all power supply pins are supplied. After all power supplies are filled, PDN and PDNA
pins should be set to “H”.
* The AK4675 supports the following two cases of partial power ON/OFF. In these cases, PDNA pin should be “L” and
all power management bits (PMVCM, PMMP, PMMICL, PMMICR, PMADL, PMADR, PMDAL, PMDAR, PMPLL,
PMLOOPL, PMLOOPR, PMAINL1, PMAINR1, PMAINL2, PMAINR2, PMAINL3, PMAINR3, PMAINL4,
PMAINR4, PMLO1, PMRO1, PMLO2S, PMRO2S, PMLO3, PMRO3, PMSRA, PMSRB, PMPCM, and PMSAD)
should be OFF or PDN and PDNA pins should be “L”.
1. DVDD=TVDDA=SVDDA=ON, AVDD=PVDD=SAVDD=TVDD2=TVDD3=AVDDA=PVDDA=OFF
2. DVDD=TVDDA=ON, AVDD=PVDD=SAVDD=TVDD2=TVDD3=AVDDA=PVDDA=SVDDA=OFF
When the power state is changed from OFF to ON in the above cases, the PDN and PDNA pins should be set to “H” after
all power supply pins are supplied.
When DVDD and TVDDA are powered OFF, AVDD, PVDD, SAVDD, TVDD2, TVDD3, AVDDA, TVDDA, SVDDA
or PVDDA must be powered OFF. When only DVDD and TVDDA are OFF, leak current of 10mA to 100mA may occur.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0963-E-00
2008/05
- 11 -
[AK4675]
ANALOG CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V;
VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Signal Frequency=1kHz; 16bit Data; fs=44.1kHz,
BICK=64fs, LP bit = “0”; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins; PMAINL1/R1/L2/R2/L3/R3/L4/R4 bits = “0”
Input Resistance
MGNL/R0 bit = “0”
28
42
56
kΩ
MGNL/R0 bit = “1”
20
30
40
kΩ
Gain (Note 17)
Max (MGNL/R3-0 bits = “FH”)
+30
dB
Min (MGNL/R3-0 bits = “1H”)
dB
−12
MIC Power Supply: MPWR pin
Output Voltage (Note 18)
2.47
2.64
2.81
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
MIC Detection: MDT pin
0.247
0.165
mV
Comparator Voltage Level (Note 19)
750
250
500
Internal pull down Resistance
kΩ
Stereo ADC Analog Input Characteristics:
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins → Stereo ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 21)
0.150
0.176
0.203
Vpp
Input Voltage (Note 20)
1.68
1.98
2.28
Vpp
(Note 22)
(Note 21)
72
82
dB
S/(N+D) (−1dBFS)
87
dB
(Note 22)
(Note 21)
75
86
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 22)
(Note 21)
75
86
dB
S/N (A-weighted)
95
dB
(Note 22)
(Note 21)
75
90
dB
Interchannel Isolation
100
dB
(Note 22)
(Note 21)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 22)
Note 17. In case of full-differential input, MGAIN=0dB (min) and AVDD=2.4V (min).
Note 18. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).
Note 19. Comparator Voltage Level is proportional to AVDD voltage. Vth = 0.05 x AVDD(min), 0.075 x AVDD(max).
Note 20. Input voltage is proportional to AVDD voltage. Vin = 0.053 x AVDD (typ)@MGNL3-0=MGNR3-0 bits =
“CH” (+21dB), Vin = 0.6 x AVDD(typ)@MGNL3-0=MGNR3-0 bits = “5H” (0dB).
Note 21. MGNL3-0=MGNR3-0 bits = “CH” (+21dB).
Note 22. MGNL3-0=MGNR3-0 bits = “5H” (0dB).
MS0963-E-00
2008/05
- 12 -
[AK4675]
min
typ
max
Units
Parameter
Stereo DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics:
Stereo DAC → LOUT1/ROUT1/LOUT3/ROUT3 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=L3VL=0dB,
RCV bit = “0”, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 23)
1.78
1.98
2.18
Vpp
S/(N+D) (0dBFS)
75
85
dB
S/N (A-weighted)
82
92
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Stereo Line Output Characteristics:
Stereo DAC → LOUT2S/ROUT2S pins, ALC=OFF, IVOL=0dB, OVOL=0dB, RL=25kΩ; unless otherwise specified.
Output Voltage (Note 23)
1.78
1.98
2.18
Vpp
S/(N+D) (0dBFS)
72
85
dB
S/N (A-weighted)
82
92
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
25
kΩ
Load Capacitance
30
pF
Mono Receiver-Amp Output Characteristics:
Stereo DAC → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=0dB, RCV bit = “1”, RL=32Ω, BTL;
unless otherwise specified.
Output Voltage (Note 24)
1.57
1.96
2.35
Vpp
−6dBFS, RL=32Ω (Po=15mW)
2.77
Vpp
−3dBFS, RL=32Ω (Po=30mW)
S/(N+D)
40
60
dB
−6dBFS, RL=32Ω (Po=15mW)
20
dB
−3dBFS, RL=32Ω (Po=30mW)
S/N (A-weighted)
82
92
dB
Load Resistance
32
Ω
Load Capacitance
30
pF
Note 23. The Output voltage is proportional to the AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 24. The Output voltage is proportional to the AVDD voltage. Vout = (RCP) − (RCN) = 0.59 x AVDD
(typ)@−6dBFS.
Note 25. VSS1 load capacitance to output pins.
MS0963-E-00
2008/05
- 13 -
[AK4675]
min
typ
max
Parameter
Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
L3VL=0dB, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 26)
3.52
3.96
4.36
S/(N+D) (0dBFS)
75
85
S/N (A-weighted)
85
95
Load Resistance (LOP/LON pins, respectively)
10
Load Capacitance (LOP/LON pins, respectively)
30
Single-ended Line Input: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins;
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
Maximum Input Voltage (Note 28)
1.98
Gain
InputÆLOUT1/ROUT1/LOUT2S/ROUT2S/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
−1
Input Æ RCP/RCN/LOP/LON (LODIF=RCV bits = “1”)
+6
Full-differential Line Input: IN1+/−, IN2+/−, IN3+/−, IN4+/− pins;
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
Maximum Input Voltage (Note 29)
1.98
Gain
InputÆLOUT1/ROUT1/LOUT2S/ROUT2S/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
−1
Input Æ RCP/RCN/LOP/LON (LODIF=RCV bits = “1”, Note 30)
+6
-
Units
Vpp
dB
dB
kΩ
pF
Vpp
dB
dB
Vpp
dB
dB
Note 26. The Output voltage is proportional to the AVDD voltage. Vout = (LOP) − (LON) = 1.2 x AVDD (typ).
Note 27. VSS1 load capacitance to output pins.
Note 28. The Maximum Input voltage is proportional to the AVDD voltage. Vin = 0.6 x AVDD (typ).
Note 29. The Maximum Input voltage is proportional to the AVDD voltage. Vin = (IN4+) − (IN4−) = 0.6 x AVDD (typ).
Note 30. Vout = (RCP) − (RCN) at RCV bit = “1”, Vout = (LOP) − (LON) at LODIF bit = “1”.
MS0963-E-00
2008/05
- 14 -
[AK4675]
ANALOG CHARACTERISTICS (HP/SPK-Amp)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V;
VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Input Signal Frequency =1kHz; Measurement band
width=10Hz ∼ 20kHz; Headphone-Amp: RL =16Ω; Speaker-Amp: RL =8Ω + 10μH; Charge Pump Circuit External
Capacitance: C1=C2= 2.2μF (Figure 3); unless otherwise specified)
Parameter
min
typ
max
Units
LIN1A, RIN1A pins
Input Resistance
25
50
110
kΩ
Input Analog Volume: L1V3-0, R1V3-0 bits
Step Size
1
2
3
dB
Gain Control Range
+10
dB
−20
Headphone-Amp: (LIN1A/RIN1A Æ HPL/HPR pins), HPGA = 0dB
Output Power (THD+N=1%) SVDDA=3.3V
64
mW
THD+N 0.7Vrms Single-ended Input, Po = 30mW
-58
dB
Output Noise (A-weighted)
24
40
μVrms
Interchannel Gain Mismatch
0.2
0.8
dB
Load Resistance
16
Ω
Load Capacitance
300
pF
Output Voltage: 0.7Vrms at single-ended Input
0.62
0.69
0.76
Vrms
PSRR
217Hz (Note 31)
70
dB
1kHz (Note 31)
70
dB
217Hz (Note 32)
100
dB
1kHz (Note 32)
80
dB
Interchannel Isolation
60
80
dB
Headphone Analog Volume 1 (HPGA4-0 bits)
Step Size
0.5
2
3.5
dB
Gain Control Range
+12
dB
−50
SPIN pins
Input Resistance
15
26
36
kΩ
Speaker Analog Volume: SPGA5-0 bits
Step Size
0.1
0.5
0.9
dB
Gain Control Range
+19.5
dB
−12
Class-D Speaker-Amp: SPIN Æ SPP/SPN; ALC = OFF, Input Volume=SPGA=0dB, BTL
Output Power (THD+N=10%)
SVDDA=5.0V
1.6
W
SVDDA=3.6V
0.8
W
Output Level (Note 33)
SVDDA = 5.0V, Input Level = 0.85Vrms
2.7
Vrms
SVDDA = 3.6V, Input Level = 0.64Vrms
2.0
Vrms
SVDDA = 3.6V, Input Level = 0.46Vrms
1.33
1.48
1.63
Vrms
THD+N: Po=0.25W, Input Level=0.46Vrms(Note 33)
-65
-40
dB
Output Noise (A-weighted)
71
150
μVrms
Load Resistance
8
Ω
Load Capacitance (Note 34)
300
pF
PSRR
217Hz (Note 35)
60
dB
1kHz (Note 35)
50
dB
217Hz (Note 36)
50
dB
1kHz (Note 36)
50
dB
Switching Frequency
150
250
400
kHz
Short Protection Current (Note 37)
40
120
mA
Start-Up Time
18
30
48
ms
MS0963-E-00
2008/05
- 15 -
[AK4675]
Note 31. PSR is applied to AVDDA and PVDDA with 100mVpp. This is the value of convoluting sinusoidal voltage of
100mVpp.
Note 32. PSR is applied to SVDDA with 0.89Vpp. This is the value of convoluting sinusoidal voltage of 100mVpp.
Note 33. When the input data is single-ended.
Note 34. VSS1 load capacitance to output pins. For differential signals, the load capacitance will be twice as big as this
value.
Note 35. PSR is applied to AVDDA with 100mVpp. This is the value of convoluting sinusoidal voltage of 100mVpp.
Note 36. PSR is applied to SVDDA with 100mVpp. This is the value of convoluting sinusoidal voltage of 100mVpp.
Note 37. The average current between SVDDA and VSS2A, when the SPP pin and SPN pin are shorted and 1kHz,
0.85Vrms sine wave is input at Single-ended mode.
Headphone-amp negative voltage
PVEE pin
C1
CN pin
VSS3A
CP pin
C2
Charge Pump Circuit
Figure 3. Charge Pump Circuit External Capacitor
Parameter
Battery Monitor: (BATCPU bit = “1”)
Input Resistance (VBATIN pin)
Attenuation (VBATO / VBATIN) (Note 38)
Note 38. When input 4.4V to the VBATIN pin.
MS0963-E-00
min
typ
max
Units
5
0.245
10
0.25
0.255
kΩ
-
2008/05
- 16 -
[AK4675]
ANALOG CHARACTERISTICS (Power Supply Current)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V;
VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V;
Signal Frequency=1kHz; 16bit Data; fs=44.1kHz, BICK=64fs, LP bit = “0”; Measurement frequency=20Hz ∼ 20kHz;
Headphone-Amp: RL =16Ω; Speaker-Amp: RL =8Ω + 10μH; Charge Pump Circuit External Capacitance: C1=C2=2.2μF
(Figure 3); unless otherwise specified)
Parameter
min
typ
max
Units
Power Supplies:
CODEC Block Power Up (PDN pin = “H”, All Circuits Power-up)
(Note 39)
20
mA
AVDD+PVDD+DVDD
40)
21
30
mA
(Note
+TVDD2+TVDD3+SAVDD
8
12
mA
(Note 41)
HP/SPK-Amp Block Power Up (PDNA pin = “H”, All Circuits Power-up)
AVDDA+TVDDA: ALL ON (Note 42)
4.0
6.5
mA
HP-Amp ON (Note 43)
2.0
mA
SPK-Amp ON (Note 44)
2.8
mA
PVDDA (No Output) HP-Amp ON
1.3
3.2
mA
SVDDA (No Output): HP-Amp ON
2.0
4.0
mA
SPK-Amp ON
1.0
4.0
mA
Power Down (PDN=PDNA pins = “L”) (Note 45)
AVDD+PVDD+DVDD+TVDD2+TVDD3+SAVD
1
60
μA
D+ AVDDA+PVDDA+SVDDA+TVDDA
Note 39. EXT Slave Mode and LP bit = “0”, fs=44.1kHz, PMMICL = PMMICR = PMADL = PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD = PMVCM bits = “1”,
PMPLL = MCKO = PMMP = M/S = PMSRA = PMSRB = PMPCM bits = “0”.
AVDD=12.1mA (typ), PVDD=0mA (typ), DVDD=5.6mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0.8mA (typ).
Note 40. PLL Master Mode and LP bit = “0”, fs=44.1kHz, PMADL = PMMICL= PMMICR= PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD = PMVCM = PMPLL =
M/S = PMMP bits = “1”, MCKO = PMSRA = PMSRB = PMPCM bits = “0”, MCKI=11.2896MHz.
AVDD=TBDmA (typ), PVDD=TBDmA (typ), DVDD=TBDmA (typ), TVDD2=TBDmA (typ),
TVDD3=TBDmA (typ), SAVDD=TBDmA (typ).
Note 41. EXT Slave Mode and LP bit = “1”, fs=8kHz, PMVCM = PMMP = PMMICL = PMADL = PMDAL = RCV =
PMLO1 = PMRO1 = PMSRA = PMSRB = PMPCM = “1”.
AVDD=3.2mA (typ), PVDD=0.8mA (typ), DVDD=2.7mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0mA (typ).
Note 42. Headphone-Amp & Speaker-Amp are powered-up.
(PMVCMA=PMOSC=PMCP=PMHPL=PMHPR=PMMHL=PMMHR=PMSPK=PMV1 bits= “1”)
Note 43. Headphone-Amp is powered-up.
(PMVCMA=PMOSC=PMCP=PMHPL=PMHPR=PMMHL=PMMHR=PMV1 bits= “1”,
PMSPK bits= “0”)
Note 44. Speaker-Amp is powered-up
(PMVCMA=PMOSC=PMCP=PMSPK bits= “1”,
PMHPL=PMHPR=PMMHL=PMMHR=PMV1 bits= “0”)
Note 45. All digital input pins are fixed to each supply pin (DVDD, TVDD2 or TVDD3) or VSS4.
MS0963-E-00
2008/05
- 17 -
[AK4675]
SRC CHARACTERISTICS
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; unless otherwise specified)
Parameter
Symbol
min
typ
max
SRC Characteristics (Down Sampling: SRC-A): SDTI Æ SRC-A Æ SDTOA/SDTOB
Resolution
16
Input Sample Rate (Note 47)
FSI (fs)
8
48
Output Sample Rate (Note 47)
FSO (fs2)
8
THD+N (Input = 1kHz, −1dBFS, Note 46)
FSO/FSI = 8kHz/44.1kHz
-94
Dynamic Range (Input = 1kHz, −60dBFS, Note 46)
FSO/FSI = 8kHz/44.1kHz
97
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
1
SRC Characteristics (Up Sampling: SRC-B): SDTIA/SDTIB Æ SRC-B Æ SDTO
Resolution
16
Input Sample Rate (Note 47)
FSI (fs2)
8
Output Sample Rate (Note 47)
FSO (fs)
8
48
THD+N (Input = 1kHz, −1dBFS, Note 46)
FSO/FSI = 44.1kHz/8kHz
-95
Dynamic Range (Input = 1kHz, −60dBFS, Note 46)
FSO/FSI = 44.1kHz/8kHz
100
Ratio between Input and Output Sample Rate
FSO/FSI
1
6
Units
Bits
kHz
kHz
dB
dB
Bits
kHz
kHz
dB
dB
-
Note 46. Measured by Audio Precision System Two Cascade.
Note 47. “fs” is the sampling frequency for Stereo CODEC. “fs2” is for PCM I/F.
MS0963-E-00
2008/05
- 18 -
[AK4675]
ANALOG CHARACTERISTICS (10bit SAR ADC)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V; unless
otherwise specified)
Parameter
min
typ
max
Units
10bit SAR ADC Characteristics
Resolution
10
Bits
No Missing Codes
9
10
Bits
Integral Linearity Error
LSB
±2
DNL
LSB
±1
Analog Input Voltage Range
0
SAVDD
V
Offset Error
LSB
±3
Gain Error
LSB
±2
Accuracy (Note 48)
%
±1
Note 48. Accuracy is the difference between the output code when 1.1V is input to SAIN1, SAIN2 or SAIN3 pin and the
“ideal” code at 1.1V.
MS0963-E-00
2008/05
- 19 -
[AK4675]
FILTER CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; fs=44.1kHz; Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 49)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
25.9
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 50)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
DAC Digital Filter (LPF):
Passband (Note 49)
PB
0
17.4
kHz
±0.1dB
20.0
kHz
−1.0dB
21.1
kHz
−3.0dB
Stopband
SB
25.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 50)
GD
19
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.4
Note 49. The passband and stopband frequencies scale with fs (system sampling rate).
For example, DAC is PB=0.454 x fs (@−0.7dB). Each response refers to that of 1kHz.
Note 50. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of both channels from the input register to the output register of the ADC.
For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of
analog signal.
MS0963-E-00
2008/05
- 20 -
[AK4675]
FILTER CHARACTERISTICS (SRC)
(Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; fs2=8kHz; Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
Down Sampling (SRC-A): fs=8kHz
Passband
PB
0
3.0
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
5
ms
Down Sampling (SRC-A): fs=11.025kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
4
ms
Down Sampling (SRC-A): fs=12kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
4
ms
Down Sampling (SRC-A): fs=16kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Down Sampling (SRC-A): fs=22.05kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Down Sampling (SRC-A): fs=24kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Note 51. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0963-E-00
2008/05
- 21 -
[AK4675]
Parameter
Symbol
min
typ
max
Units
Down Sampling (SRC-A): fs=32kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Down Sampling (SRC-A): fs=44.1kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Down Sampling (SRC-A): fs=48kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 51)
GD
3
ms
Note 51. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0963-E-00
2008/05
- 22 -
[AK4675]
Parameter
Symbol
min
typ
max
Units
Up Sampling (SRC-B): fs=8kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=11.025kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=12kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=16kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=22.05kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=24kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Note 51. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0963-E-00
2008/05
- 23 -
[AK4675]
Parameter
Symbol
min
typ
max
Units
Up Sampling (SRC-B): fs=32kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=44.1kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Up Sampling (SRC-B): fs=48kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 51)
GD
2
ms
Note 51. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0963-E-00
2008/05
- 24 -
[AK4675]
DC CHARACTERISTICS (CODEC, SRC)
(Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V)
Parameter
Symbol
min
typ
High-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIH1
70%DVDD
(Note 52)
1.6V≤DVDD<2.2V
VIH1
80%DVDD
Low-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIL1
(Note 52)
1.6V≤DVDD<2.2V
VIL1
High-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIH2
70%TVDD2
(Note 53)
1.6V≤TVDD2<2.2V
VIH2
80%TVDD2
Low-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIL2
(Note 53)
1.6V≤TVDD2<2.2V
VIL2
High-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIH3
70%TVDD3
(Note 54)
1.6V≤TVDD3<2.2V
VIH3
80%TVDD3
Low-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIL3
(Note 54)
1.6V≤TVDD3<2.2V
VIL3
High-Level Output Voltage
(Note 55, Iout=−200μA) VOH1
DVDD−0.2
VOH2
(Note 56, Iout=−200μA)
TVDD2−0.2
(Note 57, Iout=−200μA) VOH3
TVDD3−0.2
Low-Level Output Voltage
(Except SDA pin: Iout=200μA) VOL1
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA) VOL2
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA) VOL2
Input Leakage Current
(Note 58)
Iind
(Note 59)
Iina
-
max
30%DVDD
20%DVDD
30%TVDD2
20%TVDD2
30%TVDD3
20%TVDD3
Units
V
V
V
V
V
V
V
V
V
V
V
V
-
V
V
V
0.2
0.4
20%DVDD
V
V
V
±2
±2
μA
μA
Note 52. TEST5, SCL, SDA, TEST3, PDN, BICK, LRCK, SDTI, MCKI pins.
Note 53. BICKA, SYNCA, SDTIA pins.
Note 54. BICKB, SYNCB, SDTIB pins.
Note 55. MCKO, BICK, LRCK, SDTO, GPO1, GPO2 pins.
Note 56. BICKA, SYNCA, SDTOA pins.
Note 57. BICKB, SYNCB, SDTOB pins.
Note 58. SYNCB, BICKB, SDTIB, SDTI, LRCK, MCKI, BICK, SCL, SDA, SDTIA, BICKA, SYNCA pins. I/O pins
(SYNCB, BICKB, LRCK, BICK, SDA, BICKA, SYNCA) are at the time of Input state.
Note 59. SAIN1, SAIN2, SAIN3 pins.
DC CHARACTERISTICS (HP/SPK-Amp)
(Ta= 25°C; AVDDA=PVDDA=2.6 ∼ 3.6V; SVDDA=2.6 ∼ 5.5V, TVDDA=1.6 ∼ 3.6V)
Parameter
Symbol
min
typ
max
High-Level Input Voltage (2.2V≤TVDDA≤3.6V)
VIH4
70%TVDDA
(Note 60)
VIH4
80%TVDDA
(1.6V≤TVDDA<2.2V)
Low-Level Input Voltage (2.2V≤TVDDA≤3.6V)
VIL4
30%TVDDA
(Note 60)
VIL4
(1.6V≤TVDDA<2.2V)
20%TVDDA
Input Leakage Current (Note 61)
Iin
±10
Note 60. PDNA, MCKIA pins.
Note 61. Except the MCKIA pin. The MCKIA pin has internal pulled-down device, nominally 100kΩ.
Units
V
V
V
V
μA
MS0963-E-00
2008/05
- 25 -
[AK4675]
SWITCHING CHARACTERISTICS (CODEC, SRC)
(Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; CL=20pF (except SDA pin) or
400pF (SDA pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz
dMCK
40
50
60
%
256fs at fs=32kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0963-E-00
2008/05
- 26 -
[AK4675]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs/384fs
fs
512fs/768fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0963-E-00
min
typ
max
Units
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
8
8
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2008/05
- 27 -
[AK4675]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 62)
tDBF
LRCK “↑” to BICK “↓” (Note 63)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 62)
tLRB
LRCK “↑” to BICK “↓” (Note 63)
tBLR
BCLK “↑” to LRCK “↑” (Note 62)
tBLR
BICK “↓” to LRCK “↑” (Note 63)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 64)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 64)
tBLR
BICK “↑” to LRCK Edge (Note 64)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
Note 62. MSBS, BCKP bits = “00” or “11”.
Note 63. MSBS, BCKP bits = “01” or “10”.
Note 64. BICK rising edge must not occur at the same time as LRCK edge.
MS0963-E-00
2008/05
- 28 -
[AK4675]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Slave Mode):
SYNCA Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKA Frequency
fBCK2
128
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↑” (Note 65)
tSYB2
50
SYNCA Edge to BICKA “↓” (Note 66)
tBSY2
50
BICKA “↑” to SYNCA Edge (Note 65)
tBSY2
50
BICKA “↓” to SYNCA Edge (Note 66)
SYNCA to SDTOA (MSB) (Except Short Frame)
tSYD2
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width Low
tSYL2
0.8 x tBCK2
Pulse Width High
tSYH2
0.8 x tBCK2
Serial Interface Timing at MSB justified and I2S
BICKA Frequency
fBCK2
256
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↑”
tBSY2
50
BICKA “↑” to SYNCA Edge
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
tBSD2
BICKA “↓” to SDTOA
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDH2
50
SYNCA Duty Cycle
dSYC2
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 65. MSBSA, BCKPA bits = “00” or “11”.
Note 66. MSBSA, BCKPA bits = “01” or “10”.
MS0963-E-00
2008/05
- 29 -
[AK4675]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Master Mode):
SYNCA Timing
Frequency
fs2
BICKA Timing
Period (BCKO2 bit = “0”)
tBCK2
(BCKO2 bit = “1”)
tBCK2
Duty Cycle
dBCK2
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↑” (Note 65)
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↓” (Note 66)
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
−70
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width High
tSYH2
Serial Interface Timing at MSB justified and I2S
tBSY2
BICKA “↓” to SYNCA Edge
−40
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
−70
tBSD2
BICKA “↓” to SDTOA
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDH2
50
SYNCA Duty Cycle
dSYC2
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
kHz
kHz
%
0.5 x tBCK2
0.5 x tBCK2 + 40
0.5 x tBCK2
0.5 x tBCK2 + 40
tBCK2
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 65. MSBSA, BCKPA bits = “00” or “11”.
Note 66. MSBSA, BCKPA bits = “01” or “10”.
MS0963-E-00
2008/05
- 30 -
[AK4675]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Slave Mode):
SYNCB Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKB Frequency
fBCK3
128
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↑” (Note 67)
tSYB3
50
SYNCB Edge to BICKB “↓” (Note 68)
tBSY3
50
BICKB “↑” to SYNCB Edge (Note 67)
tBSY3
50
BICKB “↓” to SYNCB Edge (Note 68)
SYNCB to SDTOB (MSB) (Except Short Frame)
tSYD3
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width Low
tSYL3
0.8 x tBCK2
Pulse Width High
tSYH3
0.8 x tBCK2
Serial Interface Timing at MSB justified and I2S
BICKB Frequency
fBCK3
256
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↑”
tBSY3
50
BICKB “↑” to SYNCB Edge
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
tBSD3
BICKB “↓” to SDTOB
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDH3
50
SYNCB Duty Cycle
dSYC3
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 67. MSBSB, BCKPB bits = “00” or “11”.
Note 68. MSBSB, BCKPB bits = “01” or “10”.
MS0963-E-00
2008/05
- 31 -
[AK4675]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Master Mode):
SYNCB Timing
Frequency
fs2
BICKB Timing
Period (BCKO2 bit = “0”)
tBCK2
(BCKO2 bit = “1”)
tBCK2
Duty Cycle
dBCK2
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK2 − 40
tSYB3
SYNCB Edge to BICKB “↑” (Note 67)
0.5 x tBCK2 − 40
tSYB3
SYNCB Edge to BICKB “↓” (Note 68)
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
−70
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width High
tSYH3
Serial Interface Timing at MSB justified and I2S
tBSY3
BICKB “↓” to SYNCB Edge
−40
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
−70
tBSD3
BICKB “↓” to SDTOB
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDH3
50
SYNCB Duty Cycle
dSYC3
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
kHz
kHz
%
0.5 x tBCK2
0.5 x tBCK2 + 40
0.5 x tBCK2
0.5 x tBCK2 + 40
tBCK2
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 67. MSBSB, BCKPB bits = “00” or “11”.
Note 68. MSBSB, BCKPB bits = “01” or “10”.
MS0963-E-00
2008/05
- 32 -
[AK4675]
Parameter
Symbol
min
typ
max
Units
2
Control Interface Timing (I C Bus mode): (Note 69)
SCL Clock Frequency (Note 70)
fSCL
30
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
μs
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling (Note 71)
tHD:DAT
0
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Capacitive Load on Bus
Cb
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
50
ns
Power-down & Reset Timing
PDN Pulse Width (Note 72)
tPD
150
ns
tPDV
1059
1/fs
PMADL or PMADR “↑” to SDTO valid (Note 73)
tPDV2
21
1/fs2
PMSRA “↑” to SDTOA valid (Note 74)
tPDV3
135
1/fs
PMSRB “↑” to SDTO valid (Note 75)
Note 69. I2C is a registered trademark of Philips Semiconductors.
Note 70. In case that SAR ADC data is read out via I2C bus, SCL should be input corresponding 2 byte data including
ACK (Figure 110).
Note 71. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 72. CODEC & SRC blocks of the AK4675 can be reset by bringing PDN pin = “L” to “H” only upon power up
Note 73. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1” when PMSRB bit = “0”.
Note 74. The signal path is SDTI → SRC-A → SDTOA and PLLBT is locked.
Note 75. The signal path is SDTIA → SRC-B → SDTO.
MS0963-E-00
2008/05
- 33 -
[AK4675]
SWITCHING CHARACTERISTICS (HP/SPK-Amp)
(Ta= 25°C; AVDDA=PVDDA=2.6 ∼ 3.6V; SVDDA=2.6 ∼ 5.5V; TVDDA=1.6 ∼ 3.6V)
Parameter
Symbol
min
typ
max
MCKIA Input Timing (OSCN bit = “1”)
Frequency
fCLK
2.048
3.072
Pulse Width Low
fCLKL
0.4/fCLK
Pulse Width High
fCLKH
0.4/fCLK
Power-down & Reset Timing
PDNA Pulse Width (Note 76)
tPD
150
Note 76. HP/SPK-Amp blocks can be reset by power up of the AK4675 when the PDNA pin = “L”.
MS0963-E-00
Units
MHz
ns
ns
ns
2008/05
- 34 -
[AK4675]
■ Timing Diagram (CODEC, SRC)
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
50%DVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL/EXT Master mode)
Note 77. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
VIL1
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0963-E-00
2008/05
- 35 -
[AK4675]
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
VIL1
Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”)
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0963-E-00
2008/05
- 36 -
[AK4675]
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "0")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "1")
VIL1
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”)
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "1")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "0")
VIL1
Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”)
MS0963-E-00
2008/05
- 37 -
[AK4675]
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH1
BICK
VIL1
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "0")
VIH1
BICK
(BCKP = "1")
VIL1
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
MSB
VIL1
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0963-E-00
2008/05
- 38 -
[AK4675]
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "1")
VIH1
BICK
(BCKP = "0")
VIL1
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
MSB
VIL1
Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”)
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH1
BICK
VIL1
tBCKH
tBCKL
Figure 13. Clock Timing (EXT Slave mode)
MS0963-E-00
2008/05
- 39 -
[AK4675]
VIH1
LRCK
VIL1
tBLR
tLRB
VIH1
BICK
VIL1
tBSD
tLRD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH1
SDTI
VIL1
Figure 14. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
1/fs2
VIH2
SYNCA
VIL2
tSYH2
tSYL2
dSYC2 = tSYL2 x fs2 x 100
tBC K2
VIH 2
VIL2
BIC KA
tBC KH 2
tBC KL2
dBC K2 = tBC KL2 / tBC K2 x 100
Figure 15. Clock Timing of PCM I/F A (SYNCA, BICKA)
MS0963-E-00
2008/05
- 40 -
[AK4675]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “0”)
VIH2
BICKA
VIL2
(BCKPA = “1”)
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 16. PCM I/F A Timing at short and long frame sync (SYNCA, BICKA, SDTOA, SDTIA)
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “1”)
VIH2
BICKA
(BCKPA = “0”)
VIL2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
2
Figure 17. PCM I/F B Timing at MSB justified and I S (SYNCA, BICKA, SDTOA, SDTIA)
MS0963-E-00
2008/05
- 41 -
[AK4675]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 18. PCM I/F A Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD2
SYNCA
tSYH2
tSYL2
dSYC2 = tSYL2 x fs2 x 100
tBC K2 = 1/fBC K2
50% T VD D 2
BIC KA
tBC KH 2
tBC KL2
dBC K2 = tBC KL2 / tBC K2 x 100
Figure 19. Clock Timing of PCM I/F A (Master mode)
MS0963-E-00
2008/05
- 42 -
[AK4675]
SYNCA
50%TVDD2
tSYB2
BICKA
(BCKPA = “0”)
50%TVDD2
BICKA
50%TVDD2
(BCKPA = “1”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 20. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “0”)
SYNCA
50%TVDD2
tSYB2
50%TVDD2
BICKA
(BCKPA = “1”)
50%TVDD2
BICKA
(BCKPA = “0”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 21. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “1”)
MS0963-E-00
2008/05
- 43 -
[AK4675]
50%TVDD2
SYNCA
tMBSY2
50%TVDD2
BICKA
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 22. PCM I/F A Timing at MSB justified and I2S (Master mode)
1/fs2
VIH3
SYNCB
VIL3
tSYH3
tSYL3
dSYC3 = tSYH3 x fs2 x 100
tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
VIH 3
VIL3
BIC KB
tBC KH 3
tBC KL3
Figure 23. Clock Timing of PCM I/F B (Slave mode)
MS0963-E-00
2008/05
- 44 -
[AK4675]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “0”)
VIH3
BICKB
VIL3
(BCKPB = “1”)
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 24. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “0”)
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “1”)
VIH3
BICKB
(BCKPB = “0”)
VIL3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
2
Figure 25. PCM I/F B Timing at MSB justified and I S (Slave mode; MSBSB = “1”)
MS0963-E-00
2008/05
- 45 -
[AK4675]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 26. PCM I/F B Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD3
SYNCB
tSYH3
tSYL3
dSYC3 = tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
50% T VD D 3
BIC KB
tBC KH 3
tBC KL3
dBC K3 = tBC KL3 / tBC K3 x 100
Figure 27. Clock Timing of PCM I/F B (Master mode)
MS0963-E-00
2008/05
- 46 -
[AK4675]
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “0”)
50%TVDD3
BICKB
(BCKPB = “1”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 28. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “0”)
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “1”)
50%TVDD3
BICKB
(BCKPB = “0”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 29. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “1”)
MS0963-E-00
2008/05
- 47 -
[AK4675]
50%TVDD3
SYNCB
tMBSY3
50%TVDD3
BICKB
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 30. PCM I/F B Timing at MSB justified and I2S (Master mode)
VIH1
SDA
VIL1
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH1
SCL
VIL1
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
Start
tSU:STO
Stop
Figure 31. I2C Bus Mode Timing
MS0963-E-00
2008/05
- 48 -
[AK4675]
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 32. Power Down & Reset Timing 1
tPD
PDN
VIL1
Figure 33. Power Down & Reset Timing 2
PMSRA bit
tPDV2
SDTOA
50%TVDD2
Figure 34. Power Down & Reset Timing 3
PMSRB bit
tPDV3
SDTO
50%DVDD
Figure 35. Power Down & Reset Timing 4
MS0963-E-00
2008/05
- 49 -
[AK4675]
■ Timing Diagram (HP/SPK-Amp)
1/fCLK
VIH4
MCKIA
VIL4
tCLKH
tCLKL
Figure 36. MCKIA Input Timing
tPD
PDNA
VIL4
Figure 37. Power-down & Reset Timing
MS0963-E-00
2008/05
- 50 -
[AK4675]
OPERATION OVERVIEW
■ System Clock (Audio I/F)
There are the following five clock modes to interface with external devices. (Table 1 and Table 2.)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 78)
1
1
See Table 4
Figure 38
PLL Slave Mode 1
Figure 39
1
0
See Table 4
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Figure 40
1
0
See Table 4
Figure 41
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
0
0
x
Figure 42
EXT Master Mode
0
1
x
Figure 43
Note 78. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
GND
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(Selected by
PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 2. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4675 is power-down mode (PDN pin = “L”) and exits reset state, the AK4675 is in slave mode. After exiting reset
state, the AK4675 goes to master mode by changing M/S bit = “1”.
When the AK4675 is in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and
BICK pins of the AK4675 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS0963-E-00
(default)
2008/05
- 51 -
[AK4675]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, an integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0
and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4675 is supplied stable clock after PLL is
powered-up (PMPLL bit = “0” → “1”) or sampling frequency is changed. When AIN3 bit = “1”, the PLL is not available.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
0
0
0
0
0
LRCK pin
1fs
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
Others
Others
R and C of
VCOC pin
C[F]
R[Ω]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
PLL Lock
Time
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
5
0
1
0
1
11.025kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
15
1
1
1
1
44.1kHz
(default)
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0963-E-00
2008/05
- 52 -
[AK4675]
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (Table 6).
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
Don’t
care
Don’t
care
0
0
0
8kHz ≤ fs ≤ 12kHz
Don’t care
Don’t care
1
0
1
12kHz < fs ≤ 24kHz
Don’t care
Don’t care
Don’t care
(default)
2
1
24kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pins at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L”.
(Table 7)
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
See Table 9
See Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ
“1”. After that, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACR,
DACH and DACS bits.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0963-E-00
2008/05
- 53 -
[AK4675]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO
output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output frequency
is selected between 32fs or 64fs, by BCKO bit (Table 10).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
AK4675
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 38. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0963-E-00
2008/05
- 54 -
[AK4675]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the
AK4675 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL reference clock: MCKI pin
The BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this
case, BICK and LRCK can be stopped.
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4675
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 39. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0963-E-00
2008/05
- 55 -
[AK4675]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits. (Table 6)
AK4675
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 40. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4675
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 41. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4675 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
MS0963-E-00
2008/05
- 56 -
[AK4675]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4675 becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are
MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be
synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by
FS1-0 bits (Table 11).
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this
case, BICK and LRCK can be stopped.
Mode
0
1
4
5
6
7
Others
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(N/A: Not available, x: Don’t care)
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
FS3 bit
FS2 bit
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 12.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1”, PMDAL bit = “1” or PMDAR bit = “1”). If these clocks are not provided, the
AK4675 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode
(PMADL=PMADR=PMDAL=PMDAR bits = “0”).
AK4675
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 42. EXT Slave Mode
MS0963-E-00
2008/05
- 57 -
[AK4675]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4675 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or
1024fs). The input frequency of MCKI is selected by FS2-0 bits (Table 13).
Mode
0
1
4
5
6
7
Others
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(N/A: Not available, x: Don’t care)
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
FS3 bit
FS2 bit
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through the LOUT/ROUT pins at fs=8kHz is shown in Table 14.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 14. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “0” or PMDAR bit = “1”). If MCKI is not provided, the AK4675 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
AK4675
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs or 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 43. EXT Master Mode
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
MS0963-E-00
2008/05
- 58 -
[AK4675]
■ System Reset
The PDNA pin must keep “L” until all power supply pins are supplied, and must be set to “H”. After exiting reset (PDNA
pin: “L” Æ “H”), all blocks of HP/SPK-Amp blocks (Input Volume, VCOMA, Oscillator, Mixer, Headphone-Amp,
Speaker-Amp and charge pump circuit) switch to the power-down state. The contents of the control register are
maintained until this reset by the PDNA pin.
Upon power-up, CODEC & SRC blocks of the AK4675 must be reset by bringing the PDN pin = “L”. This ensures that
all internal registers of CODEC & SRC blocks reset to their initial values.
The ADC enters initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” if PMDAL and
PMDAR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During initialization cycle, the ADC
digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input signal
after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an initialization
cycle.
MS0963-E-00
2008/05
- 59 -
[AK4675]
■ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 16). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and
BICK are output from the AK4675 in master mode, but must be input to the AK4675 in slave mode.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC)
SDTI (DAC)
DSP Mode
DSP Mode
MSB justified LSB justified
MSB justified MSB justified
I2S compatible I2S compatible
Table 16. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Table 17
Figure 48
Figure 49
Figure 50
(default)
In modes 1-3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 17).
DIF1
0
DIF0
MSBS
BCKP
0
0
0
1
1
0
1
1
0
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
Table 17. Audio Interface Format in Mode 0
Figure
Figure 44
(default)
Figure 45
Figure 46
Figure 47
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0963-E-00
2008/05
- 60 -
[AK4675]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 44. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
2
1
0
15 14
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 45. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
MS0963-E-00
2008/05
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[AK4675]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 46. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
Lch
SDTI(i)
15 14
15 14
2
1
0
2
1
0
Rch
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 47. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
MS0963-E-00
2008/05
- 62 -
[AK4675]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 48. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 49. Mode 2 Timing
MS0963-E-00
2008/05
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[AK4675]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 50. Mode 3 Timing
MS0963-E-00
2008/05
- 64 -
[AK4675]
■ MIC/LINE Input Selector
The AK4675 has input selector. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “0”, INL1-0 and INR1-0 bits select
LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are
“1”, LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 pins become IN1+/−, IN2+/−, IN3+/− and IN4+/− pins,
respectively. In this case, full-differential input is available (Figure 52).
MDIF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MDIF2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
MDIF3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
MDIF4
INL1
INL0
INR1
INR0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
1
1
0
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
Others
Table 18. MIC-Amp Input Signal
MS0963-E-00
Lch
LIN1
LIN1
LIN1
LIN1
LIN2
LIN2
LIN2
LIN2
LIN3
LIN3
LIN3
LIN3
LIN4
LIN4
LIN4
LIN4
LIN1
LIN2
LIN3
IN3+/−
IN3+/−
IN3+/−
IN3+/−
LIN1
LIN3
LIN4
IN3+/−
IN1+/−
IN1+/−
IN1+/−
IN1+/−
IN1+/−
Rch
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
RIN1
RIN2
RIN3
RIN4
IN4+/−
IN4+/−
IN4+/−
RIN1
RIN2
RIN4
IN4+/−
IN2+/−
IN2+/−
IN2+/−
IN2+/−
RIN2
RIN3
RIN4
IN4+/−
IN2+/−
(default)
N/A
2008/05
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[AK4675]
AK4675
INL1-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR1-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINR1 bit
PMAINL1 bit
RIN4/IN4− pin
Lineout
Figure 51. Mic/Line Input Selector
AK4675
MPWR pin
1k
MIC-Amp
IN1+ pin
IN1− pin
1k
Figure 52. Connection Example for Full-differential Mic Input (MDIF1/2/3/4 bits = “1”)
AK4675
MIC-Amp
IN1+ pin
IN1− pin
Figure 53. Connection Example for Full-differential Mic Input (MDIF1/2/3/4 bits = “1”)
MS0963-E-00
2008/05
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[AK4675]
■ MIC Gain Amplifier
The AK4675 has a gain amplifier for microphone input. The gain of MIC-Amp Lch and Rch is independently selected by
the MGNL3-0 and MGNR3-0 bits (Table 19). The typical input impedance is 42kΩ(typ)@MGNL/R0 bits = “0” or
30kΩ(typ)@MGNL/R0 bits = “1”.
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MGNL3
MGNR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MGNL2
MGNR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MGNL1
MGNL0
Input Gain
MGNR1
MGNR0
0
0
N/A
0
1
−12dB
1
0
−9dB
1
1
−6dB
0
0
−3dB
0
1
0dB
1
0
+3dB
1
1
+6dB
0
0
+9dB
0
1
+12dB
1
0
+15dB
1
1
+18dB
0
0
+21dB
0
1
+24dB
1
0
+27dB
1
1
+30dB
Table 19. Mic Input Gain
MS0963-E-00
Input Resistance
N/A
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
(default)
2008/05
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[AK4675]
■ MIC Power
When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.8 x AVDD
and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for
each channel. Any capacitor must not be connected directly to the MPWR pin (Figure 54).
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 20. MIC Power
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 54. MIC Block Circuit
MS0963-E-00
2008/05
- 68 -
[AK4675]
■ MIC Detection
The AK4675 has a detect function of microphone inputs.
The followings show the example of external microphone detection sequence:
(1) PMMP bit should be set to “1” after CPU detects the jack insertion of microphone or headphone.
(2) The MPWR pin drives external microphone.
(3) The GPO2 pin (at GPOM2 bit = “1”) and DTMIC bit are set as Table 21. In case of Headset (with Mic), the input
voltage of the MDT pin is higher than 0.075 x AVDD because of the relationship between the bias resistance at the
MPWR pin (typ. 2.2kΩ) and the microphone impedance. In case of Headphone (No Mic), the input voltage of the
MDT pin is 0V because the pin of headphone jack is connected to the MDT pin is assigned as ground.
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MPWR
Result
Mic (Headset)
No Mic (Headphone)
PMMP bit
AK4675
LIN1
LIN2
Headset
G
M
R
MDT
L
DTMIC bit
typ.
500k
or
Headphone
G
R
0.075 x AVDD
L
Figure 55. Microphone Power Supply and Mic Detection
MS0963-E-00
2008/05
- 69 -
[AK4675]
■ Digital Block
Digital block is composed as Figure 56. Each block can be powered-down by power management bit (PMADL, PMADR,
PMDAL, PMDAR, PMSRA, PMSRB and PMPCM bits). When blocks from HPF to MIX are powered-down, both MIX
and SVOLA blocks should not be selected by SDOL/R bits and PFMXL/R bits.
PMADL or PMADR
HPF
A/D
HPFAD
PFSEL
PFSEL=0
PMADL
or
PMADR
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
HPF
HPF
LPF
LPF
Stereo
Separation
5-band
Notch
FIL3, EQ0,
GN1-0
EQ1-5
ALC
ALC, IVL/R
MIX
ADM
SDOL/R1-0 SDOD
SDTO Lch
SDTO Rch
SVAL/R2-0
SVOLA
DAM, MIXD
D/A
PMDAL
or PMDAR
OVL/R
EQ
SRMXL/R1-0
M DATT 5-band
I SMUTE
EQ
X
PMDAL or PMDAR or PMSRA
S
E
L
SDTI Lch
SDTI Rch
SDIM1-0
PFMXL/R1-0
SRA1-0, MIXD
PMPCM
PMSRA
SDOA
SRC-A
SDOAD
SDTOA
SVOLB
SVB2-0
PMSRB
SRC-B
BVMX1-0
DATT-B
SDTIA
BVL7-0
SBMX1-0
DATT-C
CVL7-0
BIV2-0
BIVOL
SDOBD
SDTOB
SDTIB
Figure 56. Path Select of Digital Block
MS0963-E-00
2008/05
- 70 -
[AK4675]
(1)
(2)
(3)
(4)
(5)
ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter”.)
LPF: Low Pass Filter (See “Digital Programmable Filter”.)
Stereo Separation: Stereo Separation Emphasis Filter & Gain Comparison. (See “Digital Programmable Filter”.)
Gain Comparison is composed with EQ0 and Gain blocks. This block adjusts the frequency response after Stereo
Separation Emphasis.
(6) 5-Band Notch: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter”.)
(7) ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”.)
(8) SVOLA: Side Tone Volume at Internal MIC/SPK or External Headset Phone Call. (See “Side Tone Volume
(SVOLA)”.)
(9) 5-Band EQ: Equalizer for playback path. (See “5-band Equalizer”.)
(10) DATT: Digital Volume for playback path. (See “Digital Output Volume”.)
(11) SMUTE: Soft mute. (See “Soft Mute”.)
(12) DATT-B: Digital Volume for Recording of Received Voice. (See “Digital Volume for Recording of Received
Voice”)
(13) DATT-C: Digital Volume of Received Voice. (See “Digital Volume of Received Voice”)
(14) SVOLA: Side Tone Volume at B/T Headset Phone Call. (See “Side Tone Volume for B/T Phone Call”.)
Mode
Recording Mode
PMADL
1
1
0
1
1
0
0
Recording &
Playback Mode
Playback Mode
ADC
PMADR
PMDAL
PMDAR
1
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Table 22. Recode/Playback Mode
2nd Order
1st Order
HPF
LPF
Stereo
Separation
Gain
Compensation
PFSEL
0
0
0
0
0
0
1
Figure
Figure 57
Figure 58
Figure 59
5 Band
Notch
ALC
(Volume)
Figure 57. Path at Recording Mode
ADC
DAC
2nd Order
1st Order
HPF
LPF
DEM
SMUTE
DATT
Stereo
Separation
Gain
Compensation
5 Band
Notch
ALC
(Volume)
5 Band
EQ
Figure 58. Path at Recording & Playback Mode
ADC
DAC
1st Order
“0” Data
HPF
DEM
SMUTE
DATT
5 Band
EQ
ALC
(Volume)
5 Band
EQ
Gain
Compensation
Stereo
Separation
1st Order
1st Order
LPF
HPF
Figure 59. Path at Playback Mode
MS0963-E-00
2008/05
- 71 -
[AK4675]
■ Digital Programmable Filter
(1) High Pass Filter (HPF)
Normally, this HPF is used for a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The
coefficient of both HPF is the same and set by F1A13-0 bits and F1B13-0 bits. HPFAD bit controls ON/OFF of the 1st
step HPF and HPF bit controls ON/OFF of the 2nd step HPF. When the HPF is OFF, the audio data passes this block by
0dB gain. The coefficient should be set when HPFAD=HPF bits = “0” or PMADL=PMADR=PMDAL=PMDAR bits =
“0”.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 79)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when LPF
bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 79)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
MS0963-E-00
2008/05
- 72 -
[AK4675]
(3) Stereo Separation Emphasis Filter (FIL3)
FIL3 is used to emphasize the stereo separation of stereo mic recording data or playback data. F3A13-0 and F3B13-0 bits
set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at
F3AS bit = “1”. FIL3 bit controls ON/OFF of FIL3. When Stereo Separation Emphasis Filter is OFF, the audio data
passes this block by 0dB gain. The coefficient should be set when FIL3 bit = “0” or PMADL = PMADR = PMDAL =
PMDAR bits = “0”.
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 79)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
A = 10K/20 x
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 79)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
MS0963-E-00
2008/05
- 73 -
[AK4675]
(4) Gain Compensation (EQ0)
Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation
Emphasis Filter. Gain Compensation is composed with Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A15-0,
E0B13-0 and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits set the gain (Table 23). EQ0 bit controls ON/OFF of
EQ0. When EQ is OFF and the gain is 0dB, the audio data passes this block by 0dB gain. The coefficient should be set
when EQ0 bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Note 79)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
,
B=
1 − 1 / tan (πfc1/fs)
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Transfer function
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 60. EQ0 Frequency Response
GN1
GN0
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 23. Gain select of gain block (x: Don’t care)
MS0963-E-00
2008/05
- 74 -
[AK4675]
(5) 5-band Notch
This block can be used as Equalizer or Notch Filter. 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) is ON/OFF
independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When Equalizer is OFF, the audio data passes this block by 0dB
gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the
coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0
bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the coefficient of EQ5. The EQx (x=1∼5)
coefficient should be set when EQx bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fo1 ~ fo5: Center frequency
fb1 ~ fb5: Band width where the gain is 3dB different from center frequency
K1 ~ K5 : Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 79)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
An = Kn x
tan (πfbn/fs)
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer function
H(z) = 1 + h1(z) + h2(z) + h3(z) + h4(z) + h5(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency should be set as below.
fon / fs < 0.497
Note 79. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
MS0963-E-00
2008/05
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[AK4675]
■ ALC Operation
The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. ALC circuit operates at playback path
for Playback mode and operates at recording path for Recording mode as shown in Table 22.
1.
ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 24), the IVL
and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 25).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout periods of both ALC limiter and recovery operation (Table 26). IVL and IVR values are attenuated 1 step
immediately (period: 1/fs) by ALC limiter operation when output level is over FS (Digital Full Scale). When output level
is not over FS, the IVL and IVR values are changed at the individual zero crossing points of Lch and Rch or at the zero
crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
24) or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0
0
1
0
1
ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 24. ALC Limiter Detection Level / Recovery Counter Reset Level
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC Limiter ATT Step
ALC Output
ALC Output
ALC Output
≥ LMTH
≥ FS
≥ FS + 6dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 25. ALC Limiter ATT Step (x: Don’t care)
ALC Output
≥ FS + 12dB
1
2
8
8
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 26. ALC Zero Crossing Timeout Period
MS0963-E-00
(default)
(default)
(default)
2008/05
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[AK4675]
2.
ALC Recovery Operation
ALC recovery operation waits for the WTM2-0 bits (Table 27) to be set after completing ALC limiter operation. If the
input signal does not exceed “ALC recovery waiting counter reset level” (Table 24) during the wait time, ALC recovery
operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 28) up to the set
reference level (Table 29) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 26). Then the
IVL and IVR are set to the same value for both channels. ALC recovery operation is executed at a period set by WTM2-0
bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, ALC recovery operation
waits until WTM2-0 period and the next recovery operation is executed. If ZTM1-0 is longer than WTM2-0 and no zero
crossing occurs, the ALC recovery operation is executed at a period set by ZTM1-0 bits.
For example, when the current IVL and IVR values are 30H and RGAIN1-0 bits are set to “01”, IVL and IVR values are
changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When
the IVL and IVR values exceed the reference level (REF7-0 bits), the IVL and IVR values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone
instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. The speed of
fast recovery operation is set by RFST1-0 bits (Table 30).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 27. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 28. ALC Recovery GAIN Step
MS0963-E-00
(default)
(default)
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[AK4675]
REF7-0 bits
GAIN (dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
−0.375
:
:
2H
−53.625
1H
−54.0
0H
MUTE
Table 29. Reference Level at ALC Recovery Operation
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 30. Fast Recovery Speed Setting (N/A: Not available)
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[AK4675]
3.
Example of ALC Operation
Table 31 and Table 32 show the examples of the ALC setting for mic recording and playback, respectively.
Register Name
Comment
LMTH1-0
ZELMN
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
* ZTM1-0 bits should be equal to or
shorter than WTM2-0 bits.
Recovery waiting period
Maximum gain at recovery operation
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of IVOL
Data
01
0
fs=8kHz
Operation
−4.1dBFS
Enable
Data
01
0
fs=44.1kHz
Operation
−4.1dBFS
Enable
01
32ms
11
23.2ms
001
E1H
32ms
+30dB
100
E1H
46.4ms
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
1 step
1 step
4 times
Enable
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 31. Example of the ALC setting (Recording Path)
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
001
32ms
100
46.4ms
A1H
+6dB
A1H
+6dB
Gain of IVOL
91H
0dB
91H
0dB
00
00
00
1
1 step
1 step
4 times
Enable
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Data
01
0
01
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 32. Example of the ALC setting (Playback Path)
MS0963-E-00
Data
01
0
11
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[AK4675]
The following registers should not be changed during ALC operation. These bits should be changed after ALC operation
is finished by ALC bit = “0”.
Each bit of LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN and RFST1-0.
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (IVL7-0)
(1) Addr=12H, Data=E1H
WR (IVR7-0)
(2) Addr=13H, Data=E1H
WR (REF7-0)
* The value of IVOL should be
(3) Addr=14H, Data=E1H
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0)
(4) Addr=16H, Data=05H
WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN)
(5) Addr=17H, Data=01H
WR (ALC = “1”)
(6) Addr=18H, Data=03H
ALC Operation
Note : WR : Write
Figure 61. Registers set-up sequence at ALC operation
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[AK4675]
■ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example, in the case that the change of the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 33). When IVOLC bit is “0”, IVL7-0 and IVR7-0 bits
control Lch and Rch volume values independently. When IVOLC bit is “1”, IVL7-0 bits controls both channels. The
IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or
IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of
the ADC initialization cycle after PMADL or PMADR bit is changed to “1”.
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
92H
91H
90H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+0.375
0.375dB
0.0
−0.375
:
−53.25
−53.625
−54
MUTE
Table 33. Input Digital Volume Setting
(default)
■ Side Tone Volume (SVOLA)
The AK4675 has the channel independent side tone volume (5 levels, 6dB step). The volume can be set by the
SVAL/R2-0 bits. The volume is included at mixing path from ALC to 5-band EQ. The output data of ALC is changed
from 0 to –24dB.
SVAL/R2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 34. Side Tone Volume A Code Table (N/A: Not available)
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[AK4675]
■ 5-Band Equalizer
The AK4675 has 5-Band Equalizer before DAC of Stereo CODEC.
The center frequencies and cut/boost amount are the followings.
• Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 80, Note 81, Note 82)
• Cut/Boost amount: –10.5dB ∼ +12dB, 1.5dB step
Note 80: These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the
sampling frequency.
Note 81: 100Hz is not center frequency but the frequency component lower than 100Hz is controlled.
Note 82: 10kHz is not center frequency but the frequency component higher than 10kHz is controlled.
EQ bit controls ON/OFF of this Equalizer and these Boost amount are set by EQA3-0, EQB3-0, EQC3-0, EQD3-0 and
EQE3-0 bits, respectively, as shown in Table 35.
EQA3-0:
EQB3-0:
EQC3-0:
EQD3-0:
EQE3-0:
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
EQx3-0
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
−7.5dB
EH
−9.0dB
FH
−10.5dB
Table 35. Boost amount of 5-Band Equalizer
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[AK4675]
■ Digital Output Volume
The AK4675 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the OVL7-0 and
OVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or
MUTE. When the OVOLC bit = “1”, the OVL7-0 bits control both Lch and Rch attenuation levels. When the OVOLC bit
= “0”, the OVL7-0 bits control Lch level and OVR7-0 bits control Rch level. This volume has a soft transition function.
The OVTM bit sets the transition time between set values of OVL/R7-0 bits as either 1061/fs or 256/fs (Table 37). When
OVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz)
from 00H (+12dB) to FFH (MUTE).
OVL/R7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 36. Digital Volume Code Table
(default)
Transition time between DVL/R7-0 bits = 00H and FFH
Setting
fs=8kHz
fs=44.1kHz
1061/fs
133ms
24ms
256/fs
32ms
6ms
Table 37. Transition Time Setting of Digital Output Volume
OVTM bit
0
1
MS0963-E-00
(default)
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[AK4675]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated
by −∞ (“0”) during the cycle set by the OVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to the value set by the OVL/R7-0 bits during the cycle set of the OVTM bit. If the
soft mute is cancelled within the cycle set by the OVTM bit after starting the operation, the attenuation is discontinued and
returned to the value set by the OVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping
the signal transmission (Figure 62).
S M U T E bit
O VTM bit
O VL/R 7-0 bits
O VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 62. Soft Mute Function
(1) The output signal is attenuated until −∞ (“0”) by the cycle set by the OVTM bit.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled within the cycle set by the OVTM bit, the attenuation is discounted and returned to the
value set by the OVL/R7-0 bits.
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[AK4675]
■ Digital Volume Control for Recording of Received Voice (DATT-B)
The AK4675 has a digital output volume control (DATT-B: 256 levels, 0.5dB step, Mute) for recording of received voice.
The volume can be set by the BVL7-0 bits. The volume is included in front of an SRC-B block. The input data of SRC-B
is changed from +12 to –115dB or MUTE. This volume has a soft transition function. The transition time between set
values of BVL7-0 bits is 256/fs2. It takes 256/fs2 (=32ms@fs2=8kHz) from 00H (+12dB) to FFH (MUTE).
BVL7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 38. Digital Volume B Code Table
(default)
■ Digital Volume Control for Received Voice (DATT-C)
The AK4675 has a digital output volume control (DATT-C: 256 levels, 0.5dB step, Mute) for received voice. The volume
can be set by the CVL7-0 bits. The volume is included in front of SDTOB output. The input data of SRC-C is changed
from +12 to –115dB or MUTE. This volume has a soft transition function. The transition time between set values of
CVL7-0 bits is 256/fs2. It takes 256/fs2 (=32ms@fs2=8kHz) from 00H (+12dB) to FFH (MUTE).
CVL7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 39. Digital Volume C Code Table
(default)
■ Side Tone Volume Control for B/T Phone Call (SVOLB)
The AK4675 has a side tone volume control (5 levels, 6dB step) for B/T phone call. The volume can be set by the SVL2-0
bits. The volume is included at mixing path from SRC-A to DATT-C. The output data of SRC-A is changed from 0 to
–24dB.
SVB2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 40. Side Tone Volume B Code Table (N/A: Not available)
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2008/05
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[AK4675]
■ Digital Volume Control for B/T MIC Input (BIVOL)
The AK4675 has a digital volume control (5 levels, 6dB step) for B/T mic input. The volume can be set by the BIV2-0
bits. The volume is included at SDTIB input. The input data is changed from 0 to –24dB.
BIV2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 41. B/T Mic Volume Code Table (N/A: Not available)
■ Path & Mixing Setting of Digital Block (Figure 56.)
PMADL and PMADR bits set both ADC power management and output data selection. In case of mono operation, the
same data is output to both channel slots.
PMADL
0
0
1
1
PMADR
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 42. ADC Mono/Stereo Select
(default)
PFSEL bit select the input data of programmable filter.
PFSEL
Programmable Filter Input
0
ADC Output (selected by Table 42.) (default)
1
SDTI Input (selected by Table 48)
Table 43. Programmable Filter Input Signal Select
When ADM bit is “1”, ALC output data is output to both channels of SDTO and SVOLA as (L+R)/2, respectively.
ADM
Lch
Rch
0
L
R
(default)
1
(L+R)/2
(L+R)/2
Table 44. ALC Output Mono Mixing
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[AK4675]
SDOL1-0 and SDOR1-0 bits set the data mixing for each channel of SDTO from the data selected by Table 44 and SRC-B
output data.
SDOL1
0
0
1
1
SDOL0
SDTO Lch
0
Lch Signal selected by Table 44
1
SRC-B
0
(Lch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 45. SDTO Lch Output Mixing (N/A: Not available)
SDOR1
0
0
1
1
SDOR0
SDTO Rch
0
Rch Signal selected by Table 44
1
SRC-B
0
(Rch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 46. SDTO Rch Output Mixing (N/A: Not available)
(default)
(default)
When SDOD bit is “1”, SDTO output data can be disabled (fixed to “L”). Input data of SVOLA is not disabled.
SDOD
0
1
SDTO
Enable (Output) (default)
Disable (“L”)
Table 47. SDTO Disable
SDIM1-0 bits select stereo or mono of SDTI input data. In case of mono mode, the same data is input to both channels.
SDIM1
SDIM0
Lch
Rch
0
0
L
R
(default)
0
1
L
L
1
0
R
R
1
1
N/A
Table 48. SDTI Stereo/Mono Select (N/A: Not available)
PFMXL1-0 and PFMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table 48
and SVOLA output data.
PFMXL1
0
0
1
1
PFMXL0
5-band EQ Lch Input
0
Lch Signal selected by Table 48
1
SVOLA Lch
0
(Lch Signal selected by Table 48) + (SVOLA Lch)
1
N/A
Table 49. 5-band EQ Lch Input Mixing 1 (N/A: Not available)
PFMXR1
0
0
1
1
PFMXR0
5-band EQ Rch Input
0
Rch Signal selected by Table 48
1
SVOLA Rch
0
(Rch Signal selected by Table 48) + (SVOLA Rch)
1
N/A
Table 50. 5-band EQ Rch Input Mixing 1 (N/A: Not available)
MS0963-E-00
(default)
(default)
2008/05
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[AK4675]
SRMXL1-0 and SRMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table
49/Table 50 and SVOLA output data.
SRMXL1 SRMXL0
5-band EQ Lch Input
0
0
Signal selected by Table 49
(default)
0
1
SRC-B
1
0
(Signal selected by Table 49) + (SRC-B)
1
1
N/A
Table 51. 5-band EQ Lch Input Mixing 2 (N/A: Not available)
SRMXR1 SRMXR0
5-band EQ Rch Input
0
0
Signal selected by Table 50
(default)
0
1
SRC-B
1
0
(Signal selected by Table 50) + (SRC-B)
1
1
N/A
Table 52. 5-band EQ Rch Input Mixing 2 (N/A: Not available)
DAM and MIXD bits set the data mixing for DAC input.
DAM
0
1
1
MIXD
Lch
Rch
x
L
R
(default)
0
L+R
L+R
1
(L+R)/2
(L+R)/2
Table 53. DAC Mono Mixing (x: Don’t care)
SRA1-0 and MIXD bits set the data mixing for SRC-A input.
SRA1
SRA0
MIXD
SRC-A
0
0
x
L
(default)
0
1
x
R
1
0
0
L+R
1
0
1
(L+R)/2
1
1
x
N/A
Table 54. SRC-A Input Mixing (x: Don’t care, N/A: Not available)
SDOA bit selects the output data of SDTOA.
SDOA
0
1
SDTOA
SRC-A
(default)
SDTIB
Table 55. SDTOA Output Select
When SDOAD bit is “1”, SDTOA output data can be disabled (fixed to “L”). Input data of SVOLB is not disabled.
SDOAD
SDTOA
0
Enable (Output) (default)
1
Disable (“L”)
Table 56. SDTOA Disable
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[AK4675]
SBMX1-0 bits set the data mixing from SDTIA input and SVOLB output. The mixed data is output to SDTOB via
DATT-C.
SBMX1
0
0
1
1
SBMX0
DATT-C Input
0
SDTIA
(default)
1
SVOLB
0
(SDTIA) + (SVOLB)
1
N/A
Table 57. SDTOB Mixing (N/A: Not available)
When SDOBD bit is “1”, SDTOB output data can be disabled (fixed to “L”).
SDOBD
SDTOB
0
Enable (Output) (default)
1
Disable (“L”)
Table 58. SDTOB Disable
BVMX1-0 bits set the data mixing for SRC-B from SDTIA input (DATT-B output) and SDTIB input (BIVOL output).
BVMX1
BVMX0
SRC-B Input
0
0
SDTIA
(default)
0
1
SDTIB
1
0
(SDTIA) + (SDTIB)
1
1
N/A
Table 59. SRC-B Input Mixing (N/A: Not available)
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[AK4675]
■ Analog Mixing: Single-ended Input (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins)
AK4675 supports analog mixing function from each line input to each line output (Figure 63).
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”, the input resistance of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins becomes 25kΩ (typ) at
MGNL/R0 bits = “0” and 20kΩ (typ) at MGNL/R0 bits = “1”, respectively.
L1G1-0, L2G1-0, L3G1-0, L4G1-0 and LPG1-0 bits adjust the gain for each path (Table 60, Table 61, Table 62, Table 63,
Table 64).
AK4675
INL4-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR4-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
Figure 63, 64, 66, 67
LOUT1 pin
Figure 68, 69
ROUT1 pin
LOUT2S pin
ROUT2S pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINL1 bit
PMAINR1 bit
RIN4/IN4− pin
Figure 72, 73, 75, 76
LOUT3 pin
ROUT3 pin
Figure 63. Analog Mixing Circuit
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[AK4675]
L1G1 bit
L1G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 60. LIN1/RIN1 (or IN1+/−) Mixing Gain (typ) (N/A: Not available)
L2G1 bit
L2G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 61. LIN2/RIN2 (or IN2+/−) Mixing Gain (typ) (N/A: Not available)
L3G1 bit
L3G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 62. LIN3/RIN3 (or IN3+/−) Mixing Gain (typ) (N/A: Not available)
L4G1 bit
L4G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 63. LIN4/RIN4 (or IN4+/−) Mixing Gain (typ) (N/A: Not available)
LPG1 bit
LPG0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 64. MIC-Amp Mixing Gain (typ) (N/A: Not available)
■ Analog Mixing: Full-differential Input (IN1+/IN1−/IN2+/IN2−/IN3+/IN3−/IN4+/IN4− pins)
When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “1”, LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 pins
become IN1+/−, IN2+/−, IN3+/− and IN4+/− pins, respectively, and analog mixing is available.
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”, the input resistance of IN1+/−, IN2+/−, IN3+/− and IN4+/− pins becomes 25kΩ (typ) at MGNL/R0 bits = “0”
and 20kΩ (typ) at MGNL/R0 bits = “1”, respectively.
L1G1-0, L2G1-0, L3G1-0, L4G1-0 and LPG1-0 bits adjust the gain for each path (Table 60, Table 61, Table 62, Table 63,
Table 64).
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■ Stereo Line Output (LOUT1/ROUT1 pins)
When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT1/ROUT1 pins which is
single-ended. When DACL and DACR bits are “0”, output signal is muted and LOUT1/ROUT1 pins output VCOM
voltage. The load impedance is 10kΩ (min.). When the PMLO1=PMRO1=LOPS1 bits = “0”, LOUT1/ROUT1 enters
power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS1 bit is “1”, LOUT1/ROUT1
enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO1 and PMRO1 bits at LOPS1
bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 64. Rise/Fall
time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO1=PMRO1 bits = “1” and LOPS1 bit = “0”,
LOUT1/ROUT1 is in normal operation.
L1VL2-0 bits control the volume of LOUT1/ROUT1.
When LOM bit = “1”, DAC output signal is output to LOUT1 and ROUT1 pins as (L+R) mono signal.
When LOOPM bit = “1”, the MIC-Amp signal is output to LOUT1 and ROUT1 pins as (L+R) mono signal.
LOPS1
0
1
LOPS1
0
1
PMLO1
Mode
LOUT1 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 65. Stereo Line Output Mode Select (LOUT1)
PMRO1
Mode
ROUT1 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 66. Stereo Line Output Mode Select (ROUT1)
(default)
(default)
L1VL2-0
Attenuation
6H
+6dB
5H
0dB
(default)
4H
−6dB
3H
−12dB
2H
−18dB
1H
−24dB
0H
MUTE
Table 67. Stereo Line Output Volume Setting
LOUT1
ROUT1
1μF
220Ω
20kΩ
Figure 64. External Circuit for Stereo Line Output (in case of using Pop Noise Reduction Circuit)
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<Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2 )
(5 )
P M L O 1 b it
P M R O 1 b it
(1 )
(3 )
(4 )
(6 )
L O P S 1 b it
L O U T 1 p in
R O U T 1 p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 65. Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS1 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO1=PMRO1 bits = “1”. Stereo line output exits the power-down mode.
LOUT1 and ROUT1 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS1 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO1=PMRO1 bits = “0”. Stereo line output enters power-down mode.
LOUT1 and ROUT1 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins fall down. Stereo line output exits the power-save mode.
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<Analog Mixing Circuit for LOUT1/ROUT1>
DACL, DACR, LOM, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL, LOOPR and LOOPM
bits control each path switch.
LINL1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINL2 bit
LINL3 bit
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
DATT
Stereo DAC Lch
0dB
DACR bit x LOM bit
RINR1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINR2 bit
RINR3 bit
RINR4 bit
M
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 66. LOUT1/ROUT1 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
LINL3 bit
+6/0/−6dB
IN3+/− pins
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
DATT
Stereo DAC Lch
0dB
DACR bit x LOM bit
RINL1 bit
RINR2 bit
+6/0/−6dB
IN2+/− pins
RINR3 bit
RINR4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 67. LOUT1/ROUT1 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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■ Receiver-Amp (RCP/RCN pins)
When RCV bit = “1”, LOUT1/ROUT1 pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the RCP/RCN pins which is BTL as (L+R) signal. The
load impedance is 32Ω (min). When the PMLO1 = PMRO1 bits = “0”, the mono receiver output enters power-down
mode and the output is Hi-Z. When the PMLO1 = PMRO1 bits = “1” and LOPS1 bit = “1”, mono receiver output enters
power-save mode. Pop noise at power-up/down can be reduced by changing PMLO1 and PMRO1 bits at LOPS1 bit =
“0”. When PMLO1 = PMRO1 bits = “1” and LOPS1 bit = “0”, mono receiver output enters in normal operation.
L1VL3-0 bits control the volume of mono receiver output.
L1VL2-0
Attenuation
6H
+12dB
5H
+6dB
(default)
4H
0dB
3H
−6dB
2H
−12dB
1H
−18dB
0H
MUTE
Table 68. Mono Receiver Output Volume Setting
PMLO1/RO1
0
1
LOPS1
x
1
0
Mode
RCP
RCN
Power-down
Hi-Z
Hi-Z
Power-save
Hi-Z
VCOM
Normal Operation
Normal Operation Normal Operation
Table 69. Receiver-Amp Mode Setting (x: Don’t care)
(default)
PMLO1 bit
PMRO1 bit
LOPS1 bit
RCP pin
RCN pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
>1ms
>0
Hi-Z
Figure 68. Power-up/Power-down Timing for Receiver-Amp
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<Analog Mixing Circuit for Receiver Output>
DACL, DACR, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL and LOOPR bits control each
path switch.
When MDIF1/2/3/4 bits = “1”, RINR1/2/3/4 bits should be “0”.
LINL1 bit
LIN1 pin
+6/0/−6dB
LINL2 bit
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LINL3 bit
LINL4 bit
LIN4 pin
+6/0/−6dB
LOOPL bit
+6/0/−6dB
MIC-Amp Lch
RINR1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
M
RINR2 bit
I
X
RCP/RCN pins
L1VL2-0 bits
RINR3 bit
RINR4 bit
RIN4 pin
+6/0/−6dB
LOOPR bit
+6/0/−6dB
MIC-Amp Rch
DATT
Stereo DAC Lch
DACL bit
0dB
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 69. Receiver Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
+6/0/−6dB
IN2+/− pins
LINL3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINL4 bit
LOOPL bit
RCP/RCN pins
+6/0/−6dB
MIC-Amp Lch
L1VL2-0 bits
LOOPR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACR bit
Figure 70. Receiver Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
■ Stereo Line Output 2 (LOUT2S/ROUT2S pins)
Power supply voltage for the LOUT2S/ROUT2S is supplied from the AVDD pin and centered on the 0.5 x AVDD (typ)
voltage. The load resistance is 25kΩ (min).
When LOM2 bit = “1”, DAC output signal is output to LOUT2S and ROUT2S pins as (L+R) mono signal.
When LOOPM2 bit = “1”, the MIC-Amp signal is output to LOUT2S and ROUT2S pins as (L+R) mono signal.
When PMLO2S and PMRO2S bits are “0”, the LOUT2S/ROUT2S is powered-down, and the outputs (LOUT2S and
ROUT2S pins) go to “L” (VSS1).
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<Analog Mixing Circuit for LOUT2S/ROUT2S>
DACHL, DACHR, LOM2, LINH1, RINH1, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, LOOPHL, LOOPHR and
LOOPM2 bits control each path switch.
LINH1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINH2 bit
LINH3 bit
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
LOUT2S pin
X
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
Stereo DAC Lch
DATT
0dB
DACHR bit x LOM2 bit
RINH1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RINH2 bit
RINH3 bit
RINH4 bit
RIN4 pin
M
+6/0/−6dB
LOOPHL bit x LOOPM2 bit
I
ROUT2S pin
X
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
Stereo DAC Rch
DATT
0dB
Figure 71. LOUT2S/ROUT2S Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINH1 bit
+6/0/−6dB
IN1+/− pins
LINH2 bit
LINH3 bit
+6/0/−6dB
IN3+/− pins
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
LOUT2S pin
X
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
Stereo DAC Lch
DATT
0dB
DACHR bit x LOM2 bit
RINH1 bit
RINH2 bit
+6/0/−6dB
IN2+/− pins
RINH3 bit
RINH4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPHL bit x LOOPM2 bit
I
ROUT2S pin
X
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
Stereo DAC Rch
DATT
0dB
Figure 72. LOUT2S/ROUT2S Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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■ Stereo Line Output 3 (LOUT3/ROUT3 pins)
When DACSL and DACSR bits are “1”, Lch/Rch signal of DAC is output from the LOUT3/ROUT3 pins which is
single-ended. When DACSL and DACSR bits are “0”, output signal is muted and LOUT3/ROUT3 pins output VCOM
voltage. The load impedance is 10kΩ (min.). When the PMLO3=PMRO3=LOPS3 bits = “0”, LOUT3/ROUT3 enters
power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS3 bit is “1”, LOUT3/ROUT3
enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO3 and PMRO3 bits at LOPS3
bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 64. Rise/Fall
time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO3=PMRO3 bits = “1” and LOPS3 bit = “0”,
LOUT3/ROUT3 is in normal operation.
L3VL3-0 bits control the volume of LOUT3/ROUT3.
When LOM3 bit = “1”, DAC output signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
When LOOPM3 bit = “1”, the MIC-Amp signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
LOPS3
0
1
LOPS3
0
1
PMLO3
Mode
LOUT3 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 70. Stereo Line Output Mode Select (LOUT3)
PMRO3
Mode
ROUT3 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 71. Stereo Line Output Mode Select (ROUT3)
(default)
(default)
L3VL1
L3VL0
Attenuation
1
1
+3dB
1
0
0dB
(default)
0
1
−3dB
0
0
−6dB
Table 72. Stereo Line Output Volume Setting
LOUT3
ROUT3
1μF
220Ω
20kΩ
Figure 73. External Circuit for Stereo Line Output (when using Pop Noise Reduction Circuit)
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<Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O U T 3 , R O U T 3 p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 74. Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO3=PMRO3 bits = “1”. Stereo line output exits the power-down mode.
LOUT3 and ROUT3 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS3 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO3=PMRO3 bits = “0”. Stereo line output enters power-down mode.
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins fall down. Stereo line output exits the power-save mode.
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<Analog Mixing Circuit for LOUT3/ROUT3>
DACSL, DACSR, LOM3, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL, LOOPSR and
LOM3 bits control each path switch. The summing gain for each path is 0dB (typ).
LINS1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINS2 bit
LINS3 bit
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINS2 bit
RINS3 bit
RINS4 bit
M
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 75. LOUT3/ROUT3 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINS1 bit
+6/0/−6dB
IN1+/− pins
LINS2 bit
LINS3 bit
+6/0/−6dB
IN3+/− pins
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RINS2 bit
+6/0/−6dB
IN2+/− pins
RINS3 bit
RINS4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 76. LOUT3/ROUT3 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT3/ROUT3 pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)
signal. The load impedance is 10kΩ (min) for the LOP and LON pins, respectively. When the PMLO3 = PMRO3 bits =
“0”, the mono line output enters power-down mode and the output is pulled-down to VSS1. When the PMLO3 = PMRO3
bits = “1” and LOPS3 bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced
by changing PMLO3 and PMRO3 bits at LOPS3 bit = “0”. When PMLO3 = PMRO3 bits = “1” and LOPS3 bit = “0”,
mono line output enters in normal operation. L3VL1-0 bits set the volume of mono line output.
L3VL1-0
Attenuation
3H
+9dB
2H
+6dB
(default)
1H
+3dB
0H
0dB
Table 73. Mono Line Output Gain Setting
LOPS3
PMLO3/RO3
Mode
LOP/LON pins
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 74. Mono Line Output Mode Setting (x: Don’t care)
0
1
(default)
<Full-differential Mono Line Output Control Sequence (in case of using Pop Noise Reduction
Circuit)>
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O P , L O N p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 77. Mono Line Output 3 Control Sequence (when using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Mono line output enters the power-save mode.
(2) Set PMLO3 = PMRO3 bits = “1”. Mono line output exits the power-down mode.
The LOP and LON pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOP and LON pins rise up. Mono line output exits the power-save mode.
Mono line output is enabled.
(4) Set LOPS3 bit = “1”. Mono line output enters power-save mode.
(5) Set PMLO3 = PMRO3 bits = “0”. Mono line output enters power-down mode.
The LOP and LON pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOP and LON pins fall down. Mono line output exits the power-save mode.
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<Analog Mixing Circuit for Mono Line Output>
DACSL, DACSR, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL and LOOPSR bits control
each path switch. The summing gain for each path is 0dB (typ).
When MDIF1/2/3/4 bits = “1”, RINS1/2/3/4 bits should be “0”.
LINS1 bit
LIN1 pin
+6/0/−6dB
LINS2 bit
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LINS3 bit
LINS4 bit
LIN4 pin
+6/0/−6dB
LOOPSL bit
+6/0/−6dB
MIC-Amp Lch
RINS1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
M
RINS2 bit
I
X
LOP/LON pins
L3VL1-0 bits
RINS3 bit
RIN3 pin
+6/0/−6dB
RINS4 bit
RIN4 pin
+6/0/−6dB
LOOPSR bit
+6/0/−6dB
MIC-Amp Rch
DATT
Stereo DAC Lch
DACSL bit
0dB
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 78. Mono Line Output Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINS1 bit
IN1+/− pins
+6/0/−6dB
LINS2 bit
IN2+/− pins
+6/0/−6dB
LINS3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINS4 bit
LOOPSL bit
LOP/LON pins
+6/0/−6dB
MIC-Amp Lch
L3VL1-0 bits
LOOPSR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACSL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACSR bit
Figure 79. Mono Line Output Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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[AK4675]
■ Headphone Volume (LIN1A/RIN1A pins)
The AK4675 has the mixing circuits for headphone amplifier. The each mixing circuit can be controlled independently.
When all input paths are OFF, the mixing circuit outputs VCOMA voltage. The volume of each input pin can be
controlled independently. The input volume range is from +10 dB to –20dB by 2dB step. When the input volume is
changed, pop noise may occur. The input volume has power management mode that is common to the left and right
channels. The power-up/down of input volume can be controlled by PMV1 bit. The power-up time of the input volume is
16.4ms (typ.) and 26.3ms(max) at OSCN bit = “0”. when OSCN bit = “1”, power-up time depends on both the MSEL bit
setting and the MCKIA frequency (Table 75). During power-up time, the input volume block outputs VCOMA voltage
regardless of the input signal. AC coupling capacitor of 0.22μF or less should be connected at the LIN1A/RIN1A pins to
reduce pop noise at the power-up of the input volume block.
MSEL bit
0
MCKIA Freq
Power-Up Time
2.048MHz
16ms (32768/MCKIA)
2.8224MHz
17.1ms (49152/MCKIA)
1
3.072MHz
16ms (49152/MCKIA)
Table 75. Input Volume Power-Up Time (OSCN bit = “1”)
L1V3-0 bits
GAIN (dB)
Step
R1V3-0 bits
FH
+10
EH
+8
:
CH
+4
BH
+2
AH
0
2dB
9H
−2
8H
−4
:
:
2H
−16
1H
−18
0H
−20
Table 76. Input Volume Setting
HPLL1bit
LIN1A
VOL(L1V3-0 bits)
HPLR1 bit
(default)
PREL
Mixing
&
To Lch Headphone-Amp
Selector
HPRL1 bit
Mixing
HPRR1 bit
RIN1A
VOL(R1V3-0 bits)
&
To Rch Headphone-Amp
Selector
Figure 80. Input Selector & Volume
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[AK4675]
■ Headphone-Amp (HPL/HPR pins)
Power supply voltage for headphone amplifiers is applied from PVDDA and PVEE pins. The PVEE pin outputs the
negative voltage generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and
centered on 0V (VSS3A). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is
16Ω. When the input signal level is 0.7Vrms, the output voltage is 0.69Vrms (= 30mW @ 16Ω) at HPGA4-0 bits = 0dB
and HPG bit = 0dB. HPGA3-0 and HPG bits control the output level of headphone-amp. HPGA4-0 bits can control from
+12dB to –50dB by 2dB step and HPG bit can control 0dB or +6dB. The volume is common to L/R channels. When the
volume is changed, pop noise may occur.
HPGA4-0 bits
GAIN (dB)
Step
1FH
+12
1EH
+10
:
1AH
+2
19H
0
18H
−2
2dB
17H
−4
16H
−6
:
:
2H
−46
1H
−48
0H
−50
Table 77. Headphone-Amp Volume Setting
Input
(default)
Input Volume
Mixing & Selector
HP Volume
HP-Amp
(-1.94dB @ Vol =0dB)
(0dB)
(HPGA=0dB)
(+1.94dB)
Figure 81. Headphone-Amp Path Level Diagram
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[AK4675]
The headphone output is enabled when HPMTN bit is “1” and muted when HPMTN bit is “0”. PTS1-0 bits set the mute
ON/OFF time when MOFF1 bit is “0”. When MOFF1 bit is “1”, the ON/OFF is switched immediately.
When PMHPL and PMHPR bits are “0”, the headphone-amps are powered-down completely. At that time, the HPL and
HPR pins go to VSS3 voltage via the internal pulled-down resistor. The pulled-down resistor is 20Ω (typ) at HPZ bit =
“0”, 25kΩ(typ) at HPZ bit = “1”. The power-up/down time is 16.4ms (typ.) and 26.3ms (max.)when MOFF0 bit is “0”.
When MOFF1 bit is “1”, the power up/down is switched immediately.
PMCP/PMVCM
x
x
1
1
PMHPL/R HPMTN
HPZ
Mode
HPL/R pins
0
x
0
Power-down & Mute Pull-down by 20Ω (typ) (default)
0
x
1
Power-down
Pull-down by 25kΩ (typ)
1
0
0
Mute
VSS3A
1
1
0
Normal Operation
Normal Operation
Table 78. Headphone Amplifier Mode Setting (x: Don’t’ care)
<Wired OR with External Headphone-Amp>
In case of OSCN bit = “0”, when PMVCMA=PMCP=PMOSC bits are “1” (charge pump circuit is powered-up), the
AK4675 HP-Amp can be connected to the external single supply HP-Amp by “wired OR”. In case of OSCN bit = “1”,
when PMVCMA=PMCP=HPZ bits are “1” (charge pump circuit is powered-up), the AK4675 HP-Amp can be connected
to the external single supply HP-Amp by “wired OR”. The external HP-Amp can output the signal up to ±PVDDA [Vpp]
after the charge pump circuit is powered-up.
HPL pin
AK4675
Headphone
HPR pin
Another
HP-Amp
Figure 82. Wired OR with External HP-Amp
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[AK4675]
■ Charge Pump Circuit
The charge pump operates by the output of a regulator which uses PVDDA voltage. The negative power supply (PVEE)
for headphone amplifiers is generated from internal charge pump circuit. The internal charge pump circuit generates
negative voltage from PVDDA voltage. The generated voltage (PVEE) is used to headphone amplifiers. When PMCP bit
is set to “1”, the charge pump circuit is powered-up. PMVCMA and PMOSC bits must be set to “1”.
PMOSC and PMVCM bits should be set to “1” when OSCN bit is “0”. PMVCM bit should be set to “1” and PMOSC bit
set to “0” when OSCN bit is “1”. The power-up time of charge pump circuit is typically 6.2ms and maximum 10ms at
OSCN bit = “0”. when OSCN bit = “1”, the power-up time is shown in Table 79. When PMHPL or PMHPR bit is set to
“1”, the Headphone-Amp is powered-up after the charge pump circuit is powered-up. Figure 87 shows the power-up
sequence.
MSEL bit
0
MCKIA Freq
Power-Up Time
2.048MHz
6m (12288/MCKIA)
2.8224MHz
6.5ms (18432/MCKIA)
1
3.072MHz
6ms (18432/MCKIA)
Table 79. Charge Pump Circuit Power-Up Time (OSCN bit = “1”)
■ Transition Time
PUT1-0 bits set the power-up/down time of headphone-amp and PTS1-0 bits set the mute ON/OFF time of
headphone-amp. These operations are soft transition.
MOFF bit set the Enable/Disable for the soft transition. The soft transition is disabled while these bits are “1”, and
ON/OFF is switched immediately.
As shown in Table 80, if the soft transition is enabled, the register value of same address must be changed by an interval
more than transition time. The write operation is ignored if the same values are written as the previous write operation.
PTS1-0 bits
PTS1
PTS0
0
0
1
1
0
1
0
1
Address
Register Name
Enable / Disable
0DH
HPMTN bit
MOFF bit
Table 80. Registers with Transition Time
MUTE ON/OFF Time
OSCN bit = “0”
OSCN bit = “1”
typ.
max
MSEL bit= “0”
MSEL bit = “1”
16.4ms
26.3ms
32768/MCKIA
49152/MCKIA
32.8ms
51.5ms
65536/MCKIA
98304/MCKIA
65.6ms
105.0ms
131072/MCKIA 196608/MCKIA
131.2ms
210.0ms
262144/MCKIA 393216/MCKIA
Table 81. Headphone-Amp Mute ON/OFF Transition Time
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(default)
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[AK4675]
■ Speaker-ALC Operation
The ALC (Automatic Level Control) operation of speaker-amp output is executed by ALCA block when ALCA bit = “1”.
When ALCA bit is “0”, the speaker volume depends on the setting value of SPGA5-0 bits.
(1) ALC Limiter Operation
During ALCA limiter operation, when either Lch or Rch exceeds the ALCA limiter detection level (LMTHA bit), the
SPGA value (same value for Lch and Rch) is attenuated automatically by the ALCA limiter ATT step (LMATA1-0 bits).
When ZELMNA bit is set to “0” (zero crossing detection is enabled), the SPGA value is changed by ALCA limiter
operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTMA1-0 bits set the zero
crossing timeout period of both ALCA limiter and recovery operation.
When ZELMNA bit = “1” (zero crossing detection is disabled), SPGA value is immediately changed by ALCA limiter
operation. The changing period is typ. 125μs and max. 200μs at OSCN bit = “0”, 256/MCKIA (=125μs
@MCKIA=2.048MHz at OSCN bit = “1” & MSEL bit = “0”, 384/MCKIA (= 125μs @MCKI=3.072MHz) at OSCN bit
= “1” & MSEL bit = “1”. Attenuation step is fixed to 1 step regardless of the setting of LMATA1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALCA limiter detection level or
less. After completing the attenuation operation, unless ALCA bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTHA bit.
LMTHA
ALCA Limiter Detection
ALCA Recovery Waiting Counter Reset Level
Level
0
(default)
ALCA Output ≥ −7.5dBV
−7.5dBV > ALCA Output ≥ −9.5dBV
1
ALCA Output ≥ −11.5dBV
−11.5dBV > ALCA Output ≥ −13.5dBV
Note: ALCA limiter detection level and ALCA recovery waiting counter reset level do not
depend on operation voltage.
Table 82. ALCA Limiter Detection Level / Recovery Counter Reset Level (2.0Vpp = −3dBV)
ZELMNA
0
1
ZTMA1
ZTMA0
0
0
1
1
0
1
0
1
LMATA1 LMATA0
ALCA Limiter ATT Step
0
0
1 step
0.5dB
0
1
2 step
1.0dB
1
0
4 step
2.0dB
1
1
8 step
4.0dB
x
x
1step
0.5dB
Table 83. ALCA Limiter ATT Step (x: Don’t’ care)
(default)
Zero Crossing Timeout
OSCN bit = “0”
OSCN bit = “1”
typ.
max
MSEL bit= “0”
MSEL bit = “1”
16.4ms
26.3ms
32768/MCKIA
49152/MCKIA
32.8ms
51.5ms
65536/MCKIA
98304/MCKIA
65.6ms
105.0ms
131072/MCKIA 196608/MCKIA
131.2ms
210.0ms
262144/MCKIA 393216/MCKIA
Table 84. ALCA Zero Crossing Timeout Period
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(default)
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[AK4675]
(2) ALCA Recovery Operation
ALCA recovery operation waits for the WTMA2-0 bits to be set after completing ALCA limiter operation. If the input
signal does not exceed “ALCA recovery waiting counter reset level” during the wait time, ALCA recovery operation is
executed. The SPGA value is automatically incremented by RGAINA1-0 bits up to the set reference level (REFA5-0 bits)
with zero crossing detection which timeout period is set by ZTMA1-0 bits. Then the SPGA is set to the same value for
both channels. ALCA recovery operation is executed at a period set by WTMA2-0 bits. When zero cross is detected at
both channels during the wait period set by WTMA2-0 bits, ALCA recovery operation waits until WTMA2-0 period and
the next recovery operation is executed. The setting period of WTMA2-0 bits should be same as ZTMA1-0 bits or longer
period.
When RGAINA1-0 bits are set to “10”, ALCA recovery operation is not executed though ALCA limiter
operation is executed.
During the ALCA recovery operation, when the ALCA output level exceeds ALCA limiter detection level (LMTHA bit),
the ALCA limiter operation is done immediately.
When
“ALCA recovery waiting counter reset level ≤ ALCA Output Signal < ALCA limiter detection level (LMTHA1-0)”
during the ALCA recovery operation, the waiting timer of ALCA recovery operation is reset. When
“ALCA recovery waiting counter reset level > ALCA Output Signal”,
the waiting timer of ALCA recovery operation starts.
The ALCA operation corresponds to the impulse noise. When the impulse noise is input, the ALCA recovery operation
becomes faster than a normal recovery operation.
WTMA2
WTMA1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Recovery Waiting Timer
WTMA0
OSCN bit = “0”
OSCN bit = “1”
typ.
max
MSEL bit = “0”
MSEL bit = “1”
0
16.4ms
26.3ms
32768/MCKIA
49152/MCKIA
1
32.8ms
51.5ms
65536/MCKIA
98304/MCKIA
0
65.6ms
105.0ms
131072/MCKIA
196608/MCKIA
1
131.2ms
210.0ms
262144/MCKIA
393216/MCKIA
0
262.4ms
419.9ms
524288/MCKIA
786432/MCKIA
1
524.8ms
839.7ms
1048576/MCKIA
1572864/MCKI
A
0
1049.6ms 1679.4ms 2097152/MCKIA
3145728/MCKI
A
1
2099.2ms 3358.8ms 4194304/MCKIA
6291456/MCKI
A
Table 85. ALCA Recovery Waiting Timer Period
RGAINA1
0
0
1
1
RGAINA0
GAIN STEP
0
1 step
0.5dB
1
2 step
1.0dB
0
0 step
0dB
1
Reserved
Table 86. ALCA Recovery GAIN Step
MS0963-E-00
(default)
(default)
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[AK4675]
REFA5-0
GAIN (dB)
Step
3FH
+19.5
3EH
+19.0
3DH
+18.5
3CH
+18.0
(default)
:
:
19H
+0.5
0.5dB
18H
0.0
17H
−0.5
:
:
02H
−11.0
01H
−11.5
00H
−12.0
Table 87. Reference Level at ALCA Recovery Operation
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[AK4675]
(3) Example of ALCA Operation
Table 88 shows the example of the ALCA setting. The ALCA starts from the value of SPGA5-0 bits.
Register Name
LMTHA
ZELMNA
WTMA2-0
REFA5-0
LMATA1-0
RGAINA1-0
ZTMA1-0
ALCA
Comment
Data
Parameter
Limiter detection Level
0
−7.5dBV
Limiter Zero crossing Enable
0
Limiter Zero Crossing Enable
Recovery waiting period
101
Typ. 524.8ms (@ OSCN bit = “0”)
Maximum gain at recovery operation
3CH
+18dB
Limiter ATT Step
00
0.5dB
Recovery GAIN Step
00
0.5dB
Zero-crossing Timeout
01
Typ. 32.8ms (@ OSCN bit = “0”)
ALCA Enable bit
1
Enable
Table 88. Example of the ALCA setting
The following registers must not be changed during ALCA operation. These bits should be changed after ALCA
operation is finished by ALCA bit = “0”.
- LMTHA, LMATA1-0, WTMA2-0, RGAINA1-0, REFA5-0, ZTMA1-0, ZELMNA bits
Example:
Limiter: Zero Crossing Enable
Recovery Cycle = typ. 524.8ms (@ OSCN bit = “0”)
Limiter and Recovery Step = 1
Maximum Gain = +18dB
Limiter Detection Level = −7.5dBV
ALCA=OFF
ALCA bit = “1”
WR (SPGA5-0)
(1) Addr=0EH, Data=3CH
WR (REFA5-0)
(2) Addr=0FH, Data=3CH
WR (ZTMA1-0, WTMA2-0)
(3) Addr=10H, Data=0DH
WR (ZELMNA, LMATA1-0, RGAINA1-0, LMTHA, ALCA=”1”)
(4) Addr =11H, Data=40H
ALCA Operation
Note : WR : Write
Figure 83. Registers set-up sequence at ALCA operation
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[AK4675]
■ Speaker Volume (SPGA: Manual Mode)
The speaker volume becomes manual mode when ALCA bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for ALCA operation (ZTMA1-0, LMTHA and etc).
When the registers for ALCA operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
When SPGA is used as a manual volume.
SPGA5-0 bits set the gain of the volume control. The SPGA value is changed at zero crossing or timeout. Zero crossing
timeout period is set by ZTMA1-0 bits. In case of OSCN bit = “0”, the write operation to SPGA5-0 bits is prohibited
during 1.6ms after PMSPL or PMSPR bit is set to “1”. In case of OSCN bit = “1”, the write operation to SPGA5-0 bits is
prohibited during the power-up time of the speaker volume block (Table 91) after PMSPL or PMSPR bit is set to “1”. The
speaker volume is powered-up as the default value (0dB) regardless of the setting of SPKG5-0 bits.
SPGA5-0
3FH
3EH
3DH
3CH
:
19H
18H
17H
:
02H
01H
00H
GAIN (dB)
Step
+19.5
+19.0
+18.5
+18.0
:
+0.5
0.5dB
0.0
−0.5
:
−11.0
−11.5
−12.0
Table 89. Speaker-Amp Volume Setting
(default)
When writing to the SPGA5-0 bits continuously, the control register should be written in an interval more than zero
crossing timeout.
ALCA bit
ALCA Status
Disable
Enable
SPGA5-0 bits
Internal SPGA
Disable
3CH(+18dB)
3CH(+18dB)
3CH(+18dB) --> 19H(+0.5dB)
(1)
3CH(+18dB)
(2)
Figure 84. SPGA value during ALCA operation
(1) ALCA operation starts from the SPGA value when ALCA bit is changed to “1”.
(2) Writing to SPGA registers is ignored during ALCA operation. After ALCA is disabled, the SPGA changes to the last
written data by twice period of zero crossing or timeout. When ALCA is enabled again, ALCA bit should be set to
“1” in an interval more than zero crossing timeout period after ALCA bit = “0”.
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[AK4675]
■ Class-D Speaker-Amp
The output signal from ALC block is converted by PWM and is outputted from the SPP/SPN pins by BLT. The signal of
ALC block is input from the SPIN pin. A 0.1uF capacitor should be connected between the LOUT3 (ROUT3) pin and the
SPIN pin in order to cancel DC offset of Line Out circuit.
LOUT3 (ROUT3)
SPIN pin
SPGA5-0bits
0.1μF
typ.26kΩ
-
Line Out
+
ALCA
AK4675
Figure 85. Example of normal connection for Speaker (fc = 66Hz @ -3dB)
When the input signal level is 0.56Vrms, the speaker-amp outputs 0.6W. The internal default gain is +11.76dB.
The SPK-Amp outputs 0.6W(/1ch) when 0.56Vrm mono signal is input at single-end mode and ALC = OFF
(SPGA=0dB).
When ALCA = ON (ALCA bit= “1”), ALCA outputs -7.5dBV ~ -9.5dBV if LMTHA bit = “0”, and outputs -11.5dBV ~
-13.5dBV if LMTHA bit = “1”. REFA5-0 bits set the reference level. The internal gain of the class-D speaker amplifier is
fixed to +11.76dB.
SPIN
ALCA
Class-D
ALCA OFF: SPGA5-0bit
(+11.76dB)
ON: REF5-0bit
Figure 86. Speaker-Amp Path Level Diagram
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[AK4675]
When PMSPL and PMSPR bits are set to “0”, the speaker block (ALC + Speaker-Amp) can be powered-down
completely. In case of OSCN bit = “0”, the power-up/down time is 30ms (typ.) and 48ms (max.). In case of OSCN bit =
“1”, the power-up/down time depends on MSEL bit setting and MCKIA frequency (Table 90).
MSEL bit
0
MCKIA Freq
Power-Up Time
2.048MHz
19.5ms (40000/MCKIA)
2.8224MHz
21.5ms (60000/MCKIA)
1
3.072MHz
19.5ms (60000/MCKIA)
Table 90. Class D SPK-Amp Power-Up Time (OSC bit = “1”)
In case of OSCN bit = “0”, the write operation to SPGA5-0 bits is prohibited during 1.6ms after PMSPL or PMSPR bit is
set to “1”. In case of OSCN bit = “1”, the write operation to SPGA5-0 bits is prohibited during the power-up time of the
speaker volume block (Table 91) after PMSPL or PMSPR bit is set to “1”.
MSEL bit
0
MCKIA Freq
Power-Up Time
2.048MHz
1ms (2048/MCKIA)
2.8224MHz
1.1ms (3072/MCKIA)
1
3.072MHz
1ms (3072/MCKIA)
Table 91. Write Operation Prohibited Time of Speaker Volume after Power-up (OSCN bit = “1”)
PMSP bits
Speaker-Amp
0
Power-down & Hi-Z
1
Power-up & Output
Table 92. Speaker-Amp Output State
(default)
■ Thermal Shutdown Function
When the internal device temperature rises up irregularly (e.g. output pins of speaker amplifier are shortened), the charge
pump circuit, headphone amplifier and speaker amplifier are automatically powered-down and then THDET bit becomes
“1”. The powered-down charge pump circuit, headphone amplifier and speaker amplifier do not return to normal
operation unless HP/SPK-Amp blocks of the AK4675 are reset by the PDNA pin “L”. The device status can be monitored
by THDET bit.
■ HP/SPK-Amp Operation Clock
The AK4675 includes built-in clock oscillator for the internal operation of Class-D Speaker-Amp and Charge Pump
circuit. The AK4675 supports both internal oscillator mode and external clock mode (MCKIA pin). MSEL bit selects the
clock frequency for the MCKIA pin.
OSCN bit
Operation Clock
0
Internal OSC
(default)
1
External Clock (MCKIA pin)
Table 93. Internal Oscillator / External Clock select
MSEL bit
MCKIA Frequency
0
2.048MHz
(default)
1
2.8224MHz or 3.072MHz
Table 94. MCKIA Input Frequency Select
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[AK4675]
■ HP/SPK-Amp Block Power-Up/Down Sequence
1) HP-Amp
Power Supply
(1)
PDNA pin
(2)
PMVCMA bit
PMOSC bit
PMMHL/R bit
MCKIA Input
(3)
PMCP bit
Don’t care
Don’t care
(4)
PVEE pin
0V
0V
PVEE
≥ 0s
(11)
PMV1 bit
Input Volume
Output State
(5)
Hi-Z
PMHPL/R bits
Hi-Z
VCOMA
(6)
HPMTN bit
HPL/HPR pins
0V
Normal
MUTE
(7)
(8)
MUTE
(9)
0V
(10)
Figure 87. HP-Amp Power-up/down Sequence Example
(1) PDNA pin should be changed from “L” to “H” after power up.
“L” time of 150ns or more is needed to reset the AK4675.
The PDNA pin must be held to “L” until all power supply pins are supplied. After that, the PDNA pin should be
set to “H”.
(2) PTS1-0, MOFF, HPGA4-0, OSCN, MSEL bits should be set during this period.
(3) In case of OSCN bit = “0”, the external clock (MCKIA pin) is not needed.
In case of OSCN bit = “1”, the external clock (MCKIA pin) is needed.
(4) Power-up of Charge Pump, VCOMA and HP-Amp Mixer & Selector (and the internal clock oscillator in case of
OSCN bit = “0”): PMCP = PMMHL = PMMHR = PMOSC = PMVCMA bits = “0” Æ “1”
The PVEE pin becomes PVEE voltage within 10ms (max.) at OSCN bit = “1” or within the time in Table 79 at OSCN
bit = “1”.
(5) Power-up of input volume: PMV1 bit = “0” Æ “1”
Input volume setting (L1V3-0, R1V3-0 bits)
Input path setting (HPLL1, HPLR1, HPRR1, HPRL1 bits)
Input volume block is powered-up within 26.3ms (max.) at OSCN bit = “0” or within the time in Table 75 at
OSCN bit = “1”. Input path and volume can be set when input volume block is powered up.
(6) If PMCP and PMHPL/R bits are set to “1” at the same time or PMHPL/R bits are set to “1” during the power-up time
of the Charge Pump circuit, Headphone-Amp is powered-up after the Charge Pump circuit is powered-up.
(7) Headphone-Amp power-up: PMHPL/R bits = “0” Æ “1”
Headphone-Amp is in the mute state and outputs the DC offset. Headphone-Amp power-up time depends on the
setting of OSCN bit. When OSCN bit = “0”, it is 26.3ms (max.) When OSCN bit = “1”, refer to Table 81.
(8) Headphone-Amp mute release: HPMTN bit = “0” Æ “1”
Headphone-Amp goes to the normal operation after the transition time. Headphone-Amp mute release time
depends on the setting of PTS1-0 and MOFF1 bits.
(9) Headphone-Amp mute: HPMTN bit = “1” Æ “0”
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[AK4675]
Headphone-Amp goes to mute state after the transition time set by PTS1-0 and MOFF1 bits.
(10) Headphone-Amp power-down: PMHPL/R bits = “1” Æ “0”
Headphone-Amp is powered-down immediately.
(11) Power-down of Charge Pump, VCOMA and HP-Amp Mixer & Selector (and the internal clock oscillator in case of
OSCN bit = “0”): PMCP = PMMHL = PMMHR = PMOSC = PMVCMA bits = “1” Æ “0”
The PVEE pin goes 0V according to the time constant of the capacitor at the PVEE pin and the internal resistor. The
internal resistor is typ. 17.5kΩ. Charge Pump circuit can be powered-up during this period.
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[AK4675]
2) SPK-Amp (SPIN to SPP/SPN)
Power Supply
(1)
PDNA pin
(2)
PMVCMA bit
PMOSC bit
Don’t care
MCKIA Input
Don’t care
(3)
(9)≥ 500us
(4)≥ 0s
PMSPK bit
SPIN pin
(5)
(5)
Hi-Z
VCOMA
Hi-Z
(6) ≥ 1.6ms
(6)≥ 1.6ms
SPGA bits
Default
Hi-Z
VCOMA
Default
xxH
xxH
Default
ALCA bit
(7)
ALCA state
Disable
(7)
Enable
Enable
Disable
(10)VCOM(No signal)
LOUT3/ROUT3 pins
0V
Signal Output
(10)VCOM(No signal)
0V
(8)
SPP/SPN pins
0V
Disable
Signal Output
0V
Normal
0V
(8)
Normal
0V
Figure 88. SPK-Amp Power-up/down Sequence Example
(1) The PDNA pin should be changed from “L” to “H” after the power is supplied.
“L” time of 150ns or more is needed to reset the AK4675.
The PDNA pin must be held to “L” until all power supply pins are applied. After that, the PDNA pin should be set
to “H”.
(2) Power-up of VCOMA (and the internal clock oscillator in case of OSCN bit = “0”): PMVCMA= PMOSC bits = “0”
Æ “1”. OSCN and MSEL bits should be set during this period.
(3) In case of OSCN bit = “0”, the external clock (MCKIA pin) is not needed.
In case of OSCN bit = “1”, the external clock (MCKIA pin) is needed.
(4) Speaker-Amp power-up: PMSPK bit = “0”Æ “1”
Stereo line output3 power-up: PMLO3/RO3 bits = “0”Æ “1”(LOPS3 bit = “0”)
(5) The SPIN pin goes to “H” in 26.3ms (max) when OSCN bit = “0”, in the time shown in Table 75 when OSCN bit=
“1”.
(6) SPGA5-0 bits setting: When PMSP bits = “0”, SPGA5-0 bits are default value (0dB). The setting of SPKG5-0 and
ALCA bits is enabled at 1.6ms or more after PMSP bits are set to “1” at OSCN bit = “0” or after the power-up time in
Table 91 at OSCN bit = “1”.
(7) ALCA setting: ALCA is enabled at 30ms (max.) in case of OSCN bit = “0”, at 36864/MCKIA (= 18ms @ MCKIA =
2.048MHz) in case of OSCN bit = “1” & MSEL bit = “0”, or 55296/MCKIA (= 18ms @ MCKIA = 3.072MHz) in
case of OSCN bit = MSEL bit = “1”. Refer to “Example of ALCA Operation”.
(8) Speaker-Amp goes to normal operation at 48ms (max.) after PMSPL/R bits is changed to “1” in case of OSCN bit =
“0” or after the power-up time in Table 90 in case of OSCN bit = “1”.
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(9) Once Speaker-Amp is powered-down, Speaker-Amp can be powered-up again at 500μs or more later in case of
OSCN bit = “0”, at 1024/MCKIA (=500μs @ MCKI = 2.048MHz) or more later in case of OSCN bit = “1” & MSEL
bit = “0”, 1536/MCKIA (=500μs @ MCKIA = 3.072MHz) or more later in case of OSCN bit = MSEL bit = “1”.
(10) Signal input to the SPIN pin is prohibited when ALCA bit = “0”. The path selecting bits of the stereo line output3
(LOUT3/ROUT3 pins) must be set OFF(DACSL/R, LINS1, LINS2, LINS3, LINS4, RINS1, RINS2, RINS3, RINS4,
LOOPSL/R bits = “0”).
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[AK4675]
■ System Clock (PCM I/F)
A reference clock of PLLBT is selected among the input clocks to the SYNCA, BICKA, SYNCB or BICKB pin. The
required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input
frequency is selected by PLLBT3-0 bits (Table 95). BCKO2 bit select the output clock frequency of the BICKA or
BICKB pin (Table 96).
The AK4675 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B.
Whether PCM I/F A or B should be set as slave mode. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and BICKB
pins are Hi-Z. Table 97 indicates the output data of the SDTOA and SDTOB pins in case of PMPCM bit = “0” and during
lock time in Table 95, respectively. Table 98 indicates the output clock at master mode during lock time in Table 95.
The AK4675 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B. When
PMPCM bit is “0”, the SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z.
Mode
PLLBT3
PLLBT2
PLLBT1
PLLBT0
Reference Clock
Input Pin
Frequency
0
0
0
0
0
SYNCA
1fs2
1
0
0
0
1
BICKA
16fs2
2
0
0
1
0
BICKA
32fs2
3
0
0
1
1
BICKA
64fs2
4
0
1
0
0
SYNCB
1fs2
5
0
1
0
1
BICKB
16fs2
6
0
1
1
0
BICKB
32fs2
7
0
1
1
1
BICKB
64fs2
11
1
0
1
1
BICKA
48fs2
15
1
1
1
1
BICKB
48fs2
Others
N/A
Note 83. Mode 1 is available at only FMTA1 bit = “0”.
Note 84. Mode 5 is available at only FMTB1 bit = “0”.
Table 95. PLLBT Reference Clock
R, C at
VCOCBT pin
R
C
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
Lock Time
(max)
260ms
40ms
40ms
40ms
260ms
40ms
40ms
40ms
40ms
40ms
(default)
BICKA/BICKB
Output Frequency
0
16fs2
(default)
1
32fs2
Table 96. BICKA/B Output Frequency
BCKO2 bit
Mode
16bit Linear
8bit A-Law
8bit μ-Law
After PMPCM bit = “0” → “1”
& Before SYNCA/SYNCB Input
L
L
L
H
L
H
Table 97. SDTOA, SDTOB pins Output Data
PMPCM bit = “0”
PMPCM bit = “1”
During Lock time
“0000H”
“11010101b”
“11111111b”
Format
SYNCA, SYNCB
BICKA, BICKB
2
Except for I S
L
L
I2S
H
L
Table 98. Output Clock during Lock Time
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[AK4675]
a) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via
the SYNCB and BICKB pins.
AK4675
Phone Module
SYNCA
BICKA
1fs2
≥ 16fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 89. PCM I/F (PLLBT Reference Clock: SYNCA or BICKA pin)
b) PLLBT reference clock: SYNCB or BICKB pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via
the SYNCA and BICKA pins.
AK4675
SYNCA
BICKA
Phone Module
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
1fs2
≥ 16fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 90. PCM I/F (PLLBT Reference Clock: SYNCB or BICKB pin)
PLLBT should always be powered-up (PMPCM bit = “1”) whenever SRC-A or SRC-B is in operation (PMSRA bit = “1”
or PMSRB bit = “1”). If PLLBT is powered-down, the AK4675 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If PLLBT is powered-down, SRC-A and SRC-B should be
in the power-down mode (PMSRA=PMSRB bits = “0”).
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[AK4675]
■ PCM I/F Master Mode/Slave Mode
The PLLBT2 bit selects either master or slave mode (Table 99). When either PCM I/F A or PCM I/F B is set in slave
mode, the other is set in master mode. (For example, when PCM I/F B is set in slave mode, PCM I/F A is set in master
mode.) When the AK4675 is power-down mode (PDN pin = “L”) or PMPCM bit = “0”, each clock pins (SYNCA,
BICKA, SYNCB, BICKB) of PCM I/F become a Hi-Z (Table 100).
PLLBT3-0 bits should be set when PMPCM bit = “0” to avoid shorting out of the slave mode clock pins and master mode
clock output.
After setting the PDN pin = “H”, the PCM I/F clock pins are the Hi-Z state until PMPCM bit becomes “1”. The PCM I/F
clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
PLLBT2 bit
0
1
PCM I/F A
Slave Mode
Master Mode
PDN pin
L
H
SYNCA, BICKA pins
PCM I/F B
SYNCB, BICKB pins
Input
Master Mode
Output
Output
Slave Mode
Input
Table 99. Select PCM I/F Master/Slave Mode
PMPCM bit
0
1
(default)
SYNCA, BICKA pin
SYNCB, BICKB pin
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O Select by PLLBT2 bit I/O Select by PLLBT2 bit
(Table 99)
(Table 100)
Table 100. PCM I/F Clock I/O State
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[AK4675]
■ PCM I/F A & B Format
The AK4675 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and
8bit μ-Law) independently (Table 101, Table 102).
Mode
0
1
2
3
LAWA1
0
0
1
1
LAWA0
Format
0
16bit Linear
1
N/A
0
8bit A-Law
1
8bit μ-Law
Table 101. PCM I/F A Mode
Mode
0
1
2
3
LAWB1
0
0
1
1
LAWB0
Format
0
16bit Linear
1
N/A
0
8bit A-Law
1
8bit μ-Law
Table 102. PCM I/F B Mode
(default)
(default)
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (Table
103, Table 104). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and μ-Law
Mode, the serial data is MSB first. PCM I/F formats can be used in both master and slave modes. SYNCA/B and
BICKA/B are output from the AK4675 in master mode, but must be input to the AK4675 in slave mode.
Mode
0
1
2
3
FMTA1
0
0
1
1
FMTA0
Format
BICKA
0
Short Frame Sync
≥ 16fs2
1
Long Frame Sync
≥ 16fs2
0
MSB justified
≥ 32fs2
1
I2S
≥ 32fs2
Table 103. PCM I/F A Format
Figure
See Table 105
See Table 107
Figure 99
Figure 100
Mode
0
1
2
3
FMTB1
0
0
1
1
FMTB0
0
1
0
1
Figure
See Table 106
See Table 108
Figure 99
Figure 100
Format
BICKB
Short Frame Sync
≥ 16fs2
Long Frame Sync
≥ 16fs2
MSB justified
≥ 32fs2
I2S
≥ 32fs2
Table 104. PCM I/F B Format
(default)
(default)
In modes 2/ 3, the SDTOA/B is clocked out on the falling edge (“↓”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“↑”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits, and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“↑”) of BICKA and the SDTIA is latched on the
falling edge (“↓”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“↓”) of BICKA and the
SDTIA is latched on the rising edge (“↑”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“↑”) of BICKB and the SDTIB is latched on the
falling edge (“↓”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“↓”) of BICKB and the
SDTIB is latched on the rising edge (“↑”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
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MSBSA
BCKPA
0
0
0
1
1
0
1
1
MSBSB
BCKPB
0
0
0
1
1
0
1
1
MSBSA
BCKPA
0
0
0
1
1
0
1
1
MSBSB
BCKPB
0
0
0
1
1
0
1
1
Data Interface Format
MSB of SDTOA is output by the falling edge (“↓”) of SYNCA. MSB of SDTIA is
latched by the falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s
MSB.
MSB of SDTOA is output by the falling edge (“↓”) of SYNCA. MSB of SDTIA is
latched by the rising edge (“↑”) of the BICKA just after the output timing of SDTOA’s
MSB.
MSB of SDTOA is output by the rising edge (“↑”) of the first BICKA after the rising
edge (“↑”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA
just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the falling edge (“↓”) of the first BICKA after the rising
edge (“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the BICKA
just after the output timing of SDTOA’s MSB.
Table 105. PCM I/F A Format in Mode 0
Data Interface Format
MSB of SDTOB is output by the falling edge (“↓”) of SYNCB. MSB of SDTIB is latched
by the falling edge (“↓”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the falling edge (“↓”) of SYNCB. MSB of SDTIB is latched
by the rising edge (“↑”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of the first BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB just
after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the falling edge (“↓”) of the first BICKB after the rising
edge (“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB
just after the output timing of SDTOB’s MSB.
Table 106. PCM I/F B Format in Mode 0
Data Interface Format
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched
by the falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched
by the rising edge (“↑”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of the first BICKA after the falling
edge (“↓”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA
just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the falling edge (“↓”) of the first BICKA after the falling
edge (“↓”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the BICKA
just after the output timing of SDTOA’s MSB.
Table 107. PCM I/F A Format in Mode 1
Data Interface Format
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched
by the falling edge (“↓”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched
by the rising edge (“↑”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of the first BICKB after the falling
edge (“↓”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB
just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the falling edge (“↓”) of the first BICKB after the falling
edge (“↓”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB
just after the output timing of SDTOB’s MSB.
Table 108. PCM I/F B Format in Mode 1
MS0963-E-00
Figure
Figure 91
Figure 92
Figure 93
Figure 94
Figure
Figure 91
Figure 92
Figure 93
Figure 94
Figure
Figure 95
Figure 96
Figure 97
Figure 98
Figure
Figure 95
Figure 96
Figure 97
Figure 98
2008/05
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[AK4675]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don’t Care
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D7
D6
Figure 91. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don’t Care
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D7
D6
Figure 92. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don’t Care
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D7
D6
Figure 93. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
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[AK4675]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 Don’t Care
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D7
D6
Figure 94. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
1/fs2
SYNCA
(Master)
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care
Don’t Care
D15 D14 D13
D7
D6
D5
D7
D6
D5
Figure 95. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
(Master)
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care
Don’t Care
D15 D14 D13
D7
D6
D5
D7
D6
D5
Figure 96. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
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[AK4675]
1/fs2
SYNCA
(Master)
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care
Don’t Care
D15 D14 D13
D7
D6
D5
D7
D6
D5
Figure 97. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
1/fs2
SYNCA
(Master)
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care
Don’t Care
D15 D14 D13
D7
D6
D5
D7
D6
D5
Figure 98. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
MS0963-E-00
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[AK4675]
SYNCA
BICKA
(32fs2)
SDTOA(o)
SDTIA(i)
BICKA
(64fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
15 14 13
7 6 5 4 3 2 1 0
15 14 13
7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
SDTOA(o)
15 14 13
1 0
SDTIA(i)
15 14 13
1 0
9 10 11 12 13 14 15 0 1
15
Don't Care
31 0 1 2 3
Don't Care
15 16 17 18
15
31 0 1
15
Don't Care
Don't Care
15
15:MSB, 0:LSB
Figure 99. Timing of MSB justified
SYNCA
BICKA
(32fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
SDTOA(o)
15 14
8 7 6 5 4 3 2 1 0
SDTIA(i)
15 14
8 7 6 5 4 3 2 1 0
BICKA
(64fs2)
0 1 2 3
15 16 17 18
SDTOA(o)
15 14
2 1 0
SDTIA(i)
15 14
2 1 0
31 0 1 2 3
Don't Care
9 10 11 12 13 14 15 0 1
Don't Care
15 16 17 18
31 0 1
Don't Care
15:MSB, 0:LSB
Figure 100. Timing of I2S
MS0963-E-00
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[AK4675]
■ Phone Path
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
BIVOL
SDTOB
SDTIB
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 101. Internal MIC/SPK or External MIC/HP Call & Recording
MS0963-E-00
2008/05
- 132 -
[AK4675]
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
BIVOL
SDTOB
SDTIB
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 102. B/T Headset Phone Call & Recording
MS0963-E-00
2008/05
- 133 -
[AK4675]
■ General Purpose Output
The AK4675 has General Purpose Output Pin (GPO) to control the external component.
In case of GPOM1 bit = “0”, the GPO1 pin goes to “H” at GPOE1 bit = “1”.
GPOE1 bit
GPO1 pin
0
L
(default)
1
H
Table 109. General Purpose Output 1 Pin Control (GPOM1 bit = “0”)
In the case of GPOM1 bit = “1”, the GPO1 pin goes to “H” if the input level of the channel selected by A0 bit (SAIN1 or
SAIN2 pin) is higher than the reference voltage that is input the SAIN3 pin. In the case of GPOM1 bit = “1”, the reference
voltage input to the SAIN3 pin should be lower than 0.5 x AVDD.
SAIN1/2 pin
GPO1 pin
< SAIN3 pin
L
(default)
H
≥ SAIN3 pin
Table 110. General Purpose Output 1 Pin Control (GPOM1 bit = “1”)
In the case of GPOM2 bit = “0”, the GPO2 pin goes to “H” at GPOE2 bit = “0”.
GPOE2 bit
GPO2 pin
0
L
(default)
1
H
Table 111. General Purpose Output 2 Pin Control (GPOM2 bit = “0”)
In the case of GPOM2 bit = “1”, the GPO2 pin outputs the mic detection result. (Table 21.)
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MS0963-E-00
External microphone
Mic (Headset)
No Mic (Headphone)
2008/05
- 134 -
[AK4675]
■ SAR 10bit ADC
The AK4675 incorporates a 10-bit successive approximation resistor A/D converter for DC measurement.
The A/D converter output is a straight binary format as shown in Table 112:
Input Voltage
(AVDD−1.5LSB) ~ AVDD
(AVDD−2.5LSB) ~ (AVDD−1.5LSB)
:
0.5LSB ~ 1.5LSB
0 ~ 0.5LSB
Table 112. Output Code
Output Code
3FFH
3FEH
:
001H
000H
When PMSAD bit is set to “1”, 10bit ADC is powered-up. When the control register is read, A/D conversion is executed
and data is output.
10bit ADC supports 3 kinds of analog input. A1-0 bits select the measurement modes.
Mode
0
1
2
3
A1
A0
Input Channel
0
0
SAIN1
0
1
SAIN2
1
0
SAIN3
1
1
N/A
Table 113. SAR ADC Measurement Mode
(default)
<SAR ADC Execute Sequence (in case that the interrupt function is enabled.)>
(1) Select the measurement mode by A1-0 bits and set PMSAD bit = “1” to power-up SAR ADC.
(2) Read Addr=5BH so that A/D conversion is executed and MSB 8bit data is output.
(3) Additionally read Addr=5CH then LSB 2bit data is output.
<SAR ADC Execute Sequence (in case that the interrupt function is disabled.)>
(1) GPOM1 bit should be set to “1”. The GPO1 pin can be used as the interrupt output pin.
(2) Select the measurement mode by A0 bit.
(3) The GPO1 pin goes to “H” when the input DC voltage of the SAIN1 or SAIN2 pin (selected by A0 bit) is higher than
the input voltage of the SAIN3 pin.
(4) After CPU detects the GPO1 pin = “H”, set GPOM1 bit = “0” and PMSAD bit = “1” to power-up SAR ADC.
(5) Read Addr=5BH so that A/D conversion is executed and MSB 8bit data is output.
(6) Additionally read Addr=5CH then LSB 2bit data is output.
MS0963-E-00
2008/05
- 135 -
[AK4675]
■ ATT Circuit for Battery Monitor
When BATCPU bit = “1”, the input voltage for the VBATIN pin is divided by the internal resistors R1 (7.5k) and R2
(2.5k). The VBATO pin outputs the internally divided voltage. When BATCPU bit = “0”, the VBATO pin goes to Hi-Z.
This block can operate even if PMVCMA=PMOSC bits = “0”.
AK4675
VBATIN pin
VBATO pin
R1=7.5K
R2=2.5K
BATCPU bit
Figure 103. ATT circuit for Battery Monitor
■ Serial Control Interface
(1) I2C Bus Control Mode
The AK4675 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(1)-1. WRITE Operations
Figure 104 shows the data transfer sequence for I2C-bus mode. All commands are preceded by START condition. HIGH
to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 111). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
Addresses for CODEC and HP/SPK-Amp are fixed (Figure 105). If the slave address matches that of the AK4675, the
AK4675 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related
clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 112). R/W bit value of “1”
indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4675. The format is MSB first, and the most significant
1-bit is fixed to “0” (Figure 106). The data after the second byte contains control data. The format is MSB first, 8bits
(Figure 107). The AK4675 generates an acknowledge after each byte has been received. Data transfer is always
terminated by a STOP condition generated by the master. LOW to HIGH transition on the SDA line while SCL is HIGH
defines a STOP condition (Figure 111).
MS0963-E-00
2008/05
- 136 -
[AK4675]
The AK4675 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4675
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. In case of CODEC & SRC blocks, if
the address exceeds 5AH prior to generating stop condition, the address counter will “roll over” to 00H and the previous
data will be overwritten. In case of HP/SPK-Amp blocks, if the address exceeds 12H prior to generating stop condition,
the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 113) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 104. Data Transfer Sequence at the I2C-Bus Mode
CODEC
0
0
1
0
0
1
0
R/W
AMP
0
0
1
0
0
1
1
R/W
Figure 105. The First Byte
0
A6
A5
A4
A3
A2
A1
A0
D1
D0
Figure 106. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 107. Byte Structure after The Second Byte
MS0963-E-00
2008/05
- 137 -
[AK4675]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4675. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 7-bit address counter is incremented by one, and the next data is
automatically taken into the next address. In case of CODEC & SRC blocks, if the address exceeds 5AH prior to
generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. In case of
HP/SPK-Amp blocks, if the address exceeds 12H prior to generating stop condition, the address counter will “roll over”
to 00H and the data of 00H will be read out.
The AK4675 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ (except for 10bit SAR ADC Data)
The AK4675 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit set to “1”, the AK4675 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates stop condition, the
AK4675 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
P
MA
AC
SK
T
E
R
MN
AA
SC
T
EK
R
Figure 108. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform “dummy” write operation. The master issues start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4675 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4675 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S K
T
E
R
A
C
K
P
MN
A A
S
T C
E K
R
MA
AC
S
T K
E
R
Figure 109. RANDOM ADDRESS READ
When SAR ADC data is read, register data of Addr=5BH should be read by RANDOM ADDRESS READ, then stop
condition should be input.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(5BH)
A
C
K
S
T
O
P
R/W="1"
A
C
K
Data(D9-2)
A
C
K
Data(D1-0)
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 110. RANDOM ADDRESS READ of SAR ADC Data
MS0963-E-00
2008/05
- 138 -
[AK4675]
SDA
SCL
S
P
start condition
stop condition
Figure 111. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 112. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 113. Bit Transfer on the I2C-Bus
MS0963-E-00
2008/05
- 139 -
[AK4675]
■ Register Map (CODEC & SRC Blocks)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
AD/DA Power Management
PLL Mode Select 0
PLL Mode Select 1
Format Select
MIC Signal Select
MIC Amp Gain
Mixing Power Management 0
Mixing Power Management 1
Output Volume Control
LOUT1 Signal Select
ROUT1 Signal Select
LOUT2S Signal Select
ROUT2S Signal Select
LOUT3 Signal Select
ROUT3 Signal Select
LOUT1 Power Management
LOUT2S Power Management
LOUT3 Power Management
Lch Input Volume Control
Rch Input Volume Control
ALC Reference Select
Digital Mixing Control
ALC Timer Select
ALC Mode Control
Mode Control 1
Mode Control 2
Lch Output Volume Control
Rch Output Volume Control
Side Tone A Control
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
PMDAR
FS3
BTCLK
0
MDIF4
D6
PMDAL
FS2
LP
0
MDIF3
D5
PMADR
FS1
BCKO
0
MDIF2
D4
PMADL
FS0
PS1
SDOD
MDIF1
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
0
0
0
0
0
DTMIC
PMLOOPR
PMLOOPL
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
1
L1G1
L2G1
L3G1
L4G1
LPG1
0
0
0
L3VL1
IVL7
IVR7
REF7
0
L1G0
L2G0
L3G0
L4G0
LPG0
0
0
1
LOOPL
LOOPR
1
LINL4
RINR4
LINH4
RINH4
LINS4
RINS4
LOOPM
IVL4
IVR4
REF4
0
LINL3
RINR3
LINH3
RINH3
LINS3
RINS3
LOM
LOM2
LOM3
IVL3
IVR3
REF3
L1VL2
LINL2
RINR2
LINH2
RINH2
LINS2
RINS2
LOPS1
0
LOPS3
IVL2
IVR2
REF2
L1VL1
LINL1
RINR1
LINH1
RINH1
LINS1
RINS1
PMRO1
0
PMRO3
IVL1
IVR1
REF1
L1VL0
DACL
DACR
DACHL
DACHR
DACSL
DACSR
PMLO1
0
PMLO3
IVL0
IVR0
REF0
LOOPHL
LOOPHR
LOOPSL
LOOPSR
RCV
D2
PMMICL
PLL3
PS0
MSBS
INR1
PLL2
MCKO
BCKP
INR0
D1
PMMP
PLL1
M/S
DIF1
INL1
D0
PMVCM
PLL0
PMPLL
DIF0
INL0
PMRO2S
PMLO2S
L3VL0
IVL6
IVR6
REF6
LODIF
IVL5
IVR5
REF5
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
0
0
DAM
SRA1
OVL7
OVR7
0
GN1
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
F1A7
0
F1B7
0
F2A7
0
F2B7
0
RFST1
ZELMN
MIXD
SRA0
OVL6
OVR6
0
GN0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
F1A6
0
F1B6
0
F2A6
0
F2B6
0
RFST0
LMAT1
SDIM1
BIV2
OVL5
OVR5
SVAR2
LPF
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
WTM2
LMAT0
SDIM0
BIV1
OVL4
OVR4
SVAR1
HPF
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
WTM1
RGAIN1
EQ
BIV0
OVL3
OVR3
SVAR0
EQ0
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
WTM0
RGAIN0
ADM
SMUTE
OVL2
OVR2
SVAL2
FIL3
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
ZTM1
LMTH1
IVOLC
OVTM
OVL1
OVR1
SVAL1
HPFAD
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
ZTM0
LMTH0
ALC
OVOLC
OVL0
OVR0
SVAL0
PFSEL
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
MS0963-E-00
LOOPM2
LOOPM3
D3
PMMICR
2008/05
- 140 -
[AK4675]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
PCM I/F Control 0
PCM I/F Control 1
PCM I/F Control 2
Digital Volume B Control
Digital Volume C Control
Side Tone Volume Control
Digital Mixing Control
SAR ADC Control
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
EQB3
EQD3
0
GPOM2
SDOAD
SDOBD
BVL7
CVL7
0
SDOR1
0
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
EQB2
EQD2
0
GPOE2
BCKO2
PLLBT3
BVL6
CVL6
0
SDOR0
0
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
EQB1
EQD1
0
PLLBT2
MSBSA
MSBSB
BVL5
CVL5
0
SDOL1
0
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
EQB0
EQD0
0
PLLBT1
BCKPA
BCKPB
BVL4
CVL4
0
SDOL0
GPOM1
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
EQA3
EQC3
EQE3
PLLBT0
LAWA1
LAWB1
BVL3
CVL3
SDOA
BVMX1
GPOE1
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
EQA2
EQC2
EQE2
PMPCM
LAWA0
LAWB0
BVL2
CVL2
SVB2
BVMX0
A1
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
EQA1
EQC1
EQE1
PMSRB
FMTA1
FMTB1
BVL1
CVL1
SVB1
SBMX1
A0
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
EQA0
EQC0
EQE0
PMSRA
FMTA0
FMTB0
BVL0
CVL0
SVB0
SBMX0
PMSAD
Note 85. PDN pin = “L” resets the registers of CODEC & SRC blocks to their default values.
Note 86. The bits defined as 0 must contain a “0” value.
Note 87. Addresses 1EH to 2FH and 32H to 4FH cannot be read.
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■ Register Definitions (CODEC & SRC Blocks)
Addr
00H
Register Name
AD/DA Power Management
R/W
Default
D7
PMDAR
R/W
0
D6
PMDAL
R/W
0
D5
PMADR
R/W
0
D4
PMADL
R/W
0
D3
D2
PMMICR
PMMICL
R/W
0
R/W
0
D1
PMMP
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
PMMICL: MIC-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch Power Management
0: Power down (default)
1: Power up
PMADL: ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADR: ADC Rch Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks of CODEC & SRC are powered-down regardless of setting of this address. In this case, register of CODEC &
SRC is initialized to the default value.
When all power management bits are “0”, all blocks of CODEC & SRC are powered-down. The register values of
CODEC & SRC remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA),
PDN pin should be “L”.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
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Addr
01H
Register Name
PLL Mode Select 0
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
1
D5
FS1
R/W
1
D4
FS0
R/W
1
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “0110”(MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Addr
02H
Register Name
PLL Mode Select 1
R/W
Default
D7
BTCLK
R/W
0
D6
LP
R/W
0
D5
BCKO
R/W
0
D4
PS1
R/W
0
D3
PS0
R/W
0
D2
MCKO
R/W
0
D1
M/S
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
BCKO: BICK Output Frequency Select at Master Mode (Table 10)
LP: Low Power Mode
0: Normal Mode (default)
1: Low Power Mode: available at fs=22.05kHz or less.
BTCLK: Clock Mode of Audio CODEC
0: Synchronized to Audio I/F (default)
1: Synchronized to PCM I/F
BTCLK bit is enabled at only PMPLL bit = “0”. When BTCLK bit is “1”, Audio CODEC and the digital block
(Figure 56) operate by the clock generated by PLLBT.
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Addr
03H
Register Name
Format Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
SDOD
R/W
0
D3
MSBS
R/W
0
D2
BCKP
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF1-0: Audio Interface Format (Table 16)
Default: “10” (Left jutified)
BCKP: BICK Polarity at DSP Mode (Table 17)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Phase at DSP Mode (Table 17)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
SDOD: SDTO Disable (Table 47)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
04H
Register Name
MIC Signal Select
R/W
Default
D7
MDIF4
R/W
0
D6
MDIF3
R/W
0
D5
MDIF2
R/W
0
D4
MDIF1
R/W
0
D3
INR1
R/W
0
D2
INR0
R/W
0
D1
INL1
R/W
0
D0
INL0
R/W
0
INL1-0: MIC-Amp Lch Input Source Select (Table 18)
Default: “00” (LIN1)
INR1-0: MIC-Amp Rch Input Source Select (Table 18)
Default: “00” (RIN1)
MDIF1: Line1 Input Type Select
0: Single-ended input (LIN1/RIN1 pins: default)
1: Full-differential input (IN1+/IN1− pins)
MDIF2: Line2 Input Type Select
0: Single-ended input (LIN2/RIN2 pins: default)
1: Full-differential input (IN2+/IN2− pins)
MDIF3: Line3 Input Type Select
0: Single-ended input (LIN3/RIN3 pins: default)
1: Full-differential input (IN3+/IN3− pins)
MDIF4: Line4 Input Type Select
0: Single-ended input (LIN4/RIN4 pins: default)
1: Full-differential input (IN4+/IN4− pins)
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Addr
05H
Register Name
MIC Amp Gain
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
DTMIC
RD
0
MGNL3-0: MIC-Amp Lch Gain Control (Table 19)
Default: “0101” (0dB)
MGNR3-0: MIC-Amp Rch Gain Control (Table 19)
Default: “0101” (0dB)
Addr
06H
Register Name
Mixing Power Management 0
R/W
Default
D7
0
RD
0
D6
0
RD
0
D1
D0
PMLOOPR
PMLOOPL
R/W
0
R/W
0
PMLOOPL: MIC-Amp Lch Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMLOOPR: MIC-Amp Rch Mixing Circuit Power Management
0: Power down (default)
1: Power up
DTMIC: Microphone Detection Result (Read Only: Table 21)
0: Microphone is not detected. (default)
1: Microphone is detected.
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Addr
07H
Register Name
Mixing Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D5
1
RD
1
D4
1
RD
1
D3
0
RD
0
PMAINL1: LIN1 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR1: RIN1 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL2: LIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR2: RIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL3: LIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR3: RIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL4: LIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR4: RIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
Addr
08H
Register Name
Output Volume Control
R/W
Default
D7
1
RD
1
D6
0
RD
0
D2
L1VL2
R/W
1
D1
L1VL1
R/W
0
D0
L1VL0
R/W
1
L1VL3-0: LOUT1/ROUT1 Output Volume Control (Table 67)
Default: “5H” (0dB)
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Addr
09H
Register Name
LOUT1 Signal Select
R/W
Default
D7
L1G1
R/W
0
D6
L1G0
R/W
0
D5
LOOPL
R/W
0
D4
LINL4
R/W
0
D3
LINL3
R/W
0
D2
LINL2
R/W
0
D1
LINL1
R/W
0
D0
DACL
R/W
0
DACL: Switch Control from DAC Lch to LOUT1
0: OFF (default)
1: ON
When PMLO1 bit is “1”, DACL bit is enabled. When PMLO1 bit is “0”, the LOUT1 pin goes to VSS1.
LINL1: Switch Control from LIN1 to LOUT1
0: OFF (default)
1: ON
LINL2: Switch Control from LIN2 to LOUT1
0: OFF (default)
1: ON
LINL3: Switch Control from LIN3 to LOUT1
0: OFF (default)
1: ON
LINL4: Switch Control from LIN4 to LOUT1
0: OFF (default)
1: ON
LOOPL: Switch Control from MIC-Amp Lch to LOUT1
0: OFF (default)
1: ON
L1G1-0: LIN1/RIN1 Mixing Gain Control (Table 60)
Default: “00” (0dB)
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Addr
0AH
Register Name
ROUT1 Signal Select
R/W
Default
D7
L2G1
R/W
0
D6
L2G0
R/W
0
D5
LOOPR
R/W
0
D4
RINR4
R/W
0
D3
RINR3
R/W
0
D2
RINR2
R/W
0
D1
RINR1
R/W
0
D0
DACR
R/W
0
DACR: Switch Control from DAC Rch to ROUT1
0: OFF (default)
1: ON
When PMRO1 bit is “1”, DACR bit is enabled. When PMRO1 bit is “0”, the ROUT1 pin goes to VSS1.
RINR1: Switch Control from RIN1 to ROUT1
0: OFF (default)
1: ON
RINR2: Switch Control from RIN2 to ROUT1
0: OFF (default)
1: ON
RINR3: Switch Control from RIN3 to ROUT1
0: OFF (default)
1: ON
RINR4: Switch Control from RIN4 to ROUT1
0: OFF (default)
1: ON
LOOPR: Switch Control from MIC-Amp Rch to ROUT1
0: OFF (default)
1: ON
L2G1-0: LIN2/RIN2 Mixing Gain Control (Table 61)
Default: “00” (0dB)
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Addr
0BH
Register Name
LOUT2S Signal Select
R/W
Default
D7
L3G1
R/W
0
D6
L3G0
R/W
0
D5
LOOPHL
R/W
0
D4
LINH4
R/W
0
D3
LINH3
R/W
0
D2
LINH2
R/W
0
D1
LINH1
R/W
0
D0
DACHL
R/W
0
DACHL: Switch Control from DAC Lch to LOUT2S
0: OFF (default)
1: ON
LINH1: Switch Control from LIN1 to LOUT2S
0: OFF (default)
1: ON
LINH2: Switch Control from LIN2 to LOUT2S
0: OFF (default)
1: ON
LINH3: Switch Control from LIN3 to LOUT2S
0: OFF (default)
1: ON
LINH4: Switch Control from LIN4 to LOUT2S
0: OFF (default)
1: ON
LOOPHL: Switch Control from MIC-Amp Lch to LOUT2S
0: OFF (default)
1: ON
L3G1-0: LIN3/RIN3 Mixing Gain Control (Table 62)
Default: “00” (0dB)
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Addr
0CH
Register Name
ROUT2S Signal Select
R/W
Default
D7
L4G1
R/W
0
D6
L4G0
R/W
0
D5
LOOPHR
R/W
0
D4
RINH4
R/W
0
D3
RINH3
R/W
0
D2
RINH2
R/W
0
D1
RINH1
R/W
0
D0
DACHR
R/W
0
DACHR: Switch Control from DAC Rch to ROUT2S
0: OFF (default)
1: ON
RINH1: Switch Control from RIN1 to ROUT2S
0: OFF (default)
1: ON
RINH2: Switch Control from RIN2 to ROUT2S
0: OFF (default)
1: ON
RINH3: Switch Control from RIN3 to ROUT2S
0: OFF (default)
1: ON
RINH4: Switch Control from RIN4 to ROUT2S
0: OFF (default)
1: ON
LOOPHR: Switch Control from MIC-Amp Rch to ROUT2S
0: OFF (default)
1: ON
L4G1-0: LIN4/RIN4 Mixing Gain Control (Table 63)
Default: “00” (0dB)
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Addr
0DH
Register Name
LOUT3 Signal Select
R/W
Default
D7
LPG1
R/W
0
D6
LPG0
R/W
0
D5
LOOPSL
R/W
0
D4
LINS4
R/W
0
D3
LINS3
R/W
0
D2
LINS2
R/W
0
D1
LINS1
R/W
0
D0
DACSL
R/W
0
DACSL: Switch Control from DAC Lch to LOUT3
0: OFF (default)
1: ON
When PMLO3 bit is “1”, DACSL bit is enabled. When PMLO3 bit is “0”, the LOUT3 pin goes to VSS1.
LINS1: Switch Control from LIN1 to LOUT3
0: OFF (default)
1: ON
LINS2: Switch Control from LIN2 to LOUT3
0: OFF (default)
1: ON
LINS3: Switch Control from LIN3 to LOUT3
0: OFF (default)
1: ON
LINS4: Switch Control from LIN4 to LOUT3
0: OFF (default)
1: ON
LOOPSL: Switch Control from MIC-Amp Lch to LOUT3
0: OFF (default)
1: ON
LPG1-0: MIC-Amp Mixing Gain Control (Table 64)
Default: “00” (0dB)
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Addr
0EH
Register Name
ROUT3 Signal Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
LOOPSR
R/W
0
D4
RINS4
R/W
0
D3
RINS3
R/W
0
D2
RINS2
R/W
0
D1
RINS1
R/W
0
D0
DACSR
R/W
0
DACSR: Switch Control from DAC Rch to ROUT3
0: OFF (default)
1: ON
When PMRO3 bit is “1”, DACR bit is enabled. When PMRO3 bit is “0”, the ROUT3 pin goes to VSS1.
RINS1: Switch Control from RIN1 to ROUT3
0: OFF (default)
1: ON
RINS2: Switch Control from RIN2 to ROUT3
0: OFF (default)
1: ON
RINS3: Switch Control from RIN3 to ROUT3
0: OFF (default)
1: ON
RINS4: Switch Control from RIN4 to ROUT3
0: OFF (default)
1: ON
LOOPSR: Switch Control from MIC-Amp Rch to ROUT3
0: OFF (default)
1: ON
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[AK4675]
Addr
0FH
Register Name
LOUT1 Power Management
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
RCV
R/W
0
D4
LOOPM
R/W
0
D3
LOM
R/W
0
D2
LOPS1
R/W
0
D1
PMRO1
R/W
0
D0
PMLO1
R/W
0
PMLO1: LOUT1 Power Management
0: Power down (default)
1: Power up
PMRO1: ROUT1 Power Management
0: Power down (default)
1: Power up
LOPS1: LOUT1/ROUT1 Power Save Mode
0: Normal Operation (default)
1: Power Save Mode
LOM: Mono Mixing from DAC to LOUT1/ROUT1
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM: Mono Mixing from MIC-Amp to LOUT1/ROUT1
0: Stereo Mixing (default)
1: Mono Mixing
RCV: Receiver Select
0: Stereo Line Output (LOUT1/ROUT1 pins) (default)
1: Mono Receiver Output (RCP/RCN pins)
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[AK4675]
Addr
10H
Register Name
LOUT2S Power Management
R/W
Default
D7
0
RD
0
D6
D5
D4
PMRO2S
PMLO2S
LOOPM2
R/W
0
R/W
0
R/W
0
D3
LOM2
R/W
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
LOM2: Mono Mixing from DAC to LOUT2S/ROUT2S
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM2: Mono Mixing from MIC-Amp to LOUT2S/ROUT2S
0: Stereo Mixing (default)
1: Mono Mixing
PMLO2S: LOUT2S MIX-Amp Power Management
0: Power down (default)
1: Power up
PMRO2S: ROUT2S MIX-Amp Power Management
0: Power down (default)
1: Power up
MS0963-E-00
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[AK4675]
Addr
11H
Register Name
LOUT3 Power Management
R/W
Default
D7
L3VL1
R/W
1
D6
L3VL0
R/W
0
D5
D4
LODIF
LOOPM3
R/W
0
R/W
0
D3
LOM3
R/W
0
D2
LOPS3
R/W
0
D1
PMRO3
R/W
0
D0
PMLO3
R/W
0
PMLO3: LOUT3 Power Management
0: Power down (default)
1: Power up
PMRO3: ROUT3 Power Management
0: Power down (default)
1: Power up
LOPS3: LOUT3/ROUT3 Power Save Mode
0: Normal Operation (default)
1: Power Save Mode
LOM3: Mono Mixing from DAC to LOUT3/ROUT3
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM3: Mono Mixing from MIC-Amp to LOUT3/ROUT3
0: Stereo Mixing (default)
1: Mono Mixing
LODIF: Lineout Select
0: Single-ended Stereo Line Output (LOUT3/ROUT3 pins) (default)
1: Full-differential Mono Line Output (LOP/LON pins)
L3VL1-0: LOUT3/ROUT3 Output Gain Control (Table 72)
Default: “10” (0dB)
MS0963-E-00
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[AK4675]
Addr
12H
13H
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
0
D5
IVL5
IVR5
R/W
0
D4
IVL4
IVR4
R/W
1
D3
IVL3
IVR3
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D3
REF3
R/W
0
D2
REF2
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 33)
Default: “91H” (0dB)
Addr
14H
Register Name
ALC Reference Select
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
D5
REF5
R/W
1
D4
REF4
R/W
0
REF7-0: Reference Value at ALC Recovery Operation; 0.375dB step, 242 Level (Table 29)
Default: “E1H” (+30.0dB)
Addr
15H
Register Name
Digital Mixing Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D4
WTM2
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
ZTM1
R/W
0
D0
ZTM0
R/W
0
PFMXL1-0: 5-band EQ Lch Input Mixing 1 (Table 49.)
Default: “00” (SDTI)
PFMXR 1-0: 5-band EQ Rch Input Mixing 1 (Table 50.)
Default: “00” (SDTI)
SRMXL1-0: 5-band EQ Lch Input Mixing 2 (Table 51.)
Default: “00” (SDTI)
SRMXR 1-0: 5-band EQ Rch Input Mixing 2 (Table 52.)
Default: “00” (SDTI)
Addr
16H
Register Name
ALC Timer Select
R/W
Default
D7
0
RD
0
D6
RFST1
R/W
0
D5
RFST0
R/W
0
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 26)
Gain is changed by micro computer writing or ALC limiter operation at the zero crossing point or at the zero
crossing timeout. Default value is “00” (128/fs)
WTM2-0: ALC Recovery Waiting Period (Table 27)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation; Default
is “000” (128/fs).
RFST1-0: ALC First recovery Speed (Table 30)
Default: “00”(4times)
MS0963-E-00
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[AK4675]
Addr
17H
Register Name
ALC Mode Control
R/W
Default
D7
0
RD
0
D6
ZELMN
R/W
0
D5
LMAT1
R/W
0
D4
LMAT0
R/W
0
D3
RGAIN1
R/W
0
D2
RGAIN0
R/W
0
D1
LMTH1
R/W
0
D0
LMTH0
R/W
0
D2
ADM
R/W
0
D1
IVOLC
R/W
1
D0
ALC
R/W
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 24)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (Table 28)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 25)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
Addr
18H
Register Name
Mode Control 1
R/W
Default
D7
DAM
R/W
0
D6
MIXD
R/W
0
D5
SDIM1
R/W
0
D4
SDIM0
R/W
0
D3
EQ
R/W
0
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
ADM: Mono Recording (Table 44)
0: Stereo (default)
1: Mono: (L+R)/2
EQ: Select 5-Band Equalizer
0: OFF (default)
1: ON
SDIM1-0: SDTI Input Signal Select (Table 48)
Default: “00” (L=Lch, R=Rch)
MIXD: DAC and SRC-A Mono Mixing (Table 53 and Table 54.)
0: L+R (default)
1: (L+R)/2
DAM: DAC Mono Mixing (Table 53)
0: Stereo (default)
1: Mono: (L+R) or (L+R)/2 is selected by MIXD bit.
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[AK4675]
Addr
19H
Register Name
Mode Control 2
R/W
Default
D7
SRA1
R/W
0
D6
SRA0
R/W
0
D5
BIV2
R/W
0
D4
BIV1
R/W
0
D3
BIV0
R/W
0
D2
SMUTE
R/W
0
D1
OVTM
R/W
0
D0
OVOLC
R/W
1
OVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume level, while register values of
OVL7-0 bits are not written to OVR7-0 bits. When OVOLC bit = “0”, OVL7-0 bits control Lch level and
OVR7-0 bits control Rch level, respectively.
OVTM: Digital Volume Transition Time Setting
0: 1061/fs (default)
1: 256/fs
This is the transition time between OVL/R7-0 bits = 00H and FFH.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
BIV2-0: SDTIB Input Volume Control (Table 41)
Default: “0H” (0dB)
SRA1-0: SRC-A Input Signal Select (Table 54)
Default: “00” (Lch)
Addr
1AH
1BH
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
D7
OVL7
OVR7
R/W
0
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
1
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
0
D5
SVAR2
R/W
0
D4
SVAR1
R/W
0
D3
SVAR0
R/W
0
D2
SVAL2
R/W
0
D1
SVAL1
R/W
0
D0
SVAL0
R/W
0
OVL7-0, OVR7-0: Output Digital Volume (Table 36)
Default: “18H” (0dB)
Addr
1CH
Register Name
Side Tone A Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
SVAL2-0, SVAR2-0: Side Tone Volume A (SVOLA) (Table 34)
Default: “000” (0dB))
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Addr
1DH
Register Name
Digital Filter Select
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
EQ0
R/W
0
D2
FIL3
R/W
0
D1
HPFAD
R/W
1
D0
PFSEL
R/W
0
PFSEL: Signal Select of Programmable Filter Block (Table 43.)
0: ADC Output Data (default)
1: SDTI Input Data
HPFAD: HPF Control of ADC
0: OFF
1: ON (default)
When HPFAD bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPFAD bit is “0”,
HPFAD block is through (0dB).
GN1-0: Gain Select at GAIN block (Table 23)
Default: “00” (0dB)
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block
is OFF (MUTE).
EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E0C15-0 bits are enabled. When EQ0 bit is “0”,
EQ0 block is through (0dB).
HPF: HPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block
is through (0dB).
LPF: LPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block
is through (0dB).
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[AK4675]
Addr
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
W
0
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
W
0
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
W
0
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
W
0
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
W
0
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3 (Stereo Separation Emphasis Filter) Select
0: HPF (Default)
1: LPF
E0A15-0, E0B13-0, E0C15-C0: EQ0 (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
Default: “0000H”
Addr
28H
29H
2AH
2BH
Register Name
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
F1A5
F1A13
F1B5
F1B13
W
D4
F1A4
F1A12
F1B4
F1B12
W
D3
F1A3
F1A11
F1B3
F1B11
W
D2
F1A2
F1A10
F1B2
F1B10
W
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH”
F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” (fc=150Hz@fs=44.1kHz)
Addr
2CH
2DH
2EH
2FH
Register Name
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
F2A13-0, F2B13-B0: FIL2 (LPF) Coefficient (14bit x 2)
Default: “0000H”
MS0963-E-00
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[AK4675]
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”,
EQ4 block is through (0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”,
EQ5 block is through (0dB).
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[AK4675]
Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
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Addr
50H
51H
Register Name
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
R/W
Default
Addr
52H
Register Name
EQ Control 10kHz
R/W
Default
D7
EQB3
EQD3
R/W
1
D6
EQB2
EQD2
R/W
0
D5
EQB1
EQD1
R/W
0
D4
EQB0
EQD0
R/W
0
D3
EQA3
EQC3
R/W
1
D2
EQA2
EQC2
R/W
0
D1
EQA1
EQC1
R/W
0
D0
EQA0
EQC0
R/W
0
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
EQE3
R/W
1
D2
EQE2
R/W
0
D1
EQE1
R/W
0
D0
EQE0
R/W
0
EQA3-0: Select the boost level of 100Hz
EQB3-0: Select the boost level of 250Hz
EQC3-0: Select the boost level of 1kHz
EQD3-0: Select the boost level of 3.5kHz
EQE3-0: Select the boost level of 10kHz
See Table 35.
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[AK4675]
Addr
53H
Register Name
PCM I/F Control 0
R/W
Default
D7
GPOM2
R/W
0
D6
GPOE2
R/W
0
D5
PLLBT2
R/W
0
D4
PLLBT1
R/W
0
D3
PLLBT0
R/W
0
D2
PMPCM
R/W
0
D1
PMSRB
R/W
0
D0
PMSRA
R/W
0
PMSRA: SRC-A Power Management
0: Power down (default)
1: Power up
PMSRB: SRC-B Power Management
0: Power down (default)
1: Power up
PMPCM: PCM I/F Power Management
0: Power down (default)
1: Power up
PLLBT2-0: PLLBT Reference Clock Select
PLLBT3 bit is D6 of Addr=55H.
Default: “0000”: SYNCA
GPOE2: General Purpose Output 2 Enable at GPOM2 bit = “1”
“0”: GPO2 pin = “L” (default)
“1”: GPO2 pin = “H”
GPOM2: General Purpose Output 2 Operation Mode (Table 111.)
“0”: Controlled by GPOE2 bit (default)
“1”: MIC Detection Interrupt
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[AK4675]
Addr
54H
Register Name
PCM I/F Control 2
R/W
Default
D7
SDOAD
R/W
0
D6
BCKO2
R/W
0
D5
MSBSA
R/W
0
D4
BCKPA
R/W
0
D3
LAWA1
R/W
0
D2
LAWA0
R/W
0
D1
FMTA1
R/W
0
D0
FMTA0
R/W
0
FMTA1-0: PCM I/F A Format (Table 103)
Default: “00” (Mode 0)
LAWA1-0: PCM I/F A Mode (Table 101)
Default: “00” (Mode 0)
BCKPA: BICKA Polarity of PCM I/F A (Table 105)
“0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”). (default)
“1”: SDTOA is output by the falling edge (“↓”) of BICKA and SDTIA is latched by the rising edge (“↑”).
MSBSA: SYNCA Phase of PCM I/F A (Table 105)
“0”: The rising edge (“↑”) of SYNCA is half clock of BICKA before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCA is one clock of BICKA before the channel change.
BCKO2: BICKA/B Output Frequency Select at Master Mode (Table 96)
0: 16fs2 (default)
1: 32fs2
SDOAD: SDTOA Disable (Table 56.)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
55H
Register Name
PCM I/F Control 3
R/W
Default
D7
SDOBD
R/W
0
D6
PLLBT3
R/W
0
D5
MSBSB
R/W
0
D4
BCKPB
R/W
0
D3
LAWB1
R/W
0
D2
LAWB0
R/W
0
D1
FMTB1
R/W
0
D0
FMTB0
R/W
0
FMTB1-0: PCM I/F B Format (Table 104)
Default: “00” (Mode 0)
LAWB1-0: PCM I/F B Mode (Table 102)
Default: “00” (Mode 0)
BCKPB: BICKB Polarity of PCM I/F B (Table 106)
“0”: SDTOB is output by the rising edge (“↑”) of BICKB and SDTIB is latched by the falling edge (“↓”). (default)
“1”: SDTOB is output by the falling edge (“↓”) of BICKB and SDTIB is latched by the rising edge (“↑”).
MSBSB: SYNCB Phase of PCM I/F B (Table 106)
“0”: The rising edge (“↑”) of SYNCB is half clock of BICKB before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCB is one clock of BICKB before the channel change.
PLLBT3: PLLBT Reference Clock Select
PLLBT2-0 bits is D5-3 of Addr=53H.
Default: “0000”: SYNCA
SDOBD: SDTOB Disable (Table 58)
“0”: Enable (default)
“1”: Disable (“L”)
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[AK4675]
Addr
56H
Register Name
Digital Volume B Control
R/W
Default
D7
BVL7
R/W
0
D6
BVL6
R/W
0
D5
BVL5
R/W
0
D4
BVL4
R/W
1
D3
BVL3
R/W
1
D2
BVL2
R/W
0
D1
BVL1
R/W
0
D0
BVL0
R/W
0
D6
CVL6
R/W
0
D5
CVL5
R/W
0
D4
CVL4
R/W
1
D3
CVL3
R/W
1
D2
CVL2
R/W
0
D1
CVL1
R/W
0
D0
CVL0
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
SDOA
R/W
0
D2
SVB2
R/W
0
D1
SVB1
R/W
0
D0
SVB0
R/W
0
D5
SDOL1
R/W
0
D4
SDOL0
R/W
0
D3
BVMX1
R/W
0
D2
BVMX0
R/W
0
D1
SBMX1
R/W
0
D0
SBMX0
R/W
0
BVL7-0: Digital Volume B (Table 38)
Default: “18H” (0dB)
Addr
57H
Register Name
Digital Volume C Control
R/W
Default
D7
CVL7
R/W
0
CVL7-0: Digital Volume B (Table 39)
Default: “18H” (0dB)
Addr
58H
Register Name
Side Tone Volume Control
R/W
Default
D7
0
RD
0
SVB2-0: Side Tone Volume (Table 40)
Default: “5H” (−12dB)
SDOA: SDTOA Output Signal Select (Table 55.)
“0”: SRC-A (default)
“1”: SDTI-B
Addr
59H
Register Name
Digital Mixing Control
R/W
Default
D7
SDOR1
R/W
0
D6
SDOR0
R/W
0
SBMX1-0: SDTOB Output Signal Select (Table 57.)
Default: “00” (SDTIA)
BVMX1-0: SRC-B Input Signal Select (Table 59.)
Default: “00” (SDTIA)
SDOL1-0: SDTO Lch Output Mixing (Table 45.)
Default: “00” (Lch Signal Selected by Table 44)
SDOR1-0: SDTO Rch Output Mixing (Table 46.)
Default: “00” (Rch Signal Selected by Table 44)
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[AK4675]
Addr
5AH
Register Name
SAR ADC Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
GPOM1
R/W
0
D3
GPOE1
R/W
0
D2
A1
R/W
0
D1
A0
R/W
0
D0
PMSAD
R/W
0
PMSAD: 10bit ADC Power Management
“0”: Power down (default)
“1”: Power up
A1-0: SAR ADC Measurement Mode (Table 113)
Default: “00” (SAIN1)
GPOE1: General Purpose Output 1 Enable at GPOM1 bit = “1”
“0”: GPO pin = “L” (default)
“1”: GPO pin = “H”
GPOM1: General Purpose Output 1 Operation Mode
“0”: Controlled by GPOE1 bit (default)
“1”: Controlled by A0 bit
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[AK4675]
■ Register Map (HP/SPK-Amp Blocks)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
Register Name
Power Management 0
Power Management 1
Power Management 2
Mode Control 0
Lch Headphone Mixer
Rch Headphone Mixer
Reserved
Reserved
Input Volume #1
Reserved
Reserved
Reserved
Mode Control 1
Headphone PGA Control
Speaker PGA Control
ALCA Mode Control 1
ALCA Mode Control 2
ALCA Mode Control 3
Mode Control 2
D7
0
D6
D5
D4
D3
PMMHR
PMMHL
PMHPR
0
0
THDET
0
0
0
0
0
0
0
PMHPL
0
0
0
0
0
0
0
0
0
R1V3
0
0
0
0
0
0
R1V2
0
0
0
0
0
0
0
0
0
0
0
R1V1
0
0
0
0
R1V0
0
0
0
0
L1V3
0
0
0
0
L1V2
0
0
0
0
L1V1
0
0
0
0
L1V0
0
0
0
MOFF
0
0
HPZ
0
HPMTN
0
HPGA4
SPGA4
PTS1
HPGA3
SPGA3
PTS0
HPGA2
SPGA2
0
HPGA1
SPGA1
0
HPGA0
SPGA0
0
0
0
0
REFA5
0
REFA4
REFA3
REFA2
REFA1
REFA0
ZTMA1
ZTMA0
WTMA2
WTMA1
WTMA0
0
0
ALCA
0
ZELMNA
LMATA1
LMATA0
RGAINA1
RGAINA0
LMTHA
0
0
0
BATCPU
MSEL
OSCN
GDDLY
SPGA5
D2
PMCP
D1
D0
PMVCMA
0
PMOSC
0
PMSPK
0
0
0
0
0
0
0
PMV1
0
0
0
0
0
0
0
HPLR1
HPRR1
HPLL1
HPRL1
All registers writing are inhibited at PDNA pin = “L”.
The PDNA pin = “L” resets the HP/SPK-Amp’s registers to their default value.
Note 88: The bits defined as 0 must contain a “0” value.
Note 89: Only write to address 00H to 12H.
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[AK4675]
■ Register Definitions (HP/SPK-Amp Blocks)
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
PMMHR
PMMHL
PMHPR
PMHPL
PMCP
PMOSC
PMVCMA
RD
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PMVCMA: Power Management for VCOM and Regulator which used for Headphone-Amp
0: Power OFF (default)
1: Power ON
PMOSC: I Power Management for Internal Oscillator
0: Power OFF (default)
1: Power ON
PMCP: Power Management for Charge Pump Circuit
0: Power OFF (default)
1: Power ON
PMHPL: Power Management for Lch Headphone-Amp
0: Power OFF (default)
1: Power ON
PMHPR: Power Management for Rch Headphone-Amp
0: Power OFF (default)
1: Power ON
PMMHL: Power Management for Mixing & Selector Circuit of Lch Headphone-Amp
0: Power OFF (default)
1: Power ON
PMMHR: Power Management for Mixing & Selector Circuit of Rch Headphone-Amp
0: Power OFF (default)
1: Power ON
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[AK4675]
Addr
01H
Register Name
Power Management 1
R/W
Default
D7
GDDLY
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
D2
0
0
RD
0
RD
0
D1
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
PMSPK
R/W
0
PMSPK: Power Management for Speaker-Amp
0: Power OFF (default)
1: Power ON
When PMSP bit is “0”, the SPP pin and SPN pin become Hi-Z.
GDDLY: Gate driver delay setting for dulling output wave of Class-D
0: 15ns (default)
1: 60ns
Delay increase, EMI improve, Efficiency down when “0” Æ “1”
Addr
02H
Register Name
Power Management 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D0
PMV1
R/W
0
PMV1: Power Management for Input Volume #1
0: Power OFF (default)
1: Power ON
All blocks of HP/SPK-Amp blocks can be powered-down by setting the PDNA pin to “L” regardless of register
values setup. In this case, all control register values of HP/SPK-Amp blocks are initilized.
When all registers in address 00H, 01H and 02H are set to “0”, all blocks of HP/SPK-Amp blocks are
powered-down. The register values of HP/SPK-Amp blocks remain unchanged. Power supply current is 18μA(typ).
For fully shut down, set the PDNA pin to “L”.
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[AK4675]
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
D7
0
0
RD
0
D6
0
0
RD
0
D5
0
0
RD
0
D4
0
0
RD
0
D3
0
0
RD
0
D2
0
0
RD
0
D1
HPLR1
HPRR1
R/W
0
D0
HPLL1
HPRL1
R/W
0
D7
R1V3
R/W
1
D6
R1V2
R/W
0
D5
R1V1
R/W
1
D4
R1V0
R/W
0
D3
L1V3
R/W
1
D2
L1V2
R/W
0
D1
L1V1
R/W
1
D0
L1V0
R/W
0
THDET
RD
0
THDET: Thermal Shutdown Detection
0: Normal Operation (default)
1: Thermal Shutdown
Addr
04H
05H
Register Name
Lch Headphone Mixer
Rch Headphone Mixer
R/W
Default
Input Mixers: (Figure 80)
0: OFF (default)
1: ON
Addr
08H
Register Name
Input Volume #1
R/W
Default
Input Volumes: Default: 0dB (Table 76)
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[AK4675]
Addr
0CH
Register Name
Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
MOFF
R/W
0
D4
0
RD
0
D3
PTS1
R/W
0
D2
PTS0
R/W
0
D1
0
RD
0
D0
0
RD
0
D4
HPGA4
R/W
1
D3
HPGA3
R/W
1
D2
HPGA2
R/W
0
D1
HPGA1
R/W
0
D0
HPGA0
R/W
1
D3
SPGA3
R/W
1
D2
SPGA2
R/W
0
D1
SPGA1
R/W
0
D0
SPGA0
R/W
0
PTS1-0: Headphone-Amp Mute ON/OFF Transition Time
Default: “00”; typ. 16.4ms (Table 81)
MOFF: Soft transition for changing HPMTN bit
0: Enable (default)
1: Disable
Addr
0DH
Register Name
Headphone PGA Control
R/W
Default
D7
0
RD
0
D6
HPZ
R/W
0
D5
HPMTN
R/W
0
HPGA4-0: Headphone-Amp Volume Setting
Default: 19H; 0dB (Table 77)
HPMTN: Headphone-Amp Mute
0: Mute (default)
1: Normal Output
HPZ: Headphone-Amp Pull-down Control
0: Ground Mode (default)
HPL/HPR pins are shorted to VSS3.
1: Hi-Z Mode
HPL/HPR pins are pulled-down by 25kΩ(typ) to VSS3.
Addr
0EH
Register Name
Speaker PGA Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
SPGA5
R/W
0
D4
SPGA4
R/W
1
SPGA5-0: Speaker-Amp Volume Setting
Default: 18H; 0dB (Table 89)
When PMSPK bit is set to “0”, reading and writing of SPGA5-0 bits are inhibited. When changing from
PMSPK bit = “0” to PMSPK bit = “1”, SPGA volume becomes default value (0dB) regardless of the setting
of SPGA5-0 bits.
Addr
0FH
Register Name
ALCA Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
REFA5
R/W
1
D4
REFA4
R/W
1
D3
REFA3
R/W
1
D2
REFA2
R/W
1
D1
REFA1
R/W
0
D0
REFA0
R/W
0
REFA5-0: Reference value at ALC Recovery Operation
Default: 3CH; +18dB (Table 87)
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[AK4675]
Addr
10H
Register Name
ALCA Mode Control 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
D3
D2
D1
D0
ZTMA1
ZTMA0
WTMA2
WTMA1
WTMA0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
WTMA2-0: ALCA Recovery Waiting Period
Default: “101”, typ. 524.8ms (@OSCN bit = “0”) (Table 85)
ZTMA1-0: ALCA Zero Crossing Timeout Period
Default: “01”, typ. 32.8ms (@ OSCN bit = “0”) (Table 84)
Addr
11H
Register Name
ALCA Mode Control 3
R/W
Default
D7
0
RD
0
D6
ALCA
R/W
0
D5
D4
D3
D2
D1
D0
ZELMNA
LMATA1
LMATA0
RGAINA1
RGAINA0
LMTHA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
LMTHA: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level
Default: “0” (Table 82)
RGAINA1-0: ALCA Recovery GAIN Step
Default: “00”; 1 step (Table 86)
LMATA1-0: ALCA Limiter ATT Step
Default: “00”; 1 step (Table 83)
ZELMNA: Zero Crossing Detection Enable at ALCA Limiter Operation
0: Enable (default)
1: Disable
ALCA: ALCA Enable
0: ALCA Disable (default)
1: ALCA Enable
When ALC bit is set to “1”, the ALCA operation is enabled. The initial value is “0” (Disable).
Addr
12H
Register Name
Mode Control 2
R/W
Default
D7
D6
0
0
RD
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
BATCPU
R/W
0
D1
MSEL
R/W
0
D0
OSCN
R/W
0
OSCN: Internal Oscillator / External Clock Select
0: Internal Oscillator (default)
1: External Clock (MCKIA pin)
MSEL: MCKIA Input Frequency Select
0: 2.048MHz (default)
1: 2.8224MHz or 3.072MHz
BATCPU: Battery Monitor Circuit Enable
0: Disable (default)
1: Enable
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[AK4675]
SYSTEM DESIGN
Figure 114 shows the system connection diagram for the AK4675. An evaluation board [AKD4675] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
Condition: Internal Full-differential Mic, External pseudo differential Mic, Receiver Output, I²C mode; Battery Monitor
is used; the PDNA pin of HP/SPK-Amp blocks is controlled by the GPO1 pin.
Analog
Ground
Headphone
10u
0.1u
0.1u
Base Band
2.2u
C
Cp
Rp
0.1u
R
0.1u
2.2u
Digital
(Base Band)
1.6 ∼ 3.6V
2.2u
Analog
2.6 ∼ 3.6V
Digital
Ground
2.2u
Battery
TEST
HPR
VCOM
VCOC
AVDD
RCN
VBATO VCOCBT
HPL
PVDDA
VSS3A
CP
SDTIA
GPO2
PVEE
SDTOA
SYNCA
CN
PDNA
BICKA
Receiver
0.1u
0.1u
0.1u
VSS1
Line In
0.22u
DC
Measurement
ROUT3 VCOMA
RIN4
PVDD
TVDD2
TVDDA
VSS4
MCKIA
TEST6
DVDD
SDA
MCKO
NC
SCL
VBATIN
LOUT3
LIN3
RCP
LIN4
RIN1A
RIN3
IN2−
SAIN2
MCKI
TEST5
BICK
IN2+
SAIN3
SAIN1
LRCK
PDN
VSS1A
IN1+
IN1−
AK4675EG
Digital
(μP & CPU)
1.6 ∼ 3.6V
μP
Top View
LIN1A
MPWR ROUT2S
SAVDD
SDTOB
SDTO
BICKB
NC
TEST3
AVDDA
NC
VSS3
SPN
SYNCB
SDTIB
TEST4
SPIN
SVDDA
VSS2A
TVDD3
SPP
TEST2
SDTI
GPO1
0.1u
CPU
1k
0.22u
1k
2.2k
Internal MIC
0.1u
External MIC
MDT
LOUT2S
NC
0.1u
Battery or
AC Adaptor
3.0 ∼ 5.5V
VSS2
0.1u
Bluetooth
Module
10u
Digital
(Bluetooth)
1.6 ∼ 3.6V
Speaker
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[AK4675]
Notes:
- VSS1, VSS2, VSS3, VSS4, VSS1A, VSS2A and VSS3A of the AK4675 must be distributed separately from
the ground of external controllers.
- All digital input pins msut not be left floating.
- When the AK4675 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK4675 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4.
- When the AK4675 is in master mode, the LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor msut be connected to the LRCK and BICK pins of the AK4675.
- A resistor and capacitor of the VCOCBT pin is shown in Table 95.
- When PCM I/F is used at master mode, SYNCA, BICKA, SYNCB and BICKB pins are floating before
PMPCM bit is changed to “1”. Therefore, 100kΩ around pull-up or pull-down resistor msut be connected to the
SYNCA, BICKA, SYNCB and SYNCB pins of the AK4675.
- These capacitors at the CP/CN pins and VSS3A/PVEE pins require low ESR (Equivalent Series Resistance)
over all temperature range. When these capacitors are polarized, the positive side must be connected to the CP
and VSS3A pins, respectively.
- A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates
the effects of high frequency noise. No load current may be drawn from the VCOM pin.
- A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOMA pin eliminates
the effects of high frequency noise. No load current may be drawn from the VCOMA pin.
- AC coupling capacitors of 0.22μF or smaller value msut be connected at the LIN1A/RIN1A pins respectively to
reduce pop noise at Headphone-Amp power-up.
- AC coupling capacitors of 0.1μF or smaller value must be connected at the SPIN pins respectively to reduce
pop noise at power-up of ALCA block for Speaker.
Figure 114. Typical Connection Diagram
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[AK4675]
1. Grounding and Power Supply Decoupling
The AK4675 requires careful attention to power supply and grounding arrangements. AVDD, PVDD, SAVDD, DVDD,
TVDD2, TVDD3, AVDDA, PVDDA, SVDDA and TVDDA are usually supplied from the system’s analog supply.
TVDDA must be connected to DVDD. If AVDD, PVDD, SAVDD, DVDD, TVDD2, AVDDA, PVDDA and SVDDA
are supplied separately, the power-up sequence is not critical. VSS1, VSS2, VSS3, VSS4, VSS1A, VSS2A and VSS3A of
the AK4675 must be connected to the analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4675 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of CODEC block. VCOMA is a signal ground of HP/SPK-Amp blocks. A 2.2μF electrolytic
capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency
noise. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOMA pin eliminates the
effects of high frequency noise. No load current may be drawn from the VCOM/VCOMA pins. All signals, especially
clocks, should be kept away from the VCOM and VCOMA pins in order to avoid unwanted coupling into the AK4675.
3. Analog Inputs
The Mic, Line and MIN inputs of CODEC block are single-ended. The input signal range scales with nominally at 0.6 x
AVDD Vpp (typ) at MGNL=MGNR=0dB and single-ended input, centered at the internal common voltage of CODEC
block (0.5 x AVDD). The inputs of HP/SPK-Amp blocks are single-ended. The input signal range is 2.0Vpp (typ) for
LIN1A/RIN1A pins and 1.6Vpp (typ) for SPLIN/SPRIN pins respectively, centered at the internal common voltage of
HP/SPK-Amp blocks (VCOMA=1.2V (typ)). The input signal should be AC coupled using a capacitor. The cut-off
frequency is fc = 1/ (2πRC). The AK4675 can accept input voltages from VSS1 to AVDD for CODEC block and from
VSS1A to AVDDA for HP/SPK-Amp blocks, respectively.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). The ideal output for 0000H(@16bit) is VCOM voltage for CODEC block and
VCOMA voltage for HP/SPK-Amp blocks, respectively. VCOM voltage is 0.5 x AVDD (typ) and VCOMA voltage is
1.2Vpp (typ), respectively. The output of LOUT1/RCP, ROUT1/RCN, LOUT2S, ROUT2S, LOUT3/LOP, ROUT3/LON
pins must be AC coupled using a capacitor. The output of HPL and HPR pins must be directly connected to the headphone
without AC coupling.
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[AK4675]
PACKAGE
5.5 ± 0.1
φ 0.05
A
83 - φ 0.3 ± 0.05
M S AB
5 4 3 2 1
A
B
C
D
E
4.5
5.5 ± 0.1
10 9 8 7 6
B
F
G
H
J
K
0.5
0.5
S
1.2MAX
0.25 ± 0.05
0.08 S
„ Material & Lead finish
Package molding compound:
Interposer material:
Solder ball material:
Epoxy
BT resin
SnAgCu
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[AK4675]
MARKING
4675
XXXXX
1
XXXXX: Date code identifier (5digits)
Pin #1 indication
REVISION HISTORY
Date (YY/MM/DD)
08/05/23
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
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