LINER LTC2294 Dual 12-bit, 80msps low power 3v adc Datasheet

LTC2294
Dual 12-Bit, 80Msps
Low Power 3V ADC
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FEATURES
DESCRIPTIO
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The LTC®2294 is a 12-bit 80Msps, low power dual 3V
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2294 is perfect for
demanding imaging and communications applications
with AC performance that includes 70.6dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
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Integrated Dual 12-Bit ADCs
Sample Rate: 80Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 422mW
70.6dB SNR at 70MHz Input
90dB SFDR at 70MHz Input
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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APPLICATIO S
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Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
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TYPICAL APPLICATIO
+
ANALOG
INPUT A
INPUT
S/H
–
SNR vs Input Frequency,
–1dB, 2V Range
OVDD
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D11A
75
•
••
74
D0A
73
OGND
CLOCK/DUTY CYCLE
CONTROL
CLK B
CLOCK/DUTY CYCLE
CONTROL
MUX
SNR (dBFS)
CLK A
72
71
70
69
68
67
66
OVDD
+
ANALOG
INPUT B
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D11B
•
••
D0B
65
0
100
50
150
INPUT FREQUENCY (MHz)
200
2294 TA02
OGND
2294 TA01
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LTC2294
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PACKAGE/ORDER I FOR ATIO
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ABSOLUTE
AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2294C ............................................... 0°C to 70°C
LTC2294I .............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
64 GND
63 VDD
62 SENSEA
61 VCMA
60 MODE
59 SHDNA
58 OEA
57 OFA
56 DA11
55 DA10
54 DA9
53 DA8
52 DA7
51 DA6
50 OGND
49 OVDD
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
REFHA 4
REFLA 5
REFLA 6
VDD 7
CLKA 8
CLKB 9
VDD 10
REFLB 11
REFLB 12
REFHB 13
REFHB 14
AINB– 15
AINB+ 16
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
41 NC
40 OFB
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5
GND 17
VDD 18
SENSEB 19
VCMB 20
MUX 21
SHDNB 22
OEB 23
NC 24
NC 25
DB0 26
DB1 27
DB2 28
DB3 29
DB4 30
OGND 31
OVDD 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
LTC2294IUP
LTC2294CUP
QFN PART*
MARKING
LTC2294UP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
CONDITIONS
MIN
●
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
External Reference
Internal Reference
External Reference
External Reference
SENSE = 1V
●
●
●
●
12
–1.4
–0.8
–12
–2.5
TYP
MAX
±0.4
±0.2
±2
±0.5
±10
±30
±5
±0.3
±2
0.3
1.4
0.8
12
2.5
UNITS
Bits
LSB
LSB
mV
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSBRMS
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LTC2294
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIN
Analog Input Range (AIN+ –AIN–)
VIN,CM
Analog Input Common Mode (AIN+
CONDITIONS
+AIN
–)/2
MIN
2.7V < VDD < 3.4V (Note 7)
●
TYP
MAX
UNITS
±0.5 to ±1
V
Differential Input (Note 7)
●
1
1.5
1.9
V
Single Ended Input (Note 7)
●
0.5
1.5
2
V
0V < AIN+, AIN–
●
–1
1
µA
IIN
Analog Input Leakage Current
ISENSE
SENSEA, SENSEB Input Leakage
0V < SENSEA, SENSEB < 1V
●
–3
3
µA
IMODE
MODE Input Leakage Current
0V < MODE < VDD
●
–3
3
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
575
MHz
Full Power Bandwidth
< VDD
0
Figure 8 Test Circuit
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
Spurious Free Dynamic Range
4th Harmonic or Higher
UNITS
70.6
dB
70MHz Input
70.6
dB
140MHz Input
70.3
dB
90
dB
●
69.1
5MHz Input
40MHz Input
●
90
dB
70MHz Input
74
90
dB
140MHz Input
85
dB
5MHz Input
40MHz Input
●
79
140MHz Input
90
dB
90
dB
90
dB
90
dB
70.6
dB
70.5
dB
70MHz Input
70.5
dB
140MHz Input
70
dB
Intermodulation Distortion
fIN = 40MHz, 41MHz
90
dB
Crosstalk
fIN = 100MHz
–110
dB
Signal-to-Noise Plus Distortion Ratio
5MHz Input
40MHz Input
IMD
MAX
dB
70MHz Input
S/(N+D)
TYP
70.6
40MHz Input
SFDR
MIN
●
68.7
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I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.475
1.500
1.525
V
±25
VCM Output Tempco
ppm/°C
VCM Line Regulation
2.7V < VDD < 3.4V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
VIH
High Level Input Voltage
VDD = 3V
●
VIL
Low Level Input Voltage
VDD = 3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
2
V
–10
0.8
V
10
µA
3
pF
LOGIC OUTPUTS
OVDD = 3V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
●
IO = 10µA
IO = 1.6mA
●
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
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LTC2294
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 9)
OVDD
Output Supply Voltage
IVDD
Supply Current
PDISS
UNITS
●
2.7
3
3.4
(Note 9)
●
0.5
3
3.6
V
Both ADCs at fS(MAX)
●
141
165
mA
Power Dissipation
Both ADCs at fS(MAX)
●
422
495
mW
PSHDN
Shutdown Power (Each Channel)
SHDN = H, OE = H, No CLK
2
mW
PNAP
Nap Mode Power (Each Channel)
SHDN = H, OE = L, No CLK
15
mW
V
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fs
Sampling Frequency
(Note 9)
●
MIN
1
TYP
MAX
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
●
●
5.9
5
tAP
Sample-and-Hold Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
tMD
MUX to DATA Delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
Data Access Time After OE↓
CL = 5pF (Note 7)
●
4.3
10
ns
BUS Relinquish Time
(Note 7)
●
3.3
8.5
MHz
6.25
6.25
500
500
ns
ns
6.25
6.25
500
500
ns
ns
0
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
UNITS
80
5
ns
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
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LTC2294
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TYPICAL PERFOR A CE CHARACTERISTICS
Crosstalk vs Input Frequency
Typical INL, 2V Range, 80Msps
–110
–115
–120
0.8
0.8
0.6
0.6
0.4
0.4
DNL ERROR (LSB)
INL ERROR (LSB)
CROSSTALK (dB)
–105
0.2
0
–0.2
–0.4
–130
0
20
–0.4
–0.8
–1.0
–1.0
0
1024
2048
4096
3072
0
8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range, 80Msps
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, 80Msps
0
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
–90
–40
AMPLITUDE (dB)
AMPLITUDE (dB)
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–100
–100
–100
–110
–110
–110
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
–120
40
0
5
10
15 20 25 30
FREQUENCY (MHz)
2294 G04
0
–10
–20
–20
–30
–30
–40
–40
–50
–60
–70
–80
–90
–70
–100
40
2294 G07
–120
35
40
116838
100000
–80
–110
35
15 20 25 30
FREQUENCY (MHz)
120000
–60
–100
15 20 25 30
FREQUENCY (MHz)
10
140000
–50
–110
10
5
Grounded Input Histogram,
80Msps
80000
60000
40000
–90
5
0
2294 G06
COUNT
AMPLITUDE (dB)
0
0
–120
40
8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range
–10
–120
35
2294 G05
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, 80Msps
4096
3072
2294 G03
–10
–50
2048
CODE
2294 G02
8192 Point FFT, fIN = 5MHz, –1dB,
2V Range, 80Msps
–120
1024
CODE
2294 G01
AMPLITUDE (dB)
0
–0.2
–0.8
100
40
60
80
INPUT FREQUENCY (MHz)
0.2
–0.6
–0.6
–125
AMPLITUDE (dB)
Typical DNL, 2V Range, 80Msps
1.0
1.0
–100
20000
8522
5712
0
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
2050
2051
2052
CODE
2294 G08
2294 G09
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LTC2294
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TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Input Frequency, –1dB,
2V Range, 80Msps
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
SFDR vs Input Frequency, –1dB,
2V Range, 80Msps
75
100
100
74
95
SFDR (dBFS)
SNR (dBFS)
SNR AND SFDR (dBFS)
90
72
71
70
69
68
85
80
75
80
SNR
70
60
67
70
66
65
65
50
100
50
200
150
INPUT FREQUENCY (MHz)
0
200
100
50
150
INPUT FREQUENCY (MHz)
0
SNR and SFDR vs Clock Duty
Cycle, 80Msps
2294 G12
SNR vs Input Level, fIN = 70MHz,
2V Range, 80Msps
95
SFDR vs Input Level, fIN = 70MHz,
2V Range, 80Msps
120
80
dBFS
SFDR: DCS ON
80
75
50
30
SNR: DCS ON
10
40
45
50
55
60
CLOCK DUTY CYCLE (%)
65
70
dBFS
90
80
dBc
70
100dBc SFDR
REFERENCE LINE
60
50
40
30
20
10
0
–70
–60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
–10
2294 G13
0
0
–70
–60
–50 –40 –30 –20
INPUT LEVEL (dBFS)
2294 G14
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
165
14
155
12
145
2V RANGE
135
1V RANGE
0
2294 G15
10
8
125
6
115
4
105
2
95
–10
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
IOVDD (mA)
35
dBc
40
SNR: DCS OFF
IVDD (mA)
30
60
20
65
100
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)
SFDR: DCS OFF
70
110
70
90
85
0 10 20 30 40 50 60 70 80 90 100 110
SAMPLE RATE (Msps)
2294 G11
2294 G10
SNR AND SFDR (dBFS)
SFDR
90
73
0
0 10 20 30 40 50 60 70 80 90 100
SAMPLE RATE (Msps)
2294 G16
0 10 20 30 40 50 60 70 80 90 100
SAMPLE RATE (Msps)
2294 G17
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LTC2294
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PI FU CTIO S
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
GND (Pins 17, 64): ADC Power Ground.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
OGND (Pins 31, 50): Output Driver Ground.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
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LTC2294
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PI FU CTIO S
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabi-
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
W
FUNCTIONAL BLOCK DIAGRA
U
U
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
D11
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
D0
REFH
0.1µF
2294 F01
REFL
OGND
CLK
MODE
SHDN
OE
2.2µF
1µF
1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
2294fa
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LTC2294
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TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
tAP
ANALOG
INPUT
N+4
N+2
N
N+1
tH
N+3
N+5
tL
CLK
tD
D0-D11, OF
N–4
N–5
N–3
N–2
N–1
N
2294 TD01
Multiplexed Digital Output Bus Timing
tAPA
ANALOG
INPUT A
A+4
A+2
A
A+1
A+3
tAPB
ANALOG
INPUT B
B+4
B+2
B
B+1
tH
tL
A–5
B–5
B+3
CLKA = CLKB = MUX
D0A-D11A, OFA
A–4
tD
D0B-D11B, OFB
B–5
B–4
A–3
B–3
A–2
B–2
B–3
A–3
B–2
A–2
A–1
t MD
A–5
B–4
A–4
B–1
2294 TD02
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DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Intermodulation Distortion
Crosstalk
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
CONVERTER OPERATION
As shown in Figure 1, the LTC2294 is a dual CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive
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applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2294 has two phases of operation,
determined by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2294
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (CPARASITIC) are the summation of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
LTC2294
VDD
AIN+
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
CLK
2294 F02
Figure 2. Equivalent Input Circuit
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capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2294 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
VCM
2.2µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2294
0.1µF
12pF
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2294 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
25Ω
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
2294 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
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VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
2.2µF
AIN+
2.2µF
0.1µF
LTC2294
12Ω
ANALOG
INPUT
25Ω
+
CM
–
VCM
25Ω
0.1µF
AIN–
LTC2294
0.1µF
T1
12pF
–
AIN+
8pF
25Ω
12Ω
AIN–
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2294 F04
2294 F06
Figure 4. Differential Drive with an Amplifier
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
VCM
2.2µF
VCM
1k
0.1µF
ANALOG
INPUT
1k
25Ω
0.1µF
AIN+
ANALOG
INPUT
2.2µF
25Ω
AIN+
T1
LTC2294
0.1µF
12pF
25Ω
25Ω
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
0.1µF
LTC2294
0.1µF
AIN–
2294 F07
2294 F05
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 5. Single-Ended Drive
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
VCM
2.2µF
0.1µF
6.8nH
ANALOG
INPUT
25Ω
AIN+
LTC2294
0.1µF
T1
0.1µF
25Ω
6.8nH
–
AIN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
2294 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
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Reference Operation
Figure 9 shows the LTC2294 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
LTC2294
1.5V
VCM
4Ω
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
For the best channel matching, connect an external reference
to SENSEA and SENSEB.
1.5V BANDGAP
REFERENCE
1.5V
2.2µF
VCM
0.5V
1V
2.2µF
12k
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
RANGE
DETECT
AND
CONTROL
0.75V
12k
LTC2294
SENSE
1µF
SENSE
2294 F10
BUFFER
INTERNAL ADC
HIGH REFERENCE
1µF
Figure 10. 1.5V Range ADC
REFH
Input Range
2.2µF
0.1µF
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 4dB. See the Typical Performance Characteristics section.
DIFF AMP
1µF
REFL
INTERNAL ADC
LOW REFERENCE
2294 F09
Driving the Clock Input
Figure 9. Equivalent Reference Circuit
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low jitter squaring circuit before the CLK pin (Figure 11).
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CLEAN
SUPPLY
4.7µF
SINUSOIDAL
CLOCK
INPUT
0.1µF
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
FERRITE
BEAD
0.1µF
0.1µF
1k
CLK
LTC2294
CLK
100Ω
50Ω
1k
LTC2294
NC7SVU04
2294 F11
Figure 11. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2294 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large
bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
2294 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
ETC1-1T
CLK
LTC2294
5pF-30pF
DIFFERENTIAL
CLOCK
INPUT
2294 F13
0.1µF
FERRITE
BEAD
VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2294 is 80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have
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at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on or off for
both channels.
The lower limit of the LTC2294 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency for the LTC2294 is 1Msps.
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
LTC2294
OVDD
VDD
0.5V
TO 3.6V
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
2294 F14
Figure 14. Digital Output Buffer
OF
D11 – D0
(OFFSET BINARY)
D11 – D0
(2’s COMPLEMENT)
As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital
outputs of the LTC2294 should drive a minimal capacitive
load to avoid possible interaction between the digital
outputs and sensitive input circuitry. The output should be
buffered with a device such as an ALVCH16373 CMOS
latch. For full speed operation the capacitive load should
be kept under 10pF.
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
Lower OVDD voltages will also help reduce interference
from the digital outputs.
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
Data Format
Using the MODE pin, the LTC2294 parallel digital output
can be selected for offset binary or 2’s complement
format. Note that MODE controls both Channel A and
Channel B. Connecting MODE to GND or 1/3VDD selects
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offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
Table 2. MODE Pin Function
OUTPUT FORMAN
CLOCK DUTY
CYCLE STABILIZER
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
MODE PIN
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2294 can be multiplexed onto
a single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is High, Channel A comes out
on DA0-DA11, OFA; Channel B comes out on DB0-DB11,
OFB. If MUX is Low, the output busses are swapped and
Channel A comes out on DB0-DB11, OFB; Channel B comes
out on DA0-DA11, OFA. To multiplex both channels onto
a single output bus, connect MUX, CLKA and CLKB together
(see the Timing Diagram for the multiplexed mode). The
multiplexed data is available on either data bus—the unused data bus can be disabled with its OE pin.
Grounding and Bypassing
The LTC2294 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed
2294fa
18
LTC2294
U
W
U
U
APPLICATIO S I FOR ATIO
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF
capacitor between REFH and REFL can be somewhat
further away. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC2294 differential inputs should run parallel
and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2294 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
2294fa
19
R14
49.9Ω
C19
0.1µF
2
5
R10
1k
ASSEMBLY TYPE
DC851A-H
DC851A-M
2
5
2
4
4
5
VDD
5
4
•
E5
PWR
GND
E3
VDD
3V
2
C6, C31
12pF
8pF
C31
*
VDD
E2
EXT
REF B
VCMB
VDD
VCM
VDD
4
2
INPUT FREQUENCY
fIN < 70MHz
fIN > 70MHz
C48
0.1µF
EXT REF
5
6
3
1
C2
2.2µF
C27
0.1µF
JP3 SENSE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AINA+
AINA–
REFHA
REFHA
REFLA
REFLA
VDD
CLKA
CLKB
VDD
REFLB
REFLB
REFHB
REFHB
AINB–
AINB+
C1
0.1µF
VDD
C47
0.1µF
C21
0.1µF
C11
0.1µF
C4
0.1µF
VCMB
8
6
4
2
VCC
C41
0.1µF
T1, T2
ETC1-1T
ETC1-1-13
C40
0.1µF
R24
*
C34
0.1µF
R22
24.9Ω
C23 1µF
•3
R18
*
GND
1/3VDD
2/3VDD
VDD
C20
2.2µF
C18 1µF
R39
OPT
VDD
7
5
3
1
C10
2.2µF
C9 1µF
R3
1k
R2
1k
R1
1k
C13 1µF
R20
24.9Ω
VDD
C6
*
1
R23
51
T2
*
R32
OPT
C36
4.7µF
VCMB
C33
0.1µF
C29
0.1µF
R16
33Ω
C17
0.1µF
C14
0.1µF
C8
0.1µF
VDD
R9
*
R7
24.9Ω
•3
R8
51
2
R6
24.9Ω
R5
*
C44
0.1µF
1
C22
0.1µF
•
T1
*
R5, R9, R18, R24
24.9Ω
12.4Ω
C45
100µF
6.3V
OPT
U1
LTC2294IUP
LTC2294IUP
+
J4
R17
ANALOG OPT
INPUT B
4
VCMA
C7
0.1µF
U6 3
NC7SVU04
4
VDD
VCM
EXT REF
5
6
3
1
C3
0.1µF
C15
0.1µF
C12
4.7µF
6.3V
R15 3
1k
U3
NC7SVU04
*VERSION TABLE
J3
CLOCK
INPUT
VDD
L1
BEAD
J2
ANALOG R4
INPUT A OPT
VCMA
E1
EXT
REF A
VDD
JP2 SENSEA
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LTC2294
C37
10µF
6.3V
C35
0.1µF
C28
2.2µF
R26
100k
R25
105k
C38
0.01µF
4
BYP SHDN
GND GND
GND
IN
U8
LT1763
1
OUT
2
ADJ
3
VCC
VCC
DA5
DA4
DA3
DA2
DA1
DA0
NC
NC
OFB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
GND
VDD
SENSEA
VCMA
MODE
SHDNA
OEA
OFA
DA11
DA10
DA9
DA8
DA7
DA6
OGND
OVDD
GND
VDD
SENSEB
VCMB
MUX
SHDNB
OEB
NC
NC
DB0
DB1
DB2
DB3
DB4
OGND
OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
6
8
7
C25
0.1µF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VCC
C5
0.1µF
C39
1µF
VCC
OE
GND
T/R
B2
OE
A1
A0
GND
T/R
B1
B0
74VCX245BQX
19
18
17
A2
VCC
11
A7
B7
12
A6
B6
13
B5
A5
14
A4
B4
15
U11
B3
A3
16
20
VCC
74VCX245BQX
19
20
VCC
11
A7
B7
12
A6
B6
13
B5
A5
14
A4
B4
15
U10
B3
A3
16
A2
B2
17
A1
B1
18
A0
B0
VCC
74VCX245BQX
RN6A 33Ω
RN6B 33Ω
5
10
1
2
3
4
5
6
7
9
8
10
4
E4
GND
U4
NC7SV86P5X
RN8B 33Ω
RN8A 33Ω
RN7D 33Ω
RN7B 33Ω
RN7C 33Ω
RN7A 33Ω
RN6D 33Ω
2
1
RN6C 33Ω
3
4
6
RN5C 33Ω
RN5D 33Ω
RN5B 33Ω
RN5A 33Ω
7
9
8
VCC
11
9
A7
B7
12
8
A6
B6
13
7
B5
A5
14
6
A4
B4
15
5
U9
B3
A3
16
4
A2
B2
17
3
A1
B1
18
2
B0
A0
1
T/R
19
10
OE GND
20
VCC
74VCX245BQX
RN1A 33Ω
3
5
VCC
1
2
RN4C 33Ω
RN4B 33Ω
RN4A 33Ω
RN3D 33Ω
RN1B 33Ω
RN1C 33Ω
RN1D 33Ω
RN2A 33Ω
RN2B 33Ω
RN2C 33Ω
RN2D 33Ω
RN3A 33Ω
RN3B 33Ω
RN3C 33Ω
C24
0.1µF
R35
100k
33
35
1
A0
2
A1
3
A2
4
A3
C46
0.1µF
R34
4.7k
100
98
94
96
92
84
86
88
90
76
78
80
82
72
74
68
70
64
66
8
VCC
7
WP
6
SCL
5
SDA
R36
4.99k
99
97
93
95
91
83
85
87
89
75
77
79
81
71
73
67
69
63
65
59
61
60
62
53
55
57
54
56
58
45
47
49
51
46
48
50
52
37
39
41
43
34
36
38
40
42
44
25
27
29
31
26
28
30
32
21
23
15
17
19
16
18
20
22
7
9
11
13
8
10
12
14
24
1
3
5
U5
24LC025
J1
EDGE-CON-100
2
4
6
VSS
ENABLE
SDA
VCCIN
SCL
R38
R37
4.99k
R33
4.7k
VCC
U
U
W
20
20
VCC
11
9
A7
B7
12
8
A6
B6
13
7
B5
A5
14
6
A4
B4
15
5
U2
B3
A3
16
4
A2
B2
17
3
A1
B1
18
2
A0
B0
1
T/R
19
10
OE GND
APPLICATIO S I FOR ATIO
2294 AI01
SDA
SCL
VCCIN
VSS
U
JP1 MODE
LTC2294
2294fa
LTC2294
U
W
U
U
APPLICATIO S I FOR ATIO
Silkscreen Top
Top Side
2294fa
21
LTC2294
U
W
U
U
APPLICATIO S I FOR ATIO
Inner Layer 3 Power
Inner Layer 2 GND
Bottom Side
2294fa
22
LTC2294
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
9 .00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
0.25 ± 0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
(UP64) QFN 1003
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
2294fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2294
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2220
12-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2221
12-Bit, 135Msps ADC
630mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2222
12-Bit, 105Msps ADC
475mW, 67.9dB SNR, 7mm × 7mm QFN Package
LTC2223
12-Bit, 80Msps ADC
366mW, 68dB SNR, 7mm × 7mm QFN Package
LTC2224
12-Bit, 135Msps ADC
630mW, 67.5dB SNR, 7mm × 7mm QFN Package
LTC2225
12-Bit, 10Msps ADC
60mW, 71.4dB SNR, 5mm × 5mm QFN Package
LTC2226
12-Bit, 25Msps ADC
75mW, 71.4dB SNR, 5mm × 5mm QFN Package
LTC2227
12-Bit, 40Msps ADC
120mW, 71.4dB SNR, 5mm × 5mm QFN Package
LTC2228
12-Bit, 65Msps ADC
205mW, 71.3dB SNR, 5mm × 5mm QFN Package
LTC2230
10-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2231
10-Bit, 135Msps ADC
630mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2232
10-Bit, 105Msps ADC
475mW, 61.3dB SNR, 7mm × 7mm QFN Package
LTC2233
10-Bit, 80Msps ADC
366mW, 61.3dB SNR, 7mm × 7mm QFN Package
LTC2245
14-Bit, 10Msps ADC
60mW, 74.4dB SNR, 5mm × 5mm QFN Package
LTC2246
14-Bit, 25Msps ADC
75mW, 74.5dB SNR, 5mm × 5mm QFN Package
LTC2247
14-Bit, 40Msps ADC
120mW, 74.4dB SNR, 5mm × 5mm QFN Package
LTC2248
14-Bit, 65Msps ADC
205mW, 74.3dB SNR, 5mm × 5mm QFN Package
LTC2249
14-Bit, 80Msps ADC
222mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2286
10-Bit, Dual, 25Msps ADC
150mW, 61.8dB SNR, 9mm × 9mm QFN Package
LTC2287
10-Bit, Dual, 40Msps ADC
235mW, 61.8dB SNR, 9mm × 9mm QFN Package
LTC2288
10-Bit, Dual, 65Msps ADC
400mW, 61.8dB SNR, 9mm × 9mm QFN Package
LTC2289
10-Bit, Dual, 80Msps ADC
422mW, 61dB SNR, 9mm × 9mm QFN Package
LTC2290
12-Bit, Dual, 10Msps ADC
120mW, 71.3dB SNR, 9mm × 9mm QFN Package
LTC2291
12-Bit, Dual, 25Msps ADC
150mW, 74.5dB SNR, 9mm × 9mm QFN Package
LTC2292
12-Bit, Dual, 40Msps ADC
235mW, 74.4dB SNR, 9mm × 9mm QFN Package
LTC2293
12-Bit, Dual, 65Msps ADC
400mW, 74.3dB SNR, 9mm × 9mm QFN Package
LTC2295
14-Bit, Dual, 10Msps ADC
120mW, 74.4dB SNR, 9mm × 9mm QFN Package
LTC2296
14-Bit, Dual, 25Msps ADC
150mW, 74.5dB SNR, 9mm × 9mm QFN Package
LTC2297
14-Bit, Dual, 40Msps ADC
235mW, 74.4dB SNR, 9mm × 9mm QFN Package
LTC2298
14-Bit, Dual, 65Msps ADC
400mW, 74.3dB SNR, 9mm × 9mm QFN Package
LTC2299
14-Bit, Dual, 80Msps ADC
444mW, 73dB SNR, 9mm × 9mm QFN Package
2294fa
24
Linear Technology Corporation
RD/LT 0106 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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