INNOVASIC IA82527 Serial communications controller can protocol Datasheet

04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
IA82527
Serial Communications Controller ▪ CAN Protocol
Data Sheet
Document Version 1.0
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Copyright © 2007 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
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®
Intel is a registered trademark of Intel Corporation.
MILES™ is a trademark of Innovasic Semiconductor, Inc.
®
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CAN Serial Communications Controller
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Table of Contents
Contents
1.
2.
3.
4.
5.
6.
7.
Introduction......................................................................................................................... 5
1.1 General Description .................................................................................................... 5
1.2 Features ..................................................................................................................... 6
Packaging and Pin Descriptions ......................................................................................... 7
2.1 Packages and Pinouts ................................................................................................ 7
2.2 Pin/Signal Descriptions ............................................................................................. 10
Maximum Ratings, Thermal Characteristics, and DC Parameters..................................... 18
Functional Description ...................................................................................................... 21
4.1 Hardware Architecture .............................................................................................. 21
4.1.1 CAN Controller.............................................................................................. 22
4.1.2 RAM ............................................................................................................. 22
4.1.3 CPU Interface ............................................................................................... 22
4.1.4 I/O Ports ....................................................................................................... 23
4.1.5 Programmable Clock Output......................................................................... 23
4.2 Address Map............................................................................................................. 23
4.3 CAN Message Objects.............................................................................................. 23
AC Characteristics............................................................................................................ 26
Physical Dimensions......................................................................................................... 42
Ordering Information......................................................................................................... 45
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List of Figures
Figure 1. IA82527 44-Pin PLCC Package Diagram ................................................................... 8
Figure 2. IA82527 44-Pin QFP Package Diagram ..................................................................... 9
Figure 3. IA82527 Functional Block Diagram........................................................................... 21
Figure 4. mosi/miso Connection .............................................................................................. 22
Figure 5. IA82527 Address Map .............................................................................................. 24
Figure 6. IA82527 Message Object Structure .......................................................................... 25
Figure 7. Mode 0 and Mode 1 General Bus Timing ................................................................. 29
Figure 8. Mode 0 and Mode 1 ready Timing for Read Cycle.................................................... 30
Figure 9. Mode 0 and Mode 1 ready Timing for Write Cycle with No Write Pending ................ 30
Figure 10. Mode 0 & Mode 1 ready Timing for Write Cycle with Write Active........................... 31
Figure 11. Mode 2 General Bus Timing ................................................................................... 33
Figure 12. Mode 3, Asynchronous Operation, Read Cycle ...................................................... 35
Figure 13. Mode 3, Asynchronous Operation, Write Cycle ...................................................... 36
Figure 14. Mode 3, Synchronous Operation, Read Cycle Timing ............................................ 38
Figure 15. Mode 3, Synchronous Operation, Write Cycle Timing............................................. 39
Figure 16. Serial Interface Mode, icp = 0 and cp = 0 ............................................................... 41
Figure 17. Serial Interface Mode, icp = 1 and cp = 1 ............................................................... 41
Figure 18. 44-Pin PLCC Physical Dimensions......................................................................... 43
Figure 19. 44-Pin QFP Physical Dimensions ........................................................................... 44
List of Tables
Table 1. IA82527 44-Pin PLCC Pin List..................................................................................... 8
Table 2. IA82527 44-Pin QFP Pin List ....................................................................................... 9
Table 3. IA82527 Pin/Signal Descriptions................................................................................ 10
Table 4. IA82527 Absolute Maximum Ratings ......................................................................... 18
Table 5. IA82527 Thermal Characteristics............................................................................... 18
Table 6. IA82527 DC Parameters............................................................................................ 19
Table 7. IA82527 ISO Physical Layer DC Parameters............................................................. 20
Table 8. Mode 0 and Mode 1 General Bus and ready Timing .................................................. 27
Table 9. Mode 2 General Bus Timing ...................................................................................... 32
Table 10. Mode 3 Asynchronous Operation Timing ................................................................. 34
Table 11. Mode 3 Synchronous Operation Timing................................................................... 37
Table 12. Serial Interface Mode Timing ................................................................................... 40
Table 13. 44-Pin PLCC Physical Dimensions .......................................................................... 43
Table 14. 44-Pin QFP Physical Dimensions ............................................................................ 44
Table 15. IA82527 Ordering Information.................................................................................. 45
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IA82527
CAN Serial Communications Controller
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1.
PRELIMINARY
Introduction
The Innovasic Semiconductor IA82527 Controller Area Network (CAN) Serial Communications
Controller is a form, fit, and function replacement for the original Intel® 82527 Serial
Communications Controller.
These devices are produced using Innovasic’s Managed IC Lifetime Extension System
(MILES™). This cloning technology, which produces replacement ICs beyond simple
emulations, ensures complete compatibility with the original device, including any
“undocumented features.” Additionally, MILES™ captures the clone design in such a way that
production of the clone can continue even as silicon technology advances.
The IA82527 Serial Communications Controller replaces the obsolete Intel® 82527 device,
allowing users to retain existing board designs, software compilers/assemblers, and emulation
tools, thereby avoiding expensive redesign efforts.
NOTE
This data sheet contains preliminary information for the
Innovasic Semiconductor IA82527 Serial Communications
Controller. The finalized data sheet that documents all
necessary engineering information about the IA82527 will be
available when the device nears completion in Q2 2008.
1.1
General Description
Controller Area Network (CAN) protocol uses a multi-master CSMA/CR (Carrier Sense, Multiple
Access with Collision Resolution) bus to transfer message objects between network nodes.
The IA82527 supports CAN Specification 2.0 Part A and B, standard and extended message
frames, and has the capability to transmit, receive, and perform message filtering on extended
message frames.
The IA82527 can store 15 message objects of 8-byte data length. Each message object can be
configured as either transmit or receive except for the last message object, which is receiveonly. The last message object also provides a special acceptance mask designed to allow
select groups of different message identifiers to be received.
The IA82527 also provides a programmable acceptance mask that allows users to globally
mask any identifier bits of the incoming message. This global mask can be used for both
standard and extended message frames.
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1.2
PRELIMINARY
Features
The primary features of the IA82527 are as follows:
•
CAN Protocol Support
o Specification 2.0, Part A and Part B
o Standard Data and Remote Frames
o Extended Data and Remote Frames
•
CAN Bus Interface
o Configurable Input Comparator
o Configurable Output Driver
•
Global Mask, Programmable
o Standard Message Identifier
o Extended Message Identifier
•
Message Objects
o 14 Transmit/Receive Buffers
o 1 Receive Buffer with Programmable Mask
•
Programmable Bit Rate
•
Flexible Status Interface
•
CPU Interface Options
o 16-Bit Multiplexed Intel® Architecture
o 8-Bit Multiplexed Intel® Architecture
o 8-Bit Multiplexed Non-Intel® Architecture
o 8-Bit Non-Multiplexed Non-Intel® Architecture
o Serial (SPI)
•
I/O Ports (2)
o 8-Bit
o Bidirectional
•
Flexible Interrupt Structure
•
Programmable Clock Output
A more detailed description of the IA82527, including the features listed above, is provided in
Section 4.
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2.
Packaging and Pin Descriptions
2.1
Packages and Pinouts
PRELIMINARY
The Innovasic Semiconductor IA82527 CAN Serial Communications Controller is available in
the following packages:
•
•
44-Pin Plastic Leaded Chip Carrier (PLCC)
44-Pin Quad Flat Pack (QFP)
The 44-pin PLCC package is shown in Figure 1/Table 1, and the 44-pin QFP package is shown
in Figure 2/Table 2.
Detailed descriptions of pin/signal functions are provided in section 2.2 (Table 3).
NOTE
Table 1 (PLCC package) and Table 2 (QFP package) provide
numerical indexes of pin names. Table 3 provides an
alphabetical index of pin and signal descriptions.
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Figure 1. IA82527 44-Pin PLCC Package Diagram
Table 1. IA82527 44-Pin PLCC Pin List
Pin
Name
Pin
1
2
3
4
5
6
7
8
9
10
11
vcc
a2/ad2/csas
a1/ad1/cp
a0/ad0/icp
ale/as
rd_n/e
wr_n/wrl_n/r-w_n
cs_n
dsack0_n
wrh_n/p2.7
int_n/p2.6
12
13
14
15
16
17
18
19
20
21
22
Copyright  2007
Name
p2.5
p2.4
p2.3
p2.2
p2.1
p2.0
xtal1
xtal2
vss2
rx1
rx0
Pin
23
24
25
26
27
28
29
30
31
32
33
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Name
vss1
int_n/vcc/2
tx1
tx0
clkout
ready/miso
reset_n
mode1
ad15/d7/p1.7
ad14/d6/p1.6
ad13/d5/p1.5
Pin
34
35
36
37
38
39
40
41
42
43
44
Name
ad12/d4/p1.4
ad11/d3/p1.3
ad10/d2/p1.2
ad9/d1/p1.1
ad8/d0/p1.0
a7/ad7
a6/ad6/sclk
a5/ad5
a4/ad4/mosi
a3/ad3/ste
mode0
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Figure 2. IA82527 44-Pin QFP Package Diagram
Table 2. IA82527 44-Pin QFP Pin List
Pin
Name
Pin
1
2
3
4
5
6
7
8
9
10
11
wr_n/wrl_n/r-w_n
cs_n
dsack0_n
wrh_n/p2.7
int_n/p2.6
p2.5
p2.4
p2.3
p2.2
p2.1
p2.0
12
13
14
15
16
17
18
19
20
21
22
Copyright  2007
Name
xtal1
xtal2
vss2
rx1
rx0
vss1
int_n/vcc/2
tx1
tx0
clkout
ready/miso
Pin
23
24
25
26
27
28
29
30
31
32
33
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Name
reset_n
mode1
ad15/d7/p1.7
ad14/d6/p1.6
ad13/d5/p1.5
ad12/d4/p1.4
ad11/d3/p1.3
ad10/d2/p1.2
ad9/d1/p1.1
ad8/d0/p1.0
a7/ad7
Pin
Name
34
35
36
37
38
39
40
41
42
43
44
a6/ad6/sclk
a5/ad5
a4/ad4/mosi
a3/ad3/ste
mode0
vcc
a2/ad2/csas
a1/ad1/cp
a0/ad0/icp
ale/as
rd_n/e
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2.2
Pin/Signal Descriptions
Descriptions of the pin and signal functions for the IA82527 Serial Communications Controller
are provided in Table 3.
Several of the IA82527 pins have different functions depending on the operating mode of the
device. Each of the different signals supported by a pin is listed and defined in Table 3, indexed
alphabetically in the first column of the table. Additionally, the name of the pin associated with
the signal as well as the pin numbers for both the PLCC and QFP packages are provided in the
“Pin” column. If the signal and pin names are the same, no entry is provided in the “Pin-Name”
column.
Table 3. IA82527 Pin/Signal Descriptions
Pin
Signal
Name
Description
PLCC
QFP
a0
a1
a2
a3
a4
a5
a6
a7
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
a0/ad0/icp
4
42
a1/ad1/cp
3
41
a2/ad2/csas
2
40
a3/ad3/ste
43
37
a4/ad4/mosi
42
36
a5/ad5
41
35
a6/ad6/sclk
40
34
a7/ad7
39
33
a0/ad0/icp
4
42
a1/ad1/cp
3
41
a2/ad2/csas
2
40
a3/ad3/ste
43
37
a4/ad4/mosi
42
36
a5/ad5
41
35
a6/ad6/sclk
40
34
a7/ad7
39
33
ad8/d0/p1.0
38
32
ad9
ad9/d1/p1.1
37
31
ad10
ad10/d2/p1.2
36
30
ad11
ad11/d3/p1.3
35
29
ad12
ad12/d4/p1.4
34
28
ad13
ad13/d5/p1.5
33
27
ad14
ad14/d6/p1.6
32
26
ad15
ad15/d7/p1.7
31
25
ale
ale/as
5
43
address bits 7–0. Input. Mode 3.
When the IA82527 is configured to operate in the 8-bit non®
multiplexed non-Intel architecture mode (Mode 3), these lines
provide the 8-bit address bus input to the device.
address/data bits 15–0. Input/Output. Mode 1.
When the IA82527 is configured to operate in the 16-bit multiplexed
®
Intel architecture mode (Mode 1), these lines provide the 16-bit
address bus (input) and the 16-bit data bus (input/output) for the
device.
address latch enable. Input. Active High. Mode 0 and Mode 1.
When the IA82527 is configured to operate in either the 8-bit
®
multiplexed Intel architecture mode (Mode 0) or the 16-bit
®
multiplexed Intel architecture mode (Mode 1), this signal latches the
address into the device during the address phase of the bus cycle.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
as
Description
PLCC
ale/as
5
QFP
43
address strobe. Input. Active High. Mode 2.
When the IA82527 is configured to operate in either the 8-bit
®
multiplexed non-Intel architecture mode (Mode 2), this signal latches
the address into the device during the address phase of the bus
cycle.
NOTE: If the IA82527 is configured to operate in Mode 3 (8-bit non®
multiplexed non-Intel architecture), this pin must be tied high.
clkout
cp
—
27
a1/ad1/cp
cs_n
3
—
8
21
clock out. Output (push-pull).
This output provides a programmable clock frequency. The
frequency is set via the Clockout Register (1FH) and can range from
the frequency of the xtal (crystal) input to xtal/n, where n can be an
integer value from 2 through 15. This output allows the IA82527 to
clock other devices such as the host CPU.
41
clock phase. Input. Serial Interface Mode.
When this input is a logic 0, data are sampled on the rising edge of
sclk. When this input is a logic 1, data are sampled on the falling
edge of sclk.
2
chip select. Input. Active Low (Modes 0–3); Selectable Active Level
(Serial Interface Mode).
When the IA82527 is configured to operate in one of the parallel
interface modes (Modes 0–3) or the Serial Interface Mode, this input,
during its active state, selects the device allowing CPU access.
For Serial Interface Mode operation, the active state is selectable
(i.e., either high or low) via the IA8257 csas pin.
csas
a2/ad2/csas
2
40
d0
d1
d2
d3
d4
d5
d6
d7
ad8/d0/p1.0
38
32
ad9/d1/p1.1
37
31
ad10/d2/p1.2
36
30
ad11/d3/p1.3
35
29
ad12/d4/p1.4
34
28
ad13/d5/p1.5
33
27
ad14/d6/p1.6
32
26
ad15/d7/p1.7
31
25
chip select active state. Input. Serial Interface Mode.
When this input is a logic 0, the cs_n input is configured to function
active low. When this input is a logic 1, the cs_n input is configured
to function active high.
data bits 7–0. Input/Output. Mode 3.
When the IA82527 is configured to operate in the 8-bit non®
multiplexed non-Intel architecture mode (Mode 3), these lines
provide the 8-bit data bus to the device.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
dsack0_n
e
icp
Description
PLCC
—
9
rd_n/e
6
a0/ad0/icp
4
QFP
3
data and size acknowledge 0. Output. Active Low (open drain with
active pull-up). Mode 3 (asynchronous operation).
When the IA82527 is configured to operate in the 8-bit non®
multiplexed non-Intel architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from the IA82527,
dsack0_n active low indicates that the data are valid; when the CPU
writes to the IA82527, dsack0_n active low indicates that the data
have been received.
44
enable. Input. Active High. Mode 3 (asynchronous).
When the IA82527 is configured to operate in the 8-bit non®
multiplexed non-Intel architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from or writes to the
IA82527, e active high indicates that the address is valid.
42
idle clock polarity. Input. Serial Interface Mode.
When this input is a logic 0, the polarity for the idle state of sclk is
low. When this input is a logic 1, the polarity for the idle state of sclk
is high.
interrupt. Output (open collector). Active Low.
On the IA82527, two pins can provide the interrupt (int_n) output;
however, depending on the setting of the MUX bit in the CPU
Interface Register (02H), only one of the pins will serve as the source
of int_n as follows:
int_n/ VCC/2
24
18
int_n
• PLCC Package:
-
When the MUX bit of the CPU Interface Register is 0, pin
24 functions as the int_n output and pin 11 functions as
p2.6.
-
When the MUX bit of the CPU Interface Register is 1, pin
11 functions as the int_n output and pin 24 functions as
Vcc/2.
• QFP Package:
int_n/p2.6
11
5
-
When the MUX bit of the CPU Interface Register is 0, pin
18 functions as the int_n output and pin 5 functions as
p2.6.
-
When the MUX bit of the CPU Interface Register is 1, pin
5 functions as the int_n output and pin 18 functions as
Vcc/2.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
miso
Description
PLCC
ready/miso
28
QFP
22
master in slave out. Output (open drain). Serial Interface Mode.
When the IA82527 is configured to operate with a serial interface,
miso is the serial data output.
modeN (N = 1 or 0). Input.
The logic levels at the mode0 and mode1 inputs determine the
operating mode (i.e., interface type) of the IA82527 as follows:
mode1
—
mode0
44
38
0
0
1
1
mode0
0
1
0
1
Interface Type
®
8-bit Multiplexed Intel
®
16-bit Multiplexed Intel
®
8-bit Multiplexed Non-Intel
®
8-bit Non-Multiplexed Non-Intel
The mode1 and mode0 inputs are also used to establish the Serial
Interface Mode as follows: when the IA82527 is reset, if
•
•
•
•
mode1
—
30
mode1 = 0
mode0 = 0
rd_n = 0
wr_n = 0
24
the Serial Interface Mode will be selected.
The mode1 and mode0 pins are internally connected to weak pulldowns. These pins will be pulled low during reset if unconnected.
Following reset, these pins will float.
mosi
a4/ad4/mosi
42
36
master out slave in. Input. Serial Interface Mode.
When the IA82527 is configured to operate with a serial interface,
mosi is the serial data input.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
Description
PLCC
QFP
p1.0
ad8/d0/p1.0
38
32
p1.1
ad9/d1/p1.1
37
31
p1.2
ad10/d2/p1.2
36
30
p1.3
ad11/d3/p1.3
35
29
p1.4
ad12/d4/p1.4
34
28
p1.5
ad13/d5/p1.5
33
27
p1.6
ad14/d6/p1.6
32
26
p1.7
ad15/d7/p1.7
31
25
p2.0
—
17
11
p2.1
—
16
10
p2.2
—
15
9
p2.3
—
14
8
p2.4
—
13
7
p2.5
—
12
6
p2.6
int_n/p2.6
11
5
p2.7
wrh_n/p2.7
10
4
Copyright  2007
port 1, bit N (N = 7–0). Input/Output (general-purpose). Mode 0,
Mode 2, and Serial Interface Mode.
Port 1 bits p1.7–p1.0 can be individually programmed as inputs or
outputs. Programming is accomplished by writing to the P1CONF
Register (9FH). The 8 bits of the P1CONF Register, P1CONF7–
P1CONF0, correspond directly to pins p1.7–p1.0. Writing a 0 to a bit
in the P1CONF Register causes the corresponding pin to be
configured as a high-impedance input. Writing a 1 to a bit in the
P1CONF Register causes the corresponding pin to be configured as
a push-pull output. All Port 1 pins have weak pull-ups until the port is
configured by writing to the P1CONF Register. The default value of
the P1CONF Register following a reset is 00H.
Data are read from Port 1 via the P1IN Register (BFH). A logic 0 for
any bit in this register means that a logic 0 was read from the
corresponding pin; a logic 1 for any bit means that a logic 1 was read
from the corresponding pin. The default value of the P1IN Register
following a reset is FFH.
Data are written to Port 1 via the P1OUT Register (DFH). Writing a
logic 0 to any bit in this register means that a logic 0 is written to the
corresponding pin; writing a logic 1 to any bit means that a logic 1 is
written to the corresponding pin. The default value of the P1OUT
Register following a reset is 00H.
port 2, bit N (N = 7–0). Input/Output.
Port 2 bits p2.7–p2.0, can be individually programmed as inputs or
outputs. Programming is accomplished by writing to the P2CONF
Register (AFH). The 8 bits of the P2CONF Register, P2CONF7–
P2CONF0, correspond directly to pins p2.7–p2.0. Writing a 0 to a bit
in the P2CONF Register causes the corresponding pin to be
configured as a high-impedance input. Writing a 1 to a bit in the
P2CONF Register causes the corresponding pin to be configured as
a push-pull output. All Port 2 pins have weak pull-ups until the port is
configured by writing to the P2CONF Register. The default value of
the P1CONF Register following a reset is 00H.
Data are read from Port 2 via the P2IN Register (CFH). A logic 0 for
any bit in this register means that a logic 0 was read from the
corresponding pin; a logic 1 for any bit means that a logic 1 was read
from the corresponding pin. The default value of the P2IN Register
following a reset is FFH.
Data are written to Port 2 via the P2OUT Register (EFH). Writing a
logic 0 to any bit in this register means that a logic 0 is written to the
corresponding pin; writing a logic 1 to any bit means that a logic 1 is
written to the corresponding pin. The default value of the P2OUT
Register following a reset is 00H.
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continued . . .
Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
rd_n
ready
rd_n/e
ready/miso
Description
PLCC
QFP
6
44
read. Input. Active Low. Mode 0 and Mode 1.
When rd_n is asserted (low), it causes the IA82527 to drive the data
from the location being read onto the data bus.
22
ready. Output (open drain). Active High. Mode 0 and Mode 1.
When ready is asserted (high), it signals the completion of a bus
cycle. The ready output is provided to force system CPU wait states
as required.
28
reset. Input. Active Low.
When the reset_n signal is asserted (low), the IA82527 is initialized.
There are two reset situations:
reset_n
—
29
23
Cold Reset. This is a power-on reset: As VCC is driven to a valid
level (power on), the reset_n signal must be driven low for a
minimum of 1 ms measured from a valid VCC level. No falling edge
on the reset_n pin is required during a cold reset.
Warm Reset. For this reset, VCC remains at a valid level (i.e., power
is already on and remains on) while reset_n is driven low for a
minimum of 1 ms.
r-w_n
wr_n/wrl_n/r-w_n
rx0
—
7
22
1
16
read-write. Input. Active High (read)-Active Low (write). Mode 3.
When r-w_n is high, it signals a read cycle. When r-w_n is low, it
signals a write cycle.
Receive (rx), lines 0 and 1. Input.
Pins rx0 and rx1 are the inputs to the IA82527 from the Controller
Area Network (CAN) bus lines. These pins connect internally to the
receiver input comparator. Serial data from the CAN bus can be
received using both rx0 and rx1 or by using only rx0 as follows:
• When the CoBy Bit in the Bus Configuration Register (2FH) is
a 0, rx0 and rx1 are connected to the input comparator. (rx0
is connected to the non-inverting input and rx1 is connected
to the inverting input.) A recessive level is read when rx0 >
rx1. A dominant level is read when rx1 > rx0.
rx1
—
21
15
• When the CoBy Bit in the Bus Configuration Register (2FH) is
a 1, input comparison is disabled, and rx0, which is still
connected to the non-inverting input of the comparator, is the
CAN bus line input. For this configuration, the DcR0 bit of the
Bus Configuration Register must be a 0.
After a cold reset (power on), the default configuration is the use of
both rx0 and rx1 for the CAN bus input.
sclk
a6/ad6/sclk
40
34
serial clock. Input. Serial Interface Mode.
The sclk pin is the serial clock input to the IA82527 (slave device).
The clock signal is provided by the master device.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Name
Description
PLCC
QFP
synchronization transmission enable. Input. Serial interface Mode.
The logic level at the ste pin enables the transmission of the
synchronization bytes through the IA82527 miso pin while the master
device transmits the Address and Control Byte as follows:
ste
a3/ad3/ste
43
37
• When a logic 0 is placed on the ste pin, the synchronization
bytes sent through the miso pin are 00H and 00H.
• When a logic 1 is placed on the ste pin, the synchronization
bytes sent through the miso pin are AAH and 55H.
The IA82527 sends the synchronization bytes after the cs_n signal
has been asserted (low).
tx0
—
26
20
Transmit (tx), lines 0 and 1. Output (push-pull).
Pins tx0 and tx1 are the outputs from the IA82527 to the Controller
Area Network (CAN) bus lines.
tx1
—
25
19
During a recessive bit, tx0 is high and tx1 is low. During a dominant
bit, tx0 is low and tx1 is high.
VCC
—
1
39
Power (VCC).
This pin provides power for the IA82527 device. It must be
connected to a +5V DC power source.
Reference Voltage, ISO Physical Layer (VCC/2). Output.
The VCC/2 pin provides a reference voltage for the ISO low-speed
physical layer:
VCC/2
int_n/ VCC/2
24
18
• 2.38V DC (minimum) to 2.60V DC (maximum)
(VCC = +5.00V; IOUT ≤ 75 µA)
This pin only functions as VCC/2 when the MUX bit of the CPU
Interface Register (02H) is 1.
VSS1
—
23
17
VSS2
—
20
14
Ground, Digital (VSS1).
This pin provides the digital ground (0V) for the IA82527. It must be
connected to a VSS board plane.
Ground, Analog (VSS2).
This pin provides the ground (0V) for the IA82527 analog comparator.
It must be connected to a VSS board plane.
continued . . .
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Table 3. IA82527 Pin/Signal Descriptions, continued
Pin
Signal
Description
Name
PLCC
QFP
wr_n
wr_n/wrl_n/r-w_n
7
1
wrh_n
wrh_n/p2.7
10
4
wrl_n
wr_n/wrl_n/r-w_n
7
1
xtal1
xtal2
—
18
—
19
12
13
write. Input. Active Low. Mode 0.
When wr_n is asserted (low), it signals a write cycle.
write high byte. Input. Active Low. Mode 1.
When wrh_n is asserted (low), it signals a write cycle for the high
byte of data (bits 15–8).
write low byte. Input. Active Low. Mode 1.
When wrl_n is asserted (low), it signals a write cycle for the low byte
of data (bits 7–0).
Crystal (xtal) 1. Input.
The xtal1 pin is the input connection for an external crystal that
drives the IA82527 internal oscillator. (When an external crystal is
used, it is connected between this pin and the xtal2 pin—see next
table entry.)
NOTE: If an external oscillator or clock source is used to drive the
IA82527 instead of a crystal, the xtal1 pin is the input for this clock
source.
Crystal (xtal) 2. Output (push-pull).
The xtal2 pin is the output connection for an external crystal that
drives the IA82527 internal oscillator. (When an external crystal is
used, it is connected between this pin and the xtal1 pin—see
previous table entry.)
NOTE: If an external oscillator or clock source is used to drive the
IA82527 instead of a crystal, xtal2 must be left unconnected (i.e.,
must be floated). Additionally, the xtal2 output must not be used as a
clock source for other system components.
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3.
Maximum Ratings, Thermal Characteristics, and DC Parameters
For the Innovasic Semiconductor IA82527 Serial Communications Controller, the absolute
maximum ratings, thermal characteristics, and DC parameters are provided in Tables 4–6,
respectively.
Additionally, the DC parameters of the ISO Physical Layer are provided in Table 7.
NOTE
The values provided in the following tables are preliminary.
Table 4. IA82527 Absolute Maximum Ratings
Parameter
Rating
Storage Temperature
Case Temperature under Bias
−65°C to +150°C
−65°C to +120°C
Supply Voltage with Respect to Vss
Voltage on Pins other than Supply with Respect to Vss
−0.5V to +6.5V
−0.5V to +5.5V
Table 5. IA82527 Thermal Characteristics
Symbol
TA
PINT
PI/O
PD
ΘJa
TJ
Characteristic
Value
Units
Ambient Temperature
User Determined
°C
Device Internal Power Dissipation
I/O Pin Power Dissipation
Total Power Dissipation
44-Pin PLCC Package
44-Pin QFP Package
Average Junction Temperature
IDD x VDD
User Determined
PINT + PI/O
To Be Determined
To Be Determined
TA + (PD x ΘJa)
W
W
W
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°C/W
°C
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Table 6. IA82527 DC Parameters
Symbol
VCC
Parameter
Pin(s)
Minimum
Maximum
Units
Notes
—
4.5
5.5
V
—
−0.5
0.5
p1.7–p1.0,
p2.7–p2.0
—
0.3(VCC)
rx0
—
0.5
Comparator bypassed
−0.5
0.8
All other pins
0.7(VCC)
—
Not connected to a host
CPU
reset_n
3.0
VCC + 0.5
rx0
4.0
—
3.0
VCC + 0.5
Supply Voltage
ad7–ad0
VIL
Voltage, Input Low
p1.7–p1.0,
p2.7–p2.0
VIH
Voltage, Input High
Mode 3
V
V
All other pins
See Table 7
V
Voltage, Output Low
clkout
VOH
Voltage, Output High
reset_n hysteresis = 200mV
Comparator bypassed
tx0, tx1
VOL
Not connected to a host
CPU
—
0.45
0.8(VCC)
—
All other pins; IOL = 1.6 mA
IOH = −80 µA
V
tx0, tx1
VCC − 0.8
—
See Table 7
All other pins; IOH = −200 µA
ILEAK
Input Leakage Current
—
±10
µA
VSS < VIN < VCC
CIN
Pin Capacitance
—
10
pF
fCRYSTAL = 1 KHz
ICC
Supply Current
—
50
mA
fCRYSTAL = 16 KHz; all pins
are driven to VSS or VCC.
ISLEEP-E
Sleep Current
—
700
ISLEEP-D
Sleep Current
—
100
IPD
Power-Down Current
—
25
VCC/2 enabled; no load.
µA
VCC/2 disabled.
xtal1 clocked; all pins driven
to VSS or VCC.
All ratings listed are for the temperature range TA = −40°C to +125°C (VCC = 5V ± 10%).
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Table 7. IA82527 ISO Physical Layer DC Parameters
Signal
Parameter
Input Voltage
Common Mode Range
rx0 & rx1;
tx0 & tx1
VCC/2
Differential Input Threshold
Delay 1:
receive comparator input delay +
tx0/tx1 output delay
Delay 2:
rx0 pin delay (comparator
bypassed) +
tx0/tx1 output delay
Source Current on tx0, tx1
Minimum
Maximum
Units
Notes
−0.5
VCC + 0.5
V
—
Vss + 1.0
VCC − 1.0
V
—
±100
—
mV
—
60
ns
—
50
ns
—
Load on tx0/tx1 = 100 pF;
rx0/rx1 differential =
+100 mV to −100 mV
Load on tx0/tx1 = 100 pF
—
−10
mA
VOUT = VCC − 1.0 V
Sink Current on tx0, tx1
—
10
mA
VOUT = 1.0 V
Input Hysteresis for rx0/rx1
—
0
V
2.38
2.62
V
Reference Voltage
—
IOUT ≤ 75 µA; VCC = 5.0 V
All ratings listed are for the temperature range TA = −40°C to +125°C (VCC = 5V ± 10%).
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4.
Functional Description
4.1
Hardware Architecture
PRELIMINARY
A block diagram of the IA82527 CAN Serial Communications Controller is shown in Figure 3.
The primary architectural features of the device are as follows:
•
•
•
•
•
Controller Area Network (CAN) Controller
RAM
CPU Interface
I/O Ports
Programmable Clock Output
These features are briefly described in the following subsections.
Figure 3. IA82527 Functional Block Diagram
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4.1.1
PRELIMINARY
CAN Controller
The CAN Controller block of the IA82527 supports the interface to the CAN Bus via the rx0, rx1,
tx0, and tx1 lines. The CAN Controller manages the transceiver logic, error management logic,
and the message objects, controlling the data stream between the RAM (parallel data) and the
CAN Bus (serial data).
4.1.2
RAM
The RAM block of the IA82527 provides the interface buffer between the system CPU and the
CAN Bus. The IA82527 RAM provides storage for 15 message objects of 8-byte data length.
The RAM is an interleaved-access memory, which means that access to the RAM is timeshared
between the CPU Interface Logic and the CAN Bus.
4.1.3
CPU Interface
The IA82527 is capable of interfacing to many commonly used microcontrollers. There are four
parallel interface options and a serial interface option.
Different interface options, or modes, are selected using interface mode pins, mode1 and
mode0. The parallel interface modes that can be selected are as follows:
•
•
•
•
8-bit Intel® multiplexed address and data buses
16-bit Intel® multiplexed address and data buses
8-bit non- Intel® multiplexed address and data buses
8-bit non-multiplexed address and data buses
The serial interface mode is fully compatible with the Motorola® SPI protocol and will interface to
most commonly used serial interfaces. The serial interface is implemented in slave mode only,
and responds to the master using the specially designed serial interface protocol. The serial
interface mode interconnection scheme is shown in Figure 4.
Figure 4. mosi/miso Connection
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4.1.4
PRELIMINARY
I/O Ports
The IA82527 provides two 8-bit low-speed input/output (I/O) ports. Depending on the CPU
interface mode selected, at least 7 and up to 16 I/O lines are available. Each I/O line is
individually programmable to function either as an input or an output.
4.1.5
Programmable Clock Output
Using an oscillator, clock divider register, and a driver circuit, the IA82527 provides a
programmable clock output. The output frequency range available is from the external crystal
frequency to that frequency divided by 15. The clock output allows the IA82527 to drive other
devices such as the host CPU.
4.2
Address Map
The IA82527 includes 256 8-bit locations that provide device configuration registers and
message storage. The address map is shown in Figure 5.
4.3
CAN Message Objects
Each CAN message object has a unique identifier and can be configured as either transmit or
receive, except for the last message object. The last message object is a receive-only buffer
with a special mask design to allow select groups of different message identifiers to be received.
Each message object contains control and status bits.
All message objects have separate transmit and receive interrupts and status bits that allow the
host CPU to determine when a message frame has been sent or received. The IA82527
implements a global masking feature that allows the user to globally mask any identifier bits of
the incoming message. This mask is programmable, which permits application-specific
message identification.
The Message Object Structure is shown in Figure 6.
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Address
PRELIMINARY
Register/Message
00H
Control Register
01H
Status Register
02H
CPU Interface Register
03H
Reserved
04–05H
High-Speed Read Register
06–07H
Global Mask – Standard
08–0BH
Global Mask – Extended
0V-0FH
Message 15 Mask
10–1EH
Message 1
1FH
CLKOUT Register
20–2EH
Message 2
2FH
Bus Configuration Register
30–3EH
Message 3
3FH
Bit Timing Register 0
40–4EH
Message 4
4FH
Bit Timing Register 1
50–5EH
Message 5
5FH
Interrupt Register
60–6EH
Message 6
6FH
Reserved
70H–7EH
Message 7
7FH
Reserved
80–8EH
Message 8
8FH
Reserved
90–9EH
Message 9
9FH
P1CONF Register
A0–AEH
Message 10
AFH
P2CONF Register
B0–BEH
Message 11
BFH
P1IN Register
C0–CEH
Message 12
CFH
P2IN Register
D0–DEH
Message 13
DFH
P1OUT Register
E0–EEH
Message 14
EFH
P2OUT Register
F0–FEH
Message 15
FFH
Serial Reset Address Register
Figure 5. IA82527 Address Map
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Offset
(Base Address +n)
+0
+1
+2
+3
+4
+5
+6
+7
PRELIMINARY
Message Component
Control Register 0
Control Register 1
Arbitration Register 0
Arbitration Register 1
Arbitration Register 2
Arbitration Register 3
Message Configuration Register
Data Byte 0
+8
+9
+10
+11
+12
+13
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
+14
Data Byte 7
Figure 6. IA82527 Message Object Structure
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5.
PRELIMINARY
AC Characteristics
The AC characteristics of the IA82527 are provided in the figures and tables of this chapter.
The IA82527 can be configured to operate in the following parallel and serial CPU interface
modes:
•
•
•
•
•
Mode 0: 8-Bit Multiplexed Intel® Architecture
Mode 1: 16-Bit Multiplexed Intel® Architecture
Mode 2: 8-Bit Multiplexed Non-Intel® Architecture
Mode 3: 8-Bit Non-Multiplexed Non-Intel® Architecture
Serial Interface Mode
The AC characteristics of these modes in operation of are provided as follows:
• Mode 0 and Mode 1 General Bus Timing (Table 8/Figure 7)
• Mode 0 and Mode 1 ready Timing for Read Cycle (Table 8/Figure 8)
• Mode 0 and Mode 1 ready Timing for Write Cycle with No Write Pending
(Table 8/Figure 9)
• Mode 0 & Mode 1 ready Timing for Write Cycle with Write Pending (Table 8/Figure 10)
• Mode 2 General Bus Timing (Table 9/Figure 11)
• Mode 3, Asynchronous Operation, Read Cycle (Table 10/Figure 12)
• Mode 3, Asynchronous Operation, Write Cycle (Table 10/Figure 13)
• Mode 3, Synchronous Operation, Read Cycle (Table 11/Figure 14)
• Mode 3, Synchronous Operation, Write Cycle (Table 11/Figure 15)
• Serial Interface Mode, icp = 0 and cp = 0 (Table 12/Figure 16)
• Serial Interface Mode, icp = 1 and cp = 1 (Table 12/Figure 17)
NOTE
The values provided in the following tables and figures are preliminary.
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Table 8. Mode 0 and Mode 1 General Bus and ready Timing
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tAVLL
tLLAX
tLHLL
tLLRL
tCLLL
tQVWH
tWHQX
tWLWH
tWHLH
tWHCH
tRLRH
tRLDV
tRLDV1
tRLDV1
tRHDZ
tCLYV
tWLYZ
Parameter
Minimum
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ale Low
Address Hold after ale Low
ale High Time
ale Low to rd_n Low
cs_n Low to ale Low
Data Setup to wr_n or wrh_n High
Input Data Hold after wr_n or wrh_n High
wr_n or wrh_n Pulse Width
wr_n or wrh_n High to Next ale High
wr_n or wrh_n High to cs_n High
rd_n Pulse Width
This time is long enough to initiate a double read
cycle by loading the High Speed Registers (04H,
05H), but is too short to read from 04H and 05H
(see tRLDV).
rd_n Low to Data Valid
(Only for Registers 02H, 04H, 05H)
rd_n Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle without a Previous Write
rd_n Low Data to Data Valid (for all Registers
except 02H, 04H, 05H)
for Read Cycle with a Previous Write
Data Float after rd_n High
cs_n Low to ready Setup
(Load Capacitance on the ready
Output = 50 pF, VOL = 1.0 V)
cs_n Low to ready Setup
(Load Capacitance on the ready
Output = 50 pF, VOL = 0.45 V)
wr_n or wrh_n Low to ready Float for a Write
Cycle if No Previous Write is Pending
Maximum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
0 ns
—
—
—
—
—
—
—
—
—
—
40 ns
—
0 ns
16 MHz
10 MHz
8 MHz
55 ns
—
1.5 tMCLK + 100 ns
—
3.5 tMCLK + 100 ns
0 ns
45 ns
—
32 ns
—
40 ns
—
145 ns
continued . . .
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Table 8. Mode 0 & Mode 1 General Bus and ready Timing, continued
Symbol
Parameter
Minimum
tWHYZ
End of Last Write to ready Float for a Write Cycle if
a Previous Write Cycle is Active
—
2 tMCLK + 100 ns
tRLYZ
rd_n Low to ready Float (for all registers except
02H, 04H, 05H)
for Read Cycle without a Previous Write
—
2 tMCLK + 100 ns
—
4 tMCLK + 100 ns
tRLYZ
tWHDV
tCOPO
tCHCL
rd_n Low to ready Float (for all registers except
02H, 04H, 05H)
for Read Cycle with a Previous Write
wr_n High to Output Data Valid on Port 1 or Port 2
clkout Period
(CDV is the value loaded in the CLKOUT Register
representing the clkout divisor.)
clkout High Period
(CDV is the value loaded in the CLKOUT Register
representing the clkout divisor.)
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tMCLK
Maximum
2 tMCLK + 500 ns
•
(CDV + 1) tOSC
(CDV + 1) • ½
tOSC – 10
(CDV + 1) • ½ tOSC – 15
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Figure 7. Mode 0 and Mode 1 General Bus Timing
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Figure 8. Mode 0 and Mode 1 ready Timing for Read Cycle
Figure 9. Mode 0 and Mode 1 ready Timing for Write Cycle with No Write Pending
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Figure 10. Mode 0 & Mode 1 ready Timing for Write Cycle with Write Active
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Table 9. Mode 2 General Bus Timing
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tAVSL
tSLAX
tELDZ
tEHDV
tQVEL
tELQX
tELDV
tEHEL
tSHSL
tRSEH
tSLEH
tCLSL
tELCH
tCOPD
tCHCL
Parameter
Minimum
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to as Low
Address Hold after as Low
Data Float after e Low
e High to Data Valid for Registers 02H,
04H, 05H
e High to Data Valid (all Registers except
for 02H, 04H, 05H) for Read Cycle without a
Previous Write
e High to Data Valid (all Registers except
for 02H, 04H, 05H) for Read Cycle with a
Previous Write
Data Setup to e Low
Input Data Hold after e Low
e Low to Output Data Valid on Port 1/2
e High Time
as High Time
Setup Time of r-w_n to e High
as Low to e High
cs_n Low to as Low
e Low to cs_n High
clkout Period
(CDV is the value loaded in the CLKOUT
Register representing the clkout divisor.)
clkout High Period
(CDV is the value loaded in the CLKOUT
Register representing the clkout divisor.)
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8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
0 ns
16 MHz
10 MHz
8 MHz
0 ns
45 ns
45 ns
—
1.5 tmclk + 100 ns
—
3.5 tmclk + 100 ns
—
—
2 tmclk + 500 ns
30 ns
20 ns
tmclk
45 ns
30 ns
30 ns
20 ns
20 ns
0 ns
—
—
—
—
—
•
(CDV + 1) tosc
(CDV + 1) • ½ tosc – 10
EN21070504-00
©
Maximum
(CDV + 1) • ½ tosc – 15
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Figure 11. Mode 2 General Bus Timing
Copyright  2007
EN21070504-00
©
Page 33 of 45
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IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Table 10. Mode 3 Asynchronous Operation Timing
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tAVCL
tCLDV
tKLDV
tCHDV
tCHDH
tCHDZ
tCHKH1
Parameter
Minimum
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address or r-w_n Valid to cs_n Low
Setup
cs_n Low to Data Valid
(for High-Speed Registers 02H, 04H, and
05H)
cs_n Low to Data Valid
(for Low-Speed Registers)
Read Cycle without Previous Write
cs_n Low to Data Valid
(for Low-Speed Registers)
Read Cycle with Previous Write
dsack0_n Low to Output Data Valid
(for High-Speed Read Registers)
dsack0_n Low to Output Data Valid
(for Low-Speed Read Registers)
Input Data Hold after cs_n High
Output Data Hold after cs_n High
cs_n High to Output Data Float
cs_n High to dsack0_n = 2.4V
(An on-chip pull-up will drive dsack0_n to
approximately 2.4V; an external pull-up is
required to drive this signal to a higher
voltage.)
tCHKH2
cs_n High to dsack0_n = 2.8V
tCHKZ
tCHCL
tCHAI
tCLCH
tDVCH
cs_n High to dsack0_n Float
cs_n Width between Successive Cycles
cs_n High to Address Invalid
cs_n Width Low
CPU Write Data Valid to cs_n High
Copyright  2007
Maximum
8 MHz
4 MHz
2 MHz
3 ns
©
Page 34 of 45
—
0 ns
55 ns
0 ns
1.5 tmclk + 100 ns
0 ns
3.5 tmclk + 100 ns
—
23 ns
< 0 ns
—
15 ns
0 ns
—
—
—
35 ns
0 ns
—
EN21070504-00
16 MHz
10 MHz
8 MHz
55 ns
150 ns
0 ns
25 ns
7 ns
65 ns
20 ns
100 ns
—
—
—
—
continued . . .
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Table 10. Mode 3 Asynchronous Operation Timing, continued
Symbol
tCLKL
tCHKL
tCOPD
tCHCL
Parameter
Minimum
cs_n Low to dsack0_n Low
(for High- and Low-Speed Registers)
Write Cycle without Previous Write
End of Previous Write (cs_n High) to
dsack0_n Low for a Write Cycle with a
Previous Write
clkout Period
(CDV is the value loaded in the CLKOUT
Register representing the clkout divisor.)
clkout High Period
(CDV is the value loaded in the CLKOUT
Register representing the clkout divisor.)
Maximum
0 ns
67 ns
0 ns
2 tmclk + 145 ns
(CDV + 1) * tosc
(CDV + 1) * ½ tosc – 10
(CDV + 1) * ½ tosc – 15
Figure 12. Mode 3, Asynchronous Operation, Read Cycle
Copyright  2007
EN21070504-00
©
Page 35 of 45
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Figure 13. Mode 3, Asynchronous Operation, Write Cycle
Copyright  2007
EN21070504-00
©
Page 36 of 45
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Table 11. Mode 3 Synchronous Operation Timing
Symbol
1/tXTAL
1/tSCLK
1/tMCLK
tEHDV
tELDH
tELDZ
tELDV
tAVEH
tELAV
tCVEH
tELCV
tDVEL
tEHEL
tAVAV
tAVCL
tCHAI
tCOPD
tCHCL
Parameter
Minimum
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
e High to Data Valid
(for High-Speed Registers 02H, 04H,
and 5H)
e High to Data Valid
(for Low-Speed Registers)
Read Cycle without Previous Write
e High to Data Valid
(for Low-Speed Registers)
Read Cycle with Previous Write
Data Hold after e Low for a Read Cycle
Data Float after e Low
Data Hold after e Low for a Write Cycle
Address and r-w_n to e Setup
Address and r-w_n Valid after e Falls
cs_n Valid to e High
cs_n Valid after e Low
Data Setup to e Low
e Active Width
Start of a Write Cycle after a Previous
Write Access
Address or r-w_n to cs_n Low Setup
cs_n High Address Invalid
clkout Period
(CDV is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
clkout High Period
(CDV is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
Copyright  2007
8 MHz
4 MHz
2 MHz
Page 37 of 45
16 MHz
10 MHz
8 MHz
—
55 ns
—
1.5 tmclk + 100 ns
—
3.5 tmclk + 100 ns
5 ns
—
—
35 ns
15 ns
25 ns
15 ns
0 ns
0 ns
55 ns
100 ns
—
—
—
—
—
—
—
2 tmclk
—
3 ns
7 ns
—
—
(CDV + 1) * tosc
(CDV + 1) * ½ tosc – 10
EN21070504-00
©
Maximum
(CDV + 1) * ½ tosc + 15
www.Innovasic.com
Customer Support:
1-888-824-4184
04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Figure 14. Mode 3, Synchronous Operation, Read Cycle Timing
Copyright  2007
EN21070504-00
©
Page 38 of 45
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Figure 15. Mode 3, Synchronous Operation, Write Cycle Timing
Copyright  2007
EN21070504-00
©
Page 39 of 45
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Table 12. Serial Interface Mode Timing
Symbol
sclk
tCYC
tSKHI
tSKLO
tLEAD
tLAG
tACC
tPDO
tHO
tDIS
tSETUP
tHOLD
tRISE
tFALL
tCS
tCOPD
tCHCL
Parameter
Minimum
Serial Port Interface Clock
1/sclk
Minimum Clock High Time
Minimum Clock Low Time
Enable Lead Time
Enable Lag Time
Access Time
Maximum Data Out Delay Time
Minimum Data Out Hold Time
Maximum Data Out Disable Time
Minimum Data Setup Time
Minimum Data Hold Time
Maximum Time for Input to go from
VOL to VOH
Maximum Time for input to go from
VOH to VOL
Minimum Time between Consecutive
cs_n Assertions
clkout Period
(CDV is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
clkout High Period
(CDV is the value loaded in the
CLKOUT Register representing the
clkout divisor.)
Copyright  2007
0.5 MHz
125 ns
84 ns
84 ns
70 ns
109 ns
Page 40 of 45
8 MHz
2000 ns
—
—
—
—
—
—
50 ns
59 ns
0 ns
—
35 ns
84 ns
—
—
665 ns
—
100 ns
—
100 ns
—
670 ns
(CDV + 1) * tosc
(CDV + 1) * ½ tosc – 10
EN21070504-00
©
Maximum
(CDV + 1) * ½ tosc + 15
www.Innovasic.com
Customer Support:
1-888-824-4184
04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
PRELIMINARY
Figure 16. Serial Interface Mode, icp = 0 and cp = 0
Figure 17. Serial Interface Mode, icp = 1 and cp = 1
Copyright  2007
EN21070504-00
©
Page 41 of 45
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
As of Production Ver. 00
6.
PRELIMINARY
Physical Dimensions
For the Innovasic Semiconductor IA82527 Serial Communications Interface, the physical
dimensions for the available packages are provided in the following figures:
•
•
44-Pin PLCC Package: Figure 18
44-Pin QFP Package: Figure 19
A table specifying dimensions accompanies each figure (Tables 13 and 14).
Copyright  2007
EN21070504-00
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Figure 18. 44-Pin PLCC Physical Dimensions
Table 13. 44-Pin PLCC Physical Dimensions
Dimension
Number of Pins
Number of Pins per Side
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
Copyright  2007
n
n1
p
A
A2
A1
E
D
E1
D1
c
B
CH
α
β
Minimum
Nominal
Maximum
Units
—
—
44
11
0.0500
—
—
—
—
—
—
—
—
0.0170
—
—
—
—
—
—
0.1650
0.1450
0.0200
0.6850
0.6850
0.6500
0.6500
0.0077
0.0130
0.0420
—
—
EN21070504-00
©
Page 43 of 45
7.00
7.00
—
0.1800
0.1600
—
0.6950
0.6950
0.6560
0.6560
0.1160
0.0210
0.0560
—
—
inches
degrees
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
Figure 19. 44-Pin QFP Physical Dimensions
Table 14. 44-Pin QFP Physical Dimensions
Dimensions
Number of Pins
Number of Pins per Side
Pitch
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Copyright  2007
n
n1
p
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
α
β
φ
Minimum
Nominal
Maximum
Units
—
—
—
—
—
—
0.029
—
0.510
0.510
0.390
0.390
0.005
0.012
—
5.00
5.00
0.00
44
11
0.031
—
—
—
—
0.096
—
—
0.041
—
0.530
0.530
0.398
0.398
0.009
0.018
—
16.00
16.00
10.00
—
—
EN21070504-00
©
Page 44 of 45
0.079
0.010
0.035
0.063
0.520
0.520
0.394
0.394
0.007
0.015
0.030
—
—
—
inches
degrees
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Customer Support:
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04 May 2007
IA82527
CAN Serial Communications Controller
PRELIMINARY
As of Production Ver. 00
7.
Ordering Information
Ordering information for the Innovasic IA82527 Serial Communications Controller is provided in
Table 15.
Table 15. IA82527 Ordering Information
®
Innovasic
Part Number
Intel
Part Number
Package
Status
IA82527-PLC44A
AS/AN82527F8
Standard
IA82527-PTQ44A
AS/AN82527F8
Standard
IA82527-PLC44A-R
AS/AN82527F8
RoHS
IA82527-PTQ44A-R
AS/AN82527F8
RoHS
Package
Type
44-Pin Plastic Leaded
Chip Carrier (PLCC)
44-Pin Quad Flat
Package (QFP)
44-Pin Plastic Leaded
Chip Carrier (PLCC)
44-Pin Quad Flat
Package (QFP)
Temperature
Grades
Automotive
Automotive
Automotive
Automotive
Other packages and temperature grades may be available for an additional cost, longer lead
time, or both.
Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130
Albuquerque, NM 87107-4327
Office:
FAX:
Toll Free:
505.883.5263
505.883.5477
1-888.824.4184
www.innovasic.com
Copyright  2007
EN21070504-00
©
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