2.5V/3.3V TWO INPUT , 1GHz Precision Edge™ LVTTL/CMOS-TO-LVPECL SY89834U 1:4 FANOUT BUFFER/TRANSLATOR FEATURES ■ Guaranteed AC performance over temperature and voltage: • > 1.0GHz fMAX • < 20ps within-device skew • < 225ps rise/fall times ■ Low jitter design: • Cycle-to-cycle: < 1ps (rms) • Total jitter: < 10ps (pk-pk) ■ Low voltage 2.5V and 3.3V supply operation ■ Four differential 100k LVPECL outputs ■ Wide operating temperature range: –40°C to +85°C ■ Includes a 2:1 MUX select input ■ Accepts single-ended TTL/CMOS inputs and provides four LVPECL outputs ■ Available in 16-pin (3mm × 3mm) MLF™ package Precision Edge™ DESCRIPTION The SY89834U is a high-speed, 2GHz LVTTL/CMOS-toLVPECL fanout buffer/translator optimized for high-speed ultra-low skew applications. The input stage is designed to accept two single-ended LVTTL/CMOS compatible signals that feed into a 2:1 MUX. The selected input is translated and distributed as four differential 100K compatible LVPECL outputs. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature. The single-ended input buffers accept TTL/CMOS logic levels. The internal threshold of the buffers is defined as VCC/2. The SY89834U is a part of Micrel's high-speed Precision Edge™ family. For applications that require a different I/O combination, consult Micrel's website at www.micrel.com, and choose from a comprehensive product line of highspeed, low-skew fanout buffers, translators and clock generators. APPLICATIONS ■ ■ ■ ■ ■ FUNCTIONAL BLOCK DIAGRAM Processor clock distribution/translation SONET clock distribution/translation Fibre Channel clock distribution/translation Gigabit Ethernet clock distribution/translation Single-ended ASIC-to-differential communication IC signal translation Q0 /Q0 SEL Q1 IN1 (LVTTL/CMOS) /Q1 1 MUX IN2 (LVTTL/CMOS) 0 Q2 /Q2 D Q EN Q3 /Q3 2 Single-Ended Clock/Data Inputs 4 Differential LVPECL Outputs Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: C 1 Amendment: /0 Issue Date: February 2003 PRELIMINARY Precision Edge™ SY89834U Micrel PACKAGE/ORDERING INFORMATION /Q0 Q0 VCC GND Ordering Information 16 15 14 13 Q1 1 12 IN1 /Q1 2 11 Q2 /Q2 3 4 10 9 SEL NC IN2 Part Number Package Type Operating Range Package Marking SY89834UMI MLF-16 Industrial 834U SY89834UMITR* MLF-16 Industrial 834U *Tape and Reel Q3 /Q3 VCC EN 5 6 7 8 16-Pin MLF™ PIN DESCRIPTION Pin Number Pin Name Pin Function 15, 16 1, 2, 3, 4, 5, 6 (Q0, /Q0) to (Q3, /Q3) LVPECL Differential (Outputs): Terminate to VCC–2V. See “Termination Recommendations” section. Unused outputs may be left floating without impacting jitter and skew. 8 EN TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will go LOW and /Q outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a 25kΩ pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal (IN1, IN2). 9, 12 IN2, IN1 10 NC No Connect. Not internally connected. 11 SEL TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is VCC/2V. HIGH at the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25kΩ pull-up resistor. The default state is HIGH when left floating. 13, Exposed Pad GND Ground. Exposed pad internally connected to GND and must be connected to a ground plane for proper termination. 7, 14 VCC Positive Power Supply: Connect VCC pins together on the PCB to maintain the same potential. Bypass with 0.1µF//0.01µF low ESR capacitors. TTL/CMOS Compatible Data/Clock (Inputs): IN1 and IN2 include a 25kΩ pull-up resistor. The default state is HIGH when left floating. TRUTH TABLE IN1 IN2 EN SEL Q0–Q3 /Q0–Q3 0 X 1 1 0 1 1 X 1 1 1 0 X 0 1 0 0 1 X 1 1 0 1 0 X 0(1) 0(1) X Note 1. X 0 On next negative transition of the input signal (IN). 2 PRELIMINARY Precision Edge™ SY89834U Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) ............................... –0.5V to VCC +0.3V ECL Output Current (IOUT) Continuous ............................................................. 50mA Surge .................................................................... 100mA Input Current (IN1, IN2) ............................................ ±50mA Lead Temperature (Soldering, 10sec.), ................... 220°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage Range .......................... +2.375V to +3.63V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF™ (ψJB) Junction-to-Board, Note 3 .............. 32°C/W Note 1. Note 2. Note 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) TA = –40°C to +85°C Symbol Parameter VCC Power Supply Voltage Range ICC Power Supply Current No load, maximum supply voltage VIN Input Voltage Swing see Figures 2a–2b. 0.1 VDIFF_IN Input Differential Swing see Figures 2a–2b. 0.2 Note 1. Note 2. Condition Min Typ 2.375 Max Units 3.63 V 75 mA 50 The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and airflow greater than 500lfpm is maintained. Specification for packaged product only. LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5% or VCC = 3.3V ±10% , TA = –40°C to +85°C Symbol Parameter VIH Input HIGH Voltage VIL Max Units 2.0 VCC V Input LOW Voltage 0 0.8 V IIH Input HIGH Current –125 20 µA IIL Input LOW Current –300 µA Note 1. Note 2. Condition Min Typ The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. (100KEP) LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5% or VCC = 3.3V ±10% , TA = –40°C to +85°C Symbol Parameter Condition VOH Output HIGH Voltage RL = 50Ω to VCC–2V VCC–1.145 VCC–1.020 VCC–0.895 V VOL Output LOW Voltage RL = 50Ω to VCC–2V VCC–1.945 VCC–1.820 VCC–1.695 V VOUT Output Voltage Swing see Figures 2a–2b. 550 800 1050 mV VDIFF_OUT Differential Output Voltage Swing see Figures 2a–2b. 1100 1600 2100 mV Note 1. Note 2. Min Typ Max The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. 3 Units PRELIMINARY Precision Edge™ SY89834U Micrel AC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5% or 3.3V ±10%, TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units fMAX Maximum Frequency Input tr / tf ≥ 350ps, Note 2 1.0 tPLH tPHL Propagation Delay (IN1, IN2-to-Q) Note 4 200 320 500 ps tSW Switchover Time (SEL-to-Q) 200 320 500 ps tSKEW Within-Device Skew 5 20 ps 300 ps 1 1 ps(rms) ps(pk-pk) 55 % GHz Note 5 Part-to-Part Skew tJITTER Cycle-to-Cycle Jitter Total Jitter Note 6 Note 7 DC Duty Cycle Input tr/tf ≥ 350ps, Note 8 45 tS Set-Up Time (EN to IN1, IN2) Note 9 and Note 10 300 ps tH Hold Time (EN to IN1, IN2) Note 9 and Note 10 500 ps t r, t f Output Rise/Fall Times (20% to 80%) 70 50 140 225 ps Note 1. Measured with a 2.0V input signal, 50% duty cycle, all PECL loading with 50Ω to VCC–2V. Output swing is ≥ 400mV. Note 2. Specification for packaged product only. Note 3. fMAX is defined as the maximum input frequency while enduring a valid output. fMAX is limited by the input stage. Note 4. VIH = 2.0V, VIL = 0.8V, 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with VCC/2 as the crossing of the differential output signal. See Figure 1. Note 5. Skew is measured between outputs under identical transitions. Note 6. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn – Tn+1, where T is the time between rising edges of the output signal. Note 7. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. Note 8. If tr/tf is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits. Note 9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications set-up and hold times do not apply. Note 10. See “Timing Diagrams,” Figure 1a. 4 PRELIMINARY Precision Edge™ SY89834U Micrel TIMING DIAGRAMS EN VCC/2 VCC/2 tS tH VIN IN /Q VCC/2 VCC/2 VCC/2 VCC/2 tPHL tPLH VOUT Swing Q Figure 1a. Timing Diagram (EN, IN1, IN2) IN2 HIGH IN1 LOW SEL VCC/2 /Q VCC/2 tSWITCHOVER tSWITCHOVER VOUT Q Figure 1b. Timing Diagram (SEL) DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VDIFF_IN , V DIFF_OUT VIN, VOUT Figure 2b. Differential Swing Figure 2a. Single-Ended Swing 5 PRELIMINARY Precision Edge™ SY89834U Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, TA = 25°C, VIN = 2.0V, unless otherwise stated. PROPAGATION DELAY (ps) OUTPUT SWING (mV) 800 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 FREQUENCY (GHz) 3 400 380 t Propagation Delay vs. Temperature SKEW vs. Temperature 10 9 360 340 8 7 tSKEW (ps) Output Swing vs. Frequency 320 300 280 6 5 4 260 240 3 2 220 200 -50 -30 -10 10 30 50 70 TEMPERATURE (°C) 1 0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 6 90 PRELIMINARY Precision Edge™ SY89834U Micrel FUNCTIONAL CHARACTERISTICS VCC = 3.3V, VEE = 0V, VIN = 800mV, TA = 25°C, unless otherwise stated. 155MHz Output 300mV Offset (150mV/div.) 275mV Offset (150mV/div.) 622MHz Output TIME (1ns/div.) TIME (321.9ps/div.) 300mV Offset (150mV/div.) 1GHz Output TIME (200ps/div.) 7 PRELIMINARY Precision Edge™ SY89834U Micrel DIFFERENTIAL INPUT VCC 25k R IN1 IN2 SEL EN R GND Figure 3. Simplified TTL/CMOS Input Buffer RELATED PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89830U 2.5V/3.3V/5V 2.5GHz 1:4 PECL/ECL Clock Driver with 2:1 Differential Input Mux http://www.micrel.com/product-info/products/sy89830u.shtml SY89831U 2GHz Ultra Low-Jitter and Skew 1:4 LVPECL Fanout Buffer/Translator w/ Internal Termination http://www.micrel.com/product-info/products/sy89831u.shtml SY89832U 2GHz Ultra Low-Jitter and Skew 1:4 LVPECL Fanout Buffer/Translator w/ Internal Termination http://www.micrel.com/product-info/products/sy89832u.shtml 2GHz Any Differential INPUT-to-LVDS Out 1:4 Fanout Buffer Translator w/ Internal Termination http://www.micrel.com/product-info/products/sy89833u.shtml 16-MLF™ Manufacturing Guidelines Exposed Pad Application Note http://www.amkor.com/products/notes-papers/ MLF-appnote-0301.pdf New Products + Termination App Note http://www.micrel.com/product-info/as/solutions.shtml SY89833U HBW Solutions 8 PRELIMINARY Precision Edge™ SY89834U Micrel TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V ZO = 50Ω Vt = VCC —2V Figure 4a. Parallel Termination–Thevenin Equivalent Note 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω For +3.3V systems: R1 = 130Ω, R2 = 82Ω +3.3V +3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω source destination 50Ω Rb C1 0.01µF (optional) Figure 4b. Three-Resistor “Y–Termination” Note 1. Note 2. Note 3. Power-saving alternative to Thevenin termination. Place termination resistors as close to destination inputs as possible. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 50Ω. For +2.5V systems Rb = 39Ω. +3.3V +3.3V Q +3.3V R1 130Ω R1 130Ω V = VCC —1.3V R3 t +3.3V 1kΩ ZO = 50Ω /Q R4 1.6kΩ Vt = VCC —2V R2 82Ω R2 82Ω Figure 4c. Terminating Unused LVPECL I/O Note 1. Note 2. Note 3. Unused output (/Q) must be terminated to balance the output. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ. Unused output pairs (Q and /Q) may be left floating. 9 PRELIMINARY Precision Edge™ SY89834U Micrel 16 LEAD EPAD MicroLeadFrame™ (MLF-16) 0.42 +0.18 –0.18 0.23 +0.07 –0.05 0.85 +0.15 –0.65 0.01 +0.04 –0.01 3.00BSC 1.60 +0.10 –0.10 0.65 +0.15 –0.65 0.20 REF. 2.75BSC 0.42 PIN 1 ID +0.18 –0.18 N 16 1 1 0.50 DIA 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 –0.10 4 4 12° max 0.5 BSC 0.42 +0.18 –0.18 SEATING PLANE 0.40 +0.05 –0.05 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 –0.05 CL 4 0.01 +0.04 –0.01 SECTION "C-C" SCALE: NONE 0.5BSC 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS FOR EVEN TERMINAL/SIDE Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB.) Package Notes: Note 1. Note 2. MICREL, INC. TEL Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form. Exposed pads must be soldered to a ground for proper thermal management. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 10