High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FEATURES FUNCTIONAL BLOCK DIAGRAM STANDARD USB 2.0 HSC-ADC-EVALB-SC OR HSC-ADC-EVALB-DC SINGLE OR DUAL HIGH-SPEED ADC EVALUATION BOARD FILTERED ANALOG INPUT REG ADC EQUIPMENT NEEDED Analog signal source and antialiasing filter Low jitter clock source High speed ADC evaluation board and ADC data sheet PC running Windows 98 (2nd ed.), Windows 2000, Windows Me, or Windows XP Latest version of ADC Analyzer USB 2.0 port recommended (USB 1.1-compatible) PRODUCT DESCRIPTION The high speed ADC FIFO evaluation kit includes the latest version of ADC Analyzer and a buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The FIFO board is connected to the PC through a USB port and is used with ADC Analyzer to quickly evaluate the performance of high speed ADCs. Users can view an FFT for a specific analog input and encode rate to analyze SNR, SINAD, SFDR, and harmonic information. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC. Two versions of the FIFO are available. The HSC-ADC-EVALBDC is used with multichannel ADCs and converters with demultiplexed digital outputs. The HSC-ADC-EVALB-SC evaluation board is used with single-channel ADCs. See Table 1 to choose the FIFO appropriate for your high speed ADC evaluation board. CHB FIFO, 32K, 133MHz n TIMING CIRCUIT USB CTLR CHA FIFO, 32K, 133MHz n CLOCK CIRCUIT PS +3.0V REG SPI SPI CLOCK INPUT 120-PIN CONNECTOR 05870-001 PS LOGIC Buffer memory board for capturing digital data used with high speed ADC evaluation boards to simplify evaluation 32 kB FIFO depth at 133 MSPS (upgradable) Measures performance with ADC Analyzer™ Real-time FFT and time domain analysis Analyzes SNR, SINAD, SFDR, and harmonics Simple USB port interface (2.0) Supporting ADCs with serial port interfaces (SPI®) On-board regulator circuit, no power supply required 6 V, 2 A switching power supply included Compatible with Windows® 98 (2nd ed.), Windows 2000, Windows Me, and Windows XP Figure 1. PRODUCT HIGHLIGHTS 1. Easy to Set Up. Connect the included power supply and signal sources to the two evaluation boards. Then connect to the PC and evaluate the performance instantly. 2. ADIsimADC™. ADC Analyzer supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between multiple ADCs, with or without hardware evaluation boards. For more information, see AN-737 at www.analog.com/ADIsimADC. 3. USB Port Connection to PC. PC interface is a USB 2.0 connection (1.1-compatible) to the PC. A USB cable is provided in the kit. 4. 32 kB FIFO. The FIFO stores data from the ADC for processing. A pin-compatible FIFO family is used for easy upgrading. 5. Up to 133 MSPS Encode Rate on Each Channel. Singlechannel ADCs with encode rates up to 133 MSPS can be used with the FIFO board. Multichannel and demultiplexed output ADCs can also be used with the FIFO board with clock rates up to 266 MSPS. 6. Supports ADC with Serial Port Interface or SPI. Some ADCs include a feature set that can be changed via the SPI. The FIFO supports these SPI-driven features through the existing USB connection to the computer without additional cabling needed. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC TABLE OF CONTENTS Features .............................................................................................. 1 Clocking with Interleaved Data................................................ 10 Equipment Needed........................................................................... 1 Connecting to the HSC-ADC-FPGA-4/-8 ............................. 10 Product Description......................................................................... 1 Connecting to the DEMUX BRD ............................................ 10 Functional Block Diagram .............................................................. 1 Upgrading FIFO Memory......................................................... 10 Product Highlights ........................................................................... 1 Jumpers ............................................................................................ 11 Revision History ............................................................................... 2 Default Settings........................................................................... 11 FIFO Evaluation Board Easy Start.................................................. 3 Evaluation Board ............................................................................ 13 Requirements ................................................................................ 3 Power Supplies............................................................................ 13 Easy Start Steps ............................................................................. 3 Connection and Setup ............................................................... 13 Virtual Evaluation Board Easy Start With ADIsimADC ............ 4 FIFO Schematics and PCB Layout ............................................... 14 Requirements ................................................................................ 4 Schematics................................................................................... 14 Easy Start Steps ............................................................................. 4 PCB Layout ................................................................................. 21 FIFO 4.1 Data Capture Board Features ......................................... 5 Bill of Materials............................................................................... 23 FIFO 4.1 Supported ADC Evaluation Boards .......................... 6 Ordering Information.................................................................... 25 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 25 Clocking Description................................................................... 9 ESD Caution................................................................................ 25 SPI Description............................................................................. 9 REVISION HISTORY 2/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FIFO EVALUATION BOARD EASY START REQUIREMENTS • FIFO evaluation board, ADC Analyzer, and USB cable • High speed ADC evaluation board and ADC data sheet • Power supply for ADC evaluation board • Analog signal source and appropriate filtering • Low jitter clock source applicable for specific ADC evaluation, typically <1 ps rms • PC running Windows 98 (2nd ed.), Windows 2000, Windows Me, or Windows XP • PC with a USB 2.0 port recommended (USB 1.1compatible) 6. Once the cable is connected to both the computer and the FIFO board, and power is supplied, the USB drivers start to install. To complete the total installation of the FIFO drivers, you need to complete the new hardware sequence two times. The first Found New Hardware Wizard opens with the text message This wizard helps you install software for…Pre-FIFO 4.1. Click the recommended install, and go to the next screen. A hardware installation warning window should then be displayed. Click Continue Anyway. The next window that opens should finish the PreFIFO 4.1 installation. Click Finish. Your computer should go through a second Found New Hardware Wizard, and the text message, This wizard helps you install software for…Analog Devices FIFO 4.1, should be displayed. Continue as you did in the previous installation and click Continue Anyway. Then click Finish on the next two windows. This completes the installation. 7. (Optional) Verify in the device manager that Analog Devices, FIFO4.1 is listed under the USB hardware. 8. Apply power to the evaluation board and check the voltage levels at the board level. 9. Connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. Make sure the evaluation boards are powered on before connecting the analog input and clock. EASY START STEPS Note: You need administrative rights for the Windows operating systems during the entire easy start procedure. It is recommended to complete every step before reverting to a normal user mode. 1. 2. Install ADC Analyzer from the CD provided in the FIFO evaluation kit or download the latest version on the Web. For the latest updates to the software, check the Analog Devices website at www.analog.com/hsc-FIFO. Connect the FIFO evaluation board to the ADC evaluation board. If an adapter is required, insert the adapter between the ADC evaluation board and the FIFO board. If using the HSC-ADC-EVALB-SC model, connect the evaluation board to the bottom two rows of the 120-pin connector, closest to the installed IDT FIFO chip. If using an ADC with a SPI interface, remove the two 4-pin corner keys so that the third row can be connected. 3. Connect the provided USB cable to the FIFO evaluation board and to an available USB port on the computer. 4. Refer to Table 5 for any jumper changes. Most evaluation boards can be used with the default settings. 5. After verification, connect the appropriate power supplies to the ADC evaluation boards. The FIFO evaluation board is supplied with a wall mount switching power supply that provides a 6 V, 2 A maximum output. Connect the supply end to the rated 100 ac to 240 ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at J301. Refer to the instructions included in the ADC data sheet for more information about the ADC evaluation board’s power supply and other requirements. 10. Start ADC Analyzer. 11. Choose an existing configuration file for the ADC evaluation board or create one. 12. Click Time Data in ADC Analyzer (left-most button under the menus). A reconstruction of the analog input is displayed. If the expected signal does not appear, or if there is only a flat red line, refer to the ADC Analyzer data sheet at www.analog.com/hsc-FIFO for more information. Rev. 0 | Page 3 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC VIRTUAL EVALUATION BOARD EASY START WITH ADIsimADC REQUIREMENTS 5. In the ADC Modeling dialog box, click the Device tab and then click the … (Browse) button, adjacent to the dialog box. This opens a file browser and displays all of the models found in the default directory: c:\program files\adc_analyzer\models. If no model files are found, follow the on-screen directions or see Step 1 to install available models. If you have saved the models somewhere other than the default location, use the browser to navigate to that location and select the file of interest. No hardware is required. However, if you wish to compare results of a real evaluation board and the model, you can switch easily between the two, as outlined in the following Easy Start Steps section. 6. From the menu, click Config > FFT. In the FFT Configuration dialog box, ensure that the Encode Frequency is set for a valid rate for the simulated device under test. If set too low or too high, the model does not run. EASY START STEPS 7. Once a model has been selected, information about the model displays on the Device tab of the ADC Modeling dialog box. After ensuring that you have selected the right model, click the Input tab. This lets you configure the input to the model. Click either Sine Wave or Two Tone for the input signal. 8. Click Time Data (left-most button under the pull-down menus). A reconstruction of the analog input is displayed. The model can now be used just as a standard evaluation board would be. 9. The model supports additional features not found when testing a standard evaluation board. When using the modeling capabilities, it is possible to sweep either the analog amplitude or the analog frequency. For more information consult the ADC Analyzer User Manual at www.analog.com/hsc-FIFO. Requirements include • Completed installation of ADC Analyzer, Version 4.5.17 or later. • ADIsimADC product model files for the desired converter. Models are not installed with the software, but they can be downloaded from the ADIsimADC Virtual Evaluation Board website at no charge. 1. To get ADC model files, go to www.analog.com/ADIsimADC for the product of interest. Download the product of interest to a local drive. The default location is c:\program files\adc_analyzer\models. 2. Start ADC Analyzer (see the ADC Analyzer User Manual). 3. From the menu, click Config > Buffer > Model as the buffer memory. In effect, the model functions in place of the ADC and data capture hardware. 4. After selecting the model, click the Model button (located next to the Stop button) to select and configure which converter is to be modeled. A dialog box appears in the workspace, where you can select and configure the behavior of the model. Rev. 0 | Page 4 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FIFO 4.1 DATA CAPTURE BOARD FEATURES 6V SWITCHING POWER SUPPLY CONNECTION IDT72V283 32k ⋅ 16-BIT 133MHz FIFO TIMING ADJUSTMENT JUMPERS ON BOARD +3.3V REGULATOR 120-CONNECTOR (PARALLEL CMOS INPUTS) OPTIONAL POWER CONNECTION IDT72V283 32k ⋅ 16-BIT 133MHz FIFO USB CONNECTION TO COMPUTER OPTIONAL SERIAL PORT INTERFACE CONNECTOR RESET SWITCH WHEN ENCODE RATE IS INTERRUPTED Figure 2. FIFO Components (Top View) Rev. 0 | Page 5 of 28 µCONTROLLER CRYSTAL CLOCK = 24MHz, OFF DURING DATA CAPTURE 05870-002 OPEN SOLDER MASK ON ALL DATA AND CLOCK LINES FOR EASY PROBING HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC 120-CONNECTOR (PARALLEL CMOS INPUTS) TIMING ADJUSTMENT JUMPERS EPROM TO LOAD USB FIRMWARE DRIVER CIRCUIT FOR SERIAL PORT INTERFACE (SPI) LINES CYPRESS Fx2 HIGH SPEED USB 2.0 µCONTROLLER 05870-003 OPTIONAL SERIAL PORT INTERFACE (SPI) CONNECTOR Figure 3. FIFO Components (Bottom View) FIFO 4.1 SUPPORTED ADC EVALUATION BOARDS The evaluation boards in Table 1 can be used with the high speed ADC FIFO evaluation kit. Some evaluation boards require an adapter between the ADC evaluation board connector and the FIFO connector. If an adapter is needed, send an email to [email protected] with the part number of the adapter and a mailing address. Table 1. HSC-ADC-EVALB-DC- and HSC-ADC-EVALB-SC-Compatible Evaluation Boards 1 Evaluation Board Model AD6644ST/PCB AD6645-80/PCB AD6645-105/PCB AD9051/PCB AD9200SSOP-EVAL AD9200TQFP-EVAL AD9201-EVAL AD9203-EB AD9212-65EB1 AD9215BCP-65EB AD9215BCP-80EB AD9215BCP-105EB AD9215BRU-65EB AD9215BRU-80EB AD9215BRU-105EB AD9216-80PCB AD9216-105PCB Description of ADC 14-bit, 65 MSPS ADC 14-bit, 80 MSPS ADC 14-bit, 105 MSPS ADC 10-bit, 60 MSPS ADC 10-bit, 20 MSPS ADC 10-bit, 20 MSPS ADC Dual 10-bit, 20 MSPS ADC1 10-bit, 40 MSPS ADC Octal 10-bit, 65 MSPS ADC 10-bit, 65 MSPS ADC 10-bit, 80 MSPS ADC 10-bit, 105 MSPS ADC 10-bit, 65 MSPS ADC 10-bit, 80 MSPS ADC 10-bit, 105 MSPS ADC Dual 10-bit, 80 MSPS ADC Dual 10-bit, 105 MSPS ADC FIFO Board Version SC SC SC SC SC SC SC SC DC SC SC SC SC SC SC DC DC Rev. 0 | Page 6 of 28 Comments Requires AD9051FFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires HSC-ADC-FPGA-8 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Evaluation Board Model AD9218-105PCB AD9218-65PCB AD9219-65EB1 AD9220-EB AD9222-65EB1 AD9226-EB AD9226QFP-EB AD9228-65EB1 AD9229-65EB1 AD9233-80EB AD9233-105EB AD9233-125EB AD9234-EB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9236BRU-80EB AD9236BCP-80EB AD9237BCP-20EB AD9237BCP-40EB AD9237BCP-65EB AD9238BST-20PCB AD9238BST-40PCB AD9238BST-65PCB AD9238BCP-20EB AD9238BCP-40EB AD9238BCP-65EB AD9240-EB AD9241-EB AD9243-EB AD9244-40PCB AD9244-65PCB AD9245BCP-20EB AD9245BCP-40EB AD9245BCP-65EB AD9245BCP-80EB AD9246-80EB AD9246-105EB AD9246-125EB AD9248BST-65EB AD9248BCP-20EB AD9248BCP-40EB AD9248BCP-65EB AD9259-50EB1 AD9260-EB AD9280-EB AD9281-EB AD9283/PCB AD9287-100EB1 AD9289-65EB1 AD9411/PCB Description of ADC 10-bit, 105 MSPS ADC 10-bit, 65 MSPS ADC Quad 10-bit, 65 MSPS ADC 12-bit, 10 MSPS ADC Octal 12-bit, 65 MSPS ADC 12-bit, 65 MSPS ADC 12-bit, 65 MSPS ADC Quad 12-bit, 65 MSPS ADC Quad 12-bit, 65 MSPS ADC 12-bit, 80MSPS ADC 12-bit, 105MSPS ADC 12-bit, 125MSPS ADC 12-bit, 150MSPS ADC 12-bit, 20 MSPS ADC 12-bit, 40 MSPS ADC 12-bit, 65 MSPS ADC 12-bit, 20 MSPS ADC 12-bit, 40 MSPS ADC 12-bit, 65 MSPS ADC 12-bit, 80 MSPS ADC 12-bit, 80 MSPS ADC 12-bit, 20 MSPS ADC 12-bit, 40 MSPS ADC 12-bit, 65 MSPS ADC Dual 12-bit, 20 MSPS ADC Dual 12-bit, 40 MSPS ADC Dual 12-bit, 65 MSPS ADC Dual 12-bit, 20 MSPS ADC Dual 12-bit, 40 MSPS ADC Dual 12-bit, 65 MSPS ADC 14-bit, 40 MSPS ADC 14-bit, 1.25 MSPS ADC 14-bit, 3 MSPS ADC 14-bit, 40 MSPS ADC 14-bit, 65 MSPS ADC 14-bit, 20 MSPS ADC 14-bit, 40 MSPS ADC 14-bit, 65 MSPS ADC 14-bit, 80 MSPS ADC 14-bit, 80 MSPS ADC 14-bit, 105 MSPS ADC 14-bit, 125 MSPS ADC Dual 14-bit, 65 MSPS ADC Dual 14-bit, 20 MSPS ADC Dual 14-bit, 40 MSPS ADC Dual 14-bit, 65 MSPS ADC Quad 14-bit, 50 MSPS ADC 16-bit, 2.5 MSPS ADC 8-bit, 32 MSPS ADC Dual 8-bit, 28 MSPS ADC 8-bit, 100 MSPS ADC Quad 8-bit, 100 MSPS ADC Quad 8-bit, 65 MSPS ADC 10-bit, 200 MSPS ADC FIFO Board Version DC DC DC SC DC SC SC DC DC SC SC SC SC SC SC SC SC SC SC SC SC SC SC Comments Requires HSC-ADC-FPGA-4/-8 Requires AD922xFFA Requires HSC-ADC-FPGA-8 Requires AD922xFFA Requires AD922xFFA Requires HSC-ADC-FPGA-4/-8 Requires HSC-ADC-FPGA-4/-8 SC DC DC DC DC DC DC SC SC SC SC SC SC SC SC SC SC SC SC DC DC DC DC DC SC SC SC SC DC DC DC Rev. 0 | Page 7 of 28 Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires HSC-ADC-FPGA-4/-8 Requires AD922xFFA Requires AD922xFFA Requires AD922xFFA Requires AD9283FFA Requires HSC-ADC-FPGA-4/-8 Requires HSC-ADC-FPGA-9289 Requires DEMUX BRD HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Evaluation Board Model AD9430-CMOS/PCB AD9430-LVDS/PCB2 AD9432/PCB AD9433/PCB AD9444-CMOS/PCB AD9444-LVDS/PCB AD9445-IF-LVDS/PCB AD9445-BB-LVDS/PCB AD9446-80LVDS/PCB AD9446-100LVDS/PCB AD9460-80EB-IF AD9460-80EB-BB AD9460-105EB-IF AD9460-105EB-BB AD9461-130EB-IF AD9461-130EB-BB AD9480-LVDS/PCB2 AD9481-PCB AD10200/PCB AD10201/PCB AD10226/PCB AD10265/PCB AD10465/PCB AD10677/PCB AD10678/PCB AD15252/PCB AD15452/PCB 1 2 Description of ADC 12-bit, 210 MSPS ADC 12-bit, 210 MSPS ADC 12-bit, 105 MSPS ADC 12-bit, 125 MSPS ADC 14 bit, 80 MSPS ADC 14 bit, 80 MSPS ADC 14-bit, 125 MSPS ADC 14-bit, 125 MSPS ADC 16-bit, 80 MSPS ADC 16-bit, 100 MSPS ADC 16-bit, 80 MSPS ADC 16-bit, 80 MSPS ADC 16-bit, 105 MSPS ADC 16-bit, 105 MSPS ADC 16-bit, 130 MSPS ADC 16-bit, 130 MSPS ADC 8-bit, 250 MSPS ADC 8-bit, 250 MSPS ADC Dual 12-bit, 105 MSPS ADC Dual 12-bit, 105 MSPS ADC Dual 12-bit, 125 MSPS ADC Dual 12-bit, 65 MSPS ADC Dual 14-bit, 65 MSPS ADC 16-bit, 65 MSPS ADC 16-bit, 80 MSPS ADC 12-bit, Dual 65 MSPS ADC 12-bit, Quad 65 MSPS ADC FIFO Board Version DC DC SC SC SC SC SC SC SC SC SC SC SC SC SC SC DC DC DC DC DC DC DC SC SC DC DC The high speed ADC FIFO evaluation kit can be used to evaluate two channels at a time. If a DEMUX BRD is needed, send an email to [email protected]. Rev. 0 | Page 8 of 28 Comments Requires DEMUX BRD Requires DEMUX BRD Requires GS09066 Requires GS09066 Requires GS09066 Requires GS09066 Requires GS09066 Requires GS09066 Requires GS09066 Requires HSC-ADC-FPGA-4/-8 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC THEORY OF OPERATION The FIFO evaluation board can be divided into several circuits, each of which plays an important part in acquiring digital data from the ADC and allows the PC to upload and process that data. The evaluation kit is based around the IDT72V283 FIFO chip from Integrated Device Technology, Inc (IDT). The system can acquire digital data at speeds up to 133 MSPS and data record lengths up to 32 kB using the HSC-ADC-EVALB-SC FIFO evaluation kit. The HSC-ADC-EVALB-DC, which has two FIFO chips, is available to evaluate multichannel ADCs or demultiplexed data from ADCs sampling faster than 133 MSPS. A USB 2.0 microcontroller communicating with ADC Analyzer allows for easy interfacing to newer computers using the USB 2.0 (USB 1.1-compatible) interface. The process of filling the FIFO chip or chips and reading the data back requires several steps. First, ADC Analyzer initiates the FIFO chip fill process. The FIFO chips are reset, using a master reset signal (MRS). The USB microcontroller is then suspended, which turns off the USB oscillator and ensures that it does not add noise to the ADC input. After the FIFO chips completely fill, the full flags from the FIFO chips send a signal to the USB microcontroller to wake up the microcontroller from suspend. ADC Analyzer waits for approximately 30 ms and then begins the readback process. During the readback process, the acquisition of data from FIFO 1 (U201) or FIFO 2 (U101) is controlled via Signal OEA and Signal OEB. Because the data outputs of both FIFO chips drive the same 16-bit data bus, the USB microcontroller controls the OEA and OEB signals to read data from the correct FIFO chip. From an application standpoint, ADC Analyzer sends commands to the USB microcontroller to initiate a read from the correct FIFO chip, or from both FIFO chips in dual or demultiplexed mode. CLOCKING DESCRIPTION Each channel of the buffer memory requires a clock signal to capture data. These clock signals are normally provided by the ADC evaluation board and are passed along with the data through Connector J104 (Pin 37 for both Channel A and Channel B). If only a single clock is passed for both channels, they can be connected together by Jumper J303. Jumpers J304 and J305 at the output of the LVDS receiver allow the output clock to be inverted by the LVDS receiver. By default, the clock outputs are inverted by the LVDS receiver. The single-ended clock signal from each data channel is buffered and converted to a differential CMOS signal by two gates of a low voltage differential signal (LVDS) receiver, U301. This allows the clock source for each channel to be CMOS, TTL, or ECL. The clock signals are ac-coupled by 0.1 μF capacitors. Potentiometer R312 and Potentiometer R315 allow for fine tuning the threshold of the LVDS gates. In applications where fine-tuning the threshold is critical, these potentiometers can be replaced with a higher resistance value to increase the adjustment range. Resistors R301, R302, R303, R304, R311, R313, R314, and R316 set the static input to each of the differential gates to a dc voltage of approximately 1.5 V. At assembly, Solder Jumper J310 to Solder Jumper J313 are set to bypass the potentiometer. For fine adjustment using the pot, the solder jumpers must be removed, and R312 and R315 must be populated. U302, an XOR gate array, is included in the design to let users add gate delays to the FIFO memory chip clock paths. They are not required under normal conditions and are bypassed at assembly by Jumper J314 and Jumper J315. Jumper J306 and Jumper J307 allow the clock signals to be inverted through an XOR gate. In the default setting, the clocks are not inverted by the XOR gate. The clock paths described above determine the WRT_CLK1 and WRT_CLK2 signals at each FIFO memory chip (U101 and U201). The timing options above should let you choose a clock signal that meets the setup and hold time requirements to capture valid data. A clock generator can be applied directly to S1 and/or S3. This clock generator should be the same unit that provides the clock for the ADC. These clock paths are ac-coupled, so that a sine wave generator can be used. DC bias can be adjusted by R301/R302 and R303/R304. The DS90LV048A differential line receiver is used to square the clock signal levels applied externally to the FIFO evaluation board. The output of this clock receiver can either directly drive the write clock of the IDT72V283 FIFO(s), or first pass through the XOR gate timing circuitry described above. SPI DESCRIPTION The Cypress IC (U502) supports the HSC SPI standard to allow programming of ADCs that have SPI-accessible register maps. U102 is a buffer that drives the 4-wire SPI (SCLK, SDI, SDO, CSB 1 ) through the 120-pin connector (J104) on the third or top row. J502 is an auxiliary SPI connector to monitor the SPI signals connected directly to the Cypress IC. For more information on this and other functions, consult the user manual titled Interfacing to High Speed ADCs via SPI at www.analog.com/hsc-FIFO. 1 Note that CSB1 is the default CSB line used. Rev. 0 | Page 9 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC The SPI interface designed on the Cypress IC can communicate with up to five different SPI-enabled devices. The CLK and data lines are common to all SPI devices. The correct device is chosen to communicate by using one of the five active low chip select pins. This functionality is controlled by selecting a SPI channel in the software. CLOCKING WITH INTERLEAVED DATA ADCs with very high data rates can exceed the capability of a single buffer memory channel (~133 MSPS). These converters often demultiplex the data into two channels to reduce the rate required to capture the data. In these applications, ADC Analyzer must interleave the data from both channels to process it as a single channel. The user can configure the software to process the first sample from Channel A, the second from Channel B, and so on, or vice versa. The synchronization circuit included in the buffer memory forces a small delay between the write enable signals (WENA and WENB) to the FIFO memory chips (Pin 1, U101, and U201), ensuring that the data is captured in one FIFO before the other. Jumper J401 and Jumper J402 determine which FIFO receives WENA and which FIFO receives WENB. CONNECTING TO THE HSC-ADC-FPGA-4/-8 ADCs that have serial LVDS outputs require another board that is connected between the ADC evaluation board and the FIFO data capture card. This board converts the serial data into parallel CMOS so that the FIFO data capture card can accept the data. For more detailed information on this board, refer to the HSC-ADC-FPGA datasheet at www.analog.com/hsc-FIFO. CONNECTING TO THE DEMUX BRD ADCs that have parallel LVDS outputs require another board that is connected between the ADC evaluation board and the FIFO data capture card. This board converts parallel LVDS to parallel CMOS, using both channels of the FIFO data capture card. For more detailed information on this board, send an email to [email protected] UPGRADING FIFO MEMORY The FIFO evaluation board includes one or two 32 kB FIFOs that are capable of 133 MHz clock signals, depending on the model number. Pin-compatible FIFO upgrades are available from IDT. See Table 2 for the IDT part number matrix. Table 2. IDT Part Number Matrix Part Number IDT72V283-L7-5PF (Default ) IDT72V293-L7-5PF IDT72V2103-L7-5PF IDT72V2113-L7-5PF IDT72V283-L6PF IDT72V293-L6PF IDT72V2103-L6PF IDT72V2113-L6PF FIFO Depth 32 kB 64 kB 132 kB 256 kB 32 kB 64 kB 132 kB 256 kB For more information, visit www.idt.com. Rev. 0 | Page 10 of 28 FIFO Speed 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz 166 MHz 166 MHz HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC JUMPERS Use the legends in Table 3 and Table 4 to configure the jumpers. On the FIFO evaluation board, Channel A is associated with the bottom IDT FIFO chip, and Channel B is associated with the top IDT FIFO chip (closest to the Analog Devices logo). Table 3. Jumper Legend Position In Out Position 1 or Position 3 Description Jumper in place (2-pin header). Jumper removed (2-pin header). Denotes the position of a 3-pin header. Position 1 is marked on the board. Table 4. Solder Jumper Legend Position In Out Description Solder pads should be connected with 0 Ω resistor. Solder pads should not be connected with 0 Ω resistor. DEFAULT SETTINGS Table 5 lists the default settings for each model of the FIFO evaluation kit. The single channel (SC) model is configured to work with a single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single channel ADC. To align the timing properly, some evaluation boards require modifications to these settings. Refer to the Clocking Description section in the Theory of Operation section for more information. Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under Help > About HSC_ADC_EVALB, and click Set Up Default Jumper Wizard. Then click the configuration setting that applies to the application of interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place. Table 5. Jumper Configurations Jumper # J303 J304 Single Channel Settings, Default (Bottom) In In Demultiplexed Settings Out In Dual-Channel Settings Out In Single-Channel Settings (Top) 1 In In J305 In In In In J306 Out Out Out Out J307 Out Out Out Out J310 to J313 J314 In In In In In In In In J315 In In In In J316 J401 In In In In In In In In J402 Out Out Out Out J403 Out Out Out Out J404 In In In In J405 Out In Out Out Rev. 0 | Page 11 of 28 Description Position 2 to Position 4, ties write clocks together Position 1 to Position 2, POS3: invert clock out of DS90 (U301) Position 2 to Position 3, POS3: invert clock out of DS90 (U301) No invert to encode clock from XOR (U302), 0 Ω resistor No invert to encode clock from XOR (U302), 0 Ω resistor All solder jumpers are shorted with 0 Ω resistors (bypass level shifting to input of DS90) Position 1 to Position 2, one XOR gate timing delay for top FIFO (U101) Position 1 to Position 2, one XOR gate timing delay for bottom FIFO (U201) Power connected using switching power supply Controls if top FIFO (U101) gets write enable before or after bottom FIFO, 0 Ω resistor Controls if top FIFO (U101) gets write enable before or after bottom FIFO, 0 Ω resistor Controls if bottom FIFO (U201) gets a write enable before or after the top FIFO, 0 Ω resistor Controls if bottom FIFO (U201) gets a write enable before or after the top FIFO, 0 Ω resistor When in, WRT_CLK1 is used to create write enable signal for FIFOs, 0 Ω resistor (significant only for interleave mode) HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Jumper # J406 Single Channel Settings, Default (Bottom) In Demultiplexed Settings In Dual-Channel Settings In Single-Channel Settings (Top) 1 In J503 In In In In J504 J505 Out In Out In Out In Out In J506 J602 J603 Out Out In Out Out In Out Out In Out Out In 1 Description WRT_CLK2 is used to create write enable signal for FIFOs, 0 Ω resistor (significant only for interleave mode) Connect enable empty flag of top FIFO (U101) to USB MCU, 0 Ω resistor N/A Connect enable full flag of top FIFO (U101) to USB MCU, 0 Ω resistor N/A N/A N/A Some jumpers can be a 0 Ω resistor instead of a physical jumper. This is shown in Table 5 in the jumper description column. Rev. 0 | Page 12 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC EVALUATION BOARD The FIFO provides all of the support circuitry required to accept two channels of an ADC’s digital parallel CMOS outputs. Each of the various functions and configurations can be selected by proper connection of various jumpers (see Table 5). When using this in conjunction with an ADC evaluation board, it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. When operating the evaluation board in a non-default condition, J316 can be removed to disconnect the switching power supply. This enables the user to bias the board independently. Use P302 to connect an independent supply to the board. A 3.3 V supply is needed with at least a 1 A current capability. CONNECTION AND SETUP The FIFO board has a 120-pin (40-pin, triple row) connector that accepts two 16-bit channels of parallel CMOS inputs (see Figure 6). For those ADC evaluation boards that have only an 80-pin (40-pin, double row) connector, it is pertinent for the lower two rows of the FIFO’s triple row connector to be connected in order for the data to pass to either FIFO channel correctly. The top or third row is used to pass SPI signals across to the adjacent ADC evaluation board that supports this feature. See Figure 5 to Figure 15 for complete schematics and layout plots. POWER SUPPLIES The FIFO board is supplied with a wall mount switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 ac to 240 ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at J301. On the PC board, the 6 V supply is then fused and conditioned before connecting to the low dropout 3.3 V linear regulator that supplies the proper bias to the entire board. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER EVALUATION BOARD BAND-PASS FILTER XFMR INPUT CLK CHB PARALLEL CMOS OUTPUTS SPI HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD PC RUNNING ADC ANALYZER USB CONNECTION SPI SPI Figure 4. Example Setup Using Quad ADC Evaluation Board and FIFO Data Capture Board Rev. 0 | Page 13 of 28 05870-004 ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER CHB PARALLEL CMOS OUTPUTS + VCC SWITCHING POWER SUPPLY – GND 3.3V 6V DC 2A MAX HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC FIFO SCHEMATICS AND PCB LAYOUT SCHEMATICS ALLOW Fx2 TO CONTROL FIFO’S OUTPUT WIDTH RCLK REN1 61 EF1_TF FF1_TF REN RCLK 63 RM 64 EF/OR 66 65 PFM VCC PAE 67 68 IP 70 69 BE HF FSEL1 71 72 FSEL0 73 OW 74 PAF 75 FF/IR 76 FWFT/SI LD 77 78 MRS 79 PRS GND D11 Q10 VCC D10 D9 Q9 D8 Q8 Q7 OE1 57 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 43 Q9 42 Q8 41 Q7 Q6 GND 59 58 40 39 60 Q6 Q5 38 Q5 Q4 37 Q4 VCC Q3 35 36 34 Q2 GND Q3 C107 0.1µF Q2 Q1 32 C106 0.1µF 33 Q1 22 D1_6 U101 Q0 VCC D7 20 D12 GND 19 Q11 31 D1_8 GND 30 18 GND Q0 D1_9 D13 D0 17 Q13 Q12 D1 D1_10 VCC D14 29 16 D15 28 D1_11 D16 D1_0 15 Q14 IDT72V283 TQFP80 TOP FIFO CHANNEL B D1_1 D1_12 VCC D2 14 Q15 27 13 D17 D1_2 D1_13 GND D3 12 GND D4 D1_14 GND 26 11 IW D1_3 D1_15 9 Q16 D5 10 DNC 25 D1_16 R108 DNP Q17 D1_4 8 VCC VCC GND D1_17 DNC 24 7 VCC OE 23 6 RT SEN D1_5 5 WEN D6 2 4 VCC C101 0.1µF C102 0.1µF C103 0.1µF C104 0.1µF C105 0.1µF Figure 5. PCB Schematic Rev. 0 | Page 14 of 28 C108 0.1µF C109 0.1µF 05870-005 R109 DNP MRS WRT_CLK1 80 1 WCLK WEN1 21 E102 3 WRT_CLK1 R102 10kΩ VCC D1_7 POPULATE WITH PIN SOCKET E101 R101 0Ω 62 PC2: TRISTATED, NORMAL 16-BIT DATA PATH PC2: DRIVEN HIGH, 9-BIT OUTPUT ALLOWS READING 18 BITS IN TWO READS. PC2 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC CMOS INPUTS J104 CLKB J104 A1 A2 DUT_CLK1 A3 MSB CHB LSB CLKA A4 D1_15 A5 D1_14 A6 D1_13 A7 D1_12 A8 D1_11 A9 D1_10 A10 D1_9 A11 D1_8 A12 D1_7 A13 D1_6 A14 D1_5 A15 D1_4 A16 D1_3 A17 D1_2 A18 D1_1 A19 D1_0 A20 CTRL_B D1_15 D1_14 D1_13 D1_12 D1_11 D1_10 D1_9 D1_8 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 CHA LSB B1 D1_17 B2 D1_16 C4 C5 B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16 B17 C17 B18 C18 C19 B19 D2_17 A22 B22 D2_16 D2_15 A25 D2_14 A26 D2_13 A27 D2_12 A28 D2_11 A29 D2_10 A30 D2_9 A31 D2_8 A32 D2_7 A33 D2_6 A34 D2_5 A35 D2_4 A36 D2_3 A37 D2_2 A38 D2_1 A39 D2_0 A40 CTRL_D D2_15 D2_14 D2_13 D2_12 D2_11 D2_10 D2_9 D2_8 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 CTRL_D C2 B5 B21 A24 D1_16 C1 C3 A21 DUT_CLK2 D1_17 B4 CTRL_A CTRL_B PLACEMENT OF HEADER KEY HERE J104 B3 B20 A23 MSB TEST POINTS CTRL_A D2_17 D2_16 C20 C21 C22 B23 C23 B24 C24 B25 C25 B26 C26 B27 C27 B28 C28 B29 C29 16 1 18 B30 C30 15 2 17 B31 C31 14 3 16 B32 C32 13 4 15 B33 C33 12 5 14 B34 C34 11 6 13 B35 C35 10 7 12 B36 C36 8 11 B37 C37 B38 C38 VCC 19 SDO 9 22 RZ101 20 OE2 VCC A1 Y1 Y2 Y3 OE A0 Y0 1 2 3 4 U102 A2 74VHC541MTC 5 CSB1 CSB2 A3 Y4 A4 Y5 A5 Y6 A6 Y7 A7 GND 10 6 7 8 SDI SCLK CSB3 CSB4 9 R103 10kΩ R104 10kΩ C39 B39 B40 ALL SPI LABELS ARE WITH RESPECT TO THE DUT. CTRL_C CTRL_C C40 PLACEMENT OF HEADER KEY HERE Figure 6. Schematic (Continued) Rev. 0 | Page 15 of 28 05870-006 TEST POINTS HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC RCLK REN2 61 EF2 FF2 MRS E201 R202 10kΩ 62 WRT_CLK2 R201 0Ω REN RCLK 63 RM 64 EF/OR 65 PFM 66 PAE 67 VCC 68 IP 70 69 BE HF FSEL1 71 72 FSEL0 74 73 OW FF/IR PAF 75 76 FWFT/SI LD 77 78 MRS 79 D11 Q10 VCC D10 D9 Q9 59 OE2 58 57 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 43 Q9 42 Q8 41 Q7 Q6 GND 60 40 39 Q5 38 Q5 Q1 Q4 37 Q4 35 36 34 Q3 22 D2_6 Q2 21 U201 VCC Q7 Q3 VCC Q2 Q8 GND D8 D7 20 GND 32 19 D12 33 D2_8 Q11 Q1 18 GND Q0 D2_9 GND GND 17 D13 31 D2_10 Q13 Q12 30 16 VCC D14 Q0 15 D2_11 D15 D0 D2_12 D16 D1 14 Q14 IDT72V283 TQFP80 BOTTOM FIFO CHANNEL A 29 13 VCC D2_0 D2_13 Q15 D2 12 D17 28 D2_14 GND 27 11 GND D2_1 D2_15 GND D2_2 10 IW D3 D2_16 Q16 D4 9 DNC 26 8 Q17 D2_3 D2_17 VCC D5 7 VCC 25 6 DNC D2_4 5 OE GND 4 RT SEN 24 2 3 WEN 23 1 PRS WEN2 D6 E202 WCLK 80 VCC D2_7 R203 DNP WRT_CLK2 Q6 VCC D2_5 R204 DNP VCC C201 0.1µF C202 0.1µF C203 0.1µF C204 0.1µF C205 0.1µF C206 0.1µF C207 0.1µF Figure 7. Schematic (Continued) Rev. 0 | Page 16 of 28 C208 0.1µF 05870-007 POPULATE WITH PIN SOCKET PC3 J311 J310 C310 0.1µF 05870-008 2 3 1 J301 PJ-102A + R316 331Ω R315 DNP C301 10µF 2.2A F301 J313 J312 4 1 T103 C311 0.1µF R304 331Ω R303 331Ω VCC CR301 S2A VCC R302 331Ω R301 331Ω R314 331Ω POWER SUPPLY INPUT 6V, 2A MAX R313 331Ω R312 DNP R311 331Ω VCC PLACE JUMPERS BETWEEN PADS ON TOP SIDE FOR COHERENT SAMPLING REMOVE R301-R304 AND SHORT C302 AND C303 3 2 4 3 VI 1 ADJ VO 4 EN EN VO U301 RIN4– RIN4+ RIN3– RIN3+ RIN2– RIN2+ RIN1– VCC 13 DNP 2 GND J302 C313 1µF 12 VCC + 3 J305 1 J316 C308 0.1µF + DNP C309 10µF 74VCX86 U302 74VCX86 U302 8 3 12 13 74VCX86 U302 VCC 74VCX86 C306 0.1µF 5 U302 9 20 15 17 19 REN1 MRS VCC 18 13 OE1 CR303 16 14 11 EF1_F 12 8 10 7 6 FF1_F 5 2 4 3 WRT_CLK1 DNP J308 1 R317 499Ω 11 6 E305 J315 E306 J314 1 SET 0, 1, OR 2 XOR GATE DELAYS CONTROLS BOTTOM FIFO 3 WRT_CLK2 SET 0, 1, OR 2 XOR GATE DELAYS 1 CONTROLS 3 TOP FIFO WRT_CLK1 WENS REN2 OE2 EF2 FF2 BOTTOM FIFO WRT_CLK2 RCLK AUX CLOCK SIGNAL MONITOR CONNECTOR 9 10 R310 1kΩ R309 1kΩ 2 1 4 VCC DNP J307 J306 TOP FIFO INVERT CLOCK 2 INVERT CLOCK 1 1 J304 3 INVERT CLOCK 2 10 11 14 C307 10µF ROUT4 ROUT3 ROUT2 15 INVERT CLOCK 1 C305 0.1µF ROUT1 DS90LV048A 6 9 RIN1+ VR301 ADP3339AKC-3.3 8 7 5 6 4 3 1 2 OPTIONAL POWER INPUT HEADER C312 1µF SK33MSCT CR302 REMOVE JUMPER FOR DUAL CHANNEL CONFIGURATION 3 TOP FIFO DUT_CLK1 BOTTOM FIFO DUT_CLK2 J303 1 2 C303 0.1µF C302 0.1µF 1 VCC 1 Rev. 0 | Page 17 of 28 2 Figure 8. Schematic (Continued) 2 POPULATE WITH PIN SOCKET E302 E301 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Figure 9. Schematic (Continued) Rev. 0 | Page 18 of 28 05870-009 WRT_CLK2 WRT_CLK1 WENS C401 DNP J406 DNP J405 R401 20KΩ 2 1 R404 49.9Ω R407 49.9Ω R405 49.9Ω R409 40.2Ω R408 49.9Ω U401 MC100EPT22 7 U401 MC100EPT22 3 6 4 R403 DNP R402 DNP VCC CLK0 5 D1 9 C402 0.1µF VCC U402 D1 CLK 8 7 CLK CLK0 4 6 D0 D0 VBB VCC C403 0.1µF 11 GND CLK D CLK D Q Q C404 0.1µF Q S R Q S R MC100EP29 3 VCC 10 2 1 R406 40.2Ω S1 C405 0.1µF 12 14 13 Q1 R1 15 Q1 16 17 Q0 Q0 18 19 S0 R0 R410 49.9Ω 3 4 2 1 6 R415 40.2Ω DNP U403 MC100EPT23 7 U403 R414 MC100EPT23 49.9Ω R412 40.2Ω R413 49.9Ω R411 49.9Ω J402 J401 J404 DNP J403 WEN2 WEN1 CONTROLS BOTTOM FIFO CONTROLS TOP FIFO HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC C506 0.1µF 05870-010 VCC FF2 1 14 7 U505 VCC R521 332Ω 2 C510 0.1µF VCC R522 332Ω 4 C509 0.1µF U505 FROM TOP FIFO VCC FF1_TF 3 C508 0.1µF FROM BOT TOM FIFO C507 0.1µF 1 2 D FF1_BHB 4 Q Q 3 5 6 5 U505 MRS C512 0.1µF E505 E504 E503 CLR GND CLK PRE VCC 8 VCC C511 0.1µF U504 7 R518 10kΩ EF1_BHB R519 10kΩ J505 J503 C505 12pF C504 12pF FF1_TF 2 1 C502 2.2µF Y501 24MHz 2 L501 1 EF1_TF VCC C513 0.1µF 6 R524 0Ω R523 2kΩ VCC C514 0.1µF C516 0.1µF C517 0.1µF USB_VBUS E502 R503 499Ω FF2 EF2 RCLK INTERLEAVE_FIRSTWORD C515 0.1µF CR501 J501 USB CONNECTION 4 3 2 1 DN P J506 DN P J504 3 GND GROUND TEST POINTS FROM BOT TOM FIFO 25 24 23 22 21 128 127 126 120 119 118 117 97 96 95 94 19 18 12 11 9 8 7 6 5 4 32 1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DMINUS DPLUS XTALIN XTALOUT RDY5 RDY4 RDY3 RDY2 RDY1/*SLWR RDY0/*SLRD IFCLK VCC CR502 R502 100kΩ CLKOUT C503 0.1µF VCC 2 1 S501 U503 1 A0 2 A1 3 A2 4 VSS SDA SC L WP VCC 5 6 7 8 VCC CS 4 FF_USB WR 42 5 AGND 13 GND 3 99 41 +V 10 AVCC 2 DVCC FF_USB 101 RD 2 4 3 + S501 = RESET USB CONTROLLER C501 1µF R517 2kΩ R516 2kΩ VCC INT5 SDI CSB1 CSB2 CSB3 CSB4 CSB5 SDO 109 110 111 112 113 114 115 12 11 10 9 8 7 6 5 4 3 2 1 J502 DN P CONTROL FIFO OUTPUT WIDTH OE2 AUX SPI PORT CONNECTION 16 15 14 16 15 14 SCLK 108 79 78 77 76 PC3 Q17 PC2 74 75 Q16 73 R526 24.9Ω INTERLEAVE_FIRSTWORD OE1 CTRL_D R525 24.9Ω CTRL_C R507 24.9Ω R520 24.9Ω CTRL_B R506 24.9Ω CTRL_ A R505 24.9Ω R504 24.9Ω 72 92 91 90 89 85 84 83 82 28 106 13 NC3 NC2 NC1 PE7/GPI FADR8 PE6/T2EX PE5/INT6 PE2/T2OUT PE1/T1OUT PE0/T0OUT PC0/GPIFADR0 PC1/GPIFADR1 PC2/GPIFADR2 PC3/GPIFADR3 PC4/GPIFADR4 PC5/GPIFADR5 PC6/GPIFADR6 PC7/GPIFADR7 PA7/*FLAG/SLCS PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1 PA0/INT0 INT4 ALL SPI LABELSARE PE3/RXD0OUT WITH RESPECT PE4/RXD1OUT TO THE DUT VCC;17,26,43,48,64,68,81,100,107 GND;20;27;49;58;65;80;93; 116;125 U502 CY7C68013_128AXC 34 1 BKPT 50 40 RESET PSEN Q15 124 RESE RVED 33 R509 10kΩ 51 39 *WAKEU P OE TXD0 38 RXD0 SDA Q14 123 69 R510 24.9Ω 52 36 53 SCL 35 EA R508 10kΩ 37 TXD1 Q13 122 RXD1 Q12 121 PD7/FD15 Q11 105 PD6/FD14 Q9 Q10 FF2 31 T2 30 T1 FROM TOP FIFO 29 VCC T0 59 D0 PD4/FD12 MRS 60 PD5/FD13 CTL0*FLAG A R5 11 24.9Ω 70 R512 24.9Ω WENS CTL1/*FLAGB 71 CTL2/*FLAGC REN1 D1 104 66 RENEXT R513 24.9Ω 61 PD3/FD 11 Q8 D2 103 R514 24.9Ω D3 PD2/FD10 Q7 102 REN2 CTL3 67 CTL4 R515 24.9Ω 98 CTL5 REN2M D4 62 PD1/FD9 Q6 57 D5 63 PD0/FD8 Q5 56 D6 86 PB7/FD7 Q4 55 PB6/FD6 Q3 54 PB5/FD5 Q2 47 PB4/FD4 Q1 46 PB3/FD3 Q0 PB2/FD2 45 PB1/FD1 44 PB0/FD0 D7 Rev. 0 | Page 19 of 28 87 Figure 10. Schematic (Continued) 88 U501 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC VCC CONNECTIONS FOR 2M WORD EXTERNAL MEMORY EXTERNAL MEMORY OVERRIDES ON BOARD MEMORIES WHEN PLUGGED IN. ONLY A SIDE DATA. C601 0.1µF DNP D1_9 D1_10 D1_11 D1_12 D1_13 D1_14 D1_15 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 J601 DC8 DC9 DC10 DC11 DC12 DC13 DC14 DC15 RZ601 1 DC0 DC3 DC2 D1_0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DC0 D1_17 R603 0Ω R604 0Ω 4 36 QL0 2 37 QL1 3 38 QL2 4 5 DC6 5 39 DC8 6 40 QL4 6 DC7 7 41 QL5 7 DC11 8 42 QL6 8 43 QL7 9 DC13 DC1 9 10 44 DC14 11 45 DC15 DC2 DC4 12 46 DC3 DC5 13 47 DC16 14 48 DC1 DC4 DC5 DC9 15 49 DC6 DC17 16 50 17 51 18 52 DC7 RZ602 D1_16 3 RENEXT 1 QL3 DC10 1 2 U601 35 DC12 19 53 DC16 20 54 DC17 21 55 22 56 23 57 REN1 24 58 RCLK EF1_BHB 25 59 FF1_BHB 26 60 MRS 27 61 WEN1 WRT_CLK1 28 62 QL0 29 63 QL1 30 64 QL2 QL3 31 65 QL4 32 66 QL5 33 67 QL6 34 68 QL7 Figure 11. Schematic (Continued) Rev. 0 | Page 20 of 28 10 OUT_EN VCC Q0 D0 Q1 D1 Q2 D2 D3 Q3 D4 Q4 D5 Q5 Q6 D6 Q7 D7 GND CLOCK 20 VCC 19 1 16 Q0 18 2 15 Q1 17 3 14 Q2 16 4 13 Q3 15 5 12 Q4 14 6 11 Q5 13 7 10 Q6 12 8 9 11 Q7 RZ605 74LCX574 J602 REN2M J603 RCLK DNP J603: ALLOWS 2 MEG BUFFER TO READ BACK DATA ON EACH RCLK EDGE. J602: ALLOWS 2 MEG BUFFER TO READ BACK 1 DATA ON EVERY 3RD RCLK EDGE. J602 IS FOR BACKWARD COMPATABILITY IF NEEDED. 05870-011 D1_8 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC 05870-012 PCB LAYOUT 05870-013 Figure 12. Layer 1—Primary Side Figure 13. Layer 2—Ground Plane Rev. 0 | Page 21 of 28 05870-014 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC 05870-015 Figure 14. Layer 3—Power Plane Figure 15. Layer 4—Secondary Side Rev. 0 | Page 22 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC BILL OF MATERIALS Table 6. HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Bill of Materials Item 1 Qty 42 Device Capacitor Package 402 Description Ceramic, 0.1 μF, 16 V, X5R, 10% Manufacturer Panasonic Mfg Part Number ECJ-0EB1C014K 3 Reference Designation C101 to C109, C201 to C208, C302, C303, C305, C306, C308, C310, C311, C402 to C405, C503, C506 to C517, C601 C301, C307, C309 2 Capacitor 6032-28 Kemet T491C106K016AS 3 2 C312, C313 Capacitor 603 Panasonic ECJ-1VB1A105K 4 1 C501 Capacitor 3216-18 Panasonic ECS-T1CY105R 5 1 C502 Capacitor 805 Panasonic ECJ-2FB1E225K 6 2 C504, C505 Capacitor 402 Panasonic ECJ-0EC1H120J 7 1 CR301 Diode DO-214AA 1 CR302 Diode DO-214AB 9 2 CR303, CR501 LED 603 Micro Commercial Group Micro Commercial Group Panasonic S2A 8 10 1 CR502 Diode SOD-123 Diodes, Inc. 1N4148W-7 11 1 F301 Fuse 1210 Tyco, Raychem NANOSMDC110F-2 12 1 J104 Connector AMP 650874 13 1 J301 Connector 0.08”, PCMT Switchcraft SC1153 14 1 J303 Connector 4-pin SAMTEC TSW-1-10-08-GD 15 16 4 8 Connector Connector 3-pin 603 SAMTEC Panasonic TWS-103-08-G-S ERJ-3GEY0R00V 17 18 1 1 J304, J305, J314, J315 J310 to J313, J401, J404, J406, J603 J316 J501 Connector Connector 2-pin 4-pin SAMTEC AMP TSW-1002-08-G-S 787780-1 19 1 L501 805 Steward HZ0805E601R-00 20 21 5 8 402 402 Panasonic Panasonic ERJ-2GE0R00X ERJ-2RKF1002X 22 10 Resistor 402 332 Ω, 1/16 W, 1% Panasonic ERJ-2RKF3320X 23 24 25 26 2 2 1 8 Resistor Resistor Resistor Resistor 402 402 402 402 1 kΩ, 1/16 W, 1% 499 Ω, 1/16 W, 1% 20 kΩ, 1/16 W, 1% 49.9 Ω, 1/16 W, 1% Panasonic Panasonic Panasonic Panasonic ERJ-2RKF1002X ERJ-2RKF1001X ERJ-2RKF4990X ERJ-2RKF2002X 27 28 29 4 1 13 Resistor Resistor Resistor 402 402 402 40.2 Ω, 1/16 W, 1% 100 kΩ, 1/16 W, 1% 24.9 Ω, 1/16 W, 1% Panasonic Panasonic Panasonic ERJ-2RKF40R2X ERJ-2RKF1003X ERJ-2RKF24R9X 30 31 3 1 R101, R201, R524, R603, R604 R102 to R04, R202, R508, R509, R518, R4519 R301 to R304, R311, R313, R314, R316, R521, R522 R309, R310 R317, R503 R401 R404, R405, R407, R408, R410, R411, R413, R414 R406, R409, R412, R415 R502 R504, R506, R507, R510 to R515, R520, R525, R526 R516, R517, R523 RZ101 Ferrite Bead Resistor Resistor Tantalum, 10 μF, 16 V, 10% Ceramic, 1 μF, 10 V, X5R, 10% Tantalum, 1 μF, 16 V, 20% Ceramic, 2.2 μF, 25 V, X5R 10% Ceramic, 12 pF, NPO, 50 V, 5% Schottky diode, 50 V, 2 A, SMC Schottky diode, 30 V, 3 A, SMC Green, 4 V 5 m, candela Switching, 75 V, 150 mA 6.0 V, 2.2 A trip current resettable fuse 120-pin, female, PC mount, right angle RAPC722, power supply connector Male, straight, 100 mil Male, straight, 100 mil 2-pin solder jumper, 0 Ω, 1/10 W, 5% Male, straight, 100 mil USB, PC mount, right angle, Type B, female 500 mA, 600 Ω @ 100 MHz 0 Ω, 1/16 W, 5% 10 kΩ, 1/16 W, 1% Resistor Resistor 402 Panasonic Panasonic ERJ-2RKF2001X EXB-2HV220JX 32 1 S501 Switch 2 kΩ, 1/16 W, 1% Resistor array, 22 Ω, 1/4 W, 5% Momentary (normally open), 100 GE, 5 mm, SPST Panasonic EVQ-PLDA15 Rev. 0 | Page 23 of 28 SK33MSCT LNJ314G8TRA HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Item 33 Qty 1 Reference Designation T301 Device Choke Package 2020 34 1 2 U101, U201 IC TQFP80 35 1 U102 IC SOIC20 36 1 U301 IC SOIC16 37 38 39 40 41 1 1 1 1 1 U302 U401 U402 U403 U501 IC IC IC IC IC SOIC14 SO8M1 TSSOP20 SO8M1 SOT23L5 42 1 U502 IC TQFP128 43 44 1 1 U503 U504 IC IC DIP8 DCT_8PIN_06, 5 mm 45 1 U505 IC SOIC 14 46 1 U601 IC DIP20/SOL 47 1 VR301 IC SOT-223HS 48 49 1 6 Y501 See schematic for placement Crystal Connector 50 4 Standoff 51 2 Insert from bottom side of board See schematic for placement Crystal 100 mil jumper Plastic mount standoffs Third-row header key 1 Connector Description 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz 3.3 V, IDT72V283L7-5PF 74VHC541, octal buffer/line driver, three-state DS90LV048A 74VCX86 MC100EPT22D MC100EP29DT MC100EPT23D NC7SZ32M5, NC7SZ32, tiny log UHS 2-input or gate CY7C68013 Manufacturer Murata Mfg Part Number DLW5BSN191SQ2L IDT IDT72V283L7-5PF Fairchild 74VHC541M National Semiconductor Fairchild Motorola ON Semiconductor Motorola Fairchild DS90LV048A 24LC00P SN74LVC2G74DCTR, D-type flip-flop, DCT_8PIN_0.65MM 74LVQ04SC, low voltage hex inverter 74LCX574WM-ND, 74LCX574 octal D-type flip-flop High accuracy, ADP3339AKC-3.3, 3.3 V Oscillator, 24 MHz 0.1” jumpers Microchip Texas Instruments CY7C68013-128AXC or CY7C68014A-128AXC 24LC00P SN74LVC2G74DCTR Fairchild 74LVQ04SC Fairchild 74LCX574WM-ND Analog Devices ADP3339AKC-3.3 Ecliptek Samtec EC-12-24.000M SNT-100-BK-G-H 7/8” height, standoffs Richco CBSB-14-01A-RT These header inserts for J104, Pin 81, and Pin 120 are located on the edges of the top row Samtec TSW-104-07-T-S Only U201 is populated for the single-channel version (HSC-ADC-EVALB-SC). Rev. 0 | Page 24 of 28 Cypress 74VCX86 MC100EPT22D MC100EP29DT MC100EPT23D NC7SZ32M5 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC ORDERING INFORMATION ORDERING GUIDE Model HSC-ADC-EVALB-SC HSC-ADC-EVALB-DC HSC-ADC-FPGA-4/-8 HSC-ADC-FPGA-9289 AD922XFFA 1 AD9283FFA1 AD9059FFA1 AD9051FFA1 LG-0204A1 1 Description Single FIFO Version of USB Evaluation Kit Dual FIFO Version of USB Evaluation Kit Quad/Octal Serial LVDS to Dual Parallel CMOS Interface; supports all Quad/Octal ADCs in this family except the AD9289 (not Included in Evaluation Kit) Quad Serial LVDS to Dual Parallel CMOS Interface for the AD9289 Only (Not Included in Evaluation Kit) Adapter for AD922x Family (Not Included in Evaluation Kit) Adapter for the AD9283 and AD9057 (Not Included in Evaluation Kit) Adapter for the AD9059 (Not Included in Evaluation Kit) Adapter for the AD9051 (Not Included in Evaluation Kit) Adapter for the AD10xxx and AD13xxx Families (Not Included in Evaluation Kit) If an adapter is needed, send an email to [email protected]. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 25 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC NOTES Rev. 0 | Page 26 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC NOTES Rev. 0 | Page 27 of 28 HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB05870-0-2/06(0) Rev. 0 | Page 28 of 28