Intel DE28F800B3B150 Fast boot block flash memory family 8 and 16 mbit Datasheet

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PRODUCT PREVIEW
FAST BOOT BLOCK
FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3
Includes Extended and Automotive Temperature Specifications
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High Performance
 54 MHz Effective Zero Wait-State
Performance
 Synchronous Burst-Mode Reads
 Asynchronous Page-Mode Reads
SmartVoltage Technology
 2.7 V−3.6 V Read and Write
Operations for Low Power Designs
 12 V VPP Fast Factory Programming
Flexible I/O Voltage
 1.65 V I/O Reduces Overall System
Power Consumption
 5 V-Safe I/O Enables Interfacing to
5 V Devices
Enhanced Data Protection
 Absolute Write Protection with
VPP = GND
 Block Locking
 Block Erase/Program Lockout
during Power Transitions
Density Upgrade Path
 8- and 16-Mbit
Manufactured on ETOX™ V Flash
Technology
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Supports Code Plus Data Storage
 Optimized for Flash Data Integrator
(FDI) Software
 Fast Program Suspend Capability
 Fast Erase Suspend Capability
Flexible Blocking Architecture
 Eight 4-Kword Blocks for Data
 32-Kword Main Blocks for Code
 Top or Bottom Configurations
Available
Extended Cycling Capability
 Minimum 10,000 Block Erase Cycles
Guaranteed
Low Power Consumption
 Automatic Power Savings Mode
Decreases Power Consumption
Automated Program and Block Erase
Algorithms
 Command User Interface for
Automation
 Status Register for System
Feedback
Industry-Standard Packaging
 56-Lead SSOP
 µBGA* CSP
Intel’s Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous
burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the
intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory
paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for
improved system performance. Therefore, it reduces the total memory requirement which helps increase
reliability and reduce overall system power consumption and cost.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They are available
in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged
56-lead SSOP.
May 1998
Order Number: 290644-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION, 1998
*Third-party brands and names are the property of their respective owners
CG-041493
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FAST BOOT BLOCK DATASHEET
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.2 Product Overview.........................................5
5.0 DATA PROTECTION.....................................26
5.1 VPP = VIL for Complete Protection ..............26
5.2 WP# = VIL for Block Locking ......................26
5.3 WP# = VIH for Block Unlocking...................26
2.0 PRODUCT DESCRIPTION..............................6
2.1 Pinouts.........................................................6
2.2 Pin Description .............................................6
2.3 Memory Blocking Organization.....................9
2.3.1 Parameter Blocks ..................................9
2.3.2 Main Blocks ...........................................9
3.0 PRINCIPLES OF OPERATION .....................12
3.1 Bus Operations ..........................................12
3.1.1 Read....................................................12
3.1.2 Output Disable.....................................12
3.1.3 Standby ...............................................12
3.1.4 Write....................................................12
3.1.5 Reset...................................................13
4.0 COMMAND DEFINITIONS ............................13
4.1 Read Array Command................................15
4.2 Read Identifier Codes Command ...............15
4.3 Read Status Register Command................15
4.4 Clear Status Register Command................15
4.5 Block Erase Command ..............................15
4.6 Program Command....................................17
4.7 Block Erase Suspend/Resume Command .17
4.8 Program Suspend/Resume Command.......17
4.9 Set Read Configuration Command.............19
4.9.1 Read Configuration..............................19
4.9.2 Frequency Configuration .....................20
4.9.3 Data Output Configuration ...................20
4.9.4 WAIT# Configuration ...........................20
4.9.5 Burst Sequence...................................20
4.9.6 Clock Configuration .............................20
4.9.7 Burst Length ........................................20
PRODUCT PREVIEW
6.0 VPP VOLTAGES ............................................26
7.0 POWER CONSUMPTION..............................26
7.1 Active Power ..............................................26
7.2 Automatic Power Savings ..........................26
7.3 Standby Power...........................................27
7.4 Power-Up/Down Operation.........................27
7.4.1 RST# Connection ................................27
7.4.2 VCC, VPP and RST# Transitions ...........27
7.5 Power Supply Decoupling ..........................27
7.5.1 VPP Trace on Printed Circuit Boards ....27
8.0 ELECTRICAL SPECIFICATIONS .................28
8.1 Absolute Maximum Ratings........................28
8.2 Extended Temperature Operating
Conditions .................................................28
8.3 Capacitance ...............................................29
8.4 DC Characteristics—Extended
Temperature..............................................30
8.5 AC Characteristics—Read-Only
Operations—Extended Temperature .........32
8.6 AC Characteristics—Write Operations—
Extended Temperature..............................38
8.7 AC Characteristics—Reset Operation—
Extended Temperature..............................40
8.8 Extended Temperature Block Erase and
Program Performance ...............................41
8.9 Automotive Temperature Operating
Conditions .................................................41
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FAST BOOT BLOCK DATASHEET
8.10 Capacitance .............................................42
8.11 DC Characteristics—Automotive
Temperature..............................................43
8.12 AC Characteristics—Read-Only
Operations—Automotive Temperature ......44
8.13 Automotive Temperature Frequency
Configuration Settings ...............................45
8.14 Automotive Temperature Block Erase and
Program Performance ...............................45
9.0 ORDERING INFORMATION..........................46
10.0 ADDITIONAL INFORMATION .....................47
REVISION HISTORY
4
Date of
Revision
Version
05/12/98
-001
Description
Original version
PRODUCT PREVIEW
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1.0
INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot
Block memory information. Section 1.0 provides a
flash memory overview. Sections 2.0 through 8.0
describe the memory functionality and electrical
specifications for extended and automotive
temperature product offerings.
1.2
Product Overview
The Fast Boot Block flash memory family provides
density upgrades with pinout compatibility for 8- and
16-Mbit densities. This family of products are high
performance, low voltage memories with a 16-bit
data bus and individually erasable blocks. These
blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are
positioned at either the top (denoted by -T suffix) or
bottom (denoted by -B suffix) of the address map.
The rest of the device is grouped into
32-Kword main blocks. The upper two (or lower
two) parameter and all main blocks can be locked
for complete code protection.
The device’s optimized architecture and interface
dramatically increases read performance beyond
previously
attainable
levels.
It
supports
asynchronous page-mode and synchronous burst
reads from main blocks (parameter blocks support
single asynchronous and synchronous reads).
Upon initial power-up or return from reset, the
device defaults to a page-mode read configuration.
Page-mode read configuration is ideal for non-clock
memory systems and is compatible with pagemode ROM. Synchronous burst reads are enabled
by writing to the read configuration register. In
synchronous burst mode, the CLK input increments
an internal burst address generator, synchronizes
the flash memory with the host CPU, and outputs
data on every rising (or falling) CLK edge up to
54 MHz (25 MHz for automotive temperature). An
output signal, WAIT#, is also provided to ease CPU
to
flash
memory
communication
and
synchronization during continuous burst operations.
In addition to the enhanced architecture and
interface, this family of products incorporates
SmartVoltage technology which enables fast factory
programming and low power designs. Specifically
designed for low voltage systems, Fast Boot Block
flash memory components support read operations
at 2.7 V (3.3 V for automotive temperature) VCC and
PRODUCT PREVIEW
FAST BOOT BLOCK DATASHEET
block erase and program operations at 2.7 V
(3.3 V for automotive temperature) and 12 V VPP.
The 12 V VPP option renders the fastest program
performance to increase factory programming
throughput. With the 2.7 V (3.3 V for automotive
temperature) VPP option, VCC and VPP can be tied
together for a simple, low power design. In addition
to the voltage flexibility, the dedicated VPP pin gives
complete data protection when VPP ≤ VPPLK.
The flexible input/output (I/O) voltage capability
helps reduce system power consumption and
simplify interfacing to sub 2.7 V and 5 V CPUs.
Powered by VCCQ pins, the I/O buffers can operate
at a lower voltage than the flash memory core. With
VCCQ voltage at 1.65 V, the I/Os swing between
GND and 1.65 V, reducing I/O power consumption
by 65% over standard 3 V flash memory
components. The low voltage and 5 V-safe feature
also helps ease CPU interfacing by adapting to the
CPU’s bus voltage.
The device’s Command User Interface (CUI) serves
as the interface between the system processor and
internal flash memory operation. A valid command
sequence written to the CUI initiates device
automation. This automation is controlled by an
internal Write State Machine (WSM) which
automatically executes the algorithms and timings
necessary for block erase and program operations.
The status register provides WSM feedback by
signifying block erase or program completion and
status.
Block erase and program automation allows erase
and program operations to be executed using an
industry-standard two-write command sequence. A
block erase operation erases one block at a time,
and data is programmed in word increments. Erase
suspend allows system software to suspend an
ongoing block erase operation in order to read from
or program data to any other block. Program
suspend allows system software to suspend an
ongoing program operation in order to read from
any other location.
Fast Boot Block flash memory devices offer two low
power savings features: Automatic Power Savings
(APS) and standby mode. The device automatically
enters APS mode following the completion of a read
cycle. Standby mode is initiated when the system
deselects the device by driving CE# inactive or
RST# active. RST# also resets the device to read
array, provides write protection, and clears the
status register. Combined, these two features
significantly reduce power consumption.
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FAST BOOT BLOCK DATASHEET
2.0
PRODUCT DESCRIPTION
This section describes the pinout and block
architecture of the device family.
to the 16-Mbit density. The family is available in
µBGA CSP and 56-lead SSOP packages. Pinouts
for the 8- and 16-Mbit components are illustrated in
Figures 1 and 2.
2.1
2.2
Pinouts
The pin description table describes pin usage.
Intel’s Fast Boot Block flash memory family
provides upgrade paths in each package pinout up
1
2
A15
A12
3
Pin Description
4
5
6
GND
CLK
VCC
7
8
9
10
A4
A1
A
B
32M
A14
A11
A8
C
A20
VPP
16M
ADV#
WE#
A19
A17
A5
A2
64M
A13
A10
A9
A21
RST#
WP#
A18
A7
A6
A3
VCCQ
DQ7
DQ13
DQ12
DQ4
DQ11
DQ10
DQ9
DQ0
CE#
A16
DQ15
DQ6
DQ5
VCC
DQ3
DQ2
DQ1
OE#
A0
WAIT# GND
DQ14
GND
VCCQ
DQ8
GND
D
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F
NOTES:
1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder
balls. Routing is not recommended in this area.
2. A20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).
3. Reference the Micro Ball Grid Array Package Mechanical Specification and Media Information on Intel’s World Wide Web
home page for detailed package specifications.
Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)
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PRODUCT PREVIEW
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16-Mbit
8-Mbit
VCC
CLK
ADV#
GND
NC
A15
A14
A13
A12
A11
A10
A9
A8
NC
GND
DQ6
DQ14
DQ7
DQ15
GND
VCCQ
A16
WAIT#
DQ13
DQ5
DQ12
DQ4
VCC
VCC
CLK
ADV#
GND
NC
A15
A14
A13
A12
A11
A10
A9
A8
NC
GND
DQ6
DQ14
DQ7
DQ15
GND
VCCQ
A16
WAIT#
DQ13
DQ5
DQ12
DQ4
VCC
FAST BOOT BLOCK DATASHEET
8-Mbit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Lead SSOP
16 mm x 23.7 mm
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WE#
RST#
VPP
WP#
NC
A1
A2
A3
A4
A5
A6
A7
A17
A18
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
NC
VCCQ
DQ2
DQ10
DQ3
DQ11
16-Mbit
WE#
RST#
VPP
WP#
A19
A1
A2
A3
A4
A5
A6
A7
A17
A18
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
NC
VCCQ
DQ2
DQ10
DQ3
DQ11
Figure 2. SSOP Pinout
PRODUCT PREVIEW
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FAST BOOT BLOCK DATASHEET
Table 1. Pin Descriptions
Sym
A0–A19
Type
INPUT
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during read and write cycles.
8-Mbit: A0–18, 16-Mbit: A0–19
DQ0–
DQ15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs
data during memory array, status register (DQ0–DQ7), and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CLK
INPUT
CLOCK: Synchronizes the flash memory to the system operating frequency during
synchronous burst-mode read operations. When configured for synchronous burstmode reads, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. CLK is ignored during asynchronous pagemode read and write operations.
ADV#
INPUT
ADDRESS VALID: Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during read and write
operations. ADV# may be tied active during asynchronous read and write
operations.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption
to standby levels.
RST#
INPUT
RESET: When driven low, RST# inhibits write operations which provides data
protection during power transitions, and it resets internal automation. RST#-high
enables normal operation. Exit from reset sets the device to asynchronous read
array mode.
OE#
INPUT
OUTPUT ENABLE: Gates data outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are
latched on the rising edge of the WE# pulse.
WP#
INPUT
WRITE PROTECTION: Provides a method for locking and unlocking all main
blocks and two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase
operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5
[block erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be
programmed or erased.
WAIT#
8
OUTPUT
WAIT: Provides data valid feedback when configured for synchronous burst-mode
and the burst length is set to continuous. This signal is gated by OE# and CE# and
is internally pull-up to VCCQ via a resistor. WAIT# from several components can be
tied together to form one system WAIT# signal.
PRODUCT PREVIEW
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Sym
VPP
FAST BOOT BLOCK DATASHEET
Table 1. Pin Descriptions
Type
Name and Function
SUPPLY
BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V–3.6 V,
11.4 V–12.6 V): For erasing array blocks or programming data, a valid voltage
must be applied to this pin. With V PP ≤ VPPLK, memory contents cannot be altered.
Block erase and program with an invalid VPP voltage should not be attempted.
Applying 11.4 V–12.6 V to VPP can only be done for a maximum of 1000 cycles on
main blocks and 2500 cycles on the parameter blocks. VPP may be connected to
12 V for a total of 80 hours maximum (see Section 6.0 for details).
VCC
SUPPLY
DEVICE POWER SUPPLY (2.7 V–3.6 V): With VCC ≤ VLKO, all write attempts to
the flash memory are inhibited. Device operations at invalid V CC voltages should
not be attempted.
VCCQ
SUPPLY
OUTPUT POWER SUPPLY (1.65 V–2.5 V, 2.7 V–3.6 V): Enables all outputs to be
driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When VCCQ equals 1.65 V–2.5 V, VCC
voltage must not exceed 3.3 V and should be regulated to 2.7 V–2.85 V to achieve
lowest power operation (see DC Characteristics for detailed information).
This input may be tied directly to V CC.
GND
NC
2.3
SUPPLY
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Memory Blocking Organization
The Fast Boot Block flash memory family is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. For the address locations of each
block, see the memory maps in Figure 3 (top boot
blocking) and Figure 4 (bottom boot blocking).
2.3.1
PARAMETER BLOCKS
The Fast Boot Block flash memory architecture
includes parameter blocks to facilitate storage of
frequently updated small parameters that would
PRODUCT PREVIEW
normally be stored in an EEPROM. By using
software techniques, the word-rewrite functionality
of EEPROMs can be emulated. Each 8- and
16-Mbit
device
contains
eight
4-Kwords
(4,096-words) parameter blocks.
2.3.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for code
and/or data storage. The 8-Mbit device contains
fifteen 32-Kword (32,768-word) main blocks, and
the 16-Mbit device contains thirty-one 32-Kword
(32,768-word) main blocks.
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FAST BOOT BLOCK DATASHEET
8-Mbit
16-Mbit
Address Range
7F000h - 7FFFFh
7E000h - 7EFFFh
7D000h - 7DFFFh
7C000h - 7CFFFh
7B000h - 7BFFFh
7A000h - 7AFFFh
79000h - 79FFFh
78000h - 78FFFh
Block 38
Block 37
Block 36
Block 35
Block 34
Block 33
Block 32
Block 31
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
32-KWord
70000h - 77FFFh
Block 30
32-KWord
F0000h - F7FFFh
32-KWord
68000h - 6FFFFh
Block 29
32-KWord
E8000h - EFFFFh
32-KWord
60000h - 67FFFh
Block 28
32-KWord
E0000h - E7FFFh
32-KWord
58000h - 5FFFFh
Block 27
32-KWord
D8000h - DFFFFh
32-KWord
50000h - 57FFFh
Block 26
32-KWord
D0000h - D7FFFh
32-KWord
48000h - 4FFFFh
Block 25
32-KWord
C8000h - CFFFFh
32-KWord
40000h - 47FFFh
Block 24
32-KWord
C0000h - C7FFFh
32-KWord
38000h - 3FFFFh
Block 23
32-KWord
B8000h - BFFFFh
Block 6
32-KWord
30000h - 37FFFh
Block 22
32-KWord
B0000h - B7FFFh
Block 5
32-KWord
28000h - 2FFFFh
Block 21
32-KWord
A8000h - AFFFFh
Block 4
32-KWord
20000h - 27FFFh
Block 20
32-KWord
A0000h - A7FFFh
Block 3
32-KWord
18000h - 1FFFFh
Block 19
32-KWord
98000h - 9FFFFh
Block 2
32-KWord
10000h - 17FFFh
Block 18
32-KWord
90000h - 97FFFh
Block 1
32-KWord
08000h - 0FFFFh
Block 17
32-KWord
88000h - 8FFFFh
Block 0
32-KWord
00000h - 07FFFh
Block 16
32-KWord
80000h - 87FFFh
Block 15
32-KWord
78000h - 7FFFFh
Block 14
32-KWord
70000h - 77FFFh
Block 13
32-KWord
68000h - 6FFFFh
Block 12
32-KWord
60000h - 67FFFh
Block 11
32-KWord
58000h - 5FFFFh
Block 10
32-KWord
50000h - 57FFFh
Block 9
32-KWord
48000h - 4FFFFh
Block 8
32-KWord
40000h - 47FFFh
Block 7
32-KWord
38000h - 3FFFFh
Block 6
32-KWord
30000h - 37FFFh
Block 5
32-KWord
28000h - 2FFFFh
Block 4
32-KWord
20000h - 27FFFh
Block 3
32-KWord
18000h - 1FFFFh
Block 2
32-KWord
10000h - 17FFFh
Block 1
32-KWord
08000h - 0FFFFh
Block 0
32-KWord
00000h - 07FFFh
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Address Range
FF000h - FFFFFh
FE000h - FEFFFh
FD000h - FDFFFh
FC000h - FCFFFh
FB000h - FBFFFh
FA000h - FAFFFh
F9000h - F9FFFh
F8000h - F8FFFh
Figure 3. 8- and 16-Mbit Top Boot Memory Map
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FAST BOOT BLOCK DATASHEET
16-Mbit
Address Range
Block 38
32-KWord
F8000h - FFFFFh
Block 37
32-KWord
F0000h - F7FFFh
Block 36
32-KWord
E8000h - EFFFFh
Block 35
32-KWord
E0000h - E7FFFh
Block 34
32-KWord
D8000h - DFFFFh
Block 33
32-KWord
D0000h - D7FFFh
Block 32
32-KWord
C8000h - CFFFFh
Block 31
32-KWord
C0000h - C7FFFh
Block 30
32-KWord
B8000h - BFFFFh
Block 29
32-KWord
B0000h - B7FFFh
Block 28
32-KWord
A8000h - AFFFFh
Block 27
32-KWord
A0000h - A7FFFh
Block 26
32-KWord
98000h - 9FFFFh
Block 25
32-KWord
90000h - 97FFFh
Block 24
32-KWord
88000h - 8FFFFh
8-Mbit
Address Range
Block 23
32-KWord
80000h - 87FFFh
Block 22
32-KWord
78000h - 7FFFFh
Block 22
32-KWord
78000h - 7FFFFh
Block 21
32-KWord
70000h - 77FFFh
Block 21
32-KWord
70000h - 77FFFh
Block 20
32-KWord
68000h - 6FFFFh
Block 20
32-KWord
68000h - 6FFFFh
Block 19
32-KWord
60000h - 67FFFh
Block 19
32-KWord
60000h - 67FFFh
Block 18
32-KWord
58000h - 5FFFFh
Block 18
32-KWord
58000h - 5FFFFh
Block 17
32-KWord
50000h - 57FFFh
Block 17
32-KWord
50000h - 57FFFh
Block 16
32-KWord
48000h - 4FFFFh
Block 16
32-KWord
48000h - 4FFFFh
Block 15
32-KWord
40000h - 47FFFh
Block 15
32-KWord
40000h - 47FFFh
Block 14
32-KWord
38000h - 3FFFFh
Block 14
32-KWord
38000h - 3FFFFh
Block 13
32-KWord
30000h - 37FFFh
Block 13
32-KWord
30000h - 37FFFh
Block 12
32-KWord
28000h - 2FFFFh
Block 12
32-KWord
28000h - 2FFFFh
Block 11
32-KWord
20000h - 27FFFh
Block 11
32-KWord
20000h - 27FFFh
Block 10
32-KWord
18000h - 1FFFFh
Block 10
32-KWord
18000h - 1FFFFh
Block 9
32-KWord
10000h - 17FFFh
Block 9
32-KWord
10000h - 17FFFh
Block 8
32-KWord
08000h - 0FFFFh
Block 8
32-KWord
08000h - 0FFFFh
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
07000h - 07FFFh
06000h - 06FFFh
05000h - 05FFFh
04000h - 04FFFh
03000h - 03FFFh
02000h - 02FFFh
01000h - 01FFFh
00000h - 00FFFh
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
07000h - 07FFFh
06000h - 06FFFh
05000h - 05FFFh
04000h - 04FFFh
03000h - 03FFFh
02000h - 02FFFh
01000h - 01FFFh
00000h - 00FFFh
Figure 4. 8- and 16-Mbit Bottom Boot Memory Map
PRODUCT PREVIEW
11
E
FAST BOOT BLOCK DATASHEET
3.0
PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components
include an on-chip WSM to manage block erase
and program. It allows for CMOS-level control
inputs, fixed power supplies, and minimal processor
overhead with RAM-like interface timings.
3.1
Bus Operations
All bus cycles to and from flash memory conform to
standard microprocessor bus cycles.
3.1.1
READ
The flash memory has three read modes available:
read array, identifier codes, and status register.
These modes are accessible independent of the
VPP voltage. The appropriate read command (Read
Array, Read Identifier Codes, or Read Status
Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit
from reset, the device defaults to read array mode.
When reading information from main blocks in read
array mode, the device supports two highperformance read configurations: asynchronous
page-mode
and
synchronous
burst-mode.
Asynchronous page-mode is the default state and
provides high data transfer rate for non-clocked
memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A1:0
addresses data in the page buffer. The page size is
four words. The other read configuration,
synchronous burst-mode, is enabled by writing to
read configuration register. This register sets the
read configuration, burst order, frequency
configuration, and burst length. In synchronous
burst-mode, the device latches the initial address
then outputs a sequence of data with respect to the
input CLK and read configuration setting.
12
Read operations from the parameter blocks,
identifier codes and status register transpire as
single asynchronous or synchronous read cycles.
The read configuration register setting determines
whether or not read operations are asynchronous or
synchronous.
For all read operations, CE# must be driven active
to enable the devices, ADV# must be driven low to
open the internal address latch, and OE# must be
driven low to activate the outputs. In asynchronous
mode, the address is latched when ADV# is driven
high. In synchronous mode, the address is latched
by ADV# going high or ADV# low in conjunction
with a rising (falling) clock edge, whichever occurs
first. WE# must be at VIH. Figures 14 through 19
illustrate different read cycles.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode,
which substantially reduces device power
consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
3.1.4
WRITE
Commands are written to the CUI using standard
microprocessor write timings when ADV#, WE#,
and CE# are active and OE# inactive. The CUI
does not occupy an addressable memory location.
The address is latched on the rising edge of ADV#,
WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the
rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous.
Therefore, CLK is ignored during write operations.
Figure 20 illustrates a write operation.
PRODUCT PREVIEW
E
3.1.5
FAST BOOT BLOCK DATASHEET
RESET
The device enters a reset mode when RST# is
driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance
state.
After return from reset, a time tPHQV is required until
outputs are valid, and a delay (tPHWL or tPHEL) is
required before a write sequence can be initiated.
After this wake-up interval, normal operation is
restored. The device defaults to read array mode,
the status register is set to 80H, and the read
configuration register defaults to asynchronous
page-mode reads.
If RP# is taken low during a block erase or program
operation, the operation will be aborted and the
memory contents at the aborted location are no
longer valid. See Figure 21 for detailed information
regarding reset timings.
4.0
COMMAND DEFINITIONS
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2. Bus Operations
Mode
Notes
RST#
CE#
ADV#
OE#
WE#
Address
VPP
DQ0–15
VIL
X
X
X
X
X
X
High Z
Standby
VIH
VIH
X
X
X
X
X
High Z
Output Disable
VIH
VIL
X
VIH
VIH
X
X
High Z
VIH
VIL
VIL
VIL
VIH
X
X
DOUT
VIH
VIL
VIL
VIL
VIH
See
Table 4
X
See
Table 4
VIH
VIL
VIL
VIH
VIL
X
X
DIN
Reset
Read
1,2
Read Identifier
Codes
Write
3,4
NOTES:
1.
Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2.
X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3.
Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2
(see Section 8 for operating conditions at different temperatures).
4.
Refer to Table 3 for valid DIN during a write operation.
PRODUCT PREVIEW
13
E
FAST BOOT BLOCK DATASHEET
Table 3. Command Definitions(1)
Bus Cycles
Command
Read Array/Reset
Req’d.
First Bus Cycle
Notes
1
Second Bus Cycle
Oper(2)
Addr(3)
Data(4)
Oper(2) Addr(3) Data(4)
Write
X
FFH
Write
X
90H
Read
IA
ID
Write
X
70H
Read
X
SRD
Read Identifier Codes
≥2
Read Status Register
2
Clear Status Register
1
Write
X
50H
Block Erase
2
6,7
Write
X
20H
Write
BA
D0H
Program
2
6,7,8
Write
X
40H
or
10H
Write
WA
WD
Block Erase and Program
Suspend
1
6
Write
X
B0H
Block Erase and Program
Resume
1
6
Write
X
D0H
Set Read Configuration
2
Write
X
60H
Write
RCD
03H
5
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. Bus operations are defined in Table 2.
3. X = Any valid address within the device.
IA = Identifier Code Address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
RCD = Data to be written to the read configuration register. This data is presented to the device on A15-0; set all other
address inputs to “0.”
4. SRD = Data read from status register. See Table 5 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.
RCD = Data to be written to read configuration register. See Table 6 for a description of the read configuration register bits.
5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read
configuration register.
6. Following a block erase, program, and suspend operation, read operations access the status register.
7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at VIH.
8. Either 40H or 10H are recognized by the WSM as the program setup.
14
PRODUCT PREVIEW
E
4.1
FAST BOOT BLOCK DATASHEET
Read Array Command
Upon initial device power-up or exit from reset, the
device defaults to read array mode. The read
configuration register defaults to asynchronous
page-mode. The Read Array command also causes
the device to enter read array mode. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or program, the device will not
recognize the Read Array command until the WSM
completes its operation or unless the WSM is
suspended via an Erase or Program Suspend
command. The Read Array command functions
independently of the VPP voltage.
4.2
Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. After writing
the command, read cycles retrieve the
manufacturer and device codes (see Table 4 for
identifier code values). Page-mode and burst reads
are not supported in this read mode. To terminate
the operation, write another valid command, like the
Read Array command. The Read Identifier Codes
command functions independently of the VPP
voltage.
Table 4. Identifier Codes
Code
Manufacturer Code
Device Code 8 Mbit
16 Mbit
4.3
-T
-B
-T
-B
Address
(Hex)
Data
(Hex)
00000
00001
00001
00001
00001
0089
88F1
88F2
88F3
88F4
Read Status Register
Command
The status register can be read at any time by
writing the Read Status Register command to the
CUI. After writing this command, all subsequent
read operations output status register data until
PRODUCT PREVIEW
another valid command is written. Page-mode and
burst reads are not supported in this read mode.
The status register content is updated and latched
on the rising edge of ADV# or rising (falling) CLK
edge when ADV# is low during synchronous burstmode or the falling edge of OE# or CE#, whichever
occurs first. The Read Status Register command
functions independently of the VPP voltage.
4.4
Clear Status Register
Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be cleared by
issuing the Clear Status Register command. These
bits indicate various error conditions. By allowing
system software to reset these bits, several
operations may be performed (such as cumulatively
erasing or writing several bytes in sequence). The
status register may be polled to determine if a
problem occurred during the sequence. The Clear
Status Register command functions independently
of the applied VPP voltage. After executing this
command, the device returns to read array mode.
4.5
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command
sequence
requires
appropriate
sequencing and address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM. After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see
Figure 7, Automated Block Erase Flowchart). The
CPU can detect block erase completion by
analyzing status register bit SR.7.
When the block erase completes, check status
register bit SR.5 for an error flag (“1”). If an error is
detected, check status register bits SR.4, SR.3, and
SR.1 to understand what caused the failure. After
examining the status register, it should be cleared if
an error was detected before issuing a new
command. The device will remain in status register
read mode until another command is written to the
CUI.
15
E
FAST BOOT BLOCK DATASHEET
Table 5. Status Register Definition
WSMS
ESS
ES
PS
VPPS
PSS
DPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
Check SR.7 to determine block erase or program
completion. SR.6–0 are invalid while SR.7 = “0.”
When an Erase Suspend command is issued, the
WSM halts execution and sets both SR.7 and SR.6
to “1.” SR.6 remains set until an Erase Resume
command is written to the CUI.
If both SR.5 and SR.4 are “1”s after a block erase or
program attempt, an improper command sequence
was entered.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Program
0 = Successful Program
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
16
SR.3 does not provide a continuous VPP feedback.
The WSM interrogates and indicates the VPP level
only after a block erase or program operation. SR.3
is not guaranteed to reports accurate feedback
when VPP ≠ VPPH1/2 or VPPLK.
When an Program Suspend command is issued, the
WSM halts execution and sets both SR.7 and SR.2
to “1.” SR.2 remains set until an Program Resume
command is written to the CUI.
If a block erase or program operation is attempted to
a locked block, SR.1 is set by the WSM and aborts
the operation if WP# = VIL.
SR.0 is reserved for future use and should be
masked out when polling the status register.
PRODUCT PREVIEW
E
4.6
Program Command
Program operation is executed by a two-cycle
command sequence. Program setup (standard 40H
or alternate 10H) is written, followed by a second
write that specifies the address and data. The WSM
then takes over, controlling the internal program
algorithm. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8, Automated Program
Flowchart). The CPU can detect the completion of
the program event by analyzing status register bit
SR.7.
When the program operation completes, check
status register bit SR.4 for an error flag (“1”). If an
error is detected, check status register bits SR.5,
SR.3, and SR.1 to understand what caused the
problem. After examining the status register, it
should be cleared if an error was detected before
issuing a new command. The device will remain in
status register read mode until another command is
written to the CUI.
4.7
Block Erase Suspend/Resume
Command
The Block Erase Suspend command allows block
erase interruption to read or program data in
another blocks. Once the block erase process
starts, writing the Block Erase Suspend command
requests that the WSM suspend the block erase
operation after a certain latency period. The device
continues to output status register data when read
after the Block Erase Suspend command is issued.
Status Register bits SR.7 and SR.6 indicate when
the block erase operation has been suspended
(both will be set to “1”). Specification tWHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can be suspended during an erase suspend. The
only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume.
PRODUCT PREVIEW
FAST BOOT BLOCK DATASHEET
During a block erase suspend, the chip can go into
a pseudo-standby mode by taking CE# to VIH,
which reduces active current draw. VPP must
remain at VPPH1/2 while block erase is suspended.
WP# must also remain at V IL or VIH.
To resume the block erase operation, write the
Block Erase Resume command to the CUI. This will
automatically clear status register bits SR.6 and
SR.7. After the Erase Resume command is written,
the device automatically outputs status register
data when read (see Figure 9, Block Erase
Suspend/Resume Flowchart). Block erase cannot
resume until program operations initiated during
block erase suspend have completed.
4.8
Program Suspend/Resume
Command
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
WSM suspend the program operation after a certain
latency period. The device continues to output
status register data when read after issuing
Program Suspend command. Status register bits
SR.7 and SR.2 indicate when the block erase
operation has been suspended (both will be set to
“1”). Specification tWHRH1 defines the program
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. The only other valid commands while
block erase is suspended are Read Status Register
and Program Resume.
During a program suspend, the chip can go into a
pseudo-standby mode by taking CE# to VIH, which
reduces active current draw. VPP must remain at
VPPH1/2 while program is suspended. WP# must
also remain at VIL or VIH.
To resume the program, write the Program Resume
command to the CUI. This will automatically clear
status register bits SR.7 and SR.2. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Figure 10, Program Suspend/Resume
Flowchart).
17
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FAST BOOT BLOCK DATASHEET
Table 6. Read Configuration Register Definition
RM
R
FC2
FC1
FC0
R
DOC
WC
15
14
13
12
11
10
9
8
BS
CC
R
R
R
BL2
BL1
BL0
7
6
5
4
3
2
1
0
NOTES:
RCR.15 = READ MODE (RM)
0 = Synchronous Burst Reads Enabled
1 = Page-Mode Reads Enabled (Default)
Read mode configuration effects reads from
main blocks. Parameter block, status register,
and identifier reads support single read cycles.
RCR.14 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use. Set
these bits to “0.”
RCR.13–11 = FREQUENCY CONFIGURATION (FC2-0)
001 = Code 1 reserved for future use
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6
See Section 4.9.2 for information about the
frequency configuration and its effect on the
initial read.
RCR.10 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use. Set
these bits to “0.”
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
1 = Hold Data for Two Clocks
Undocumented combinations of bits RCR.10–9
are reserved by Intel Corporation for future
implementations and should not be used.
Undocumented combinations of bits
RCR.14–11 are reserved by Intel Corporation
for future implementations and should not be
used.
RCR.8 = WAIT CONFIGURATION (WC)
0 = WAIT# Asserted During Delay
1 = WAIT# Asserted One Data Cycle Before Delay
RCR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
1 = Linear Burst Order
RCR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling
Clock Edge
1 = Burst Starts and Data Output on Rising
Clock Edge
RCR.5–3 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use. Set
these bits to “0.”
RCR.2–0 = BURST LENGTH (BL2–0)
001 = 4 Word Burst
010 = 8 Word Burst
111 = Continuous Burst
In the asynchronous page mode, the burst
length always equals four words.
Undocumented combinations of bits RCR.2–0
are reserved by Intel Corporation for future
implementations and should not be used
18
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
CLK (C)
A19-0 (A)
Valid
Address
ADV# (V)
Code 2
Valid
Output
DQ15-0 (D/Q)
Code 3
DQ15-0 (D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 4
DQ15-0 (D/Q)
Code 5
DQ15-0 (D/Q)
Code 6
Valid
Output
DQ15-0 (D/Q)
Figure 5. Frequency Configuration
Table 7. Frequency Configuration Settings(1)
Frequency
Input CLK Frequency
Configuration
Product = -90
Product = -120
Code
VCC = 3.0 V-3.6 V
VCC = 2.7 V-3.6 V
VCC = 2.7 V-3.6 V
1
Reserved
Reserved
Reserved
2
≤ 27 MHz
≤ 25 MHz
≤ 20 MHz
3
≤ 40 MHz
≤ 33 MHz
≤ 28 MHz
4
≤ 54 MHz
≤ 50 MHz
≤ 40 MHz
5
≤ 66 MHz
≤ 60 MHz
≤ 50 MHz
6
-
≤ 66 MHz
≤ 60 MHz
NOTES:
1. Reference Section 4.1. Automotive Temperature Frequency Configuration Settings for the corresponding frequency
configuration codes to different input CLK frequencies.
4.9
Set Read Configuration
Command
The Set Read Configuration command writes data
to the read configuration register. This operation is
initiated by a two-cycle command sequence. Read
configuration setup is written, followed by a second
write that specifies the data to be written to the read
configuration register. This data is placed on the
address bus, A15:0, and is latched on the rising
edge of ADV#, CE#, or WE# (whichever occurs
PRODUCT PREVIEW
first). The read configuration data sets the device’s
read configuration, burst order, frequency
configuration, and burst length. The command
functions independently of the applied VPP voltage.
After executing this command, the device returns to
read array mode.
4.9.1
READ CONFIGURATION
The device supports two high performance read
configurations: asynchronous page-mode and
19
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FAST BOOT BLOCK DATASHEET
synchronous burst-mode. Bit RCR.15 in the read
configuration register sets the read configuration.
Asynchronous page-mode is the default read
configuration state.
Parameter blocks, status register, and identifier
only support single asynchronous and synchronous
read operations.
4.9.2
FREQUENCY CONFIGURATION
The frequency configuration informs the device of
the number of clocks that must elapse after ADV#
is driven active before data will be available. This
value is determined by the input clock frequency.
See Table 7 for the specific input CLK frequency
configuration code
length is enabled. Its setting will depend on the
system and CPU characteristic.
4.9.5
BURST SEQUENCE
The burst sequence specifies the order in which
data is addressed in synchronous burst-mode. This
order is programmable as either linear or Intel burst
order. The continuous burst length only supports
linear burst order. The order chosen will depend on
the CPU characteristic. See Table 8 for more
details.
4.9.6
CLOCK CONFIGURATION
Figure 5 illustrates data output latency from ADV#
going active for different frequency configuration
codes.
The clock configuration configures the device to
start a burst cycle, output data, and assert WAIT#
on the rising or falling edge of the clock. CLK
flexibility helps ease Fast Boot Block flash memory
interface to wide range of burst CPUs.
4.9.3
4.9.7
DATA OUTPUT CONFIGURATION
The output configuration determines how many
clocks data will be held valid. The data hold time is
configurable as either one or two clocks.
The data output configuration must be set to hold
data valid for two clock cycles when the frequency
configuration value 4 and burst length is greater
than four words. Otherwise, its setting will depend
on the system CPU’s data setup requirement.
The burst length is the number of words that the
device will output. The device supports burst
lengths of four and eight words. It also supports a
continuous burst mode. In continuous burst mode,
the device will linearly output data until the internal
burst counter reaches the end of the device’s
burstable address space. Bits RCR.2–0 in the read
configuration register set the burst length.
4.9.7.1
CLK (C)
1 CLK
Data Hold
DQ15-0 (D/Q)
2 CLK
Data hold
DQ15-0 (D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Figure 6. Output Configuration
4.9.4
WAIT# CONFIGURATION
The WAIT# configuration bit controls the behavior
of the WAIT# output signal. This output signal can
be set to be asserted during or one CLK cycle
before an output delay when continuous burst
20
BURST LENGTH
Continuous Burst Length
When operating in the continuous burst mode, the
flash memory may incur an output delay when the
burst sequence crosses the first sixteen word
boundary. The starting address dictates whether or
not a delay will occur. If the starting address is
aligned to a four word boundary, the delay will not
be seen. If the starting address is the end of a four
word boundary, the output delay will be equal to the
frequency configuration setting; this is the worst
case delay. The delay will only take place once
during a continuous burst access, and if the burst
sequence never crosses a sixteen word boundary,
the delay will never happen. Using the WAIT#
output pin in the continuous burst configuration, the
system is informed if this output delay occurs.
PRODUCT PREVIEW
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FAST BOOT BLOCK DATASHEET
Table 8. Sequence and Burst Length
Burst Addressing Sequence (Dec)
Starting
Addr.
4 Word
Burst Length
8 Word
Burst Length
Continuous
Burst
(Dec)
Linear
Intel
Linear
Intel
Linear
0
0-1-2-3
0-1-2-3
0-1-2-34-5-6-7
0-1-2-34-5-6-7
0-1-2-3-4-5-6-...
1
1-2-3-0
1-0-3-2
1-2-3-45-6-7-0
1-0-3-25-4-7-6
1-2-3-4-5-6-7-...
2
2-3-0-1
2-3-0-1
2-3-4-56-7-0-1
2-3-0-16-7-4-5
2-3-4-5-6-7-8-...
3
3-0-1-2
3-2-1-0
3-4-5-67-0-1-2
3-2-1-07-6-5-4
3-4-5-6-7-8-9-...
M
M
M
M
M
M
6
6-7-0-12-3-4-5
6-7-4-52-3-0-1
6-7-8-9-10-11-12-...
7
7-0-1-23-4-5-6
7-6-5-43-2-1-0
7-8-9-10-11-12-13...
M
14
14-15-16-17-18-19-20-...
15
15-16-17-18-19-20-21-...
M
PRODUCT PREVIEW
21
E
FAST BOOT BLOCK DATASHEET
Start
Bus Operation
Write 20H,
Block Address
Write D0H,
Block Address
Command
Write
Erase Setup
Write
Erase Confirm
Data = D0H
Addr = Within Block to Be
Erased
Read
Suspend
Blk. Erase
Loop
Read Status Register
0
SR.7 =
No
Suspend
Block Erase
Comments
Data = 20H
Addr = Within Block to Be
Erased
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent block erasures.
Yes
1
Full status check can be done after each block erase or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
Command
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Block Erase Error
VPP Range Error
1
SR.1 =
Device Protect Error
0
1
SR.4, 5 =
Command Sequence
Error
0
Comments
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus
Register command, in cases where multiple blocks are erased before
full status is checked.
1
SR.5 =
Block Erase Error
If an error is detected, clear the status register before attempting retry
or other error recovery.
0
Block Erase
Successful
Figure 7. Automated Block Erase Flowchart
22
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
Start
Bus Operation
Write 40H,
Address
Command
Write
Program Setup
Write
Data
Write Data and
Address
Read
Suspend
Program
Loop
Read Status Register
0
SR.7 =
No
Suspend
Program
Comments
Data = 40H
Addr = Location to Be
Written
Data = Data to Be Written
Addr = Location to Be
Written
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent byte writes.
Yes
1
SR full status check can be done after each byte write or after a
sequence of program operations.
Write FFH after the last byte write operation to place device in read
array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Command
Comments
1
SR.3 =
0
VPP Range Error
1
SR.1 =
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL
Standby
Check SR.4
1 = Data Write Error
Device Protect Error
0
1
SR.4 =
Program Error
0
SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register
command, in cases where multiple locations are written before full
status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Program Successful
Figure 8. Automated Program Flowchart
PRODUCT PREVIEW
23
E
FAST BOOT BLOCK DATASHEET
Bus Operation
Start
Write
Command
Erase Suspend
Write B0H
Status Register Data
Addr = X
Read
Read Status Register
0
SR.7 =
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Write
1
0
SR.6 =
Comments
Data = B0H
Addr = X
Erase Resume
Data = D0H
Addr = X
Block Erase
Completed
1
Read
Program
Read or Byte
Write?
Read Array
Data
Program
Loop
No
Done
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
24
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
Start
Bus Operation
Command
Write
Program
Suspend
Comments
Data = B0H
Addr = X
Write B0H
Status Register Data
Addr = X
Read
Read Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Program Suspended
0 = Program Completed
0
SR.7 =
1
0
SR.2 =
Write
Read Array
Program Completed
Read array locations from
block other than that being
written
Read
1
Write FFH
Write
Data = FFH
Addr = X
Program Resume
Data = D0H
Addr = X
Read Array Data
Done
Reading
No
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
Figure 10. Program Suspend/Resume Flowchart
PRODUCT PREVIEW
25
FAST BOOT BLOCK DATASHEET
5.0
DATA PROTECTION
The Fast Boot Block flash memory architecture
features hardware-lockable main blocks and two
parameter blocks, so critical code can be kept
secure while other parameter blocks are
programmed or erased as necessary.
VPP ≤ VPPLK for Complete
Protection
5.1
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device. When VPP is below VPPLK, any block erase
or program operation will result in a error, prompting
the corresponding status register bit (SR.3) to be
set.
5.2
6.0
Intel’s Fast Boot Block flash memory family
provides in-system programming and erase at
2.7 V–3.6 V
(3.0 V–3.6 V
for
automotive
temperature) VPP. For customers requiring fast
programming in their manufacturing environment,
this family of products includes an additional lowcost, high-performance 12 V programming feature.
The 12 V VPP mode enhances programming
performance during short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to VPP during block erase and program operations
for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may
be connected to 12 V for a total of 80 hours
maximum. Stressing the device beyond these limits
may cause permanent damage.
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = VIL;
any block erase or program operation to a locked
block will result in an error, which will be reflected in
the status register. For top configuration, the top
two parameter and all main blocks (blocks #37,
#38, and #0 through 30 for the 16-Mbit, blocks #21,
#22, and #0 through #14 for the 8-Mbit) are
lockable. For the bottom configuration, the bottom
two parameter and all main blocks (blocks #0, #1,
and #8 through #38 for the 16-Mbit, blocks #0, #1,
and #8 through #22 for the 8-Mbit) are lockable.
Unlocked blocks can be programmed or erased
normally (unless VPP is below VPPLK).
7.0
WP# = VIH for Block Unlocking
WP# controls all block locking and VPP provides
protection against spurious writes. Table 9 defines
the write protection methods.
Table 9. Write Protection Truth Table
VPP
WP#
RST#
Write Protection
Provided
X
X
VIL
All Blocks Locked
VIL
X
VIH
All Blocks Locked
≥ VPPLK
VIL
VIH
Lockable
Blocks Locked
≥ VPPLK
VIH
VIH
All
Blocks Unlocked
POWER CONSUMPTION
While in operation, the flash device consumes
active power. However, Intel Flash devices have
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is idle. If CE# is deasserted, the
flash enters its standby mode, where current
consumption is even lower. The combination of
these features minimizes overall memory power
and system power consumption.
7.1
5.3
26
VPP VOLTAGES
E
Active Power
With CE# at a logic-low level and RST# at a logichigh level, the device is in active mode. Active
power is the largest contributor to overall system
power consumption. Minimizing active current has a
profound effect on system power consumption,
especially for battery-operated devices.
7.2
Automatic Power Savings
Automatic Power Savings (APS) provides lowpower operation during active mode, allowing the
flash to put itself into a low current state when not
being accessed. After data is read from the memory
array, the device’s power consumption enters the
APS mode where typical ICC current is comparable
to ICCS. The flash stays in this static state with
outputs valid until a new location is read.
PRODUCT PREVIEW
E
7.3
Standby Power
With CE# at a logic-high level (VIH) and the CUI in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ0–DQ15) are placed in a high-impedance state
independent of the status of the OE# signal. If CE#
transitions to a logic-high level during erase or
program operations, the device will continue to
perform the operation and consume corresponding
active power until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
7.4
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP,
VCC, or VCCQ, powers-up first.
7.4.1
RST# CONNECTION
The use of RST# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RST# to the system reset signal to allow proper
CPU/flash initialization following system reset.
System designers must guard against spurious
writes when VCC voltages are above VLKO and VPP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to VIH will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RST# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset during power-up/down,
invalid bus conditions during power-up can be
masked, providing yet another level of memory
protection.
PRODUCT PREVIEW
FAST BOOT BLOCK DATASHEET
7.4.2
VCC, VPP AND RST# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode or
after VCC transitions above VLKO (Lockout voltage),
is read array mode.
After any block erase or program operation is
complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
7.5
Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
1. Standby current levels (ICCS)
2. Active current levels (I CCR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These highfrequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
7.5.1
VPP TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin supplies the flash memory cells current
for programming and erasing. VPP trace widths and
layout should be similar to that of VCC. Adequate
VPP supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
27
E
FAST BOOT BLOCK DATASHEET
8.0
ELECTRICAL SPECIFICATIONS
8.1
Absolute Maximum Ratings*
NOTICE: This datasheet contains preliminary
information on products in the design phase of
development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest datasheet
before finalizing a design.
Temperature under Bias ............ –40 °C to +125 °C
Storage Temperature................. –65 °C to +125 °C
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operation
beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
Voltage On Any Pin
(except VCC, VCCQ, and VPP) –0.5 V to +5.5 V(1)
VPP Voltage ......................... –0.5 V to +13.5 V(1,2,4)
VCC and VCCQ Voltage ............... –0.2 V to +5.0 V (1)
Output Short Circuit Current.....................100 mA(3)
NOTES:
1.
All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC and
VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output
pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.
2.
Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns.
3.
Output shorted for no more than one second. No more than one output shorted at a time.
4.
VPP Program voltage is normally 2.7 V–3.6 V. Connection to supply of 11.4 V–12.6 V can only be done for 1000 cycles on
the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12 V for a total
of 80 hours maximum.
8.2
Extended Temperature Operating Conditions
Symbol
Parameter
Notes
Min
Max
Unit
–40
+85
°C
TA
Operating Temperature
VCC1
VCC Supply Voltage
1
2.7
2.85
V
VCC2
VCC Supply Voltage
1
2.7
3.3
V
VCC3
VCC Supply Voltage
1,4
2.7
3.6
V
VCCQ1
I/O Voltage
1,2
1.65
2.5
V
VCCQ2
I/O Voltage
1,2
1.8
2.5
V
VCCQ3
I/O Voltage
1,2,4
2.7
3.6
V
VPPH1
VPP Supply Voltage
1
2.7
3.6
V
VPPH2
VPP Supply Voltage
1,4
11.4
12.6
V
Cycling
Block Erase Cycling
3
10,000
Cycles
NOTES:
1. See DC Characteristics tables for voltage range-specific specifications.
2. The voltage swing on the inputs, VIN is required to match VCCQ.
3. Applying VPP = 11.4 V–12.6 V during a program or erase can only be done for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. A hard connection to VPP = 11.4 V–12.6 V is not allowed and can cause
damage to the device.
4. VCC, VCCQ, and VPP1 must share the same supply when all three are between 2.7 V and 3.6 V.
28
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
Capacitance(1)
8.3
TA = +25 °C, f = 1 MHz
Sym
Parameter
Typ
Max
Unit
Condition
CIN
Input Capacitance
6
8
pF
VIN = 0.0 V
COUT
Output Capacitance
8
12
pF
VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
VCCQ
Input
Test Points
VCCQ/2
VCCQ/2
Output
0V
AC test inputs are driven at VCCQ min. for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 2.7 V.
Figure 11. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V
Test Configuration Component Value
for Worst Case Speed Conditions
VCCQ
Test Configuration
R1
Device
Under Test
Out
CL
R2
CL (pF)
R1 (Ω)
R2 (Ω)
2.7 V Standard Test
50
25K
25K
1.65 V Standard Test
50
16.7K
16.7K
NOTE:
CL includes jig capacitance.
NOTE:
See table for component values.
Figure 12. Transient Equivalent Testing
Load Circuit
PRODUCT PREVIEW
29
E
FAST BOOT BLOCK DATASHEET
8.4
Sym
DC Characteristics—Extended Temperature(1)
Parameter
VCC
2.7 V–3.6 V
2.7 V–2.85 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V 1.65 V–2.5 V
Note Typ
Max
Typ
Max
2.7 V–3.3 V
Typ
Max
Unit
Test Conditions
ILI
Input Load
Current
6
±1
±1
±1
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO
Output Leakage
Current
6
± 10
± 10
± 10
µA
VCC = VCCMax
VCCQ = VCCQMax
± 25
± 25
± 25
Output Leakage
Current for
WAIT#
ICCS
VCC Standby
VIN = VCCQ or GND
6
30
50
20
50
150
250
µA
VCC = VCCMax
CE# = RP# = VCC
or during Program/
Erase Suspend
4,6
45
60
30
45
40
55
mA
Asynchronous
tAVAV = Min
VIN = VIH or VIL
45
60
30
45
40
55
mA
Synchronous
CLK = 33 MHz
CE# = VIL
OE# = VIH
Burst length = 1
Current
ICCR
VCC Read
Current
ICCW
VCC Program
Current
3,6
8
20
8
20
8
20
mA
VPP = VPP1, 2
Program in Progress
ICCE
VCC Erase
Current
3,6
8
20
8
20
8
20
mA
VPP = VPP1, 2
Erase in Progress
IPPR
VPP Read
Current
2
±15
2
±15
2
±15
µA
VPP ≤ VCC
3
50
200
50
200
50
200
µA
VPP > VCC
IPPW
VPP Program
Current
3
10
35
10
35
10
35
mA
VPP =VPP1
Program in Progress
2
10
2
10
2
10
mA
VPP = VPP2
Program in Progress
12
25
13
25
13
25
mA
VPP = VPP1
Program in Progress
8
25
8
25
8
25
mA
VPP = VPP2
Program in Progress
50
200
50
200
50
200
µA
VPP = VPP1, 2
Program or Erase
Suspend in Progress
IPPE
IPPES
IPPWS
30
VPP Erase
Current
VPP Erase
Suspend Current
3
3
PRODUCT PREVIEW
E
8.4
Sym
FAST BOOT BLOCK DATASHEET
DC Characteristics—Extended Temperature (Continued)
Parameter
VCC
2.7 V–3.6 V
2.7 V–2.85 V
2.7 V–3.3 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V
1.8 V–2.5 V
Note
Min
Max
Min
Max
Min
Max
Unit
0.4
–0.2
0.2
–0.2
0.2
V
VIL
Input Low
Voltage
–0.4
VIH
Input High
Voltage
VCCQ
–
0.4V
VOL
Output Low
Voltage
VOH
Output High
Voltage
VCCQ
–
0.2V
0.10
VCCQ
–
0.1V
2
1.5
1.5
VPP1
VPP during
2
2.7
3.6
VPP2
Program and
2
VPP3
Erase Operations
2
VLKO
2,5
VCC Prog/Erase
Lock Voltage
VLKO2 VCCQ Prog/Erase
Lock Voltage
12.6
-0.10
V
0.10
VCCQ
–
0.1V
1.5
1.5
V
VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
V
Complete Write
Protection
V
2.7
11.4
0.10
VCCQ
–
0.1V
VPPLK VPP Lock-Out
Voltage
VPP4
-0.10
VCCQ
–
0.2V
Test Conditions
11.4
2.85
12.6
V
2.7
3.3
V
11.4
12.6
V
1.5
1.5
1.5
V
1.2
1.2
1.2
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, T = +25 °C.
2. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR.
3. Erases and program operations are inhibited when VPP ≤ VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1
and VPPH2.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels, in static operation.
6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum.
7. The specification is the sum of VCC and VCCQ currents.
PRODUCT PREVIEW
31
E
FAST BOOT BLOCK DATASHEET
8.5
#
AC Characteristics—Read-Only Operations(1,6)—Extended Temperature
Sym
Parameter
Product
–95
–120
VCC
3.0 V–3.6 V 2.7 V–3.6 V
2.7 V–3.6 V
Min
Min
Notes
Max
Min
Max
Max Unit
R1
tCLK
CLK Period
15
15
15
ns
R2
tCH(tCL)
CLK High (Low) Time
2.5
2.5
2.5
ns
R3
tCHCL
CLK Fall (Rise) Time
R4
tAVCH
Address Valid Setup to CLK
7
7
7
ns
R5
tVLCH
ADV# Low Setup to CLK
7
7
7
ns
R6
tELCH
CE# Low Setup to CLK
7
R7
tCHQV
CLK to Output Delay
R8
tCHQX
Output Hold from CLK
5
5
7
14
5
7
16
5
10
5
ns
23
5
10
ns
ns
ns
R9
tCHAX
Address Hold from CLK
3
R10
tCHTL
CLK to WAIT# delay
5
R11
tAVVH
Address Setup to ADV# High
10
R12
tELVH
CE# Low to ADV# High
10
R13
tAVQV
Address to Output Delay
R14
tELQV
CE# Low to Output Delay
R15
tVLQV
ADV# Low to Output Delay
R16
tVLVH
ADV# Pulse Width Low
10
10
10
ns
R17
tVHVL
ADV# Pulse Width High
4
10
10
10
ns
R18
tVHAX
Address Hold from ADV# High
3
3
3
3
ns
R19
tAPA
Page Address Access Time
21
23
30
ns
R20
tGLQV
OE# Low to Output Delay
25
25
30
ns
R21
tRHQV
RST# High to Output Delay
600
600
600
ns
R22
tEHQZ
tGHQZ
CE# or OE# High to Output in
High Z, Whichever Occurs First
4
25
25
25
ns
R23
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
4
13
2
0
10
16
10
ns
23
10
10
ns
ns
10
ns
90
95
120
ns
90
95
120
ns
90
95
120
ns
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
3. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first.
4. Sampled, not 100% tested.
5. Output loading on WAIT# equals 15 pF.
6. Data bus voltage must be less than or equal to VCCQ when a read operation is initiated to guarantee AC specifications.
32
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
R3
CLK (C)
R2
R1
Figure 13. AC Waveform for CLK Input
A19-0 (A)
VIH
VIL
Valid
Address
R18
R13
R11
ADV# (V)
VIH
R17
VIL
R16
R22
R15
CE# (E)
VIH
VIL
R12
R14
OE# (G)
VIH
VIL
WE# (W)
VIH
VIL
WAIT# (T)
VOH
VOL
R23
R20
VOH
DQ15-0 (D/Q)
High Z
Valid
Output
VOL
R21
RST# (R)
VIH
VIL
Figure 14. AC Waveform for Single Asynchronous Read Operation
from Parameter Blocks, Status Register, Identifier Codes
PRODUCT PREVIEW
33
E
FAST BOOT BLOCK DATASHEET
A19-2 (A)
A1-0 (A)
VIH
Valid
Address
VIL
VIH
Valid
Address
VIL
Valid
Address
Valid
Address
Valid
Address
R13
R18
R11
R17
ADV# (V)
VIH
VIL
R16
R15
CE# (E)
R22
VIH
VIL
R14
OE# (G)
VIH
VIL
WE# (W)
VIH
VIL
WAIT# (T)
VOH
VOL
R20
VOH
DQ15-0 (D/Q)
High Z
R19
Valid
Output
VOL
Valid
Output
R23
Valid
Output
Valid
Output
R21
RST# (R)
VIH
VIL
Figure 15. AC Waveform for Asynchronous Page-Mode Read Operations
from Main Blocks
34
PRODUCT PREVIEW
E
CLK (C)
FAST BOOT BLOCK DATASHEET
VIH
Note 1
VIL
R4
A19-0 (A)
VIH
VIL
Valid
Address
R9
R18
R11
R17
ADV# (V)
VIH
VIL
R16
R22
R5
CE# (E)
VIH
VIL
R12
R6
OE# (G)
VIH
VIL
WE# (W)
VIH
VIL
WAIT# (T)
VOH
R20
VOL
R7
VOH
DQ15-0 (D/Q)
High Z
VOL
R23
Valid
Output
NOTE:
1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 16. AC Waveform for Single Synchronous Read Operations
from Parameter Blocks, Status Register, Identifier Codes
PRODUCT PREVIEW
35
E
FAST BOOT BLOCK DATASHEET
CLK (C)
VIH
Note 1
VIL
R4
A19-0 (A)
VIH
VIL
Valid
Address
R9
R18
R11
R17
ADV# (V)
VIH
VIL
R16
R22
R5
CE# (E)
VIH
VIL
R12
R6
OE# (G)
VIH
VIL
WE# (W)
VIH
VIL
WAIT# (T)
VOH
R20
VOL
R7
R8
VOH
DQ15-0 (D/Q)
VOL
High Z
Valid
Output
Valid
Output
R23
Valid
Output
Valid
Output
NOTE:
1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length,
from Main Blocks
36
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
CLK (C)
VIH
Note 1
VIL
A19-0 (A)
ADV# (V)
VIH
VIL
VIH
VIL
CE# (E)
VIH
VIL
OE# (G)
VIH
VIL
WE# (W)
VIH
R10
VIL
WAIT# (T)
R10
VOH
Note 2
VOL
R7
VOH
DQ15-0 (D/Q)
VOL
High
Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
NOTE:
1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about
the behavior of WAIT#.
2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further
information.
Figure 18. AC Waveform for Continuous Burst Read, Showing an Output Delay
with Data Output Configuration Set to One Clock
CLK (C)
VIH
Note 1
VIL
A19-0 (A)
ADV# (V)
VIH
VIL
VIH
VIL
CE# (E)
VIH
VIL
OE# (G)
VIH
VIL
WE# (W)
VIH
R10
VIL
WAIT# (T)
R10
VOH
VOL
Note 2
R7
VOH
DQ15-0 (D/Q)
VOL
Valid High Z
Output
Valid
Output
NOTE:
1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about
the behavior of WAIT#.
2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further
information.
Figure 19. AC Waveform for Continuous Burst Read, Showing an Output Delay
with Data Output Configuration Set to One Clock
PRODUCT PREVIEW
37
E
FAST BOOT BLOCK DATASHEET
8.6
AC Characteristics—Write Operations(1, 2)—Extended Temperature
Valid for All Speed and
Voltage Combinations
#
Sym
Parameter
Notes
Min
Max
Unit
600
µs
W1
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Going
Low
3
W2
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Going Low
6
0
ns
W3
tWP
Write Pulse Width
6
75
ns
W4
tVLVH
ADV# Pulse Width
10
ns
W5
tDVWH (tDVEH)
Data Setup to WE# (CE#) Going High
4
70
ns
W6
tAVWH (tAVEH)
Address Setup to WE# (CE#) Going High
4
75
ns
W7
tVLEH (tVLWH)
ADV# Setup to WE# (CE#) Going High
75
ns
W8
tAVVH
Address Setup to ADV# Going High
10
ns
W9
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
ns
W10
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
0
ns
W11
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
0
ns
W12
tVHAX
Address Hold from ADV# Going High
3
ns
W13
tWPH
Write Pulse Width High
7
20
ns
W14
tPHWH (tPHHEH)
WP# Setup to WE# (CE#) Going High
3
200
ns
W15
tVPWH (tVPEH)
VPP Setup to WE# (CE#) Going High
3
200
ns
W16
tWHGL (tEHGL)
Write Recovery before Read
0
ns
W17
tQVBH
WP# Hold from Valid SRD
3,5
0
ns
W18
tQVVL
VPP Hold from Valid SRD
3,5
0
ns
NOTES:
1. Read timing characteristics during block erase and program operations are the same as during read-only operations. Refer
to AC Characteristics —Read-Only Operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to Table 3 for valid AIN and DIN for block erase or program.
5. VPP should be held at VPPH1/2 until determination of block erase or program success.
6. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
7. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
38
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
Note 1
A20-0 (A)
Note 2
VIH
Note 3
Valid Address
Note 4
Note 5
Valid Address
VIL
W12
W11
W6
W8
ADV# (V)
VIH
VIL
W4
W7
CE# (WE#) [E(W)]
Note 6
VIH
VIL
W2
OE# [G]
W9
W16
VIH
VIL
W1
WE# (CE#) [W(E)]
W13
VIH
VIL
Note 6
W3
W5
W10
DATA [D/Q]
W19
VIH
Data In
Valid
SRD
Data In
VIL
RST# [P]
VIH
VIL
WP# [B]
W14
W17
W15
W18
VIH
VIL
VPPH1/2
VPP [V]
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or program setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operations, OE# and CE# must be driven active, and WE# de-asserted.
Figure 20. AC Waveform for Write Operations
PRODUCT PREVIEW
39
FAST BOOT BLOCK DATASHEET
8.7
AC Characteristics—Reset Operation—Extended Temperature
E
R20
RST# (R)
VIH
VIL
P1
(A) Reset while device is in read mode
Abort
Complete
P2
RST# (R)
R20
VIH
VIL
P1
(B) Reset during program or block erase, P1 ≤ P2
Abort
Complete
P2
R20
VIH
RST# (R)
VIL
P1
(C) Reset during program or block erase, P1 ≥ P2
Figure 21. AC Waveform for Reset Operation
Table 10. Reset Specifications
Notes
Min
P1
#
tPLPH
Symbol
RST# Low to Reset During Read
(If RST# is tied to VCC, this specification is not
applicable)
Parameter
2,4
100
P2
tPLRH
RST# Low to Reset during Block Erase or
Program
3,4
Max
Unit
ns
22
µs
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3. If RST# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
4. Sampled, but not 100% tested.
40
PRODUCT PREVIEW
E
8.8
FAST BOOT BLOCK DATASHEET
Extended Temperature Block Erase And Program Performance(3, 4, 5)
2.7 V VPP
#
W19
Sym
Parameter
12 V VPP
Notes
Typ(1)
Max
Typ(1)
Max
Unit
2
2
2
2
2
23.5
0.10
0.8
1
1.8
6
200
0.30
2.4
4
5
10
8
0.03
0.24
0.8
1.1
5
185
0.10
0.8
4
5
10
µs
sec
sec
sec
sec
µs
13
20
10
12
µs
tWHRH1, Program Time
tEHRH1 Block Program Time (Parameter)
Block Program Time (Main)
tWHRH2, Block Erase Time (Parameter)
tEHRH2 Block Erase Time (Main)
tWHRH5, Program Suspend Latency
tEHRH5
tWHRH6, Erase Suspend Time
tEHRH6
NOTES:
1. Typical values measured at TA = +25 °C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested.
5. Reference the AC Waveform for Write Operations Figure 20.
8.9
Automotive Temperature Operating Conditions
Except for the specifications given in this section, all DC and AC characteristics are identical to those listed in
the extended temperature specifications. See Section 7.2 for extended temperature specifications.
Symbol
Parameter
Notes
Min
Max
Unit
-40
+125
°C
3.0
3.6
V
TA
Operating Temperature
VCC1
VCC Supply Voltage
VCCQ1
I/O Voltage
1,2
3.0
3.6
V
VPPH1
VPP Supply Voltage
1
3.0
3.6
V
VPPH2
VPP Supply Voltage
1,3
11.4
12.6
V
Cycling
Parameter Block Erase Cycling
30,000
Cycles
Main Block Erase Cycling
1,000
Cycles
1
NOTES:
1. See DC Characteristics tables for voltage range-specific specifications.
2. The voltage swing on the inputs, VIN is required to match VCCQ.
3. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main and
parameter blocks. A hard connection to VPP = 11.4 V–12.6 V is not allowed and can cause damage to the device.
PRODUCT PREVIEW
41
E
FAST BOOT BLOCK DATASHEET
Capacitance(1)
8.10
TA = +25°C, f = 1 MHz
Sym
Parameter
Typ
Max
Unit
Condition
CIN
Input Capacitance
6
8
pF
VIN = 0.0 V
COUT
Output Capacitance
8
12
pF
VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
VCCQ
Test Points
VCCQ/2
Input
VCCQ/2
Output
0V
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 3.0 V.
Figure 22. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V
Test Configuration Component Value
for Worst Case Speed Conditions
VCCQ
Test Configuration
R1
Device
Under Test
3 V Standard Test
Out
CL
CL (pF)
R1 (Ω)
R2 (Ω)
80
25K
25K
NOTE:
CL includes jig capacitance.
R2
NOTE:
See table for component values.
Figure 23. Transient Equivalent Testing
Load Circuit
42
PRODUCT PREVIEW
E
8.11
Sym
FAST BOOT BLOCK DATASHEET
DC Characteristics(1) —Automotive Temperature
Parameter
Note
Typ
Max Unit
Test Condition
ICCS
VCC Standby Current
2,6
40
60
µA
VCC = VCC Max
VCCQ = VCCQ Max
CE# = RST# = VIH
ICCR
VCC Read Current
4,6
60
75
mA
Asynchronous
tAVAV = Min
60
75
mA
Synchronous
CE# = VIL
CLK = 22 MHz OE# = VIH
Burst length = 1
8
20
mA VPP = VPPH1 (3.0 V–3.6 V)
Program in progress
8
20
mA VPP = VPPH2 (11.4 V–12.6 V)
Program in progress
8
20
mA VPP = VPPH1 (3.0 V–3.6 V)
Block erase in progress
8
20
mA VPP = VPPH2 (11.4 V–12.6 V)
Block erase in progress
15
40
mA VPP = VPPH1 (3.0 V–3.6 V)
Program in progress
10
25
mA VPP = VPPH2 (11.4 V–12.6 V)
Program in progress
13
25
mA VPP = VPPH1 (3.0 V–3.6 V)
Block erase in progress
8
25
mA VPP = VPPH2 (11.4 V–12.6 V)
Block erase in progress
ICCW
ICCE
IPPW
IPPE
VCC Program Current
VCC Block Erase
Current
VPP Program Current
VPP Block Erase
Current
3,5,7
3,5,7
3,5,7
3,5,7
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VIH or VIL
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, T = +25 °C.
2. Erases and program operations are inhibited when VPP ≤ VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1
and VPPH2.
3. Sampled, not 100% tested.
4. Automatic Power Savings (APS) reduces ICCR to approximately standby levels, in static operation.
5. 12 V (11.4 V–12.6 V) can only be applied to VPP for a maximum of 80 hours over the lifetime of the device. VPP should not
be permanently tied to 12 V.
6. The specification is the sum of VCC and VCCQ currents.
PRODUCT PREVIEW
43
E
FAST BOOT BLOCK DATASHEET
8.12
AC Characteristics—Read-Only Operations(1) —Automotive Temperature
#
Sym
Parameter
Notes
Min
Max
Unit
R1
tCLK
CLK Period
15
ns
R2
tCH (tCL)
CLK High (Low) Time
2.5
ns
R3
tCHCL (tCLCH)
CLK Fall (Rise) Time
R4
tAVCH
Address Valid Setup to CLK
17
ns
R5
tVLCH
ADV# Low Setup to CLK
17
ns
R6
tELCH
CE# Low Setup to CLK
17
ns
R7
tCHQV
CLK to Output Delay
R8
tCHQX
Output Hold from CLK
R9
tCHAX
Address Hold from CLK
3
R10
tCHTL (tCHTH)
CLK to WAIT# delay
5
R11
tAVVH
Address Setup to ADV# Going High
19
ns
R12
tELVH
CE# Low to ADV# Going High
19
ns
R13
tAVQV
Address to Output Delay
R14
tELQV
CE# Low to Output Delay
R15
tVLQV
ADV# Low to Output Delay
R16
tVLVH
ADV# Pulse Width
R17
tVHVL
ADV# Pulse Width
R18
tVHAX
Address Hold from ADV# Going High
R19
tAPA
Page Address Access Time
35
ns
R20
tGLQV
OE# Low to Output Delay
50
ns
R21
tRHQV
RST# High to Output Delay
600
ns
R22
tEHQZ
tGHQZ
CE# or OE# High to Output in High Z,
Whichever Occurs First
4
40
ns
R23
tOH
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
4
5
30
ns
5
ns
10
ns
30
2
3
ns
ns
150
ns
150
ns
150
ns
19
ns
19
ns
3
ns
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. Output loading on WAIT# equals 15 pF.
44
PRODUCT PREVIEW
E
8.13
FAST BOOT BLOCK DATASHEET
Automotive Temperature Frequency Configuration Settings
Table 11. Frequency Configuration Settings for Automotive Temperature Components
Frequency Configuration Code
Input CLK Frequency
1
Reserved
2
≤ 22 MHz
3
≤ 33 MHz
4
≤ 40 MHz
5
≤ 50 MHz
6
≤ 66 MHz
8.14
Automotive Temperature Block Erase and Program Performance(3,4,5)
3.3 V VPP
#
W19
Sym
Parameter
tWHRH1, Program Time
tEHRH1 Block Program Time (Parameter)
Block Program Time (Main)
tWHRH2, Block Erase Time (Parameter)
tEHRH2 Block Erase Time (Main)
tWHRH5, Program Suspend Latency
tEHRH5
tWHRH6, Erase Suspend Time
tEHRH6
12 V VPP
Notes
Typ(1)
Max
Typ(1)
Max
Unit
2
2
2
2
2
23.5
0.10
0.8
1
1.8
6
TDB
TDB
TDB
TDB
TDB
TDB
8
0.03
0.24
0.8
1.1
5
TDB
TDB
TDB
TDB
TDB
TDB
µs
sec
sec
sec
sec
µs
13
TDB
10
TDB
µs
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested.
5. Reference the AC Waveform for Write Operations Figure 20.
PRODUCT PREVIEW
45
E
FAST BOOT BLOCK DATASHEET
9.0
ORDERING INFORMATION
DT 2 8 F 1 6 0 F 3 T 1 2 0
Package
DT = Extended temp.,
56-Lead SSOP
DE = Automotive temp.,
56-Lead SSOP
GT = Extended temp.,
56-Ball µBGA* CSP
Access Speed (ns)
(95,120,150)
Product line designator
for all Intel Flash products
T = Top Blocking
B = Bottom Blocking
Device Density
160 = x16 (16-Mbit)
800 = x16 (8-Mbit)
Product Family
F3 = Fast Boot Block
VCC = 2.7V - 3.6V
VPP = 2.7V - 3.6V or 11.4V - 12.6V
VALID COMBINATIONS
56-Lead SSOP
DT28F160F3T120
DT28F160F3B120
DT28F160F3T95
DT28F160F3B95
56-Ball µBGA CSP(1)
GT28F160F3T120
GT28F160F3B120
GT28F160F3T95
GT28F160F3B95
8M
DT28F800F3T120
DT28F800F3B120
DT28F800F3T95
DT28F800F3B95
GT28F800F3T120
GT28F800F3B120
GT28F800F3T95
GT28F800F3B95
8M
DE28F800B3T150
DE28F800B3B150
Extended
16M
Extended
Automotive
NOTE:
1.
The 56-Ball µBGA package top side mark reads F160F3 [or F800F3]. All product shipping boxes or trays provide the
correct information regarding bus architecture.
46
PRODUCT PREVIEW
E
FAST BOOT BLOCK DATASHEET
10.0 ADDITIONAL INFORMATION(1,2)
Order Number
Document/Tool
210830
Flash Memory Databook
292213
AP-655 Fast Boot Block Design Guide
Contact
Intel/Distribution
Sales Office
297846
See Intel’s
World Wide Web
Home Page
Fast Boot Block CPU Design Guide
Comprehensive User’s Guide for µBGA* Package
Micro Ball Grid Array Package Mechanical Specification and Media Information
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.
PRODUCT PREVIEW
47