CXK5T81000ATN/AYN -10LLX/12LLX
131072-word × 8-bit High Speed CMOS Static RAM
Preliminary
For the availability of this product, please contact the sales office.
Description
The CXK5T81000ATN/AYN is a high speed
CMOS static RAM organized as 131072-words by
8-bits.
Special feature are low power consumption and
high speed.
The CXK5T81000ATN/AYN is a suitable RAM for
portable equipment with battery back up.
Features
• Extended operating temperature range:
–25 to +85°C
• Wide supply voltage range operation: 2.7 to 3.6V
• Fast access time:
(Access time)
3.0V operation -10LLX
100ns (Max.)
-12LLX
120ns (Max.)
3.3V operation -10LLX
85ns (Max.)
-12LLX
100ns (Max.)
• Low standby current:
28µA (Max.)
• Low data retention current: 24µA (Max.)
• Low power data retention:
2.0V
(Min.)
• Package 8mm × 13.4mm 32 pin TSOP package
CXK5T81000ATN
32 pin TSOP (Plastic)
CXK5T81000AYN
32 pin TSOP (Plastic)
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
Buffer
A6
A5
A4
A3
A2
A1
A0
Buffer
Function
131072-word × 8-bit static RAM
Row
Decoder
Memory
Matrix
1024 × 1024
VCC
GND
I/O Gate
Column
Decoder
OE
Buffer
Structure
Silicon gate CMOS IC
WE
CE1
CE2
I/O Buffer
I/O1
I/O8
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96726-PS
CXK5T81000ATN/AYN
Pin Configuration (Top View)
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CE2
WE
A13
A8
A9
A11
Pin Description
1
32
2
31
3
30
4
29
5
28
6
7
27
26
CXK5T81000ATN
(Standard Pinout)
8
9
25
24
10
23
11
22
12
21
13
20
14
15
19
16
17
16
17
15
18
14
19
13
20
12
21
18
22
11
10
9
23
CXK5T81000AYN
(Mirror Image Pinout)
8
24
25
7
26
6
27
5
28
4
29
3
30
2
31
1
32
Absolute Maximum Ratings
Item
Symbol
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
Description
A0 to A16
Address input
I/O1 to I/O8
Data input output
CE1, CE2
Chip enable 1, 2 input
WE
Write enable input
OE
Output enable input
VCC
Power supply
GND
Ground
NC
No connection
(Ta = 25°C, GND = 0V)
Symbol
Rating
Unit
V
Supply voltage
VCC
Input voltage
VIN
–0.5 to +4.6
–0.5∗1 to VCC + 0.5
Input and output voltage
VI/O
–0.5∗1 to VCC + 0.5
V
Allowable power dissipation
PD
0.7
W
Operating temperature
Topr
–25 to +85
°C
Storage temperature
Tstg
–55 to +150
°C
Soldering temperature · time
Tsolder
235 · 10
°C · s
V
∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1 CE2
OE
WE
Mode
VCC Current
I/O pin
H
×
×
×
Not selected
High Z
ISB1, ISB2
×
L
×
×
Not selected
High Z
ISB1, ISB2
L
H
H
H
Output disable
High Z
ICC1, ICC2, ICC3
L
H
L
H
Read
Data out
ICC1, ICC2, ICC3
L
H
×
L
Write
Data in
ICC1, ICC2, ICC3
× : “H” or “L”
DC Recommended Operating Conditions
Item
Symbol
(Ta = –25 to +85°C, GND = 0V)
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
Min.
Typ.
Max.
Min.
Typ.
Max.
Supply voltage
VCC
2.7
3.3
3.6
3.0
3.3
3.6
Input high voltage
VIH
—
VCC + 0.3
VCC + 0.3
VIL
—
0.4
2.2
–0.3∗2
—
Input low voltage
2.4
–0.3∗2
—
0.6
∗2 VIL = –3.0V Min. for pulse width less than 50ns.
–2–
Unit
V
CXK5T81000ATN/AYN
Electrical Characteristics
• DC Characteristics
(VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C)
Item
Symbol
Test conditions
Min.
Typ.∗1
Max.
Unit
Input leakage current
ILI
VIN = GND to VCC
–1
—
+1
µA
Output leakage current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
–1
—
+1
µA
Operating power supply
current
ICC1
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
—
1
3
mA
ICC2
Min. cycle
duty = 100%
IOUT = 0mA
10LLX
—
25∗2
35∗3
12LLX
—
25
35
—
5
10
mA
ICC3
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤ 0.2V
CE2 ≥ Vcc – 0.2V
VIL ≤ 0.2V
VIH ≥ Vcc – 0.2V
—
—
28
ISB1
–25 to +85°C
CE2 ≤ 0.2V
CE1 ≥ Vcc – 0.2V –25 to +70°C
or
CE2 ≥ Vcc – 0.2V
+25°C
—
—
14
—
0.48
—
ISB2
CE1 = VIH or CE2 = VIL
—
0.12
1.4
mA
Output high voltage
VOH
IOH = –2.0mA
2.4
—
—
V
Output low voltage
VOL
IOL = 2.0mA
—
—
0.4
V
Average operating current
Standby current
{
∗1 VCC = 3.3V, Ta = 25°C
∗2 ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V)
∗3 ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V)
I/O capacitance
Item
(Ta = 25°C, f = 1MHz)
Symbol Test conditions
Min.
Typ.
Max.
Unit
Input capacitance
CIN
VIN = 0V
—
—
8
pF
I/O capacitance
CI/O
VI/O = 0V
—
—
10
pF
Note) This parameter is sampled and is not 100% tested.
–3–
mA
µA
CXK5T81000ATN/AYN
AC Characteristics
• AC test conditions
(Ta = –25 to +85°C)
Conditions
Item
VCC = 2.7 to 3.6V
Input pulse high level
VIH = 2.4V
VIH = 2.2V
Input pulse low level
VIL = 0.4V
VIL = 0.6V
Input rise time
tr = 5ns
tf = 5ns
tr = 5ns
tf = 5ns
Input fall time
Input and output reference level
Output load conditions
-10LLX
-12LLX
1.4V
1.4V
CL∗1 = 100pF, 1TTL CL∗1 = 30pF, 1TTL
CL∗1 = 100pF, 1TTL CL∗1 = 100pF, 1TTL
∗1 CL includes scope and jig capacitances.
–4–
• Test circuit
VCC = 3.3V ± 0.3V
TTL
CL
CXK5T81000ATN/AYN
• Read cycle (WE = “H”)
VCC = 2.7 to 3.6V
Item
Read cycle time
Address access time
Chip enable access time (CE1)
Chip enable access time (CE2)
Output enable to output valid
Output hold from address change
Chip enable to output in low Z
(CE1, CE2)
Output enable to output in low Z (OE)
Chip disable to output in high Z
(CE1, CE2)
Output disable to output in high Z (OE)
Symbol
tRC
tAA
tCO1
tCO2
tOE
tOH
tLZ1
tLZ2
tOLZ
tHZ1∗1
tHZ2∗1
tOHZ∗1
-10LLX
VCC = 3.3V ± 0.3V
-12LLX
-10LLX
Min.
Max.
Min.
Max.
100
—
120
—
85
—
100
—
120
—
100
—
—
100
—
Min. Max.
-12LLX
Unit
Min.
Max.
—
100
—
ns
—
85
—
100
ns
120
—
85
—
100
ns
—
120
—
85
—
100
ns
50
—
60
—
40
—
50
ns
10
—
10
—
10
—
10
—
ns
10
—
10
—
10
—
10
—
ns
5
—
5
—
5
—
5
—
ns
—
40
—
40
—
35
—
40
ns
—
35
—
35
—
30
—
35
ns
∗1 tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
VCC = 2.7 to 3.6V
Item
Symbol
-10LLX
Min.
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
100
tWC
80
tAW
80
tCW
40
tDW
0
tDH
70
tWP
0
tAS
0
tWR
0
tWR1
5
tOW
tWHZ∗2 —
VCC = 3.3V ± 0.3V
-12LLX
-10LLX
Max.
Min.
Max.
—
120
—
85
—
100
—
—
100
—
Min. Max.
-12LLX
Unit
Min.
Max.
—
100
—
ns
70
—
80
—
ns
—
70
—
80
—
ns
50
—
35
—
40
—
ns
—
0
—
0
—
0
—
ns
—
70
—
60
—
70
—
ns
—
0
—
0
—
0
—
ns
—
0
—
0
—
0
—
ns
—
0
—
0
—
0
—
ns
—
5
—
5
—
5
—
ns
40
—
40
—
35
—
40
ns
∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
CXK5T81000ATN/AYN
Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
tRC
Address
tAA
tOH
Data out
Previous data valid
Data valid
• Read cycle (2) : WE = VIH
tRC
Address
tAA
CE1
tCO1
ttHZ1
HZ
tLZ1
CE2
tCO2
tLZ2
tHZ2
OE
tOE
tOHZ
tOLZ
Data out
Data valid
High impedance
–6–
CXK5T81000ATN/AYN
• Write cycle (1) : WE control
tWC
Address
tWR
tAW
OE
tCW
CE1
tCW
CE2
(∗1)
tWP
tAS
WE
tDW
tDH
Data valid
Data in
tWHZ
tOW
Data out
High impedance
(∗2)
(∗ 2 )
• Write cycle (2) : CE1 control
tWC
Address
tAW
OE
tAS
tCW
tWR1
CE1
tCW
CE2
tWP
WE
tDW
Data valid
Data in
Data out
High impedance
–7–
tDH
(∗3)
CXK5T81000ATN/AYN
• Write cycle (3) : CE2 control
tWC
Address
tAW
OE
tCW
CE1
tCW
tAS
tWR1
(∗3)
CE2
tWP
WE
tDW
tDH
Data valid
Data in
Data out
High impedance
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until
the end of the write cycle.
–8–
CXK5T81000ATN/AYN
Data retention waveform
• Low supply voltage data retention waveform (1) (CE1 contol)
tCDRS
Data retention mode
tR
VCC
2.7V
VIH
VDR
CE1
CE1 ≥ VCC – 0.2V
GND
• Low supply voltage data retention waveform (2) (CE2 contol)
Data retention mode
VCC
2.7V
tCDRS
tR
CE2
VDR
VIL
CE2 ≤ 0.2V
GND
Data Retention Characteristics
Item
Data retention voltage
Data retention current
Symbol
VDR
ICCDR1
ICCDR2
Data retention setup time tCDRS
Recovery time
(Ta = –25 to +85°C)
Test conditions
Min.
Typ.
Max.
Unit
2.0
—
3.6
V
–25 to +85°C
—
—
24
–25 to +70°C
—
—
12
+25°C
—
—
28
µA
∗1
VCC = 3.0V∗1
µA
VCC = 2.0 to 3.6V∗1
—
0.4
0.48∗2
Chip disable to data retention mode
0
—
—
ns
5
—
—
ns
tR
∗1 CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)
∗2 VCC = 3.3V, Ta = 25°C
–9–
CXK5T81000ATN/AYN
Package Outline
Unit: mm
CXK5T81000ATN
32PIN TSOP (PLASTIC)
∗8.0 ± 0.1
1.2 MAX
32
0.1
13.4 ± 0.3
∗11.8 ± 0.1
17
A
1
16
0.145
0.2
0.5
+ 0.1
0.05 – 0.05
0.5
0.08 M
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TSOP-32P-L02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP032-P-0813.4-C
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
CXK5T81000AYN
32PIN TSOP (PLASTIC)
∗8.0 ± 0.1
1.2 MAX
0.1
∗11.8 ± 0.1
13.4 ± 0.3
32
17
A
16
1
0.145
0.08 M
0.5
+ 0.1
0.05 – 0.05
0.5
0.2
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TSOP-32P-L02R
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP032-P-0813.4-D
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 10 –