TI1 DP8238M System controller and bus driver Datasheet

DP8228,DP8228M,DP8238,DP8238M
DP8228/DP8228M/DP8238/DP8238M System Controller and Bus Driver
Literature Number: SNOSBP9A
DP8228/DP8228M/DP8238/DP8238M
System Controller and Bus Driver
General Description
when an interrupt is acknowledged by the 8080A. This feature permits the use of a multilevel priority interrupt structure
in large, interrupt-driven systems.
Features
Y
Y
Y
Y
Single chip system controller and bus driver for 8080A
Microcomputer Systems
Allows use of multibyte CALL instructions for Interrupt
Acknowledge
Provides user-selected single-level interrupt vector
(RST 7)
Provides isolation of data bus
Supports a wide variety of system bus structures
Reduces system component count
DP8238/DP8238M provides advanced Input/Output
Write and Memory Write control signals for large system timing control
et
e
The DP8228/DP8228M, DP8238/DP8238M are system
controller/bus drivers contained in a standard, 28-pin dualin-line package. The chip, which is fabricated using Schottky
Bipolar technology, generates all the read and write control
signals required to directly interface the memory and input/
output components of the 8080A microcomputer family. The
chip also provides drive and isolation for the bidirectional
data bus of the 8080A microprocessor. Data bus isolation
enables the use of slower memory and input/output components in a system, and provides for enhanced system noise
immunity.
A user-selected signal-level interrupt vector (RST 7) is provided by the device for use in the interrupt structure of small
systems that need only one basic vector. No additional
components (such as an interrupt instruction port) are required to use the single interrupt vector in these systems.
The devices also generate an Interrupt Acknowledge (INTA)
control signal for each byte of a multibyte CALL instruction
Y
Y
Y
O
bs
ol
8080A Microcomputer Family Block Diagram
TL/F/6825 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/6825
RRD-B30M105/Printed in U. S. A.
DP8228/DP8228M/DP8238/DP8238M System Controller and Bus Driver
December 1988
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Min
Max
Units
Supply Voltage (VCC)
DP8228M, DP8238M
4.50
5.50
VDC
DP8228, DP8238
4.75
5.25
VDC
Operating Temperature (TA)
b 55
a 125
DP8228M, DP8238M
§C
a 70
DP8228, DP8238
0
§C
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be limited to those conditions
specified under DC electrical characteristics.
Storage Temperature
b 65§ C to a 150§ C
Supply Voltage, VCC
Input Voltage
Output Current
Maximum Power Dissipation* at 25§ C
Cavity Package
Molded Package
b 0.5 to a 7V
b 1.5V to a 7V
100 mA
2179 mW
2361 mW
*Derate cavity package 14.5 mW/§ C above 25§ C; derate molded package
18.9 mW/§ C above 25§ C.
Electrical Characteristics Min s TA s Max, Min s VCC s Max, unless otherwise noted
Symbol
IF
Conditions
Input Clamp Voltage, All Inputs
VCC e Min, IC e b5 mA
Input Load
Current
VCC e Max
VF e 0.45V for DP8228, DP8238
VF e 0.40V for DP8228M, DP8238M
STSTB
D2 and D6
D0, D1, D4,
D5 and D7
All Other
Inputs
Input Leakage
Current
DB0–DB7
Input Threshold Voltage,
All Inputs
ICC
Power Supply Current
VCC e Max
IO (OFF)
IINT
b 1.0
V
500
mA
750
mA
250
mA
250
mA
20
mA
100
mA
2.0
V
DP8228, DP8238
185
230
mA
DP8228M, DP8238M
160
230
mA
DP8228M, DP8238M
0.50
V
DP8228, DP8238
0.45
V
All Other
Outputs
VCC e Min,
IOL e 10 mA
DP8228M, DP8238M
0.50
V
DP8228, DP8238
0.45
V
D0–D7
VC e Min,
IOL e b10 mA
DP8228M, DP8238M
3.3
3.8
V
DP8228, DP8238
3.6
3.8
V
VCC e Min, IOH e b1 mA
2.4
3.8
V
Short Circuit Current, All Outputs
VCC e 5V, VO e 0V
15
OFF State Output Current
All Control Outputs
VCC e Max, VO e VCC
All Other
Outputs
IOS
0.6
VCC e Min,
IOL e 2 mA
Output High
D0–D7
Units
0.8
bs
VOH
Output Low
Voltage
VCC e 5V
O
VOL
Max
VCC e Max, VR e VCC
All Other
Inputs
VTH
Typ
(Note 1)
ol
IR
Min
et
e
VC
Parameter
INTA Current
VCC e Max, VO e 0.45V
(See Test Conditions, Figure 3 )
Note 1: Typical values are for TA e 25§ C and typical supply voltages.
2
90
mA
100
mA
b 100
mA
5
mA
Capacitance* VBIAS e 2.5V, VCC e 5.0V, TA e 25§ C, f e 1 MHz
Symbol
Parameter
Min
Typ
(Note 1)
Max
Units
CIN
Input Capacitance
8
12
pF
COUT
Output Capacitance Control Signals
7
15
pF
I/O
I/O Capacitance (D or DB)
8
15
pF
*This parameter is periodically sampled and not 100% tested.
Switching Characteristics Min s VCC s Max, Min s TA s Max
Symbol
Parameter
DP8228M,
DP8238M
Conditions
Min
DP8228,
DP8238
Max
25
Min
Units
Max
tPW
Width of Status Strobe
tSS
Set-Up Time, Status Inputs D0–D7
8
8
ns
tSH
Hold Time, Status Inuts D0–D7
5
5
ns
tDC
Delay from STSTB to Any Control Signal
tRR
Delay from DBIN to Control Outputs
tRE
Delay from DBIN to Enable/
Disable 8080 Bus
tRD
Delay from System Bus to 8080
Bus During Read
tWR
Delay from WR to Control Outputs
tWE
Delay to Enable System Bus
DB0–DB7 after STSTB
tWD
Delay from 8080 Bus D0–D7 to
System Bus DB0–DB7 During Write
tE
Delay from System Bus Enable to
System Bus DB0–DB7
(Figure 2)
tHD
HLDA to Read Status Outputs
(Figure 2)
tDS
Set-Up Time, System Bus Inputs to HLDA
10
10
ns
tDH
Hold Time, System Bus Inputs to HLDA
20
20
ns
(Figure 2)
75
20
ns
60
ns
et
e
20
22
(Figure 2)
(Figure 1)
(Figure 1)
(Figure 2)
5
(Figure 2)
30
30
ns
45
45
ns
45
30
ns
45
ns
30
ns
40
ns
30
ns
25
ns
60
5
30
ol
(Figure 2)
5
40
5
30
bs
25
O
Test Conditions
TL/F/6825 – 3
TL/F/6825–2
FIGURE 1. Test Load
FIGURE 2. Test Load
3
TL/F/6825 – 4
FIGURE 3. INTA Test Circuit
(For RST 7)
et
e
Timing Diagram
TL/F/6825 – 5
VOLTAGE MEASUREMENT POINTS: D0 –D7 (when outputs) Logic ‘‘0’’ e 0.8V, Logic ‘‘0’’ e 0.8V, Logic ‘‘1’’ e 3.0V. All other signals measured at 1.5V.
*Advanced I/OW MEMW for 8238 only.
Functional Pin Definitions
The following describes the function of all of the DP8228/
DP8228M, DP8238/DP8238M pinouts. Some of these descriptions reference internal circuits.
ol
OUTPUT SIGNALS
Memory Read (MEMR): When low, signals data to be loaded in from memory. The MEMR signal is generated by strobing in status word 1, 2, or 4. (Refer to status word chart.)
Memory Write (MEMW): When low, signals data to be
stored in memory. The MEMW signal is generated for the
DP8238 by strobing in status word 3 or 5. (Refer to status
word chart.) For the DP8228, the MEMW signal is generated
by gating a low-level WR input with the strobed in status
word 3 or 5.
Input/Output Read (I/OR): When low, signals data to be
loaded in from an addressed input/output device. The I/OR
signal is generated by strobing in status word 6.
Input/Output Write (I/OW): When low, signals data to be
transferred to an addressed input/output device. The I/OW
signal for the DP8238 is generated by strobing in status
word 7. For the DP8238 the I/OW signal is generated by
gating in a low-level WR input with the strobed in status
word 7.
Interrupt Acknowledge (INTA): When low, indicates that
an interrupt has been acknowledged by the 8080A microprocessor. The INTA signal is generated by strobing in
staus word 8 or 10.
Signal Level Interrupt (RST 7): When the INTA output is
tied to 12V through a 1 kX resistor, strobing in status word 8
or 10 will cause the CPU data bus outputs, when active, to
go to the high state.
O
bs
INPUT SIGNALS
Status Strobe (STSTB): Activated (low) at the start of each
new machine cycle. The STSTB input is used to store a
status word (refer to chart) from the 8080A microprocessor
into the internal status latch of the DP8228, DP8238. The
status word is latched when the STSTB returns to the high
state. The 8080A outputs this status word onto its data bus
during the first state (SYNC interval) of each machine cycle.
Data Bus In (DBIN): When high, indicates that the 8080A
data bus is in the input mode. The DBIN signal is used to
gate data from memory or an input/output device onto the
data bus.
Write (WR): When low, indicates that the data on the
8080A data bus are stable for WRITE memory or output
operation.
Hold Acknowledge (HLDA): When high, indicates that the
8080A data and address buses will go to their high impedance state. When in the data bus read mode, DBIN input in
the high state, a high HLDA input will latch the data bus
information into the driver circuits and gate off the applicable control signal I/OR, MEMR, or INTA (return to the output high state).
Bus Enable (BUSEN): Asynchronous DMA input to the internal gating array. When low, normal operation of the internal bidirectional bus driver and gating array occurs. When
high, the bus driver and gating array are driven to their high
impedance state.
VCC Supply: a 5V.
INPUT/OUTPUT SIGNALS
CPU Data (D7 –D0) Bus: This bus comprises eight
TRI-STATEÉ input/output lines that connect to the 8080A
microprocessor. The bus provides bidirectional communica-
Ground: 0V reference.
4
Functional Pin Definitions (Continued)
System Data (DB7 –DB0) Bus: This bus comprises eight
TRI-STATE input/output lines that connect to the memory
and input/output components of the system. The internal
bidirectional bus driver isolates the DB7 –DB0 Data Bus from
the D7 –D0 Data Bus.
tion between the CPU, memory, and input/output devices
for instructions and data transfers. A status word (which describes the current machine cycle) is also outputted on this
data bus during the first microcycle of each machine cycle
(SYNC e logic 1).
Status Word Chart
Instruction Fetch
Memory Read
Memory Write
Stack Read
Stack Write
Input Read
Output Write
Interrupt Acknowledge
Halt Acknowledge
Interrupt Acknowledge While Halt
1
2
3
4
5
6
7
8
9
10
Data Bus Bit
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
Block and Connection Diagrams
Control
Signal
MEMR
MEMR
MEMW
MEMR
MEMW
I/OR
I/OW
INTA
(none)
INTA
et
e
Machine Cycle
Status
Word
O
bs
ol
Dual-In-Line Package
TL/F/6825 – 7
TL/F/6825 – 6
5
Order Number DP8228J, DP8228MJ,
DP8228N, DP8238J, DP8238MJ or
DP8238N
See NS Package Number J28A or N28B
bs
ol
et
e
Ceramic Dual-In-Line Package (J)
Order Number DP8228J, DP8228MJ, DP8238J or DP8238MJ
NS Package Number J28A
Molded Dual-In-Line Package (N)
Order Number DP8228N or DP8238N
NS Package Number N28B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
O
DP8228/DP8228M/DP8238/DP8238M System Controller and Bus Driver
Physical Dimensions inches (millimeters)
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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