1. Features • 80C52 Compatible • • • • • • • • • • • • • • • • • – 8051 pin and instruction compatible – Four 8-bit I/O ports – Three 16-bit timer/counters – 256 bytes scratchpad RAM High-Speed Architecture – 40 MHz @ 5V, 30MHz @ 3V – X2 Speed Improvement capability (6 clocks/machine cycle) – 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to – 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes) On-chip eXpanded RAM (XRAM) (256 or 768 bytes) Programmable Clock Out and Up/Down Timer/Counter 2 Programmable Counter Array with – High Speed Output, – Compare / Capture, – Pulse Width Modulator, – Watchdog Timer Capabilities Hardware Watchdog Timer (One-time enabled with Reset-Out) 2 extra 8-bit I/O ports available on RD2 with high pin count packages Asynchronous port reset Interrupt Structure with – 7 Interrupt sources, – 4 level priority interrupt system Full duplex Enhanced UART – Framing error detection – Automatic address recognition Low EMI (inhibit ALE) Power Control modes – Idle mode – Power-down mode – Power-off Flag Once mode (On-chip Emulation) Power supply: 4.5-5V, 2.7-5.5V Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4 2. Description Atmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. High Performance 8-bit Microcontroller TS80C51RA2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 AT80C51RA2 AT83C51RB2 AT83C51RC2 AT83C51RD2 AT87C51RB2 AT87C51RC2 The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that Rev. 4188F–8051–01/08 facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism. The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 VQFP44 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) I/O TS80C51RA2 0 0 256 512 32 TS80C51RD2 0 0 768 1024 32 TS83C51RB2 16k 0 256 512 32 TS83C51RC2 32k 0 256 512 32 TS83C51RD2 64k 0 768 1024 32 TS87C51RB2 0 16k 256 512 32 TS87C51RC2 0 32k 256 512 32 TS87C51RD2 0 64k 768 1024 32 VQFP64 1.4 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RD2 0 0 768 1024 48 TS83C51RD2 64k 0 768 1024 48 TS87C51RD2 0 64k 768 1024 48 PLCC68 2 TOTAL RAM (bytes) AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 (3) (3) (1) XTAL1 EUART XTAL2 ALE/ PROG RAM 256x8 C51 CORE PSEN ROM XRAM /EPROM 0/16/32/64Kx8 256/768x8 (1) (1) PCA T2 T2EX PCA ECI Vss Vcc TxD RxD 3. Block Diagram (1) Timer2 IB-bus CPU EA/VPP Parallel I/O Ports & Ext. Bus Watch Dog P5 P4 P3 P2 P1 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 (2) (2) P0 (3) (3) INT1 (3) (3) T1 (3) INT Ctrl INT0 Timer 0 Timer 1 RESET WR (3) T0 RD (1): Alternate function of Port 1 (2): Only available on high pin count packages (3): Alternate function of Port 3 3 4188F–8051–01/08 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3, P4, P5 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • Power and clock control registers: PCON • HDW Watchdog Timer Reset: WDTRST, WDTPRG • PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi • Interrupt system registers: IE, IP, IPH • Others: AUXR, CKCON 4 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 4-1. Bit addressable Non Bit addressable 0/8 1/9 2/A 3/B 4/C 5/D 6/E CH CCAP0H CCAP1H CCAPL2H CCAPL3H CCAPL4H 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX F8h F0h E8h D8h P5 bit addressable A0h 98h 90h 88h 80h CCAP0L CCAP1L CCAPL2L CCAPL3L CCAPL4L 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX EFh E7h CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 00XX X000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 T2CON 0000 0000 A8h CL 00X0 0000 C8h B0h F7h CCON PSW 0000 0000 B8h FFh ACC 0000 0000 D0h C0h 7/F B 0000 0000 1111 1111 E0h All SFRs with their address and their reset value DFh D7h T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CFh P4 bit addressable P5 byte addressable 1111 1111 1111 1111 IP SADEN X000 000 0000 0000 BFh P3 IPH X000 0000 1111 1111 IE SADDR 0000 0000 0000 0000 AUXR1 WDTRST WDTPRG 1111 1111 XXXX0XX0 XXXX XXXX XXXX X000 SCON SBUF XXXX XXXX B7h AFh P2 0000 0000 C7h A7h 9Fh P1 97h 1111 1111 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B AUXR XXXXXX00 CKCON XXXX XXX0 PCON 00X1 0000 4/C 5/D 6/E 8Fh 87h 7/F reserved 5 4188F–8051–01/08 VCC P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 P0.4 / A4 P0.5 / A5 P0.6 / A6 P0.7 / A7 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 6 5 4 3 2 1 44 43 42 41 40 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 PLCC/CQPJ 44 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 18 19 20 21 22 23 24 25 26 27 28 P2.2/A10 P2.3/A11 P2.4/A12 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 VSS1/NIC* VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 1 2 3 4 5 6 7 8 9 10 PDIL/ 11 12 CDIL40 13 P3.4/T0 14 P3.5/T1 15 P3.6/WR 16 P3.7/RD 17 XTAL2 18 XTAL1 19 VSS 20 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P1.0 / T2 P1.1 / T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 VSS1/NIC* VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 5. Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 VQFP44 1.4 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 12 13 14 15 16 17 18 19 20 21 22 *NIC: No Internal Connection 6 AT/TS8xC51Rx2 4188F–8051–01/08 P2.5/A13 P5.1 P2.6/A14 P5.2 P2.7/A15 PSEN NIC NIC ALE/PROG EA/VPP NIC P0.7/AD7 P0.6/AD6 P0.5/AD5 P5.3 P0.4/AD4 P5.4 AT/TS8xC51Rx2 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 P5.5 10 60 P5.0 P0.3/AD3 11 59 P2.4/A12 P0.2/AD2 12 58 P2.3/A11 P5.6 13 57 P4.7 P0.1/AD1 14 56 P2.2/A10 P0.0/AD0 15 55 P2.1/A9 P5.7 16 54 VCC 17 53 P2.0/A8 P4.6 52 NIC PLCC 68 P3.7/RD P4.1 24 46 P4.4 P1.4 25 45 P3.6/WR P4.2 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P3.5/T1 P4.3 P0.4/AD4 P5.4 P5.3 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC ALE/PROG PSEN P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 P5.0 P3.4/T0 47 P3.1/TxD 23 P3.2/INT0 P3.3/INT1 XTAL2 P1.3 NIC XTAL1 48 NIC 49 22 NIC 21 P1.2 NIC P1.1/T2EX P3.0/RxD P4.5 NIC 50 NIC 20 NIC VSS P4.0 RST 51 P1.7 19 P1.6 18 P1.5 NIC P1.0/T2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VQFP64 1.4 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3 P4.2 P1.5 P1.6 P1.7 RST NIC NIC NIC P3.0/RxD NIC NIC P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 NIC: No InternalConnection 7 4188F–8051–01/08 Pin Number Mnemonic DIL LCC VQFP 1.4 Type Name And Function 20 22 16 I Ground: 0V reference 1 39 I Optional Ground: Contact the Sales Office for ground connection. 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. P1.0-P1.7 1-8 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. VSS Vss1 VCC Alternate functions for Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock for the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 45 I/O CEX0 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 46 I/O CEX0 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 47 I/O CEX0 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during EPROM programming and verification: P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5) receive the high order address bits during EPROM programming and verification. Port 3 also serves the special features of the 80C51 family, as listed below. 8 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Pin Number Mnemonic DIL LCC VQFP 1.4 Type 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I XTAL2 18 20 14 O 5.1 Name And Function Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Pin Description for 64/68 pin Packages Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs. As inputs, pins that are externally pulled low will source current because of the internal pull-ups. Refer to the previous pin description for other pins. Table 5-1. 64/68 Pin Packages Configuration Pin PLCC68 SQUARE VQFP64 1.4 VSS 51 9/40 VCC 17 8 9 4188F–8051–01/08 P0.0 15 6 P0.1 14 5 P0.2 12 3 P0.3 11 2 P0.4 9 64 P0.5 6 61 P0.6 5 60 P0.7 3 59 P1.0 19 10 P1.1 21 12 P1.2 22 13 P1.3 23 14 P1.4 25 16 P1.5 27 18 P1.6 28 19 P1.7 29 20 P2.0 54 43 P2.1 55 44 P2.2 56 45 P2.3 58 47 P2.4 59 48 P2.5 61 50 P2.6 64 53 P2.7 65 54 P3.0 34 25 P3.1 39 28 PLCC68 SQUARE VQFP64 1.4 P3.2 40 29 P3.3 41 30 P3.4 42 31 P3.5 43 32 P3.6 45 34 P3.7 47 36 RESET 30 21 ALE/PROG 68 56 Pin 10 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 PSEN 67 55 EA/VPP 2 58 XTAL1 49 38 XTAL2 48 37 P4.0 20 11 P4.1 24 15 P4.2 26 17 P4.3 44 33 P4.4 46 35 P4.5 50 39 P4.6 53 42 P4.7 57 46 P5.0 60 49 P5.1 62 51 P5.2 63 52 P5.3 7 62 P5.4 8 63 P5.5 10 1 P5.6 13 4 P5.7 16 7 11 4188F–8051–01/08 5.2 TS80C51Rx2 Enhanced Features In comparison to the original 80C52, the TS8xC51Rx2 implements some new features, which are: • The X2 option. • The Dual Data Pointer. • The extended RAM. • The Programmable Counter Array (PCA). • The Watchdog. • The 4 level interrupt priority system. • The power-off flag. • The ONCE mode. • The ALE disabling. • Some enhanced features are also located in the UART and the timer 2. 5.3 X2 Feature The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Saves power consumption while keeping same CPU power (oscillator power saving). • Saves power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 5.3.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5-1 shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 5-2 shows the mode switching waveforms. 12 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 5-1. Clock Generation Diagram 2 XTAL1 XTAL1:2 state machine: 6 clock cycles. CPU control 0 1 FXTAL FOSC X2 CKCON reg Figure 5-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON register (Table 5-2) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). Note: In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. Table 5-2. CKCON Register CKCON - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. Description 13 4188F–8051–01/08 Bit Number Bit Mnemonic 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 Description CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL). Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel.com) 14 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 5.4 Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (Table 5-3) that allows the program code to switch between them (Refer to Figure 5-3). Figure 5-3. Use of Dual Pointer External Data Memory 7 0 DPS DPTR1 AUXR1(A2H) DPTR0 DPH(83H) DPL(82H) Table 5-3. AUXR1: Auxiliary Register 1 AUXR1 Address 0A2H Reset value Symbol - - - GF3 - - DPS X X X X 0 X X 0 Function Not implemented, reserved for future use (1) DPS GF3 1. - Data Pointer Selection. DPS Operating Mode 0 DPTR0 Selected 1 DPTR1 Selected This bit is a general purpose user flag(2). User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. GF3 will not be available on first version of the RC devices. 15 4188F–8051–01/08 6. Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 16 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 6.1 Expanded RAM (XRAM) The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data space. The TS80C51Rx2 has internal data memory that is mapped into four separate segments. The four segments are: • 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. • 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. • 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. • 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register. (See Table 6-1.) The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0H (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). • The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 or 768 bytes of external data memory. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 6-1. For RD devices, accesses to expanded RAM from 100H to 2FFH can only be done thanks to the use of DPTR. • With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the highorder eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight 17 4188F–8051–01/08 address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. Figure 6-1. Internal and External Data Memory Address FF(RA, RB, RC)/2FF (RD) FF FF Upper 128 bytes Internal Ram indirect accesses 80 XRAM FFFF Special Function Register direct accesses External Data Memory 80 256 bytes Lower 128 bytes Internal Ram direct or indirect accesses 00 00 Table 6-1. Auxiliary Register AUXR Address 08EH Reset value Symbol AO - - - - - - EXTRAM AO X X X X X X 0 0 Function Disable/Enable ALE AO EXTRAM Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 ALE is active only during a MOVX or MOVC instruction Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM 18 AUXR Not implemented, reserved for future use. (1) - 1. 0100 (RA, RB, RC) or 0300 (RD) 0000 Operating Mode 0 Internal XRAM access using MOVX @ Ri/ @ DPTR 1 External data memory access User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 6.2 Timer 2 The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 6-2) and T2MOD register (See Table 6-3). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel 8-bit Microcontroller Hardware description. Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In TS80C51RX2 Timer 2 includes the following enhancements: • Auto-reload mode with up or down counter • Programmable clock-output 6.2.1 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 6-2. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution. 19 4188F–8051–01/08 Figure 6-2. Auto-reload Mode Up/Down Counter (DCEN = 1) (:6 in X2 mode) :12 XTAL1 FXTAL FOSC 0 1 T2 TR2 C/T2 T2CONreg T2CONreg T2EX: (DOWN COUNTING RELOAD VALUE) FFh FFh (8-bit) (8-bit) if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting T2CONreg TOGGLE EXF2 TL2 (8-bit) RCAP2L (8-bit) TH2 (8-bit) TF2 T2CONreg TIMER 2 INTERRUPT RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) 6.2.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6-3) . The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F osc Clock – OutFrequency = ----------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L ) For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: • Set T2OE bit in T2MOD register. • Clear C/T2 bit in T2CON register. • Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. 20 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 6-3. Clock-Out Mode C/T2 = 0 XTAL1 :2 (:1 in X2 mode) TR2 T2CON reg TH2 (8-bit) TL2 (8-bit) OVERFLOW RCAP2H (8-bit) RCAP2L (8-bit) Toggle T2 Q D T2OE T2MOD reg T2EX TIMER 2 INTERRUPT EXF2 EXEN2 T2CON reg Table 6-2. T2CON reg T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# 21 4188F–8051–01/08 Bit Number Bit Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) 5 RCLK Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 EXEN2 2 TR2 1 0 Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. C/T2# Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. CP/RL2# Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable Table 6-3. 22 T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 T2OE Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. 0 DCEN Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Description Reset Value = XXXX XX00b Not bit addressable 23 4188F–8051–01/08 6.3 Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any one of the following signals: • Oscillator frequency ÷ 12 (÷ 6 in X2 mode) • Oscillator frequency ÷ 4 (÷ 2 in X2 mode) • Timer 0 overflow • External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: • rising and/or falling edge capture, • software timer, • high-speed output, or • pulse width modulator. Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 33). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4 The PCA timer is a common time base for all five modules (See Figure 6-4). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 6-4) and can be programmed to run at: • 1/12 the oscillator frequency. (Or 1/6 in X2 Mode) • 1/4 the oscillator frequency. (Or 1/2 in X2 Mode) • The Timer 0 overflow • The input on the ECI pin (P1.2) 24 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-4. PCA Timer/Counter To PCA modules Fosc /12 Fosc / 4 CH T0 OVF overflow CL It 16 bit up/down counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 CCF2 CCF1 CCF0 CCON 0xD8 Idle Table 6-4. CCF4 CCF3 CMOD: PCA Counter Mode Register CMOD Address 0D9H Reset value Symbol CIDL WDTE - - - CPS1 CPS0 ECF 0 0 X X X 0 0 0 Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use. (1) CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. ECF Selected PCA input. (2) CPS1 CPS0 0 0 Internal clock fosc/12 ( Or fosc/6 in X2 Mode). 0 1 Internal clock fosc/4 ( Or fosc/2 in X2 Mode). 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = fosc/ 8) PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. 1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 2. fosc = oscillator frequency The CMOD SFR includes three additional bits associated with the PCA (See Figure 6-4 and Table 6-4). 25 4188F–8051–01/08 • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4. • The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 6-5). • Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 6-5. CCON: PCA Counter Control Register CCON Address 0D8H Reset value Symbol CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 0 0 X 0 0 0 0 0 Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use. (1) CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. The watchdog timer function is implemented in module 4 (See Figure 6-7). The PCA interrupt system is shown in Figure 6-5. 26 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 PCA Interrupt System Figure 6-5. CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt priority decoder Module 2 Module 3 Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IE.6 EC IE.7 EA PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered, • 16-bit Capture, negative-edge triggered, • 16-bit Capture, both positive and negative-edge triggered, • 16-bit Software Timer, • 16-bit High Speed Output, • 8-bit Pulse Width Modulator. In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 6-6). The registers contain the bits that control the mode that each module will operate in. • The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. • PWM (CCAPMn.1) enables the pulse width modulation mode. • The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. • The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. • The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. 27 4188F–8051–01/08 • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 6-7 shows the CCAPMn settings for the various PCA functions. . CCAPMn: PCA Modules Compare/Capture Control Registers Table 6-6. CCAPMn Address n=0-4 CCAPM0=0DAH CCAPM1=0DBH CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH Reset value Symbol X 0 CAPNn MATn TOGn PWMm ECCFn 0 0 0 0 0 0 Function - Not implemented, reserved for future use. (1) ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. MATn Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 1. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. PCA Module Modes (CCAPMn Registers) Table 6-7. 28 ECOMn CAPPn ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer / Compare mode. 1 0 0 1 1 0 X 16-bit High Speed Output 1 0 0 0 0 1 0 8-bit PWM 1 0 0 1 X 0 X Watchdog Timer (module 4 only) AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 6-8 & Table 6-9) Table 6-8. CCAPnH: PCA Modules Capture/Compare Registers High CCAPnH Address n=0-4 CCAP0H=0FAH CCAP1H=0FBH CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH Reset value Table 6-9. 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 CCAPnL: PCA Modules Capture/Compare Registers Low CCAPnL Address n=0-4 CCAP0L=0EAH CCAP1L=0EBH CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH Reset value Table 6-10. 7 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 CH: PCA Counter High CH Address 0F9H Reset value Table 6-11. CL: PCA Counter Low CL Address 0E9H Reset value 6.3.1 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 6-6). 29 4188F–8051–01/08 Figure 6-6. PCA Capture Mode CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT PCA Counter/Timer Cex.n CH CL CCAPnH CCAPnL Capture ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE 6.3.2 30 16-bit Software Timer/ Compare Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 6-7). AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-7. PCA Compare Mode and PCA Watchdog Timer CCON CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16 bit comparator CH RESET * CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA to 0xDE CMOD 0xD9 * Only for Module 4 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. 6.3.3 High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 68). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. 31 4188F–8051–01/08 Figure 6-8. PCA High Speed Output Mode CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 Write to CCAPnL Reset PCA IT Write to CCAPnH 1 CCAPnH 0 Enable CCAPnL 16 bit comparator CH Match CL CEXn PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. 6.3.4 32 Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 6-9 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-9. PCA PWM Mode Overflow CCAPnH CCAPnL “0” Enable 8 bit comparator < Š CEXn “1” CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE 6.3.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 6-7 shows a diagram of how the watchdog works. The user preloads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: • 1. Periodically change the compare value so it will never match the PCA timer, • 2. periodically change the PCA timer value so it will never match the compare values, or • 3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 33 4188F–8051–01/08 6.4 TS80C51Rx2 Serial I/O Port The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition 6.4.1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 610). Figure 6-10. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1SMOD0 - POF GF1 GF0 PD PCON (87h) IDL To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 6-14.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 611 and Figure 6-12). Figure 6-11. UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 Stop bit RI SMOD0=X FE SMOD0=1 34 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-12. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 6.4.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: 6.4.3 The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b 35 4188F–8051–01/08 Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 6.4.4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 6.4.5 36 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-12. 7 SADEN - Slave Address Mask Register (B9h) 6 5 4 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 6-13. 7 SADDR - Slave Address Register (A9h) 6 5 4 Reset Value = 0000 0000b Not bit addressable Table 6-14. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI 37 4188F–8051–01/08 Bit Number Bit Mnemonic 7 FE Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 SM0 SM1ModeDescriptionBaud Rate 6 0 0 1 1 SM1 0 1 0 1 0Shift RegisterFXTAL/12 (/6 in X2 mode) 18-bit UARTVariable 29-bit UARTFXTAL/64 or FXTAL/32 (/32, /16 in X2 mode) 39-bit UARTVariable 5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. 4 REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 2 RB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 0 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 6-11. and Figure 612. in the other modes. Reset Value = 0000 0000b Bit addressable Table 6-15. 38 PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Bit Number Bit Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 39 4188F–8051–01/08 6.5 Interrupt System The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 6-13. WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the order in INT0, TF0, INT1, TF1, RI or TI, TF2 or EXF2, PCA. Figure 6-13. Interrupt Control System High priority interrupt IPH, IP INT0 IE0 3 0 3 TF0 0 INT1 IE1 3 0 3 TF1 Interrupt polling sequence, decreasing from high to low priority 0 3 PCA IT 0 RI TI 3 TF2 EXF2 3 0 0 Individual Enable Global Disable Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 6-17.Table 6-18.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 6-18.) and in the Interrupt Priority High register (See Table 6-19.). shows the bit values and priority levels associated with each combination. The PCA interrupt vector is located at address 0033H. All other vector addresses are the same as standard C52 devices. 40 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-16. Priority Level Bit Values IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 6-17. IE Register IE - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 EC PCA interrupt enable bit Clear to disable . Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. 4 ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3 ET1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2 EX1 External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1 ET0 Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0 EX0 External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable 41 4188F–8051–01/08 IP Register IP - Interrupt Priority Register (B8h) Table 6-18. 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description 7 - 6 PPC PCA interrupt priority bit Refer to PPCH for priority level. 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1 External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0 Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0 External interrupt 0 Priority bit Refer to PX0H for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = X000 0000b Bit addressable 42 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 6-19. IPH Register IPH - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic 7 - 6 5 4 3 2 1 0 PPCH Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit high. PPCHPPC Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT2H Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PSH Serial port Priority High bit PSH PS Priority Level 0 0Lowest 0 1 1 0 1 1Highest PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1Priority Level 0 0Lowest 0 1 1 0 1 1Highest PX1H External interrupt 1 Priority High bit PX1HPX1Priority Level 0 0Lowest 0 1 1 0 1 1Highest PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX0H External interrupt 0 Priority High bit PX0HPX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value = X000 0000b Not bit addressable 43 4188F–8051–01/08 6.6 Idle Mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 6.7 Power-down Mode To save maximum power, a power-down mode can be invoked by software (Refer to Table 6-15, PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 6-14. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C51Rx2 into power-down mode. 44 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 6-14. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 6-20. The state of ports during idle and power-down mode Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data* Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power-down Internal 0 0 Port Data* Port Data Port Data Port Data Power-down External 0 0 Floating Port Data Port Data Port Data * Port 0 can force a "zero" level. A "one" will leave port floating. 45 4188F–8051–01/08 6.8 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. 6.8.1 Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 6-22 (SFR0A7h). Table 6-21. WDTRST Register WDTRST Address (0A6h) Reset value 7 6 5 4 3 2 1 X X X X X X X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. Table 6-22. 46 WDTPRG Register WDTPRG Address (0A7h) 7 6 5 4 3 2 1 0 T4 T3 T2 T1 T0 S2 S1 S0 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Bit Number Bit Mnemonic 7 T4 6 T3 5 T2 4 T1 3 T0 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved Do not try to set or clear this bit. S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0Selected Time-out 0(214 - 1) machine cycles, 16.3 ms @ 12 MHz 1(215 - 1) machine cycles, 32.7 ms @ 12 MHz 0(216 - 1) machine cycles, 65.5 ms @ 12 MHz 1(217 - 1) machine cycles, 131 ms @ 12 MHz 0(218 - 1) machine cycles, 262 ms @ 12 MHz 1(219 - 1) machine cycles, 542 ms @ 12 MHz 0(220 - 1) machine cycles, 1.05 s @ 12 MHz 1(221 - 1) machine cycles, 2.09 s @ 12 MHz Reset value XXXX X000 6.8.2 WDT during Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode the user does not need to service the WDT. There are 2 methods of exiting Powerdown mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2 is reset. Exiting Powerdown with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 47 4188F–8051–01/08 6.9 ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS8xC51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the TS80C51Rx2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 6-23. 48 External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 7. Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 7-1). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 7-1. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable 49 4188F–8051–01/08 7.1 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. AUXR Register AUXR - Auxiliary Register (8Eh) Table 7-2. 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EXTRAM 0 AO EXTRAM bit See Table 6-1. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XXXX XX00b Not bit addressable 50 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 8. TS83C51RB2/RC2/RD2 ROM 8.1 ROM Structure The TS83C51RB2/RC2/RD2 ROM memory is divided in three different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. • the signature array:4 bytes. 8.2 ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 8.2.1 8.2.1 Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 8.2.2 Program Lock Bits The lock bits when programmed according to Table 8-1. will provide different level of protection for the on-chip code and data. Table 8-1. Program Lock bits Program Lock Bits Security level LB1 LB2 LB3 1 U U U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. 3 U P U Protection Description Same as level 1+ Verify disable. This security level is only available for 51RDX2 devices. U: unprogrammed P: programmed 8.2.3 Signature bytes The TS83C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 51 4188F–8051–01/08 8.2.4 52 Verify Algorithm Refer to Section “Verify algorithm”. AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 9. TS87C51RB2/RC2/RD2 EPROM 9.1 EPROM Structure The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: • the code array:16/32/64 Kbytes. • the encryption array:64 bytes. In addition a third non programmable array is implemented: • the signature array: 4 bytes. 9.2 EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 9.2.1 Encryption Array Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 9.2.2 Program Lock Bits The three lock bits, when programmed according to Table 9-1.9.2.3, will provide different level of protection for the on-chip code and data. Program Lock bits Table 9-1. Program Lock Bits Security level 1 LB1 U LB2 U LB3 Protection Description U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled. U: unprogrammed, P: programmed 53 4188F–8051–01/08 WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 9.2.3 9.3 9.3.1 Signature bytes The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in Section “Signature bytes”. EPROM Programming Set-up Modes In order to program and verify the EPROM or to read the signature bytes, the TS87C51RB2/RC2/RD2 is placed in specific set-up modes (See Figure 9-1.). Control and program signals must be held at the levels indicated in Table 9-2. 9.3.2 Definition of Terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13) for RB, P3.4 (A14) for RC, P3.5 (A15) for RD) Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, EA/VPP. Table 9-2. EPROM Set-Up Modes Mode 54 EA/VP P P2.6 P2.7 P3.3 P3.6 P3.7 12.75V 0 1 1 1 1 1 0 0 1 1 12.75V 0 1 0 1 1 0 0 0 0 0 12.75V 1 1 1 1 1 1 0 12.75V 1 1 1 0 0 1 0 12.75V 1 0 1 1 0 RST PSEN Program Code data 1 0 Verify Code data 1 0 Program Encryption Array Address 0-3Fh 1 0 Read Signature Bytes 1 0 Program Lock bit 1 1 Program Lock bit 2 Program Lock bit 3 ALE/P ROG 1 1 1 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Figure 9-1. Set-Up Modes Configuration +5V PROGRAM SIGNALS* EA/VPP VCC ALE/PROG CONTROL SIGNALS* 4 to 6 MHz RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 P0.0-P0.7 D0-D7 P1.0-P1.7 A0-A7 A8-A15 P2.0-P2.5 P3.4-P3.5 XTAL1 VSS GND * See Table 31. for proper value on these inputs 9.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS87C51RB2/RC2/RD2 the following sequence must be exercised: • Step 1: Activate the combination of control signals. • Step 2: Input the valid address on the address lines. • Step 3: Input the appropriate data on the data lines. • Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V). • Step 5: Pulse ALE/PROG once. • Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 9-2). 9.3.4 Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the TS87C51RB2/RC2/RD2. P 2.7 is used to enable data output. To verify the TS87C51RB2/RC2/RD2 code the following sequence must be exercised: • Step 1: Activate the combination of program and control signals. • Step 2: Input the valid address on the address lines. • Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 9-2.) 55 4188F–8051–01/08 The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Figure 9-2. Programming and Verification Signal’s Waveform Programming Cycle Read/Verify Cycle A0-A12 D0-D7 Data In Data Out 100µs ALE/PROG EA/VPP 12.75V 5V 0V Control signals 9.4 EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF). 9.4.1 Erasure Characteristics The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 10. Signature Bytes The TS83/87C51RB2/RC2/RD2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 10-1. shows the content of the signature byte for the TS87C51RB2/RC2/RD2. Table 10-1. 56 Signature Bytes Content Location Contents Comment 30h 58h Manufacturer Code: Atmel 31h 57h Family Code: C51 X2 60h 7Ch Product name: TS83C51RD2 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 60h FCh Product name: TS87C51RD2 60h 37h Product name: TS83C51RC2 60h B7h Product name: TS87C51RC2 60h 3Bh Product name: TS83C51RB2 60h BBh Product name: TS87C51RB2 61h FFh Product revision number 57 4188F–8051–01/08 11. Electrical Characteristics 11.1 Absolute Maximum Ratings *NOTICE: lute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package. Ambiant Temperature Under Bias: C = commercial......................................................0°C to 70°C I = industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS ........................................-0.5 V to + 7 V Voltage on Any Pin to VSS ........................-0.5 V to VCC + 0.5 V Power Dissipation .............................................................. 1 W 11.2 Stresses at or above those listed under “ Abso- Power Consumption Measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. 11.3 DC Parameters for Standard Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Table 11-1. Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL VOL1 VOL2 58 DC Parameters in Standard Voltage Output Low Voltage, ports 1, 2, 3, 4, 5 Output Low Voltage, port 0 (6) Output Low Voltage, ALE, PSEN (6) Typ Max Unit Test Conditions -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 V IOL = 100 µA(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) 0.3 V IOL = 200 µA(4) 0.45 V IOL = 3.2 mA(4) 1.0 V IOL = 7.0 mA(4) 0.3 V IOL = 100 µA(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 DC Parameters in Standard Voltage Table 11-1. Symbol VOH VOH1 VOH2 RRST Parameter Output High Voltage, ports 1, 2, 3, 4, 5 Output High Voltage, port 0 Output High Voltage,ALE, PSEN RST Pulldown Resistor Min Typ Max Unit VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V 50 90 (5) 200 kΩ Test Conditions IOH = -10 µA IOH = -30 µA IOH = -60 µA VCC = 5 V ± 10% IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% IOH = -100 µA IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4, 5 -650 µA Vin = 2.0 V CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz TA = 25°C IPD Power-down Current 50 µA 2.0 V < VCC < 5.5 V(3) ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 20(5) 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 Power Supply Current Maximum values, X1 mode: (7) 3 + 0.6 Freq (MHz) @12MHz 10.2 mA mA @16MHz 12.6 ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3 Freq (MHz) @12MHz 3.9 mA VCC = 5.5 V(1) VCC = 5.5 V(8) VCC = 5.5 V(2) @16MHz 5.1 59 4188F–8051–01/08 11.4 DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Table 11-2. Symbol DC Parameters for Low Voltage Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V Output Low Voltage, ports 1, 2, 3, 4, 5 (6) 0.45 V IOL = 0.8 mA(4) VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4) VOH Output High Voltage, ports 1, 2, 3, 4, 5 0.9 VCC V IOH = -10 µA VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC V IOH = -40 µA IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4, 5 -650 µA Vin = 2.0 V 200 kΩ 10 pF RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer IPD Power-down Current IPD Power-down Current (Only for TS87C51RD2 S287-xxx Very Low power) ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 50 Typ 90 (5) idle Fc = 1 MHz TA = 25°C 20 (5) 50 10 (5) 30 µA VCC = 2.0 V to 3.3 V(3) 2 (5) 15 µA 2.0 V < VCC < 3.6 V(3) 1 + 0.2 Freq (MHz) @12MHz 3.4 mA VCC = 3.3 V(1) VCC = 2.0 V to 5.5 V(3) @16MHz 4.2 Power Supply Current Maximum values, X1 mode: (7) 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 ICC Test Conditions Power Supply Current Maximum values, X1 mode: (7) mA VCC = 3.3 V(8) 0.15 Freq (MHz) + 0.2 @12MHz 2 mA VCC = 3.3 V(2) @16MHz 2.6 Notes: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 11-5.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 11-3.). 3. Power-down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 11-4.). 60 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3 and 4 and 5 when available: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 11-5.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 11-1. ICC Test Condition, under reset VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 11-2. Operating ICC Test Condition VCC ICC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL VCC XTAL2 XTAL1 VSS EA All other pins are disconnected. 61 4188F–8051–01/08 Figure 11-3. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 11-4. ICC Test Condition, Power-Down Mode VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles (NC) VCC P0 RST EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 11-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 11.5 11.5.1 0.7VCC 0.2VCC-0.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. 62 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 11-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 11-3. Load Capacitance versus speed range, in pF -M -V -L Port 0 100 50 100 Port 1, 2, 3 80 50 80 ALE / PSEN 100 30 100 Table 11-5., Table 39. and Table 42. give the description of each AC symbols. Table 11-6., Table 11-8. and Table 11-10. give for each range the AC parameter. Table 11-7., Table 11-9. and Table 11-11. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 11-4. Max frequency for derating formula regarding the speed grade -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode Freq (MHz) 40 20 40 30 30 20 T (ns) 25 50 25 33.3 33.3 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 11-7.) T= 50ns TLLIV= 2T - x = 2 x 50 - 22 = 78ns 63 4188F–8051–01/08 11.5.2 External Program Memory Characteristics Table 11-5. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 11-6. AC Parameters for Fix Clock -V -V Speed X2 mode -M 30 MHz 40 MHz 40 MHz 60 MHz equiv. Max Min X2 mode standard mode 20 MHz 30 MHz 40 MHz equiv. Min T 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 4 12 5 13 ns TLLAX 10 4 12 5 13 ns 45 Max Min 78 Max Units Min 70 Max -L Symbol TLLIV Min 65 Max 98 ns TLLPL 15 9 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV TPXIX 64 -L standard mode 35 0 25 0 50 0 30 0 55 0 ns ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-7. 11.5.3 AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2T-x T-x 10 8 15 ns TAVLL Min T-x 0.5 T - x 15 13 20 ns TLLAX Min T-x 0.5 T - x 15 13 20 ns TLLIV Max 4T-x 2T-x 30 22 35 ns TLLPL Min T-x 0.5 T - x 10 8 15 ns TPLPH Min 3T-x 1.5 T - x 20 15 25 ns TPLIV Max 3T-x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 0 0 ns TPXIZ Max T-x 0.5 T - x 7 5 15 ns TAVIV Max 5T-x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns External Program Memory Read Cycle Figure 11-6. External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN PORT 0 TLLAX TAVLL INSTR IN TPLIV TPLAZ A0-A7 TPXIX INSTR IN TPXAV TPXIZ A0-A7 INSTR IN TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 65 4188F–8051–01/08 11.5.4 External Data Memory Characteristics Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high AC Parameters for a Fix Clock Table 11-8. -V X2 mode Speed -M 30 MHz 40 MHz 60 MHz equiv. 20 MHz 30 MHz 40 MHz equiv. 85 135 125 175 ns TWLWH 130 85 135 125 175 ns 0 Min 60 0 Max Min 102 0 Max Units 130 Min 95 0 Max 137 0 ns ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns 130 ns TLLWL 50 TAVWL 75 47 80 70 103 ns TQVWX 10 7 15 5 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 9 17 10 18 ns TRLAZ TWHLH 66 standard mode 40 MHz TRLRH 100 Max -L standard mode Min TRHDX Min -L X2 mode Symbol TRLDV Max -V 100 30 0 10 40 70 55 0 7 27 95 45 0 15 35 105 70 0 5 45 13 0 ns 53 ns AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-9. 11.5.5 AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TRLRH Min 6T-x 3T-x 20 15 25 ns TWLWH Min 6T-x 3T-x 20 15 25 ns TRLDV Max 5T-x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 0 0 ns TRHDZ Max 2T-x T-x 20 15 25 ns TLLDV Max 8T-x 4T -x 40 35 45 ns TAVDV Max 9T-x 4.5 T - x 60 50 65 ns TLLWL Min 3T-x 1.5 T - x 25 20 30 ns TLLWL Max 3T+x 1.5 T + x 25 20 30 ns TAVWL Min 4T-x 2T-x 25 20 30 ns TQVWX Min T-x 0.5 T - x 15 10 20 ns TQVWH Min 7T-x 3.5 T - x 15 10 20 ns TWHQX Min T-x 0.5 T - x 10 8 15 ns TRLAZ Max x x 0 0 0 ns TWHLH Min T-x 0.5 T - x 15 10 20 ns TWHLH Max T+x 0.5 T + x 15 10 20 ns External Data Memory Write Cycle Figure 11-7. External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT 0 PORT 2 11.5.6 A0-A7 ADDRESS OR SFR-P2 TQVWX TQVWH TWHQX DATA OUT TAVWL ADDRESS A8-A15 OR SFR P2 External Data Memory Read Cycle 67 4188F–8051–01/08 Figure 11-8. External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH TRLDV RD PORT 0 TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 PORT 2 11.5.7 TRHDZ TAVDV TLLAX ADDRESS A8-A15 OR SFR P2 Serial Port Timing - Shift Register Mode Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 11-10. AC Parameters for a Fix Clock -V X2 mode Speed 30 MHz 40 MHz 60 MHz equiv. Max Min -L standard mode 40 MHz standard mode 20 MHz 30 MHz 40 MHz equiv. TXLXL 300 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns 34 Min Max 117 Min Max Units Min 117 Max -L X2 mode Symbol TXHDV 68 -M -V 117 Min Max 200 ns AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Table 11-11. AC Parameters for a Variable Clock: derating formula 11.5.8 Symbol Type Standard Clock X2 Clock TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 50 ns TXHQX Min 2T-x T-x 20 20 20 ns TXHDX Min x x 0 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 133 ns -M -V -L Units ns Shift Register Timing Waveforms Figure 11-9. Shift Register Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI TXHQX 0 1 2 3 4 5 6 7 TXHDX TXHDV VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI 69 4188F–8051–01/08 11.5.9 EPROM Programming and Verification Characteristics TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13 V IPP Programming Supply Current 75 mA 6 MHz 1/TCLCL Oscillator Frquency 4 TAVGL Address Setup to PROG Low 48 TCLCL TGHAX Adress Hold after PROG 48 TCLCL TDVGL Data Setup to PROG Low 48 TCLCL TGHDX Data Hold after PROG 48 TCLCL TEHSH (Enable) High to VPP 48 TCLCL TSHGL VPP Setup to PROG Low 10 µs TGHSL VPP Hold after PROG 10 µs TGLGH PROG Width 90 TAVQV Address to Valid Data 48 TCLCL TELQV ENABLE Low to Data Valid 48 TCLCL TEHQZ Data Float after ENABLE 110 0 µs 48 TCLCL verifying 11.5.10 EPROM Programming and Verification Waveforms Figure 11-10. EPROM Programming and Verification Waveforms PROGRAMMING P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* ADDRESS ADDRESS TAVQV P0 DATA OUT DATA IN TGHDX TGHAX TDVGL TAVGL ALE/PROG EA/VPP VERIFICATION TSHGL TGLGH VCC CONTROL SIGNALS (ENABLE) TGHSL VPP TEHSH VCC TELQV TEHQZ * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5 70 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 11.5.11 External Clock Drive Characteristics (XTAL1) Symbol Parameter Min Max Units TCLCL Oscillator Period 25 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 60 % TCHCX/TCLCX 11.5.12 Cyclic ratio in X2 mode 40 External Clock Drive Waveforms Figure 11-11. External Clock Drive Waveforms VCC-0.5 V 0.45 V 0.7VCC 0.2VCC-0.1 V TCHCL TCHCX TCLCH TCLCX TCLCL 11.5.13 AC Testing Input/Output Waveforms Figure 11-12. AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT 0.2VCC+0.9 0.2VCC-0.1 0.45 V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 11.5.14 Float Waveforms Figure 11-13. Float Waveforms FLOAT VOH-0.1 V VOL+0.1 V VLOAD VLOAD+0.1 V VLOAD-0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 71 4188F–8051–01/08 11.5.15 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 11-14. Clock Waveforms INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 P1P2 P1P2 P1P2 P1P2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT INDICATES ADDRESS TRANSITIONS P2 (EXT) READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT FLOAT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) P0 DPL OR Rt OUT DATA OUT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PORT OPERATION OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED RXD SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 72 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 12. Ordering Information Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS80C51RA2-MCA TS80C51RA2-MCB TS80C51RA2-MCE TS80C51RA2-MIA TS80C51RA2-MIB TS80C51RA2-MIE TS80C51RA2-LCA TS80C51RA2-LCB TS80C51RA2-LCE OBSOLETE TS80C51RA2-LIA TS80C51RA2-LIB TS80C51RA2-LIE TS80C51RA2-VCA TS80C51RA2-VCB TS80C51RA2-VCE TS80C51RA2-VIA TS80C51RA2-VIB TS80C51RA2-VIE AT80C51RA2-3CSUM Romless 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT80C51RA2-SLSUM Romless 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT80C51RA2-RLTUM Romless 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT80C51RA2-3CSIM AT80C51RA2-SLSIM AT80C51RA2-RLTIM OBSOLETE AT80C51RA2-3CSCL AT80C51RA2-SLSCL AT80C51RA2-RLTCL AT80C51RA2-3CSUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT80C51RA2-SLSUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT80C51RA2-RLTUL Romless 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 73 4188F–8051–01/08 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing AT80C51RA2-3CSCV AT80C51RA2-SLSCV AT80C51RA2-RLTCV OBSOLETE AT80C51RA2-3CSIV AT80C51RA2-SLSIV AT80C51RA2-RLSIV TS80C51RD2-MCA Not recommended use AT87C51RD2 TS80C51RD2-MCB Not recommended use AT87C51RD2 TS80C51RD2-MCE Not recommended use AT87C51RD2 TS80C51RD2-MIA Not recommended use AT87C51RD2 TS80C51RD2-MIB Not recommended use AT87C51RD2 TS80C51RD2-MIE Not recommended use AT87C51RD2 TS80C51RD2-LCA Not recommended use AT87C51RD2 TS80C51RD2-LCB Not recommended use AT87C51RD2 TS80C51RD2-LCE Not recommended use AT87C51RD2 TS80C51RD2-LIA Not recommended use AT87C51RD2 TS80C51RD2-LIB Not recommended use AT87C51RD2 TS80C51RD2-LIE Not recommended use AT87C51RD2 TS80C51RD2-VCA Not recommended use AT87C51RD2 TS80C51RD2-VCB Not recommended use AT87C51RD2 TS80C51RD2-VCE Not recommended use AT87C51RD2 TS80C51RD2-VIA Not recommended use AT87C51RD2 TS80C51RD2-VIB Not recommended use AT87C51RD2 TS80C51RD2-VIE Not recommended use AT87C51RD2 AT80C51RD2-3CSUM Not recommended use AT87C51RD2 AT80C51RD2-SLSUM Not recommended use AT87C51RD2 AT80C51RD2-RLTUM Not recommended use AT87C51RD2 AT80C51RD2-3CSUL Not recommended use AT87C51RD2 AT80C51RD2-SLSUL Not recommended use AT87C51RD2 AT80C51RD2-RLTUL Not recommended use AT87C51RD2 74 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS87C51RB2-MCA TS87C51RB2-MCB TS87C51RB2-MCE TS87C51RB2-MIA TS87C51RB2-MIB TS87C51RB2-MIE TS87C51RB2-LCA TS87C51RB2-LCB TS87C51RB2-LCE OBSOLETE TS87C51RB2-LIA TS87C51RB2-LIB TS87C51RB2-LIE TS87C51RB2-VCA TS87C51RB2-VCB TS87C51RB2-VCE TS87C51RB2-VIA TS87C51RB2-VIB TS87C51RB2-VIE AT87C51RB2-3CSUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RB2-SLSUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RB2-RLTUM OTP 16k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RB2-3CSUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RB2-SLSUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RB2-RLTUL OTP 16k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 75 4188F–8051–01/08 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS87C51RC2-MCA TS87C51RC2-MCB TS87C51RC2-MCE TS87C51RC2-MIA TS87C51RC2-MIB TS87C51RC2-MIE TS87C51RC2-LCA TS87C51RC2-LCB TS87C51RC2-LCE OBSOLETE TS87C51RC2-LIA TS87C51RC2-LIB TS87C51RC2-LIE TS87C51RC2-VCA TS87C51RC2-VCB TS87C51RC2-VCE TS87C51RC2-VIA TS87C51RC2-VIB TS87C51RC2-VIE AT87C51RC2-3CSUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RC2-SLSUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RC2-RLTUM OTP 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RC2-3CSUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RC2-SLSUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RC2-RLTUL OTP 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 76 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS87C51RD2-MCA TS87C51RD2-MCB TS87C51RD2-MCE TS87C51RD2-MIA TS87C51RD2-MIB TS87C51RD2-MIE TS87C51RD2-LCA TS87C51RD2-LCB TS87C51RD2-LCE OBSOLETE TS87C51RD2-LIA TS87C51RD2-LIB TS87C51RD2-LIE TS87C51RD2-VCA TS87C51RD2-VCB TS87C51RD2-VCE TS87C51RD2-VCL TS87C51RD2-VIA TS87C51RD2-VIB TS87C51RD2-VIE AT87C51RD2-3CSUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT87C51RD2-SLSUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT87C51RD2-RLTUM OTP 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT87C51RD2-3CSUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT87C51RD2-SLSUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT87C51RD2-RLTUL OTP 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 77 4188F–8051–01/08 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS83C51RB2-MCA TS83C51RB2-MCB TS83C51RB2-MCE TS83C51RB2-MIA TS83C51RB2-MIB TS83C51RB2-MIE TS83C51RB2-LCA TS83C51RB2-LCB TS83C51RB2-LCE OBSOLETE TS83C51RB2-LIA TS83C51RB2-LIB TS83C51RB2-LIE TS83C51RB2-VCA TS83C51RB2-VCB TS83C51RB2-VCE TS83C51RB2-VIA TS83C51RB2-VIB TS83C51RB2-VIE AT83C51RB2-3CSUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT83C51RB2-SLSUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT83C51RB2-RLTUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT83C51RB2-3CSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT83C51RB2-SLSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RB2-RLTUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 78 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS83C51RC2-MCA TS83C51RC2-MCB TS83C51RC2-MCE TS83C51RC2-MIA TS83C51RC2-MIB TS83C51RC2-MIE TS83C51RC2-LCA TS83C51RC2-LCB TS83C51RC2-LCE OBSOLETE TS83C51RC2-LIA TS83C51RC2-LIB TS83C51RC2-LIE TS83C51RC2-VCA TS83C51RC2-VCB TS83C51RC2-VCE TS83C51RC2-VIA TS83C51RC2-VIB TS83C51RC2-VIE AT83C51RC2-3CSUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT83C51RC2-SLSUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT83C51RC2-RLTUM ROM 32k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT83C51RC2-3CSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PDIL40 Stick AT83C51RC2-SLSUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RC2-RLTUL ROM 32k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray 79 4188F–8051–01/08 Part Number Memory size Supply Voltage Temperature Range Max Frequency Package Packing TS83C51RD2-MCA TS83C51RD2-MCB TS83C51RD2-MCE TS83C51RD2-MIA TS83C51RD2-MIB TS83C51RD2-MIE TS83C51RD2-LCB TS83C51RD2-LCE OBSOLETE TS83C51RD2-LIA TS83C51RD2-LIB TS83C51RD2-LIE TS83C51RD2-VCA TS83C51RD2-VCB TS83C51RD2-VCE TS83C51RD2-VIA TS83C51RD2-VIB TS83C51RD2-VIE AT83C51RD2-3CSUM ROM 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PDIL40 Stick AT83C51RD2-SLSUM ROM 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) PLCC44 Stick AT83C51RD2-RLTUM ROM 64k Bytes 5V Industrial & Green 40 MHz (20 MHz X2) VQFP44 Tray AT83C51RD2-3CSUL ROM 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) PLCC44 Stick AT83C51RD2-SLSUL ROM 64k Bytes 3-5V Industrial & Green 30 MHz (20 MHz X2) VQFP44 Tray AT83C51RD2-RLTUL ROM 64k Bytes 5V Industrial & Green 40 MHz (30 MHz X2) PDIL40 Stick 80 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 13. Package Drawings 13.1 PLCC44 81 4188F–8051–01/08 13.2 82 PDIL40 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 13.3 VQFP44 83 4188F–8051–01/08 13.4 84 VQFP64 AT/TS8xC51Rx2 4188F–8051–01/08 AT/TS8xC51Rx2 13.5 PLCC68 14. Datasheet Revision History 14.1 Changes from 4188E to 4188F 1. Removed TS80C51RD2 and AT80C51RD2 from “Ordering Information” on page 73. 2. Removed non-green part numbers from ordering information. 85 4188F–8051–01/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support Enter Product Line E-mail Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4188F–8051–01/08