TI1 DCPA10512DP Series 1-w, isolated, unregulated dc/dc converter module Datasheet

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DCPA1 Series 1-W, Isolated, Unregulated DC/DC Converter Modules
1 Features
3 Description
•
•
•
•
•
•
The DCPA1 series is a family of 1-W, isolated,
unregulated DC/DC converter modules. Requiring a
minimum of two external components, the DCPA1
series of devices include on-chip device protection,
and the ability to synchronize to an external clock.
1
2.0 kVDC Isolation (Operational)
Soft Start to Reduce In-rush Current
Frequency Synchronization
EN55022 Class B EMC Performance
UL1950 Recognized Component
7-Pin PDIP and 7-Pin SOP Packages
This combination of features and small size makes
the DCPA1 series of devices suitable for a wide
range of applications, and is an easy-to-use solution
in applications requiring signal path isolation.
2 Applications
•
•
•
•
•
WARNING: This product has operational isolation
and is intended for signal isolation only. It should not
be used as a part of a safety isolation circuit requiring
reinforced isolation. See definitions in the Feature
Description section.
Signal Path Isolation
Ground Loop Elimination
Data Acquisition
Industrial Control and Instrumentation
Test Equipment
Device Information
PART NUMBER
PACKAGE
PDIP (7)
DCPA1xxxx
SOP (7)
(1)
BODY SIZE (NOM)
19.18 mm × 10.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single Output Block Diagram
SWOUT
+VS
TEMP
+VOUT
OSC
÷2
±VOUT
FET
Driver
SYNCIN
Clock
Detect
I-LIM
Power Controller
±VS
Dual Output Block Diagram
SWOUT
+VS
TEMP
+VOUT
OSC
÷2
COM
FET
Driver
SYNCIN
±VOUT
Clock
Detect
Power Controller
I-LIM
±VS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Electrical Characteristics........................................... 4
Switching Characteristics .......................................... 6
Typical Characteristics (DCPA10505) ...................... 7
Typical Characteristics (DCPA10512) ...................... 8
Typical Characteristics (DCPA10515) ...................... 9
Typical Characteristics (DCPA10505D).................. 10
Typical Characteristics (DCPA10512D)................ 11
Typical Characteristics (DCPA10515D)................ 12
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagrams ..................................... 13
7.3 Feature Description................................................. 14
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2017
*
Initial release.
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5 Pin Configuration and Functions
NVA and DUA Package
7-Pin PDIP and SOP (Single Output)
(Top View)
+VS
1
±VS
2
14
SYNCIN
8
SWOUT
DCPA1
±VOUT
5
+VOUT
6
NC
7
NVA and DUA Package
7-Pin PDIP and SOP (Dual Output)
(Top View)
+VS
1
±VS
2
14
SYNCIN
8
SWOUT
DCPA1
COM
5
+VOUT
6
±VOUT
7
Pin Functions
PIN NUMBER
PIN NAME
SINGLEOUTPUT
DUALOUTPUT
I/O
(1)
Description
COM
—
5
O
Output side common
NC
7
—
—
No connection
SYNCIN
14
14
I
Synchronization. This pin is used to synchronize to an external clock.
Internally it is pulled to GND. If valid clock is not detected on this pin, the
SN6505 shifts automatically to internal clock.
SWOUT
8
8
O
Unrectified transformer output.
+VOUT
6
6
O
Positive output voltage
+VS
1
1
I
Input voltage
–VOUT
5
7
O
Negative output voltage
–VS
2
2
I
Input side common
(1)
I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
+VS
(1)
50ns transient
Input voltage
SYNCIN
50ns transient
MIN
MAX
UNIT
–0.5
6
V
–1.0
7
V
–0.5
+VS
V
–1.0
6
V
260
°C
125
°C
Lead temperature (soldering, 10 s)
Storage temperature, Tstg
(1)
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage
4.5
5
5.5
V
Output power
0.05
1
W
Operating ambient temperature range
–40
100
°C
MAX
UNIT
6.4 Electrical Characteristics
TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1.0 µF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
OUTPUT
POUT
Output power
Over +VS range, IOUT = 100% (full load)
DCPA10505
Output current
200
mA
mA
DCPA10512
83
mA
DCPA10512D
(1)
mA
66
mA
66 (1)
mA
83
DCPA10515
DCPA10515D
(1)
4
W
200 (1)
DCPA10505D
IOUT
1
IOUT1 + IOUT2
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Electrical Characteristics (continued)
TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1.0 µF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
DCPA10505
Output voltage
IOUT = 100% load
(2)
Line regulation
Load regulation (3)
VRIPPLE
5.0
V
V
DCPA10512
12.0
V
±12.0
V
15.0
V
DCPA10512D
Output voltage ripple
±15.0
V
–40°C ≤ TA ≤ 100°C, IOUT = 100% load
0.02
%/°C
+VS(MIN) to +VS(TYP), IOUT = 10% load
10%
+VS(TYP) to +VS(MAX), IOUT = 10% load
10%
10% to 100% load
(4)
UNIT
±5.0
DCPA10515D
Temperature variation
MAX
DCPA10505D
DCPA10515
VOUT
TYP
5%
COUT = 1 μF, IOUT = 50%
20
mVPP
INPUT
+VS
Input voltage range
UVLO
+VS Undervoltage lockout
IQ
(2)
(3)
(4)
Quiescient current
4.5
+VS increasing threshold
+VS decreasing threshold
IOUT = 0% load
5.5
V
2.25
V
1.7
V
DCPA10505
35
mA
DCPA10505D
25
mA
DCPA10512
29
mA
DCPA10512D
36
mA
DCPA10515
31
mA
DCPA10515D
38
mA
See Load Regulation graphs in the Typical Characterization section for typical voltage at all load conditions.
Load regulation = (VOUT at 10% load – VOUT at 100%)/VOUT at 75% load
Guaranteed by design. Not production tested.
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Electrical Characteristics (continued)
TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1.0 µF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISOLATION
1-second flash test,
voltage
VISO
2.0 (5) (4)
kVDC
AC
1.5 (5)
kVrms
1-second flash test, leakage current
Isolation
Continuous working
voltage across isolation
barrier
CISO
DC
Barrier capacitance
30
µA
DC
60
VDC
AC
42.5
VAC
50
V/ms
dV/dt
VISO = 750 Vrms
28
pF
PERFORMANCE
Efficiency
IOUT = 100%
50% to 100% load step
Transient response (4)
50% to 100% load step
per output (6)
DCPA10505
85%
DCPA10505D
85%
DCPA10512
87%
DCPA10512D
88%
DCPA10515
86%
DCPA10515D
86%
DCPA10505
3.0%
DCPA10512
1.9%
DCPA10515
2.0%
DCPA10505D
2.7%
DCPA10512D
2.0%
DCPA10515D
1.6%
RELIABILITY
Demonstrated
TA = 55°C
55
FITS
CAPACITANCE
CIN
External input capacitance
Ceramic
2.2
COUT
External output capacitance
Ceramic
0.1
µF
1.0
200
µF
THERMAL SHUTDOWN
TSD
Die temperature at shutdown
ISD
Shutdown current
(5)
(6)
168
°C
3
mA
See Isolation Voltage section for more information.
Transient testing for dual output devices are tested with one output loaded with a 50% static load and the other output loaded with a
50% to 100% dynamic load step.
6.5 Switching Characteristics
at TA = +25°C, +VS = nominal, CIN = 2.2 µF, COUT = 1.0 µF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fOSC
Oscillator frequency
fSYNC
Synchronization frequency range
750
VIH
High-level input threshold, SYNCIN
0.7
VIL
Low-level input threshold, SYNCIN
6
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fSW = fOSC/2
TYP
MAX
850
UNIT
kHz
1000
kHz
V
0.3
V
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6.6 Typical Characteristics (DCPA10505)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
100
40
Output Voltage Ripple (mVpp)
90
80
Efficiency (%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
35
30
25
20
15
10
5
10
100
20
DCPA10505
5.30
5.8
5.25
5.6
5.20
5.15
5.10
4.6
70
80
DCPA10505
Figure 3. Load Regulation
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90
100
D002
COUT = 1 µF
20-MHz BW
5
5.00
50
60
Load (%)
80
5.2
4.8
40
70
5.4
5.05
30
50
60
Load (%)
Figure 2. Output Ripple vs Load
6
Output Voltage (V)
Output Voltage (V)
Figure 1. Efficiency vs Load
20
40
DCPA10505
5.35
4.95
10
30
D001
90
100
D003
4.4
4.5
IOUT = 10%
IOUT = 100%
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
5.4
5.5
D004
DCPA10505
Figure 4. Line Regulation
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6.7 Typical Characteristics (DCPA10512)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
100
35
Output Voltage Ripple (mVpp)
90
80
Efficiency (%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
30
25
20
15
10
5
0
10
100
20
DCPA10512
12.20
13.2
12.15
12.9
12.10
12.6
12.05
12.00
11.95
11.90
70
80
Figure 7. Load Regulation
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100
D006
COUT = 1 µF
20-MHz BW
11.4
10.8
50
60
Load (%)
90
12
11.1
DCPA10512
8
80
11.7
11.80
40
70
12.3
11.85
30
50
60
Load (%)
Figure 6. Output Ripple vs Load
13.5
Output Voltage (V)
Output Voltage (V)
Figure 5. Efficiency vs Load
20
40
DCPA10512
12.25
11.75
10
30
D005
90
100
D007
10.5
4.5
IOUT = 10%
IOUT = 100%
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
5.4
5.5
D008
DCPA10512
Figure 8. Line Regulation
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6.8 Typical Characteristics (DCPA10515)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
30
100
Output Voltage Ripple (mVpp)
90
80
Efficiency (%)
70
60
50
40
30
20
25
20
15
10
5
10
0
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
100
20
30
40
D009
DCPA10515
50
60
Load (%)
70
80
100
D010
DCPA10515
Figure 9. Efficiency vs Load
90
COUT = 1 µF
20-MHz BW
Figure 10. Output Ripple vs Load
15.35
17
16.5
15.25
Output Voltage (V)
Output Voltage (V)
16
15.15
15.05
14.95
15.5
15
14.5
14
14.85
14.75
10
13.5
20
30
40
50
60
Load (%)
70
80
DCPA10515
Figure 11. Load Regulation
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90
100
D011
13
4.5
IOUT = 10%
IOUT = 100%
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
5.4
5.5
D012
DCPA10515
Figure 12. Line Regulation
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6.9 Typical Characteristics (DCPA10505D)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
160
90
140
Output Voltage Ripple (mVpp)
100
80
Efficiency (%)
70
60
50
40
30
20
+Vout
-Vout
120
100
80
60
40
20
10
0
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
100
20
DCPA10505D
5.30
5.8
5.25
5.6
5.20
5.15
5.10
4.6
50
60
Load (%)
70
80
90
4.4
4.5
100
4.6
+VOUT
-5.00
-4.6
-5.05
-4.8
-5.10
-5.15
-5.20
-5.8
80
Figure 17. –VOUT Load Regulation
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5.3
5.4
5.5
D017
+VOUT
90
100
D016
–VOUT
IOUT = 100%
IOUT = 10%
-5.4
-5.30
70
4.9
5
5.1 5.2
Input Voltage (V)
-5.2
-5.6
DCPA10505D
10
4.8
-5
-5.25
50
60
Load (%)
4.7
Figure 16. +VOUT Line Regulation
-4.4
Output Voltage (V)
Output Voltage (V)
Figure 15. +VOUT Load Regulation
40
D014
COUT = 1 µF
20-MHz BW
DCPA10505D
-4.95
30
100
IOUT = 10%
IOUT = 100%
D015
DCPA10505D
20
90
5
5.00
-5.35
10
80
5.2
4.8
40
70
5.4
5.05
30
50
60
Load (%)
Figure 14. Output Ripple vs Load
6
Output Voltage (V)
Output Voltage (V)
Figure 13. Efficiency vs Load
20
40
DCPA10505D
5.35
4.95
10
30
D013
-6
4.5
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
DCPA10505D
5.4
5.5
D018
–VOUT
Figure 18. –VOUT Line Regulation
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6.10 Typical Characteristics (DCPA10512D)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
80
90
70
Output Voltage Ripple (mVpp)
100
80
Efficiency (%)
70
60
50
40
30
20
+Vout
-Vout
60
50
40
30
20
10
10
0
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
100
20
DCPA10512D
12.55
13.8
12.50
13.5
12.45
13.2
12.40
12.35
12.30
12.25
70
80
100
D020
COUT = 1 µF
20-MHz BW
12
11.7
11.1
50
60
Load (%)
90
12.3
11.4
90
10.8
4.5
100
IOUT = 10%
IOUT = 100%
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
D021
DCPA10512D
+VOUT
5.3
5.4
5.5
D023
DCPA10512D
Figure 21. +VOUT Load Regulation
+VOUT
Figure 22. +VOUT Line Regulation
-12.10
-10.8
-12.15
-11.1
-12.20
-11.4
-12.25
Output Voltage (V)
Output Voltage (V)
80
12.6
12.15
40
70
12.9
12.20
30
50
60
Load (%)
Figure 20. Output Ripple vs Load
14.1
Output Voltage (V)
Output Voltage (V)
Figure 19. Efficiency vs Load
20
40
DCPA10512D
12.60
12.10
10
30
D019
-12.30
-12.35
-12.40
-12.45
-12.50
IOUT = 100%
IOUT = 10%
-11.7
-12
-12.3
-12.6
-12.9
-13.2
-13.5
-12.55
-13.8
-12.60
10
-14.1
4.5
20
30
40
50
60
Load (%)
70
80
DCPA10512D
Figure 23. –VOUT Load Regulation
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90
100
D022
–VOUT
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
DCPA10512D
5.4
5.5
D024
–VOUT
Figure 24. –VOUT Line Regulation
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6.11 Typical Characteristics (DCPA10515D)
At TA = 25°C, +VS = nominal, (unless otherwise noted)
100
70
Output Voltage Ripple (mVpp)
90
80
Efficiency (%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Load (%)
70
80
90
50
40
30
20
10
0
10
100
+Vout
-Vout
60
20
DCPA10515D
15.25
90
100
D026
COUT = 1 µF
20-MHz BW
16
Output Voltage (V)
Output Voltage (V)
80
16.5
15.30
15.20
15.15
15.10
15.05
15.00
14.95
15.5
15
14.5
14
14.90
13.5
14.85
20
30
40
50
60
Load (%)
70
80
90
13
4.5
100
IOUT = 10%
IOUT = 100%
4.6
4.7
4.8
D027
DCPA10515D
+VOUT
4.9
5
5.1 5.2
Input Voltage (V)
5.3
5.4
Figure 27. +VOUT Load Regulation
5.5
D029
DCPA10515D
+VOUT
Figure 28. +VOUT Line Regulation
-14.80
-13
-14.85
IOUT = 100%
IOUT = 10%
-13.5
-14.90
-14.95
-14
Output Voltage (V)
Output Voltage (V)
70
17
15.35
-15.00
-15.05
-15.10
-15.15
-15.20
-15.25
-14.5
-15
-15.5
-16
-15.30
-16.5
-15.35
20
30
40
50
60
Load (%)
70
80
DCPA10515D
Figure 29. –VOUT Load Regulation
12
50
60
Load (%)
Figure 26. Output Ripple vs Load
15.40
-15.40
10
40
DCPA10515D
Figure 25. Efficiency vs Load
14.80
10
30
D025
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90
100
D028
–VOUT
-17
4.5
4.6
4.7
4.8
4.9
5
5.1 5.2
Input Voltage (V)
5.3
DCPA10515D
5.4
5.5
D030
–VOUT
Figure 30. –VOUT Line Regulation
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7 Detailed Description
7.1 Overview
The DCPA1 offers up to 1 W of isolated, unregulated output power from a 5-V input source with a typical
efficiency of up to 87%. This efficiency is achieved through highly integrated packaging technology and the
implementation of a custom power stage and control device. The DCPA1 devices are specified for operational
isolation only. The circuit design uses an advanced BiCMOS and DMOS process.
7.2 Functional Block Diagrams
SWOUT
+VS
TEMP
+VOUT
OSC
÷2
±VOUT
FET
Driver
SYNCIN
Clock
Detect
I-LIM
Power Controller
±VS
Figure 31. Single Output Device
SWOUT
+VS
TEMP
+VOUT
OSC
÷2
COM
FET
Driver
SYNCIN
±VOUT
Clock
Detect
I-LIM
Power Controller
±VS
Figure 32. Dual Output Device
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7.3 Feature Description
7.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42 V peak or 60 VDC for more than 1 second.
7.3.1.1 Operation or Functional Isolation
Operational or functional isolation is defined by the use of a high-potential (hipot) test only. Typically, this
isolation is defined as the use of insulated wire in the construction of the transformer as the primary isolation
barrier. The hipot one-second duration test (dielectric voltage, withstand test) is a production test used to verify
that the isolation barrier is functioning. Products with operational isolation should never be used as an element in
a safety-isolation system.
7.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated
wire in the construction of the transformer. Input and output circuits must also be physically separated by
specified distances.
7.3.1.3 Continuous Voltage
For a device that has no specific safety agency approvals (operational isolation), the continuous voltage that can
be applied across the part in normal operation is less than 42.4 VRMS, or 60 VDC. Ensure that both input and
output voltages maintain normal SELV limits. The isolation test voltage represents a measure of immunity to
transient voltages.
WARNING
Do not use the device as an element of a safety isolation system that exceeds
the SELV limit.
If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the
isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any useraccessible circuitry according to safety standard requirements.
7.3.1.4 Isolation Voltage
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test
voltage all describe the same spec. The terms describe a test voltage applied for a specified time across a
component designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCPA1 series of dcdc converters are all 100% production tested at 1.5 kVAC for one second.
7.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on
materials, construction, and environment. The DCPA1 series of dc-dc converters have toroidal, enameled, wire
isolation transformers with no additional insulation between the primary and secondary windings. While a device
can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire
insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
14
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Feature Description (continued)
7.3.2 Power Stage
The DCPA1 series of devices uses a push-pull, center-tapped topology. The DCPA1 devices switch at 425 kHz
(divide-by-2 from an 850-kHz oscillator).
7.3.3 Input and Output Capacitors
For all DCPA1 designs, a minimum 2.2-μF, low-ESR, ceramic input capacitor is required. Place the input
capacitor as close as possible to the device input pins, +VS and –VS, to ensure good startup performance.
The recommended typical output capacitance for each output of any DCPA1 device is 1.0-μF of low-ESR,
ceramic capacitance. Adding additional output capacitance will aid in ripple reduction, however, any additional
capacitance will also require additional input current at start-up.
7.3.4 Oscillator And Watchdog Circuit
The onboard, 850-kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be
synchronized to an external source, and is used to minimize system noise. A watchdog circuit checks the
operation of the oscillator circuit.
7.3.5 Synchronization
When more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference can
be generated. This interference occurs because of the small variations in switching frequencies between the
DC/DC converters.
The DCPA1 series of devices overcomes this interference by allowing devices to synchronize to an external
clock. The SYNCIN pin responds to the rising edge of the external clock. If the external clock is removed, the
DCPA1 will return to the frequency of the internal oscillator. If unused, it is recommended to connect this pin to
the input side common, –VS.
7.3.6 SWOUT
The SWOUT pin is directly connected to one winding of the transformer secondary prior to the output rectifier. It is
not recommended to pull current from this pin. Do not connect capacitance directly to this pin as it will degrade
performance. The SWOUT pin is not compatible with the SYNCIN pin, therefore these two pins should not be
connected together.
7.3.7 Soft Start
The DCPA1 series of devices includes a soft-start feature that prevents high in-rush current during power up.
Once input power is applied, there is a delay of typically 10 ms before the output voltage begins to rise. Once the
output voltage begins to rise, the soft start time is typically 5 ms.
7.3.8 Load Regulation
The load regulation of the DCPA1 series of devices is specified at 10% to 100% load. Operation below 10% load
may cause the output voltage to increase up to 40% higher than the typical output voltage. Placing a minimum
10% load will ensure the output voltage is within the range specified in the Electrical Characteristics table.
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Feature Description (continued)
7.3.9 Thermal Performance
The DCPA1 family of devices have been characterized to operate over an ambient temperature range of –40°C
to +100°C. The Safe Operating Area curve shown below in Figure 33, represents the operating conditions of the
DCPA1 devices where the maximum thermal ratings will not be exceeded. Figure 33 shows that all DCPA1
devices can safely operate over the full ambient temperature range, without airflow, to the full current rating of
the device.
125
Ambient Temperature (°C)
115
105
95
85
75
65
55
45
DCPA10505
Nat Conv
35
25
0
10
20
30
40
50
60
Load (%)
70
80
90
100
D031
Figure 33. Thermal Safe Operating Area
7.3.9.1 Thermal Protection
The DCPA1 series of devices are protected by a thermal-shutdown circuit.
If the on-chip temperature rises above 150°C, the device shuts down. Normal operation resumes as soon as the
temperature falls below 150°C. While the overtemperature condition continues, operation randomly cycles on and
off. This cycling continues until the temperature is reduced.
7.3.10 Current Limit
For protection against a short circuit on the output, the DCPA1 series of devices have a built in current limit
protection threshold of 1.75A (typical). These devices are not intended to be used at output currents greater than
the device's output current rating as shown in the Electrical Characteristics table. Operating at currents greater
than the device's current rating, but less than current limit threshold will cause excessive stress to the internal
components. For protection against a partial short circuit condition, an input fuse or output fuse is recommended.
7.3.11 Construction
The basic construction of the DCPA1 series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCPA1 series of devices are constructed using an IC, rectifier diodes, and a
wound magnetic toroid on a leadframe. Because the package contains no solder, the devices do not require any
special printed circuit board (PCB) assembly processing. This architecture results in an isolated DC/DC converter
with inherently high reliability.
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Ripple Reduction
The high switching frequency of 425 kHz allows simple filtering. To reduce output voltage ripple, it is
recommended that a minimum of 1-µF capacitor be used on the +VOUT pin. For dual output devices, decouple
both of the outputs to the COM pin. The required 2.2-µF, low ESR ceramic input capacitor also helps to reduce
ripple and noise. See DC-to-DC Converter Noise Reduction (SBVA012).
8.1.2 Connecting the DCPA1 in Series
Multiple DCPA1 isolated 1-W DC/DC converters can be connected in series to provide non-standard voltage
rails. This configuration is possible by using the floating outputs provided by the galvanic isolation of the DCPA1
devices by connecting the +VOUT from one DCPA1 to the –VOUT of another as shown in Figure 34. The
synchronization feature allows easy synchronization to prevent power-rail beat frequencies at no additional
filtering cost.
VIN
+VS
CIN
+VOUT1
SYNCIN
CLOCK
INPUT
CIN
COUT
1.0 F
DCPA1
–VS
–VOUT1
VS
+VOUT2
SYNCIN
–VS
VOUT1
+
VOUT2
COUT
1.0 F
DCPA1
–VOUT2
Figure 34. Multiple DCPA1 Devices Connected in Series
The outputs of a dual-output DCPA1 device can also be connected in series to provide two times the magnitude
of +VOUT, as shown in Figure 35. For example, connect a dual-output, ±15-V, DCPA10515D device to provide a
30-V rail.
VIN
+VS
CIN
+VOUT
DCPA1
–VS
+VOUT
COUT
1.0 F
–VOUT
–VOUT
COUT
1.0 F
COM
Figure 35. Dual Output Devices Connected in Series
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8.1.3 Connecting the DCPA1 in Parallel
If the output power from one DCPA1 is not sufficient, it is possible to parallel the outputs of multiple DCPA1s, as
shown in Figure 36, (applies to single output devices only). The synchronization feature allows easy
synchronization to prevent power-rail beat frequencies at no additional filtering cost.
VIN
+VS
+VOUT1
DCPA1
SYNCIN
CIN
–VS
CLOCK
INPUT
COUT
1.0 F
–VOUT1
2 × Power Out
+VS
+VOUT2
COUT
1.0 F
DCPA1
SYNCIN
CIN
–VS
–VOUT2
GND
Figure 36. Multiple DCPA1 Devices Connected in Parallel
8.2 Typical Application
VIN
+VS
CIN
2.2 F
SYNC
+VOUT
+VOUT
DCPA1
–VS
COUT
1.0 F
–VOUT
–VOUT
Figure 37. Typical DCPA10505 Application
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 and follow the design procedures shown in
Detailed Design Procedure section.
Table 1. Design Example Parameters
PARAMETER
18
VALUE
UNIT
5
V
V(+VS)
Input voltage
V(+VOUT)
Output voltage
5
V
IOUT
Output current rating
200
mA
fSW
Operating frequency
425
kHz
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8.2.2 DCPA10505 Application Curves
Figure 38. DCPA10505 Turn-ON
Figure 39. DCPA10505 Turn-OFF
8.2.3 Detailed Design Procedure
8.2.3.1 Input Capacitor
For all DCPA1, 5-V input voltage designs, select a 2.2-μF low-ESR ceramic input capacitor to ensure a good
startup performance.
8.2.3.2 Output Capacitor
For any DCPA1 design, select a 1.0-μF low-ESR ceramic output capacitor to reduce output ripple.
8.2.3.3 SYNCIN Pin
In a stand-alone application, it is recommended to connect this pin to the input side common, –VS.
8.2.4 PCB Design
The copper losses (resistance and inductance) can be minimized by the use of mutual ground and power planes
where possible. If that is not possible, use wide traces to reduce the losses. If several devices are being powered
from a common power source, a star-connected system for the traces must be deployed. Do not connect the
devices in series, because that type of connection cascades the resistive losses. The position of the decoupling
capacitors is important. They must be as close to the devices as possible in order to reduce losses. See the PCB
Layout section for more details.
9 Power Supply Recommendations
The DCPA1 is a switching power supply, and as such can place high peak current demands on the input supply.
In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should
be used to connect the power to the input of DCPA1 device. If this connection is not possible, then the supplies
must be connected in a star formation with the traces made as wide as possible.
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10 Layout
10.1 Layout Guidelines
Due to the high power density of these devices, provide ground planes on the input and output rails.
Figure 40 shows the schematic for a single output DCPA1 device. Figure 40 illustrates a printed circuit board
(PCB) layout for the schematics.
Including input power and ground planes provides a low-impedance path for the input power. For the output, the
COM signal connects via a ground plane, while the connections for the positive and negative voltage outputs
conduct via wide traces in order to minimize losses.
The output should be taken from the device using ground and power planes, thereby ensuring minimum losses.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
If the SYNCIN pin is unused, it is recommended to connect this pin to the input side common, –VS. Allow the
SWOUT pin, to remain configured as a floating pad.
10.2 Layout Example
Figure 40. Typical Layout
20
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DCPA1
05
05
(D)
(P)
Basic model number: 1-W product
Voltage input:
5V
Voltage output:
5 V, 12 V or 15 V
Output type:
D (dual) or No Character (single)
Package code:
P = 7-pin PDIP (NVA package)
P-U = 7-pin SOP (DUA package)
Figure 41. Supplemental Ordering Information
11.2 Documentation Support
11.2.1 Related Documentation
DC-to-DC Converter Noise Reduction (SBVA012)
External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
Optimizing Performance of the DCP01/02 Series of DC/DC Converters (SBVA013)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DCPA10505
Click here
Click here
Click here
Click here
Click here
DCPA10505D
Click here
Click here
Click here
Click here
Click here
DCPA10512
Click here
Click here
Click here
Click here
Click here
DCPA10512D
Click here
Click here
Click here
Click here
Click here
DCPA10515
Click here
Click here
Click here
Click here
Click here
DCPA10515D
Click here
Click here
Click here
Click here
Click here
11.5 Trademarks
E2E is a trademark of Texas Instruments.
Underwriters Laboratories, UL are trademarks of UL LLC.
All other trademarks are the property of their respective owners.
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11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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26-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
DCPA10505DP
PREVIEW
PDIP
NVA
7
25
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
Device Marking
(4/5)
DCPA10505DP
DCPA10505DP-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10505DP-U/700
PREVIEW
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCPA10505DP-U
DCPA10505P
PREVIEW
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCPA10505P
DCPA10505P-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10505P-U/700
PREVIEW
SOP
DUA
7
700
TBD
Call TI
Call TI
-40 to 100
DCPA10505P-U
DCPA10512DP
PREVIEW
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCPA10512DP
DCPA10512DP-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10512DP-U/700
PREVIEW
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCPA10512DP-U
DCPA10512P
PREVIEW
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCPA10512P
DCPA10512P-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10512P-U/700
PREVIEW
SOP
DUA
7
700
TBD
Call TI
Call TI
-40 to 100
DCPA10512P-U
DCPA10515DP
PREVIEW
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCPA10515DP
DCPA10515DP-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10515DP-U/700
PREVIEW
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCPA10515DP-U
DCPA10515P
PREVIEW
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCPA10515P
DCPA10515P-U
PREVIEW
SOP
DUA
7
25
TBD
Call TI
Call TI
-40 to 100
DCPA10515P-U/700
PREVIEW
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
DCPA10515P-U
Samples
PACKAGE OPTION ADDENDUM
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26-Apr-2017
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 2
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