APW7078 Single PWM Switching Controller Features • • • • • • • • • General Description 2.3 to 5.5V Input Voltage Range The A PW 7078 is a single P W M, s tep-up DC-DC Adjustable Frequency: Maximum 1MHZ c ont roller wit h low operating volt age applic at ion int egr at ing s oft-st art and short circ uit detect ion Incorporates Soft-start Function function. And the oscillator switching frequency on chip Built-in Short-circuit Detection Circuit (SCP) can be operated by terminating OSC pin to connect Low Operating Current: Maximum to 1mA c apac itor and resis t or for adjus t able operating Low Shutdown Current: Maximum to 1mA frequency. Soft-start is adjusted with external capacitor, Package: MSOP-8, TSSOP-8 whic h s et s t he input current ramp. Bes ides, the external compensation FB pin will apply the flexibility in Under Voltage Lockout the dynamic loop status, which allow using small, low Lead Free Available (RoHS Compliant) equivalent series res istance (ES R) c eramic output capacitors. Applications • • • • Pinouts LCD Display Power Source Camcorders VCRs, MP3 and Digital Still INV 1 8 FB Camera SCP 2 7 OSC Hand-held and Communication Instruments VDD 3 6 GND PDAs CTL 4 Ordering and Marking Information 5 OUT APW7078 Package Code X : MSOP - 8 O : TSSOP-8 Temp. Range I : -40 to 85 °C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APW7078 Lead Free Code Handling Code Temp. Range Package Code APW7078 X : APW7078 XXX XX XXXXX - Date Code APW7078 O : APW7078 XXXXX XXXXX - Date Code No tes : ANPEC lea d-free produ cts co nta in mol din g comp oun ds/die attach m ate ria ls and 10 0% matte in pla te te rmin atio n fi nish ; wh ich are full y compl iant with Ro HS and compa tibl e wi th both SnPb an d le ad-free sold ieri ng op era tio ns. AN PEC le ad-free produ cts me et or exceed th e l ead -free req uireme nts of IPC /JEDEC J STD -02 0C fo r MSL classi ficati on at lea d-fre e p eak re flo w temp era ture. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 1 www.anpec.com.tw APW7078 Block Diagram VDD OSC UVLO 0.9 V Sawtooth wave oscillator 0.16V 0.1 V VDD - INV VDD Error Amp. PWM Comp. + + Output drive circuit + + Vref 0.5V OUT DTC 0.8V FB Soft start SCP SCP GND CTL Absolute Maximum Ratings Symbol Parameter Value Unit VDD Supply Voltage -0.3 to 7 V VIO Input / Output Pins -0.3 to 7 V TA Operating Ambient Temperature Range -40 to 85 °C TJ Junction Temperature Range -40 to 150 °C T STG Storage Temperature Range -65 to +150 °C 300, 10 seconds °C TS Soldering Temperature Recommended Operating Condition Symbol Value Parameter Min. Typ. Max. Unit VDD Supply Voltage 2.3 - 5.5 V VINV Error Amplifier Invert Input Voltage -0.2 - 1 V VCTL Control Pin Input Voltage -0.2 - VDD V C SCP SCP Pin Capacitor - 0.1 - µF RT Timing Resistance 1.0 3.3 10 KΩ CT Timing Capacitor 100 - 270 pF FSW Oscillator Frequency 200 600 1000 KHz C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 2 www.anpec.com.tw APW7078 Electrical Characteristics Symbol Parameter (TA = 25°C, VDD = 3.3V, unless otherwise specified) Test Conditions APW7078 Min Typ Max Unit Entire Device VDD Supply Voltage IDD Supply Current VDD=2.3V to 5.5V ISD Shutdown Current CTL pin open or VDD Maximum Duty Cycle Rt=3.3K, Ct=270pF Dmax 2.3 5.5 V 0.7 1 mA 0.1 1 µA 80 85 92 % 1.9 2.0 2.1 V - 1.8 1.9 V 0.7 0.8 0.9 V -0.7 -1.0 -1.5 µA 0.7 0.8 0.9 V Vscp=0V -0.7 -1.0 -1.5 µA Oscillator Frequency Rt=3.3KΩ, Ct=270pF 500 600 700 KHz Frequency Stability for Voltage VDD=2.3V to 5.5V - 2 5 % Ta=-40°C to 85°C - 5 - % 0.49 0.5 0.51 V VDD=2.3V to 5.5V 5 20 mV Ta=-40°C to 85°C 1 Under Voltage Lockout Protection VTH VR VDD Startup Threshold Voltage Hysteresis voltage - Soft-Start Vss Voltage at Soft-Start completion Ics Soft-Start Charge Current Vscp=0V Short Circuit Protection(SCP) Vscp Threshold Voltage Iscp Charge Current Sawtooth waveform oscillator(OSC) Fosc Fdv Frequency Stability for Temperature Error Amplifier Fdt Vref Reference Voltage Vref/dV Vref stability Vref variation with Vref/dT Temperature gm Transconductance IB VOH VOL Input Bias Current VFB=INV 1000 1300 INV=0V - Output Voltage Range 1.6 % 1600 µA/V 1 µA 1.8 - V 0.01 V Output Source Current INV=0V,FB=0.5V -150 -180 -210 µA Output Sink Current INV=1V,FB=0.5V 140 170 200 µA C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 3 www.anpec.com.tw APW7078 Electrical Characteristics (Cont.) (TA = 25°C, VDD = 3.3V, unless otherwise specified) Symbol Parameter Test Conditions APW7078 Unit Min Typ Max Duty<5%, OUT=0V -150 -200 mA Duty>5%, OUT=5V 150 200 mA PWM Controller Driver ISOURCE Output Source Current ISINK Output Sink Current Control Block VIL Active mode Control Voltage VIH 0.2V DD Switch-off mode 0.8VDD Function Pin Description Pin No. Symbol I/O Description Internal 0.5V reference voltage. Use a resistor divider to set the output voltage. Soft-start and short-circuit detection, connects a capacitor from the pin to ground. Power supply input pin for IC voltage. Output control pin. Low = operating mode; High = shutdown mode. External MOSFET driving pin. Ground pins of the IC. 1 INV I 2 SCP - 3 4 5 6 VDD CTL OUT GND I O - 7 OSC - Setting capacitor and resister to provide oscillation switching frequency adjustment. 8 FB O Error amplifier output pin. Setting circuit for IC compensation. Application Schematic VIN 2.5V~4.2V L1 10uH C1 22uF C2 0.1uF C7 1uF R1 390K 1 INV 2 SCP FB 8 OSC 7 3 VDD GND 6 4 CTL OUT 5 R3 R2 91K Q2 2N7002 D1 VOUT SS12 5V 300mA Q1 APM2300A R5 1K C5 47uF C3 270pF R4 3.3K C6 0.1uF C4 0.1uF 820K Cp *R2≦100KΩ is recommended 33pF Fig1: APW7078 Step-up Application for Adjust Voltage C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 4 www.anpec.com.tw APW7078 Application Schematic VIN 2.5V~5.5V L1 10uH R6 2R2 C1 22uF C2 0.1uF R1 390K C8 1uF 1 INV 2 SCP FB 8 OSC 7 3 VDD GND 6 5 OUT 4 CTL VOUT SS12 9V 100mA Q1 APM2300A R5 12K C6 0.1uF C5 33uF C4 0.1uF R4 4.3K C3 270pF R3 D1 150K R2 9.1K Cp Q2 2N7002 68pF Fig2: APW7078 Step-up Application for Adjust Voltage D2 26V C10 -9V 0.1uF C8 D3 1uF C12 C11 1uF 1uF L1 C1 22uF C2 0.1uF C7 1uF R10 390K 1 INV FB 2 SCP OSC 3 VDD GND 4 CTL OUT R3 R2 75K 9V D1 22uH R6 2R2 C13 3.3uF 0.1uF C9 VIN 2.5V~5.5V D4 SS12 8 7 6 Q1 APM2300A R5 1K 5 C3 270pF C5 100uF R4 3.3K C6 0.1uF C4 0.1uF 1.2M *R2≦100KΩ is recommended Q2 2N7002 Fig3. APW7078 Multiple-output for TFT LCD Panel Power C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 5 www.anpec.com.tw APW7078 Timing Diagram FB input voltage Short cirucit detect comparator Sawtooth wave output Soft-start setting voltage Output pin waveform SCP detect voltage SCP pin waveform tscp ts Output short circuit Soft start ON Power supply control SW Output short circuit Output short circuit detection OFF Typical Characteristics (TA = 25°C, VDD = 3.3V, unless otherwise specified) SHDN and Release Supply Current vs. Supply Voltage 800 600 Maximum Duty(%) Supply Current(µA) 700 500 400 300 200 TA =25° C RT=3.3kΩ CT=270pF 100 0 1 2 3 4 5 CH1=VOUT 2V/DIV TIME=20ms/DIV CH2=VCTL 2V/DIV CH3=Vss 0.5V/DIV CH4=IL 1A/DIV Supply Voltage(V) C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 6 www.anpec.com.tw APW7078 Typical Characteristics (Cont.) (TA = 25°C, VDD = 3.3V, unless otherwise specified) Reference Voltage vs. Temperature Reference Voltage vs. Supply Voltage 0.54 520 0.53 Reference Voltage(V) Reference Voltage(mV) 516 512 508 504 TA =25° C 500 496 492 0.52 0.51 VDD=3.3V 0.50 0.49 0.48 488 0.47 484 0.46 480 1 2 3 4 -40 5 0 20 40 60 80 Temperature(° C) Supply Voltage(V) Oscillator Frequency vs. Timing Resistor Maximum Duty vs. Oscillator Frequency 100 1000 90 CT=270pF 800 Maximum Duty(%) Oscillator Frequency(kHz) -20 CT=100pF 600 400 CT=270pF 200 80 70 CT=200pF CT=100pF 60 50 40 10 0 0 2 4 6 8 10 1000 Oscillator Frequency(kHz) Timing Resistor(kΩ) C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 100 7 www.anpec.com.tw APW7078 Typical Characteristics (Cont.) (TA = 25°C, VDD = 3.3V, unless otherwise specified) Power on and off under light load Power on and off under heavy load IIOUT= 400mA, TIME=40ms/DIV CH1=OUT 5VDIV CH2=VOUT=VDD 2V/DIV CH3=IL 0.5A/DIV CH4=Vss 1V/DIV IOUT= 5mA, TIME=40ms/DIV CH1=OUT 5VDIV CH2=VOUT=VDD 2V/DIV CH3=IL 0.5A/DIV CH4=Vss 1V/DIV Efficiency Efficiency 100 100 90 95 90 Efficiency(%) 80 Efficiency(%) VDD=3.3V VDD=2.5V VDD=3.3V 70 VDD=5V 60 50 40 VDD=3.6V 80 75 VOUT=5V L=10µH CT=270pF RT=3.3K 70 VOUT=9V L=10µH CT=270pF RT=4.3K 30 85 65 60 20 1 10 10 100 1000 Output Current(mA) Output Current(mA) C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 100 8 www.anpec.com.tw APW7078 Typical Characteristics (TA = 25°C, VDD = 3.3V, unless otherwise specified) Frequency Variation Ratio vs. Temperature 10 Frequency Variation Ration Δ f/f(%) Frequency Variation Ration Δ f/f(%) Frequency Variation Ratio vs. Supply Voltage TA =25° C RT=3.3k Ω CT=270pF 8 6 4 2 0 -2 -4 -6 -8 -10 1 2 3 4 5 5 CT=270pF RT=3.3kΩ 4 3 2 1 0 -1 -2 -3 -4 -5 -40 -20 0 20 40 60 80 Temperature(° C) Supply Voltage(V) Function Description Setting Oscillating Frequency i=c The oscillator circuit generat e a triangular sawt ooth ∆V ∆t t1 = C t wave with a peak of 0.9V and through of 0.16V using ⋅ 0.9V − 0.16V 2mA the timing capacitor(Ct) and the timing resistor(Rt) that are connected to OSC pin. This oscillator can provide V (t ) = VH ⋅ e oscillating frequency up to 1MHz. − = 370 ⋅ C t t Rt Ct t 2 = R t Ct ln(VH / VL ) = 1.72 ⋅ Rt C t Vosc T = t1 + t 2 = C t (370 + 1.72Rt ) VH 0.9V Setting Output Voltage The out put voltage is set using t he INV pin and a resistor divider connected to the output as shown in the V(t) typical operating circuit. The internal reference volt0.16V VL t1 t C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 age is 0.5V with 2% variation, so the ratio of the feedbac k res istors set s the output voltage according to t2 Time the following equation: 9 www.anpec.com.tw APW7078 Function Description (Cont.) Setting Output Voltage (Cont.) (pin 5) is set low and the SCP pin stays low. Once the protection circuit operates, the circuit can be restored R3 VOUT = 1 + × 0 .5 V R2 by resetting the power supply. Short circuit detection time can be calculate as follow: To avoid the thermal nois e from feedback resistor, t SCP = 0 .8 × Cscp(µ F ) Resistance R2 smaller than 100k Ω and 1% variation is recommended. Under Voltage Lock Out(UVLO) Error amplifier Trans ient s during powering on or inst ant aneous The error amplifier detects the output voltage of the glitches in the supply voltage can cause system dam- swit ching regulat or and out put s the PW M control age or failure. The circuit to prevent malfunction at low signal. The voltage gain is fixed, and connec ting a input voltage detect s a low input voltage by compar- phase compensation resistor and capacitor to the FB ing the supply voltage to the internal reference voltage. pin (pin 8) provides stable phase compensation for the On detection, the circuit fixes the output pin to low. system. The system recovers when the supply voltage rises back above the t hreshold volt age of the malfunc tion PWM comparator prevention circuit. The volt age c omparator has one invert ing and three Layout Considerations non-inverting inputs. The comparator is a voltage/pulse width converter that controls the ON time of the output Switching Noise Decoupling Capacitor pulse depending on the input voltage. The output level A 0.1µF ceramic capacitor should be placed close to is high (H) when the sawtooth wave is lower than the the V OUT pin and GND pin of the chip t o filter t he error amplifier output voltage, soft start setting voltage, switc hing spikes in t he output voltage monitored by and idle period setting voltage. the VOUT pin. Output circuit Feedback Network The output circuit is a typical push-pull configuration On A PW7078 applicat ion, the feedback networks to drive an external NMOS transistor directly. It can should be connec ted directly to a dedicated analog provide a 200mA source/sink to/from OUT(pin 6). ground plane and this ground plane must connect to Soft start and short circuit detection the GND pin. If no analog ground plane is available then this ground must tie directly to the GND pin. The Soft start operation is set by connecting capacitor Cscp feedback network, resistors R2 and R3, should be kept to t he SCP pin (pin 2). Soft s tart prevents a current close to the FB pin, and away from the inductor, to spike on start-up.On completion of soft start operation, minimize copper trace connections that can inject noise the SCP pin (pin 2) s tays low and enters the short into the system. circuit detection wait stat e.When an output short circuit occurs, the error amplifier output is fixed at 1.8V Input Capacitor and capacitor Cscp starts charging. The input capacitor CIN in VIN must be placed close to After charging to approximately 0.8 V, t he output pin C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 the IC. This will reduce copper trace resistance which 10 www.anpec.com.tw APW7078 Function Description(Cont.) Input Capacitor (Cont.) effects input voltage ripple of the IC. For additional input voltage filtering, a 1µF capac itor can be placed in parallel with CIN , close to the VDD pin, to shunt any high frequency noise to ground. Demo Board Circuit Layout Top Layer Bottom Layer C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 11 www.anpec.com.tw APW7078 Packaging Information MSOP-8 e1 E E1 e1 L1 A1 Dim A1 A2 A3 e e1 E E1 L1 L2 A3 A2 L2 Millimeters Min. 0.06 Inches Max. Min. 0.15 0.002 0.86 TYP 0.25 0.4 0.01 0.0126 0.0256TYP 3.1 5.0 3.1 0.114 0.189 0.169 0.25 REF 0.0375 REF C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 0.006 0.34 TYP 0.65 TYP 2.90 4.8 2.90 Max. 0.124 0.197 0.177 0.039REF 0.953 REF 12 www.anpec.com.tw APW7078 Packaging Information TSSOP-8 e 8 7 2x E/2 E1 ( 2) E GAUGE PLANE S 1 2 e/2 0.25 D L A2 A b Dim A A1 A2 b D e E E1 L L1 R R1 S φ1 φ2 φ3 1 (L1) ( 3) A1 Millimeters Min. Inches Max. 1.2 0.15 1.05 0.30 3.1 0.00 0.80 0.19 2.9 Min. 0.000 0.031 0.007 0.114 0.65 BSC 6.40 BSC 4.30 0.45 0.026 BSC 0.252 BSC 4.50 0.75 0.169 0.018 8° 0.004 0.004 0.008 0° 1.0 REF 0.09 0.09 0.2 0° 0.177 0.030 0.039REF 12° REF 12° REF C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 Max. 0.047 0.006 0.041 0.012 0.122 8° 12° REF 12° REF 13 www.anpec.com.tw APW7078 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 ° t 25 C to Peak Time Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate 3°C/second max. 3°C/second max. (TL to T P) Preheat 100°C 150°C - Temperature Min (Tsmin) °C 150 200°C - Temperature Max (Tsmax) 60-120 seconds 60-180 seconds - Time (min to max) (ts) Time maintained above: 183°C 217°C - Temperature (TL) 60-150 seconds 60-150 seconds - Time (t L) Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5 °C of actual 10-30 seconds 20-40 seconds Peak Temperature (tp) Ramp-down Rate 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25 °C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 14 www.anpec.com.tw APW7078 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm Volume mm <350 ≥ 350 <2.5 mm 240 +0/-5 °C 225 +0/- 5 ° C ≥ 2.5 mm 225 +0/-5 °C 225 +0/- 5 ° C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350 -2000 >2000 <1.6 mm 260 +0 ° C * 260 +0° C* 260 +0 ° C * 1.6 mm – 2.5 mm 260 +0 ° C * 250 +0° C* 245 +0 ° C * ≥ 2.5 mm 250 +0 ° C * 245 +0° C* 245 +0 ° C * *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 °C. For example 260 ° C+0 °C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST Method MIL-STD-883D-2003 MIL-STD 883D-1005.7 JESD-22-B, A102 MIL-STD 883D-1011.9 Description 245°C,5 SEC 1000 Hrs Bias @ 125°C 168 Hrs, 100% RH, 121°C -65°C ~ 150°C, 200 Cycles Carrier Tape & Reel Dimensions t E P Po D P1 Bo F W Ao C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 D1 15 Ko www.anpec.com.tw APW7078 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application M S O P- 8 A B 330 ± 1 62 +1.5 F D 5.5 ± 1 Application TSSOP-8 C 12.75+ 0.15 D1 J T1 T2 W P E 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12 ± 0. 3 8 ± 0.1 1.75 ± 0.1 Po P1 Ao Bo Ko t 2.0 ± 0.1 6.4 ± 0.1 5.2 ± 0. 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 A B 330 ± 1 62 +1.5 F D 5.5 ± 0. 1 1.5 + 0.1 2.1 ± 0.1 0.3 ±0.013 C 12.75+ 0.15 D1 J T1 T2 W P E 2 + 0.5 12.4 ± 0.2 2 ± 0.2 12 ± 0. 3 8 ± 0.1 1.75 ± 0.1 Po P1 Ao Bo Ko t 1.5 + 0.1 4.0 ± 0.1 2.0 ± 0.1 7.0 ± 0.1 3.6 ± 0.3 1.6 ± 0.1 0.3 ±0.013 (mm) Cover Tape Dimensions Application MSOP- 8 TSSOP- 8 Carrier Width 12 12 Cover Tape Width 9.3 9.3 Devices Per Reel 2500 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 C opyright ANPEC Electronics C orp. Rev. A.3 - Nov., 2005 16 www.anpec.com.tw