AD EV-ADF4159EB2Z Direct modulation/fast waveform generating, 13 ghz, fractional-n frequency synthesizer Datasheet

Direct Modulation/Fast Waveform Generating,
13 GHz, Fractional-N Frequency Synthesizer
ADF4159
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13 GHz
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth, triangular, and parabolic waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
capability. The part uses a 25-bit fixed modulus, allowing subhertz
frequency resolution.
The ADF4159 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth and triangular waveforms. The ADF4159 features cycle slip reduction circuitry, which
enables faster lock times without the need for modifications to
the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4159 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.62 V
to 1.98 V. The device can be powered down when not in use.
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD SDVDD
VP
RSET
ADF4159
÷2
DIVIDER
+
PHASE
FREQUENCY
DETECTOR
CSR
DGND
LOCK
DETECT
OUTPUT
MUX
CP
CHARGE
PUMP
–
HIGH-Z
MUXOUT
SW2
REFERENCE
5-BIT
R COUNTER
×2
DOUBLER
REFIN
FAST LOCK
SWITCH
SDOUT
SW1
DVDD
RDIV
N COUNTER
NDIV
LE
RFINB
MODULUS
225 VALUE
FRACTION
VALUE
32-BIT
DATA
REGISTER
AGND
DGND
SDGND
INTEGER
VALUE
CPGND
10849-001
CE
CLK
RFINA
–
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
TXDATA
DATA
+
Figure 1.
Rev. B
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ADF4159
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Deviation Register (R5) Map .................................................... 21
Applications ....................................................................................... 1
Step Register (R6) Map .............................................................. 22
General Description ......................................................................... 1
Delay Register (R7) Map ........................................................... 23
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 24
Revision History ............................................................................... 2
Initialization Sequence .............................................................. 24
Specifications..................................................................................... 3
RF Synthesizer Worked Example ............................................. 24
Timing Specifications .................................................................. 4
Reference Doubler ...................................................................... 24
Absolute Maximum Ratings ............................................................ 6
Cycle Slip Reduction for Faster Lock Times ........................... 24
Thermal Resistance ...................................................................... 6
Modulation .................................................................................. 25
ESD Caution .................................................................................. 6
Waveform Generation ............................................................... 25
Pin Configuration and Function Descriptions ............................. 7
Waveform Deviations and Timing ........................................... 26
Typical Performance Characteristics ............................................. 8
Single Ramp Burst ...................................................................... 26
Theory of Operation ...................................................................... 10
Single Triangular Burst .............................................................. 26
Reference Input Section ............................................................. 10
Single Sawtooth Burst ................................................................ 26
RF Input Stage ............................................................................. 10
Sawtooth Ramp........................................................................... 26
RF INT Divider ........................................................................... 10
Triangular Ramp ........................................................................ 26
25-Bit Fixed Modulus ................................................................ 10
FMCW Radar Ramp Settings Worked Example ...................... 26
INT, FRAC, and R Counter Relationship ................................ 10
Activating the Ramp .................................................................. 27
R Counter .................................................................................... 10
Other Waveforms ....................................................................... 27
Phase Frequency Detector (PFD) and Charge Pump ............ 11
Ramp Complete Signal to MUXOUT ..................................... 30
MUXOUT and Lock Detect ...................................................... 11
Interrupt Modes and Frequency Readback ............................ 31
Input Shift Register..................................................................... 11
Fast Lock Mode .......................................................................... 32
Program Modes .......................................................................... 11
Spur Mechanisms ....................................................................... 33
Register Maps .................................................................................. 12
Filter Design Using ADIsimPLL .............................................. 33
FRAC/INT Register (R0) Map .................................................. 14
PCB Design Guidelines for the Chip Scale Package .............. 33
LSB FRAC Register (R1) Map ................................................... 15
Application of the ADF4159 in FMCW Radar........................... 34
R Divider Register (R2) Map .................................................... 16
Outline Dimensions ....................................................................... 35
Function Register (R3) Map...................................................... 18
Ordering Guide .......................................................................... 35
Clock Register (R4) Map ........................................................... 20
REVISION HISTORY
6/13—Rev. A to Rev. B
Changed PFD Antibacklash Pulse from 3 ns to 1 ns in Phase
Frequency Detector (PFD) and Charge Pump Section ............. 11
Changes to Charge Pump Current Setting Section and
Reference Doubler Section ............................................................ 16
Changes to Negative Bleed Current Enable Section and Loss of
Lock (LOL) Section ........................................................................ 18
5/13—Revision A: Initial Version
Rev. B | Page 2 of 36
Data Sheet
ADF4159
SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, fPFD = 110 MHz, TA = TMIN to TMAX,
dBm referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter 1
RF CHARACTERISTICS
RF Input Frequency (RFIN)
Prescaler Output Frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
Reference Doubler Enabled
REFIN Input Capacitance
REFIN Input Current
PHASE FREQUENCY DETECTOR (PFD)
Phase Detector Frequency 2
CHARGE PUMP
ICP Sink/Source Current
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
POWER SUPPLIES
AVDD
DVDD, SDVDD
VP
AIDD
Min
Typ
Max
Unit
Test Conditions/Comments
13
GHz
2
GHz
−10 dBm min to 0 dBm max; for lower
frequencies, ensure a slew rate ≥ 400 V/µs
For higher frequencies, use 8/9 prescaler
10
260
MHz
10
50
1.2
±100
MHz
pF
µA
110
MHz
0.5
4.59
4.8
300
2.5
5.1
1
2
2
2
5.61
1.4
mA
µA
%
kΩ
nA
%
%
%
0.4
±1
10
V
V
µA
pF
0.3
100
V
V
µA
26
3.45
1.98
3.45
40
V
V
V
mA
DIDD
7.5
10
mA
IP
Power-Down Mode
5.5
2
7
mA
µA
DVDD − 0.4
2.7
1.62
2.7
1.8
Rev. B | Page 3 of 36
−5 dBm min to +9 dBm max biased at
1.8/2 (ac coupling ensures 1.8/2 bias); for
frequencies < 10 MHz, use a dc-coupled,
CMOS-compatible square wave with a
slew rate > 25 V/µs
Bit DB20 in Register R2 set to 1
Programmable
RSET = 5.1 kΩ
RSET = 5.1 kΩ
Sink and source current
0.5 V < VCP < VP − 0.5 V
0.5 V < VCP < VP − 0.5 V
VCP = VP/2
CMOS output selected
IOL = 500 µA
Supply current drawn by AVDD;
fPFD = 110 MHz
Supply current drawn by DVDD;
fPFD = 110 MHz
Supply current drawn by VP; fPFD = 110 MHz
ADF4159
Data Sheet
Parameter 1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor 3
Integer-N Mode
Fractional-N Mode
Normalized 1/f Noise (PN1_f) 4
Min
Typ
Phase Noise Performance 5
12,002 MHz Output 6
Max
Unit
−224
−217
−120
dBc/Hz
dBc/Hz
dBc/Hz
−96
dBc/Hz
Test Conditions/Comments
PLL loop BW = 1 MHz
FRAC = 0
Measured at 10 kHz offset, normalized
to 1 GHz
At VCO output
At 50 kHz offset, 100 MHz PFD frequency
Operating temperature: −40°C to +125°C.
Guaranteed by design. Sample tested to ensure compliance.
3
This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5
The phase noise is measured with the EV-ADF4159EB3Z and the Rohde & Schwarz FSUP signal source analyzer.
6
fREFIN = 100 MHz; fPFD = 100 MHz; offset frequency = 50 kHz; RFOUT = 12,002 MHz; N = 120.02; loop bandwidth = 250 kHz.
1
2
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
10849-002
t6
LE
Figure 2. Write Timing Diagram
Rev. B | Page 4 of 36
Data Sheet
ADF4159
Table 3. Read Timing
Parameter
t1 1
t2
t3
t4
t5
1
Limit at TMIN to TMAX
tPFD + 20
20
25
25
10
Unit
ns min
ns min
ns min
ns min
ns min
Description
TXDATA setup time
CLK setup time to data (on MUXOUT)
CLK high duration
CLK low duration
CLK to LE setup time
tPFD is the period of the PFD frequency; for example, if the PFD frequency is 50 MHz, tPFD = 20 ns.
Read Timing Diagram
TXDATA
t1
t3
t4
CLK
t2
MUXOUT
DB36
DB2
DB35
DB1
DB0
t5
10849-003
LE
NOTES
1. LE SHOULD BE KEPT HIGH DURING READBACK.
Figure 3. Read Timing Diagram
500µA
0.9V
CL
10pF
100µA
IOH
10849-004
TO MUXOUT
PIN
IOL
Figure 4. Load Circuit for MUXOUT Timing, CL = 10 pF
Rev. B | Page 5 of 36
ADF4159
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = SDGND = CPGND =
0 V, unless otherwise noted.
Table 4.
Parameter
AVDD to GND
DVDD to GND
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN to GND
RFIN to GND
Operating Temperature Range,
Industrial
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
ESD
Charged Device Model
Human Body Model
Rating
−0.3 V to +3.9 V
−0.3 V to +2.4 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +125°C
−65°C to +125°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Thermal impedance (θJA) is specified for a device with the
exposed pad soldered to AGND.
Table 5. Thermal Resistance
Package Type
24-Lead LFCSP_WQ
ESD CAUTION
260°C
40 sec
1000 V
3000 V
Rev. B | Page 6 of 36
θJA
30.4
Unit
°C/W
Data Sheet
ADF4159
19 DVDD
21 SW2
20 SW1
22 VP
24 CP
23 RSET
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 SDVDD
CPGND 1
AGND 2
17 MUXOUT
ADF4159
RFINB 4
TOP VIEW
(Not to Scale)
16 LE
15 DATA
TXDATA 12
SDGND 11
DGND 10
REFIN 9
13 CE
AVDD 8
14 CLK
AVDD 6
AVDD 7
RFINA 5
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO AGND.
10849-005
AGND 3
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2, 3
4
Mnemonic
CPGND
AGND
RFINB
5
6, 7, 8
RFINA
AVDD
9
REFIN
10
11
12
DGND
SDGND
TXDATA
13
CE
14
CLK
15
DATA
16
LE
17
18
MUXOUT
SDVDD
19
DVDD
20, 21
22
23
SW1, SW2
VP
RSET
24
CP
25
EPAD
Description
Charge Pump Ground. This pin is the ground return path for the charge pump.
Analog Ground.
Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,
typically 100 pF.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Place decoupling capacitors to the ground plane as close as possible
to these pins.
Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Digital Ground.
Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.
Transmit Data Pin. This pin provides the data to be transmitted in FSK or PSK mode and also controls some
ramping functionality.
Chip Enable (1.8 V Logic). A logic low on this pin powers down the device and places the charge pump output
into three-state mode.
Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first; the three LSBs are the control bits. This input is a high
impedance CMOS input.
Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight
latches; the latch is selected using the control bits. This input is a high impedance CMOS input.
Multiplexer Output. This pin allows various internal signals to be accessed externally.
Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as
possible to this pin.
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close
as possible to this pin.
Switches for Fast Lock.
Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.
Connecting a resistor between this pin and ground sets the maximum charge pump output current. The
relationship between ICP and RSET is as follows:
ICP_MAX = 24.48/RSET
where:
ICP_MAX = 4.8 mA.
RSET = 5.1 kΩ.
Charge Pump Output. When the charge pump is enabled, this output provides ±ICP to the external loop filter,
which, in turn, drives the external VCO.
Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.
Rev. B | Page 7 of 36
ADF4159
Data Sheet
–40
12.06
–60
12.05
12.04
–80
FREQUENCY (GHz)
–100
–120
–140
12.01
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
11.98
12.05
12.05
12.04
12.04
FREQUENCY (GHz)
12.06
12.03
12.02
12.01
11.99
TIME (µs)
11.98
10849-107
200
0
100
200
300
400
500
TIME (µs)
Figure 10. Dual Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3; First Ramp: CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64; Second Ramp: CLK2 = 52,
DEV = 1024, DEV_OFFSET = 7, Number of Steps = 64
Figure 7. Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
12.06
12.06
12.05
12.05
FREQUENCY (GHz)
12.04
12.03
12.02
12.01
12.04
12.03
12.02
12.01
12.00
12.00
0
50
100
150
200
TIME (µs)
10849-108
11.99
11.98
100
12.01
11.99
150
80
12.02
12.00
100
60
12.03
12.00
50
40
Figure 9. Sawtooth Burst, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
12.06
0
20
TIME (µs)
Figure 6. Phase Noise at 12.002 GHz, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, Bleed Current = 11.03 µA
11.98
0
10849-110
10k
10849-106
1k
10849-109
11.99
–180
100
FREQUENCY (GHz)
12.02
12.00
–160
FREQUENCY (GHz)
12.03
Figure 8. Sawtooth Ramp with Delay, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64, Delay Word = 1000
11.99
0
100
200
300
400
500
TIME (µs)
Figure 11. Triangle Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
Rev. B | Page 8 of 36
10849-111
PHASE NOISE (dBc/Hz)
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
ADF4159
12.06
12.014
12.012
12.05
12.04
FREQUENCY (GHz)
FREQUENCY (GHz)
12.010
12.03
12.02
12.01
12.008
12.006
12.004
12.002
12.000
11.998
12.00
11.996
50
100
150
200
11.994
TIME (µs)
Figure 12. Fast Ramp (Triangle Ramp with Different Slopes), fPFD = 100 MHz,
ICP = 2.5 mA, Loop Bandwidth = 250 kHz, CLK1 = 3; Up Ramp: CLK2 = 26,
DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64; Down Ramp: CLK2 = 70,
DEV = 16,384, DEV_OFFSET = 8, Number of Steps = 4
0
100
400
300
200
10849-115
0
10849-112
11.99
500
TIME (µs)
Figure 15. FSK Ramp, fPFD = 100 MHz, ICP = 2.5 mA, Loop Bandwidth = 250 kHz,
CLK1 = 3, CLK2 = 26, DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64;
FSK: DEV = −512, DEV_OFFSET = 8
200
0
150
–5
100
–10
50
0
–50
–15
–20
–25
–100
–30
–150
–35
0
50
100
150
200
TIME (µs)
–40
10849-113
–200
0
5
10
15
20
FREQUENCY (GHz)
Figure 13. Phase Shift Keying (PSK), Loop Bandwidth = 250 kHz,
Phase Value = 1024, Data Rate = 20 kHz
10849-116
RF SENSITIVITY (dBm)
PHASE (Degrees)
PRESCALER 8/9
PRESCALER 4/5
Figure 16. RFIN Sensitivity at Nominal Temperature
12.004
6
12.003
4
2
ICP (mA)
12.001
12.000
0
11.999
–2
11.998
–4
11.996
0
50
100
150
200
TIME (µs)
–6
0
0.5
1.0
1.5
2.0
2.5
VCP (V)
Figure 17. Charge Pump Output Characteristics
Figure 14. Frequency Shift Keying (FSK), Loop Bandwidth = 250 kHz,
DEV = 1049, DEV_OFFSET = 9, Data Rate = 20 kHz
Rev. B | Page 9 of 36
3.0
10849-117
11.997
10849-114
FREQUENCY (GHz)
12.002
ADF4159
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
25-BIT FIXED MODULUS
Figure 18 shows the reference input stage. The SW1 and SW2
switches are normally closed (NC in Figure 18). The SW3 switch
is normally open (NO in Figure 18). When power-down is
initiated, SW3 is closed, and SW1 and SW2 are opened. In this
way, no loading of the REFIN pin occurs during power-down.
The ADF4159 has a 25-bit fixed modulus. This modulus allows
output frequencies to be spaced with a resolution of
POWER-DOWN
CONTROL
SW2
BUFFER
10849-013
SW1
SW3
NO
The RF VCO frequency (RFOUT) equation is
Figure 18. Reference Input Stage
RFOUT = (INT + (FRAC/225)) × fPFD
RF INPUT STAGE
Figure 19 shows the RF input stage. The input stage is followed
by a two-stage limiting amplifier to generate the current-mode
logic (CML) clock levels required for the prescaler.
1.6V
BIAS
GENERATOR
(2)
where:
RFOUT is the output frequency of the external voltage
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
FRAC is the numerator of the fractional division (0 to (225 − 1)).
The PFD frequency (fPFD) equation is
AVDD
2kΩ
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 100 MHz,
frequency steps of 2.98 Hz are possible.
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the PFD frequency.
TO R COUNTER
REFIN NC
(1)
INT, FRAC, AND R COUNTER RELATIONSHIP
100kΩ
NC
fRES = fPFD/225
2kΩ
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(3)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference (R) counter (1 to 32).
T is the REFIN divide-by-2 bit (0 or 1).
RFINA
RFINB
10849-014
R COUNTER
AGND
Figure 19. RF Input Stage
RF INT DIVIDER
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.
The RF INT CMOS divider allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
RF INT DIVIDER
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
VALUE
MOD
VALUE
FRAC
VALUE
10849-015
FROM RF
INPUT STAGE
N = INT + FRAC/MOD
Figure 20. RF INT Divider
Rev. B | Page 10 of 36
Data Sheet
ADF4159
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
INPUT SHIFT REGISTER
The ADF4159 digital section includes a 5-bit R counter, a 12-bit
INT counter, and a 25-bit FRAC counter. Data is clocked into the
32-bit input shift register on each rising edge of CLK. The data
is clocked in MSB first. Data is transferred from the input shift
register to one of eight latches on the rising edge of LE.
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 21 shows a simplified schematic of the PFD.
HIGH
D1
Q1
The destination latch is determined by the state of the three
control bits (C3, C2, and C1) in the input shift register. As shown
in Figure 2, the control bits are the three LSBs (DB2, DB1, and
DB0, respectively). Table 7 shows the truth table for these bits.
Figure 23 and Figure 24 provide a summary of how the latches
are programmed.
UP
U1
+IN
CLR1
DELAY
CHARGE
PUMP
U3
CP
Table 7. Truth Table for the C3, C2, and C1 Control Bits
HIGH
CLR2
DOWN
D2
Q2
10849-016
U2
C3
0
0
0
0
1
1
1
1
–IN
Figure 21. PFD Simplified Schematic
The PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 1 ns. This pulse ensures that
there is no dead zone in the PFD transfer function and gives a
consistent reference spur level.
MUXOUT AND LOCK DETECT
The following settings in the ADF4159 are double buffered:
LSB fractional value, phase value, charge pump current setting,
reference divide-by-2, reference doubler, R counter value, and
CLK1 divider value. Before the part uses a new value for any
double-buffered setting, the following two events must occur:
DVDD
DGND
1.
R DIVIDER OUTPUT
N DIVIDER OUTPUT
CONTROL
2.
MUXOUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
N DIVIDER/2
DGND
10849-017
R DIVIDER/2
READBACK TO MUXOUT
Register
R0
R1
R2
R3
R4
R5
R6
R7
Table 7 and Figure 25 through Figure 32 show how the program
modes are set up in the ADF4159.
DVDD
MUX
C1
0
1
0
1
0
1
0
1
PROGRAM MODES
The multiplexer output on the ADF4159 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M4, M3, M2, and M1 bits in
Register R0 (see Figure 25). Figure 22 shows the MUXOUT
section in block diagram form.
THREE-S TATE OUTPUT
Control Bits
C2
0
0
1
1
0
0
1
1
The new value is latched into the device by writing to the
appropriate register.
A new write is performed to Register 0 (R0).
For example, updating the fractional value involves a write to
the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 must be
written to first, followed by the write to R0. The frequency change
begins after the write to R0. Double-buffering ensures that the
bits written to R1 do not take effect until after the write to R0.
Figure 22. MUXOUT Schematic
Rev. B | Page 11 of 36
ADF4159
Data Sheet
REGISTER MAPS
RAMP ON
FRAC/INT REGISTER (R0)
MUXOUT
CONTROL
12-BIT MSB FRACTIONAL VALUE
(FRAC)
12-BIT INTEGER VALUE (INT)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1
M4
M3
M2
M1
N12
N10
N11
N9
N8
N7
N6
N5
N4
N3
N2
N1
F25
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14 C3(0) C2(0) C1(0)
LSB FRAC REGISTER (R1)
PHASE
ADJUST
DBB
RESERVED
DBB
13-BIT LSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT PHASE VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
P1
F13
F12
F10
F11
F9
F8
F7
F6
F5
F4
F3
F2
F1
P12
P11
P10
P8
P9
P7
P6
P5
P4
P3
P2
P1
C3(0) C2(0) C1(1)
R DIVIDER REGISTER (R2)
RDIV2 DBB
DBB
REFERENCE
DOUBLER DBB
PRESCALER
CP
CURRENT
SETTING
CSR
RESERVED
RESERVED
DBB
DBB
5-BIT R COUNTER
CONTROL
BITS
12-BIT CLK1 DIVIDER VALUE
0
P1
U2
U1
R5
R4
R3
R2
R1
D12
D11
D10
D8
D9
D7
D6
D5
D4
D3
POWER-DOWN
CR1 CPI4 CPI3 CPI2 CPI1
PD
POLARITY
0
FSK
0
LDP
0
PSK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D2
D1
C3(0) C2(1) C1(0)
CP
THREE-STATE
COUNTER
RESET
RAMP MODE
RESERVED
SD
RESET
N SEL
LOL
RESERVED
RESERVED
NEG BLEED
CURRENT
RESERVED
NEG BLEED
ENABLE
FUNCTION REGISTER (R3)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
NB3 NB2
NB1
0
0
0
0
1
L1
NS1
U12
0
0
RM2 RM1
0
0
U11
U10
U9
U8
U7
C3(0) C2(1) C1(1)
10849-018
0
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 23. Register Summary 1
Rev. B | Page 12 of 36
Data Sheet
ADF4159
CLK
DIV
MODE
RAMP
STATUS
RESERVED
CLK DIV SEL
LE SEL
CLOCK REGISTER (R4)
12-BIT CLK2 DIVIDER VALUE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1
0
0
0
0
0
R5
R4
R3
R2
R1
C2
C1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
CS1
0
0
0
C3(1) C2(0) C1(0)
DEV SEL
DUAL RAMP
FSK RAMP
INTERRUPT
PARABOLIC
RAMP
TX RAMP CLK
TXDATA
INVERT
RESERVED
DEVIATION REGISTER (R5)
4-BIT DEVIATION
OFFSET WORD
CONTROL
BITS
16-BIT DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
TR1
0
I2
I1
0
0
DS1
DO4 DO3 DO2 DO1 D16
D15
D14 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C3(1) C2(0) C1(1)
STEP SEL
STEP REGISTER (R6)
RESERVED
CONTROL
BITS
20-BIT STEP WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
SSE1 S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
C3(1) C2(1) C1(0)
DEL CLK SEL
DEL START EN
RAMP DELAY
FAST RAMP
RAMP DELAY FL
TXDATA
TRIGGER
SING FULL TRI
RESERVED
TRI DELAY
TXDATA
TRIGGER DELAY
DELAY REGISTER (R7)
12-BIT DELAY START WORD
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
TD1
ST1
TR1
FR1
0
RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5
DS4
DS3 DS2 DS1 C3(1) C2(1) C1(1)
10849-019
0
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 24. Register Summary 2
Rev. B | Page 13 of 36
ADF4159
Data Sheet
FRAC/INT REGISTER (R0) MAP
12-Bit Integer Value (INT)
When Bits DB[2:0] are set to 000, the on-chip FRAC/INT
register (Register R0) is programmed (see Figure 25).
Bits DB[26:15] set the INT value, which forms part of the overall
feedback division factor. For more information, see the INT, FRAC,
and R Counter Relationship section.
Ramp On
12-Bit MSB Fractional Value (FRAC)
When Bit DB31 is set to 1, the ramp function is enabled. When
Bit DB31 is set to 0, the ramp function is disabled.
Bits DB[14:3], along with Bits DB[27:15] in the LSB FRAC register
(Register R1), set the FRAC value that is loaded into the fractional
interpolator. The FRAC value forms part of the overall feedback
division factor. These 12 bits are the most significant bits (MSBs)
of the 25-bit FRAC value; Bits DB[27:15] in the LSB FRAC register
(Register R1) are the least significant bits (LSBs). For more information, see the RF Synthesizer Worked Example section.
MUXOUT Control
RAMP ON
The on-chip multiplexer of the ADF4159 is controlled by
Bits DB[30:27]. See Figure 25 for the truth table.
MUXOUT
CONTROL
12-BIT MSB FRACTIONAL VALUE
(FRAC)
12-BIT INTEGER VALUE (INT)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4
M3
M2
R1 RAMP ON
M1
N12
N11
M4 M3 M2
N10
N9
M1
N8
N7
N6
N5
N4
N3
N2
N1
F25
F24
F23
OUTPUT
0
RAMP DISABLED
0
0
0
0
THREE-STATE OUTPUT
1
RAMP ENABLED
0
0
0
1
DVDD
0
0
1
0
DGND
0
0
1
1
R DIVIDER OUTPUT
0
1
0
0
N DIVIDER OUTPUT
0
1
0
1
RESERVED
0
1
1
0
DIGITAL LOCK DETECT
0
1
1
1
SERIAL DATA OUTPUT
1
0
0
0
RESERVED
1
0
0
1
RESERVED
1
0
1
0
CLK DIVIDER OUTPUT
1
0
1
1
RESERVED
1
1
0
0
RESERVED
1
1
0
1
R DIVIDER/2
1
1
1
0
N DIVIDER/2
1
1
1
1
READBACK TO MUXOUT
F22
F21
F20
F19
F18
F17
F16
F15
F14 C3(0) C2(0) C1(0)
MSB FRACTIONAL VALUE
(FRAC)*
F25
F24
...
F15
F14
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
4092
1
1
...
0
1
4093
1
1
...
1
0
4094
1
1
...
1
1
4095
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0 AND THE 13-BIT LSB STORED IN REGISTER R1.
FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
0
0
0
0
0
0
0
1
0
1
1
1
23
0
0
0
0
0
0
0
1
1
0
0
0
24
0
0
0
0
0
0
0
1
1
0
0
1
25
0
0
0
0
0
0
0
1
1
0
1
0
26
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
0
1
4093
1
1
1
1
1
1
1
1
1
1
1
0
4094
1
1
1
1
1
1
1
1
1
1
1
1
4095
Figure 25. FRAC/INT Register (R0) Map
Rev. B | Page 14 of 36
INTEGER VALUE (INT)
10849-020
R1
Data Sheet
ADF4159
LSB FRAC REGISTER (R1) MAP
These 13 bits are the least significant bits (LSBs) of the 25-bit
FRAC value; Bits DB[14:3] in the FRAC/INT register are the
most significant bits (MSBs). For more information, see the
RF Synthesizer Worked Example section.
When Bits DB[2:0] are set to 001, the on-chip LSB FRAC
register (Register R1) is programmed (see Figure 26).
Reserved Bits
12-Bit Phase Value
All reserved bits must be set to 0 for normal operation.
Bits DB[14:3] control the phase word. The phase word is used
to increase the RF output phase relative to the current phase.
The phase change occurs after a write to Register R0.
Phase Adjustment
Bit DB28 enables and disables phase adjustment. The phase
shift is generated by the value programmed in Bits DB[14:3].
Phase Shift = (Phase Value × 360°)/212
13-Bit LSB Fractional Value (FRAC)
For example, Phase Value = 512 increases the phase by 45°.
RESERVED
PHASE ADJ
Bits DB[27:15], along with Bits DB[14:3] in the FRAC/INT
register (Register R0), set the FRAC value that is loaded into
the fractional interpolator. The FRAC value forms part of the
overall feedback division factor.
To use phase adjustment, Bit DB28 must be set to 1. If phase
adjustment is not used, it is recommended that the phase value
be set to 0.
DBB
DBB
13-BIT LSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT PHASE VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
F13
F12
...
F2
F1
P12
P11
...
P2
P1
PHASE VALUE
P1
PHASE ADJ
0
0
...
0
0
0
0
1
...
1
1
2047
0
DISABLED
0
0
...
0
1
1
.
.
...
.
.
.
1
ENABLED
0
0
...
1
0
2
0
0
...
1
1
3
0
0
...
1
1
3
0
0
...
1
0
2
.
.
...
.
.
.
0
0
...
0
1
1
.
.
...
.
.
.
0
0
...
0
0
0 (RECOMMENDED)
.
.
...
.
.
.
1
1
...
1
1
–1
1
1
...
0
0
8188
1
1
...
1
0
–2
1
1
...
0
1
8189
1
1
...
0
1
–3
1
1
...
1
0
8190
.
.
...
.
.
.
1
1
...
1
1
8191
1
0
...
0
0
–2048
P1
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
P12
P11
LSB FRACTIONAL VALUE
(FRAC)*
P10
P9
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0 AND THE 13-BIT LSB STORED IN REGISTER R1.
FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 26. LSB FRAC Register (R1) Map
Rev. B | Page 15 of 36
P8
P7
P6
P5
P4
P3
P2
P1
C3(0) C2(0) C1(1)
10849-021
0
ADF4159
Data Sheet
R DIVIDER REGISTER (R2) MAP
When Bits DB[2:0] are set to 010, the on-chip R divider register
(Register R2) is programmed (see Figure 27).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
when operating the ADF4159 at frequencies greater than 8 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
•
•
Prescaler = 4/5: NMIN = 23
Prescaler = 8/9: NMIN = 75
CSR Enable
RDIV2
When Bit DB28 is set to 1, cycle slip reduction (CSR) is enabled.
Cycle slip reduction is a method for improving lock times. Note
that the signal at the PFD must have a 50% duty cycle for cycle
slip reduction to work. In addition, the charge pump current
setting must be set to its minimum value. For more information,
see the Cycle Slip Reduction for Faster Lock Times section.
When Bit DB21 is set to 1, a divide-by-2 toggle flip-flop is
inserted between the R counter and the PFD. This feature
can be used to provide a 50% duty cycle signal at the PFD.
The cycle slip reduction feature can be used only when the phase
detector polarity setting is positive (Bit DB6 = 1 in Register R3).
CSR cannot be used if the phase detector polarity setting is negative (Bit DB6 = 0 in Register R3).
Charge Pump Current Setting
Bits DB[27:24] set the charge pump current (see Figure 27).
Set these bits to the charge pump current that the loop filter
is designed with. Best practice is to design the loop filter for a
charge pump current of 2.5 mA or 2.81 mA and then use the
programmable charge pump current to tweak the frequency
response. See the Reference Doubler section for information on
setting the charge pump current when the doubler is enabled.
Prescaler (P/P + 1)
Reference Doubler
When Bit DB20 is set to 0, the reference doubler is disabled,
and the REFIN signal is fed directly to the 5-bit R counter. When
Bit DB20 is set to 1, the reference doubler is enabled, and the REFIN
frequency is multiplied by a factor of 2 before the signal is fed into
the 5-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
When the reference doubler is enabled, for optimum phase
noise performance, it is recommended to only use charge pump
current settings 0b0000 to 0b0111, that is, 0.31 mA to 2.5 mA.
In this case, best practice is to design the loop filter to for a
charge pump current of 1.25 mA or 1.57 mA and then use the
programmable charge pump current to tweak the frequency
response.
5-Bit R Counter
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and fixed modulus values, determines the overall
division ratio from RFIN to the PFD input. Bit DB22 sets the
prescaler value.
The 5-bit R counter (Bits DB[19:15]) allows the input reference
frequency (REFIN) to be divided down to supply the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
Operating at CML levels, the prescaler takes the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 8 GHz. Therefore,
Bits DB[14:3] program the CLK1 divider value, which determines
the duration of the time step in ramp mode.
12-Bit CLK1 Divider Value
Rev. B | Page 16 of 36
DBB
REFERENCE
DOUBLER DBB
RESERVED
RDIV2 DBB
CSR
DBB
CP
CURRENT
SETTING
PRESCALER
ADF4159
RESERVED
Data Sheet
DBB
5-BIT R COUNTER
CONTROL
BITS
12-BIT CLK1 DIVIDER VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
CR1
0
CR1 CPI4 CPI3 CPI2 CPI1
0
P1
U2
CYCLE SLIP
REDUCTION
0
DISABLED
1
ENABLED
U1
R5
R4
R3
U1
REFERENCE
DOUBLER
R2
R1
D12
D11
D10
D9
D8
D7
0
DISABLED
D12
D11
...
D2
D1
1
ENABLED
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
U2
R DIVIDER
0
DISABLED
1
ENABLED
ICP (mA)
CPI4
CPI3
CPI2
CPI1
5.1kΩ
0
0
0
0
0.31
P1
0
0
0
1
0.63
0
4/5
0
0
1
0
0.94
1
8/9
0
0
1
1
1.25
0
1
0
0
1.57
0
1
0
1
1.88
R5
R4
R3
R2
R1
0
1
1
0
2.19
0
0
0
0
1
1
0
1
1
1
2.5
0
0
0
1
0
2
1
0
0
0
2.81
0
0
0
1
1
3
1
0
0
1
3.13
0
0
1
0
0
4
1
0
1
0
3.44
.
.
.
.
.
1
0
1
1
3.75
.
.
.
.
.
1
1
0
0
4.06
.
.
.
.
.
1
1
0
1
4.38
1
1
1
0
1
29
1
1
1
0
4.69
1
1
1
1
0
30
1
1
1
1
5.0
1
1
1
1
1
31
0
0
0
0
0
32
PRESCALER
D6
D5
D4
D3
D2
D1
C3(0) C2(1) C1(0)
CLK 1 DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
R COUNTER DIVIDE RATIO
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 27. R Divider Register (R2) Map
Rev. B | Page 17 of 36
10849-022
0
ADF4159
Data Sheet
FUNCTION REGISTER (R3) MAP
When Bits DB[2:0] are set to 011, the on-chip function register
(Register R3) is programmed (see Figure 28).
Reserved Bits
All reserved bits except Bit DB17 must be set to 0 for normal
operation. Bit DB17 must be set to 1 for normal operation.
Negative Bleed Current
Bits DB[24:22] set the negative bleed current value (IBLEED).
Calculate IBLEED using the following formula, and then select the
value of Bits DB[24:22] that is closest to the calculated value.
IBLEED = (4 × ICP)/N
FRAC values to be loaded at the same time, preventing frequency
overshoot. The delay is turned on by setting Bit DB15 to 1.
Σ-Δ Reset
For most applications, Bit DB14 should be set to 0. When this bit is
set to 0, the Σ-Δ modulator is reset on each write to Register R0.
If it is not required that the Σ-Δ modulator be reset on each write
to Register R0, set this bit to 1.
Ramp Mode
Bits DB[11:10] determine the type of generated waveform (see
Figure 28 and the Waveform Generation section).
PSK Enable
When Bit DB9 is set to 1, PSK modulation is enabled. When
this bit is set to 0, PSK modulation is disabled. For more information, see the Phase Shift Keying (PSK) section.
where:
ICP is the charge pump current.
N is the N counter value.
FSK Enable
Negative Bleed Current Enable
DB21 enables a negative bleed current in the charge pump.
When the charge pump is operating in a nonlinear region,
phase noise and spurious performance can degrade. Negative
bleed current operates by pushing the charge pump operation
region away from this nonlinear region. The programmability
feature controls how far the region of operation is moved. If the
current is too little, the charge pump will remain in the nonlinear region; if the current is too high, the charge pump will
become unstable or degrade the maximum PFD frequency. It
is necessary to experiment with various charge pump currents
to find the optimum.
The formula for calculating the optimum negative bleed current
is shown in the Negative Bleed Current section; however, experimentation may show a different current gives the optimum
result.
When Bit DB8 is set to 1, FSK modulation is enabled. When
this bit is set to 0, FSK modulation is disabled. For more information, see the Frequency Shift Keying (FSK) section.
Lock Detect Precision (LDP)
The digital lock detect circuit monitors the PFD up and down
pulses (logical OR of the up and down pulses; see Figure 21).
Every 32nd pulse is measured. The LDP bit (Bit DB7) specifies
the length of each lock detect reference cycle.
•
•
LDP = 0: if five consecutive pulses of less than 14 ns are
measured, digital lock detect is asserted.
LDP = 1: if five consecutive pulses of less than 6 ns are
measured, digital lock detect is asserted.
Digital lock detect remains asserted until the pulse width exceeds
22 ns, a write to Register R0 occurs, or the part is powered down.
Loss of Lock (LOL)
Phase Detector (PD) Polarity
Bit DB16 enables or disables the loss of lock indication. When
this bit is set to 0 (loss of lock enabled), the part indicates loss of
lock even when the reference is removed. This feature provides
an advantage over the standard implementation of lock detect.
The loss of lock feature may not operate as expected when
negative bleed current is enabled.
Bit DB6 sets the phase detector polarity. When the VCO
characteristics are positive, set this bit to 1. When the VCO
characteristics are negative, set this bit to 0.
N SEL
Bit DB15 can be used to circumvent the issue of pipeline delay
between updates of the integer and fractional values in the
N counter. Typically, the INT value is loaded first, followed by
the FRAC value. This can cause the N counter value to be incorrect for a brief period of time equal to the pipeline delay (about
four PFD cycles). This delay has no effect if the INT value was not
updated. However, if the INT value has changed, this incorrect
N counter value can cause the PLL to overshoot in frequency
while it tries to lock to the temporarily incorrect N counter value.
After the correct fractional value is loaded, the PLL quickly locks
to the correct frequency. Introducing an additional delay to the
loading of the INT value using the N SEL bit causes the INT and
Power-Down
Bit DB5 provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. When the part is in software
power-down mode, it retains all information in its registers. The
register contents are lost only when the supplies are removed.
When power-down is activated, the following events occur:
•
•
•
•
•
•
Rev. B | Page 18 of 36
All active dc current paths are removed.
The RF synthesizer counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFIN input is debiased.
The input shift register remains active and capable
of loading and latching data.
Data Sheet
ADF4159
CP
THREE-STATE
COUNTER
RESET
POWER-DOWN
PD
POLARITY
LDP
FSK
PSK
RESERVED
Σ-Δ
RESET
RESERVED
N SEL
NEG BLEED
CURRENT
RESERVED
RAMP MODE
Bit DB3 is the RF counter reset bit. When this bit is set to 1, the
RF synthesizer counters are held in reset. For normal operation,
set this bit to 0.
LOL
When Bit DB4 is set to 1, the charge pump is placed into threestate mode. For normal charge pump operation, set this bit to 0.
RESERVED
Counter Reset
NEG BLEED EN
Charge Pump Three-State
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
NEG BLEED EN
0
DISABLED
1
ENABLED
0
NB3 NB2 NB1
0
L1
LOL
0
ENABLED
1
DISABLED
0
0
1
L1
NS1
U12
0
0
U12
Σ-Δ RESET
0
ENABLED
1
DISABLED
RM2 RM1
0
0
U10
U11
U9
U8
U7
C3(0) C2(1) C1(1)
U7
COUNTER
RESET
0
DISABLED
1
ENABLED
U8
NS1
NB3 NB2 NB1
0
CP
THREE-STATE
0
DISABLED
1
ENABLED
N SEL
0
N WORD LOAD ON Σ-Δ CLOCK
1
N WORD LOAD DELAYED 4 CYCLES
U9
POWER-DOWN
0
DISABLED
1
ENABLED
NEGATIVE BLEED CURRENT (µA)
RM2 RM1
RAMP MODE
0
0
0
3.73
0
0
1
11.03
0
0
CONTINUOUS SAWTOOTH
0
NEGATIVE
0
1
0
25.25
0
1
CONTINUOUS TRIANGULAR
1
POSITIVE
0
1
1
53.1
1
0
SINGLE SAWTOOTH BURST
1
1
0
0
0
1
109.7
1
1
SINGLE RAMP BURST
1
1
1
1
0
1
454.7
U10
U11
LDP
0
14ns
1
6ns
224.7
916.4
Figure 28. Function Register (R3) Map
Rev. B | Page 19 of 36
0
FSK
0
DISABLED
1
ENABLED
0
PSK
0
DISABLED
1
ENABLED
PD POLARITY
10849-023
0
0
ADF4159
Data Sheet
CLOCK REGISTER (R4) MAP
When using the readback to MUXOUT or ramp complete
to MUXOUT option, the MUXOUT bits in Register R0
(Bits DB[30:27]) must be set to 1111.
When Bits DB[2:0] are set to 100, the on-chip clock register
(Register R4) is programmed (see Figure 29).
Clock Divider Mode
LE SEL
Bits DB[20:19] specify whether the 12-bit clock divider functions as a counter for the ramp functions (CLK2) or is turned
off. These bits are also used to enable the fast lock divider (see
the Fast Lock Mode section).
In some applications, it is necessary to synchronize the LE pin
with the reference signal. To do this, Bit DB31 must be set to 1.
Synchronization is done internally on the part.
Reserved Bits
12-Bit CLK2 Divider Value
All reserved bits must be set to 0 for normal operation.
Bits DB[18:7] program the clock divider (the CLK2 timer) when
the part operates in ramp mode (see the Timeout Interval section).
The CLK2 timer also determines how long the loop remains in
wideband mode when fast lock mode is used (see the Fast Lock
Mode section).
Ramp Status
Bits DB[25:21] provide access to the following advanced
features (see Figure 29):
RESERVED
CLK
DIV
MODE
RAMP STATUS
Bit DB6 selects the clock divider that is loaded with the 12-bit
clock divider value. When Bit DB6 is set to 0, CLK1 is loaded; when
Bit DB6 is set to 1, CLK2 for Ramp 1 or Ramp 2 is loaded. For more
information, see the Waveform Deviations and Timing section.
12-BIT CLK2 DIVIDER VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
LS1
0
0
0
0
0
R5
R4
R3
R2
R1
C2
C1
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
CS1
CS1
R5 R4 R3 R2 R1
0
0
0
1
1
LS1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
LE FROM PIN
1
LE SYNCH WITH REFIN
CONTROL
BITS
DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
C3(1) C2(0) C1(0)
CLK DIV SEL
RAMP STATUS
0
LOAD CLK DIV 1
NORMAL OPERATION
READBACK TO MUXOUT
RAMP COMPLETE TO MUXOUT
CHARGE PUMP UP
CHARGE PUMP DOWN
1
LOAD CLK DIV 2
LE SEL
0
RESERVED
C2
C1
0
0
1
1
0
1
0
1
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
FAST LOCK DIVIDER
RESERVED
RAMP DIVIDER
D12
D11
...
D2
D1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
Figure 29. Clock Register (R4) Map
Rev. B | Page 20 of 36
CLK2 DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
10849-024
•
Clock Divider Select
CLK DIV SEL
•
Readback to MUXOUT option: the synthesizer frequency
at the moment of interruption can be read back (see the
Interrupt Modes and Frequency Readback section).
Ramp complete to MUXOUT option: a logic high pulse
is output on the MUXOUT pin at the end of each ramp.
Charge pump up and charge pump down options: the
charge pump is forced to constantly output up or down
pulses, respectively.
LE SEL
•
Data Sheet
ADF4159
DEVIATION REGISTER (R5) MAP
Interrupt
When Bits DB[2:0] are set to 101, the on-chip deviation register
(Register R5) is programmed (see Figure 30).
Bits DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FRAC value of a
ramp at a given moment in time (a rising edge on the TXDATA
pin triggers the interrupt). From the INT and FRAC bits, the
frequency can be obtained. After readback, the sweep can continue
or stop at the readback frequency. For more information, see the
Interrupt Modes and Frequency Readback section.
Reserved Bit
The reserved bit must be set to 0 for normal operation.
TXDATA Invert
When Bit DB30 is set to 0, events triggered by TXDATA occur
on the rising edge of the TXDATA pulse. When Bit DB30 is set
to 1, events triggered by TXDATA occur on the falling edge of
the TXDATA pulse.
FSK Ramp Enable
When Bit DB25 is set to 1, the FSK ramp is enabled. When
Bit DB25 is set to 0, the FSK ramp is disabled.
TXDATA Ramp Clock
Dual Ramp Enable
When Bit DB29 is set to 0, the clock divider clock is used to
clock the ramp. When Bit DB29 is set to 1, the TXDATA clock
is used to clock the ramp.
When Bit DB24 is set to 1, the second ramp is enabled. When
Bit DB24 is set to 0, the second ramp is disabled.
Deviation Select
Parabolic Ramp
When Bit DB23 is set to 0, the first deviation word is selected.
When Bit DB23 is set to 1, the second deviation word is selected.
When Bit DB28 is set to 1, the parabolic ramp is enabled. When
Bit DB28 is set to 0, the parabolic ramp is disabled. For more
information, see the Parabolic (Nonlinear) Ramp Mode section.
4-Bit Deviation Offset Word
Bits DB[22:19] determine the deviation offset word. The deviation offset word affects the deviation resolution.
16-Bit Deviation Word
DEV SEL
FSK RAMP
DUAL RAMP
INTERRUPT
TXDATA RAMP
CLK
PARABOLIC
RAMP
RESERVED
TXDATA INVERT
Bits DB[18:3] determine the signed deviation word. The
deviation word defines the deviation step.
4-BIT DEVIATION
OFFSET WORD
CONTROL
BITS
16-BIT DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
TR1
0
I2
I1
0
0
DS1 DO4 DO3 DO2 DO1 D16
0
TXDATA INVERT
0
DUAL RAMP
0
DISABLED
0
DISABLED
0
DEV WORD 1
1
ENABLED
1
ENABLED
1
DEV WORD 2
TR1 TXDATA RAMP CLK
0
1
CLK DIV
TXDATA
0
FSK RAMP
0
DISABLED
1
ENABLED
DS1
D15 D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C3(1) C2(0) C1(1)
DEV SEL
D16
D15
...
D2
D1
0
1
...
1
1
DEVIATION WORD
32,767
.
.
...
.
.
.
DEV OFFSET WORD
0
0
...
1
1
3
0
0
0
0
0
0
0
...
1
0
2
0
0
0
1
1
0
0
...
0
1
1
DO4 DO3 DO2 DO1
0
PARABOLIC RAMP
0
0
1
0
2
0
0
...
0
0
0
0
DISABLED
.
.
.
.
.
1
1
...
1
1
–1
1
ENABLED
.
.
.
.
.
1
1
...
1
0
–2
0
1
1
1
7
1
1
1
–3
.
0
...
...
...
0
.
1
.
0
.
0
.
–32,768
I1
INTERRUPT
1
0
0
0
8
0
0
INTERRUPT OFF
1
0
0
1
9
0
1
LOAD CHANNEL CONTINUE SWEEP
1
0
NOT USED
1
1
LOAD CHANNEL STOP SWEEP
10849-025
I2
Figure 30. Deviation Register (R5) Map
Rev. B | Page 21 of 36
ADF4159
Data Sheet
Step Select
When Bits DB[2:0] are set to 110, the on-chip step register
(Register R6) is programmed (see Figure 31).
When Bit DB23 is set to 0, Step Word 1 is selected. When
Bit DB23 is set to 1, Step Word 2 is selected.
Reserved Bits
20-Bit Step Word
All reserved bits must be set to 0 for normal operation.
Bits DB[22:3] determine the step word. The step word is the
number of steps in the ramp.
STEP SEL
STEP REGISTER (R6) MAP
RESERVED
CONTROL
BITS
20-BIT STEP WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
SSE1 S20
S19
S18
SSE1 STEP SEL
0
STEP WORD 1
1
STEP WORD 2
S17
S16
S15 S14
S13
S12
S11
S10
S20
S19
...
S2
S1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
Figure 31. Step Register (R6) Map
Rev. B | Page 22 of 36
S9
S8
S7
S6
S5
S4
S3
S2
S1
C3(1) C2(1) C1(0)
STEP WORD
0
1
2
3
.
.
.
1,048,572
1,048,573
1,048,574
1,048,575
10849-026
0
Data Sheet
ADF4159
DELAY REGISTER (R7) MAP
Fast Ramp
When Bits DB[2:0] are set to 111, the on-chip delay register
(Register R7) is programmed (see Figure 32).
When Bit DB19 is set to 1, the triangular waveform is activated
with two different slopes. This waveform can be used as an alternative to the sawtooth ramp because it mitigates the overshoot
at the end of the ramp in a waveform. Fast ramp is achieved by
changing the top frequency to the bottom frequency in a series of
small steps instead of one big step. When Bit DB19 is set to 0, the
fast ramp function is disabled (see the Fast Ramp Mode section).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
TXDATA Trigger Delay
When Bit DB23 is set to 0, there is no delay before the start of
the ramp when using TXDATA to trigger a ramp. When Bit DB23
is set to 1, a delay is enabled before the start of the ramp if the
delayed start is enabled via Bit DB15.
Ramp Delay Fast Lock
When Bit DB18 is set to 1, the ramp delay fast lock function is
enabled. When Bit DB18 is set to 0, this function is disabled.
Triangular Delay
Ramp Delay
When Bit DB22 is set to 1, a delay is enabled between each
section of a triangular ramp, resulting in a clipped ramp. This
setting works only for triangular ramps and when the ramp
delay is activated. When Bit DB22 is set to 0, the delay between
triangular ramps is disabled.
When Bit DB17 is set to 1, the delay between ramps function is
enabled. When Bit DB17 is set to 0, this function is disabled.
Delay Clock Select
When Bit DB16 is set to 0, the PFD clock is selected as the delay
clock. When Bit DB16 is set to 1, PFD clock × CLK1 is selected
as the delay clock. (CLK1 is set by Bits DB[14:3] in Register R2.)
Single Full Triangle
When Bit DB21 is set to 1, the single full triangle function is
enabled. When Bit DB21 is set to 0, this function is disabled.
For more information, see the Waveform Generation section.
Delayed Start Enable
When Bit DB15 is set to 1, the delayed start is enabled. When
Bit DB15 is set to 0, the delayed start is disabled.
TXDATA Trigger
12-Bit Delay Start Word
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
TD1
TD1 TRI DELAY
0
DISABLED
1
ENABLED
0
TXDATA TRIGGER DELAY
0
DISABLED
1
ENABLED
ST1
TR1
0
FR1
RD1 DC1 DSE1 DS12 DS11 DS10 DS9
0
0
RAMP DELAY FL
DISABLED
1
ENABLED
DS12 DS11
0
DISABLED
1
ENABLED
1
TR1 TXDATA TRIGGER
DB7
DB6
DB5
DB4
DB3
DS6
DS5 DS4
DS3
DS2
DS1 C3(1) C2(1) C1(1)
DS2
DS1
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
4092
RAMP DELAY
1
1
...
0
1
4093
DC1
0
1
RD1
DB8
...
0
1
ENABLED
DS7
0
DSE1 DEL START EN
ST1 SING FULL TRI
0
DISABLED
DS8
0
FR1 FAST RAMP
DISABLED
ENABLED
DEL CLK SEL
PFD CLK
PFD CLK × CLK1
DISABLED
0
DISABLED
1
1
...
1
0
4094
1
ENABLED
1
ENABLED
1
1
...
1
1
4095
Figure 32. Delay Register (R7) Map
DB2
DB1
DB0
DELAY START WORD
0
Rev. B | Page 23 of 36
CONTROL
BITS
12-BIT DELAY START WORD
10849-027
DEL START EN
Bits DB[14:3] determine the delay start word. The delay start
word affects the duration of the ramp start delay.
DEL CLK SEL
RAMP DELAY
RAMP DELAY FL
FAST RAMP
TXDATA
TRIGGER
TRI DELAY
RESERVED
SING FULL TRI
TXDATA
TRIGGER DELAY
When Bit DB20 is set to 1, a logic high on TXDATA activates the
ramp. When Bit DB20 is set to 0, this function is disabled.
ADF4159
Data Sheet
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
REFERENCE DOUBLER
After powering up the ADF4159, initialize the part by programming the registers in the following sequence:
The on-chip reference doubler allows the input reference signal to
be doubled. This doubling is useful for increasing the PFD comparison frequency. Doubling the PFD frequency usually improves
the noise performance of the system by 3 dB. It is important to
note that the PFD cannot be operated above 110 MHz due to a
limitation in the speed of the Σ-Δ circuit of the N divider.
1.
2.
3.
4.
5.
6.
7.
8.
Delay register (R7).
Step register (R6). Load the step register twice, first with
STEP SEL = 0 and then with STEP SEL = 1.
Deviation register (R5). Load the deviation register twice,
first with DEV SEL = 0 and then with DEV SEL = 1.
Clock register (R4). Load the clock register twice, first with
CLK DIV SEL = 0 and then with CLK DIV SEL = 1.
Function register (R3).
R divider register (R2).
LSB FRAC register (R1).
FRAC/INT register (R0).
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using cycle
slip reduction, the loop bandwidth can be kept narrow to reduce
integrated phase noise and attenuate spurs while still realizing fast
lock times.
RF SYNTHESIZER WORKED EXAMPLE
Cycle Slips
The following equation governs how the synthesizer must
be programmed.
Cycle slips occur in integer-N/fractional-N synthesizers when the
loop bandwidth is narrow compared with the PFD frequency. The
phase error at the PFD inputs accumulates too fast for the PLL to
correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4159
contains a cycle slip reduction circuit to extend the linear range
of the PFD, allowing faster lock times without loop filter changes.
RFOUT = (INT + (FRAC/225)) × fPFD
(4)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
The PFD frequency (fPFD) equation is
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(5)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit, Bit DB20 in Register R2 (0 or 1).
R is the RF reference division factor (1 to 32).
T is the reference divide-by-2 bit, Bit DB21 in Register R2 (0 or 1).
For example, in a system where a 12.102 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, the frequency resolution is
fRES = REFIN/225
(6)
fRES = 100 MHz/225 = 2.98 Hz
If the phase error increases again to a point where another cycle
slip is likely, the ADF4159 turns on another charge pump cell. This
continues until the ADF4159 detects that the VCO frequency has
exceeded the desired frequency. It then begins to turn off the
extra charge pump cells one by one until they are all turned off
and the frequency is settled.
Up to seven extra charge pump cells can be turned on. In most
applications, seven cells is enough to eliminate cycle slips altogether, giving much faster lock times.
From Equation 5,
fPFD = [100 MHz × (1 + 0)/1] = 100 MHz
12.102 GHz = 100 MHz × (N + FRAC/225)
Calculating the N and FRAC values,
N = int(RFOUT/fPFD) = 121
FRAC = FMSB × 213 + FLSB
FMSB = int(((RFOUT/fPFD) − N) × 212) = 81
FLSB = int(((((RFOUT/fPFD) − N) × 212) − FMSB) × 213) = 7536
where:
FMSB is the 12-bit MSB FRAC value in Register R0.
FLSB is the 13-bit LSB FRAC value in Register R1.
int() makes an integer of the argument in parentheses.
When the ADF4159 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a constant
current to the loop filter or removes a constant current from the
loop filter (depending on whether the VCO tuning voltage must
increase or decrease to acquire the new frequency). The effect is
that the linear range of the PFD is increased. Stability is maintained
because the current is constant and is not a pulsed current.
When Bit DB28 in the R divider register (Register R2) is set to 1,
cycle slip reduction is enabled. Note that a 45% to 55% duty cycle
is needed on the signal at the PFD in order for CSR to operate
correctly. The reference divide-by-2 flip-flop can help to provide
a 50% duty cycle at the PFD. For example, if a 100 MHz reference
frequency is available and the user wants to run the PFD at
10 MHz, setting the R divide factor to 10 results in a 10 MHz PFD
signal that is not 50% duty cycle. By setting the R divide factor
to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle
10 MHz signal can be achieved.
Rev. B | Page 24 of 36
Data Sheet
ADF4159
Note that the cycle slip reduction feature can only be operated
when the phase detector polarity setting is positive (Bit DB6 in
Register R3 is set to 1). It cannot be used if the phase detector
polarity is negative.
MODULATION
The ADF4159 can operate in frequency shift keying (FSK) or
phase shift keying (PSK) mode.
The ADF4159 is capable of generating five types of waveforms
in the frequency domain: single ramp burst, single triangular
burst, single sawtooth burst, continuous sawtooth ramp, and
continuous triangular ramp. Figure 33 through Figure 37 show
the types of waveforms available.
FSK is implemented by configuring the ADF4159 N divider
for the center frequency and then toggling the TXDATA pin.
The deviation from the center frequency is set by
fDEV = (fPFD/225) × (DEV × 2DEV_OFFSET)
(7)
The ADF4159 implements fDEV by incrementing or decrementing
the configured N divider value by DEV × 2DEV_OFFSET.
TIME
Figure 33. Single Ramp Burst
FREQUENCY
where:
fPFD is the PFD frequency.
DEV is a 16-bit word (Bits DB[18:3] in Register R5).
DEV_OFFSET is a 4-bit word (Bits DB[22:19] in Register R5).
10849-028
FREQUENCY
Frequency Shift Keying (FSK)
WAVEFORM GENERATION
In this example, an FSK system operates at 5.8 GHz with a
25 MHz fPFD, requiring 250 kHz deviation (fDEV).
10849-029
FSK Settings Worked Example
TIME
Figure 34. Single Triangular Burst
Rearrange Equation 7 as follows:
(DEV × 2DEV_OFFSET) = 250 kHz/(25 MHz/225)
(DEV × 2DEV_OFFSET) = 335,544.32
If DEV_OFFSET is set to 6,
DEV = 335,544.32/(26) = 5242.88 ≈ 5243
TIME
10849-030
FREQUENCY
(DEV × 2DEV_OFFSET) = fDEV/(fPFD/225)
Figure 35. Single Sawtooth Burst
Phase Shift Keying (PSK)
When the ADF4159 is configured for PSK mode, the output
phase of the ADF4159 is equal to
(Phase Value × 360°)/212
TIME
10849-031
Toggling the TXDATA pin causes the frequency to hop between
±250 kHz from the programmed center frequency.
FREQUENCY
Due to the rounding of DEV, fDEV = 250.005722 kHz.
Figure 36. Continuous Sawtooth Ramp
TIME
Figure 37. Continuous Triangular Ramp
Rev. B | Page 25 of 36
10849-032
For example, if the phase value is 1024, a logic high on the TXDATA
pin results in a 90° increase of the output phase. A logic low on
the TXDATA pin results in a 90° decrease of the output phase. The
polarity can be inverted by negating the phase value.
FREQUENCY
The phase value is set in Register 1, Bits DB[14:3]. The PSK
modulation is controlled by the TXDATA pin.
ADF4159
Data Sheet
WAVEFORM DEVIATIONS AND TIMING
SINGLE SAWTOOTH BURST
Figure 38 shows a version of a ramp.
In the single sawtooth burst, the N divider value is reset to its
initial value on the next timeout interval after the number of
steps has taken place. The ADF4159 retains this N divider value.
TIMER
SAWTOOTH RAMP
FREQUENCY
fDEV
10849-033
The sawtooth ramp is a repeated version of the single sawtooth
burst. The waveform is repeated until the ramp is disabled.
TIME
Figure 38. Waveform Timing
The key parameters that define a ramp are



Frequency deviation
Timeout interval
Number of steps
TRIANGULAR RAMP
The triangular ramp is a repeated version of the single triangular burst. However, when the steps are completed, the ADF4159
begins to decrement the N divider value by DEV × 2DEV_OFFSET on
each timeout interval. When the number of steps has again been
completed, the part reverts to incrementing the N divider value.
Repeating this pattern creates a triangular waveform. The waveform is repeated until the ramp is disabled.
Frequency Deviation
FMCW RADAR RAMP SETTINGS WORKED EXAMPLE
The frequency deviation for each frequency hop is set by
This example describes a frequency modulated continuous wave
(FMCW) radar system that requires the RF LO to use a sawtooth
ramp over a 50 MHz range every 2 ms. The PFD frequency is
25 MHz, and the RF output range is 5800 MHz to 5850 MHz.
fDEV = (fPFD/225) × (DEV × 2DEV_OFFSET)
(7)
where:
fPFD is the PFD frequency.
DEV is a 16-bit word (Bits DB[18:3] in Register R5).
DEV_OFFSET is a 4-bit word (Bits DB[22:19] in Register R5).
The frequency deviation for each hop in the ramp is set to
~250 kHz.
The frequency resolution of the ADF4159 is calculated
as follows:
Timeout Interval
The time between each frequency hop is set by
Timer = CLK1 × CLK2 × (1/fPFD)
fRES = fPFD/225
(8)
where:
CLK1 and CLK2 are the 12-bit clock values (12-bit CLK1 divider in
Register R2 and 12-bit CLK2 divider in Register R4). Bits DB[20:19]
in Register R4 must be set to 11 for ramp divider.
fPFD is the PFD frequency.
Number of Steps
A 20-bit step value (Bits DB[22:3] in Register R6) defines the
number of frequency hops that take place. The INT value cannot
be incremented by more than 28 = 256 from its starting value.
SINGLE RAMP BURST
The most basic waveform is the single ramp burst. All other
waveforms are variations of this waveform. In the single ramp
burst, the ADF4159 is locked to the frequency defined in the
FRAC/INT register (R0). When the ramp mode is enabled, the
ADF4159 increments the N divider value by DEV × 2DEV_OFFSET,
causing a frequency shift, fDEV, on each timer interval. This shift
is repeated until the set number of steps has taken place. The
ADF4159 then retains the final N divider value.
(9)
Using Equation 9, fRES is calculated as follows:
fRES = 25 MHz/225 = 0.745 Hz
DEV_OFFSET is calculated after rearranging Equation 7.
DEV_OFFSET = log2(fDEV/(fRES × DEVMAX))
(10)
Expressed in log10(x), Equation 10 can be rearranged into
the following equation:
DEV_OFFSET = log10(fDEV/(fRES × DEVMAX))/log10(2)
(11)
where:
fDEV is the frequency deviation.
DEVMAX = 215 (maximum value of the deviation word).
DEV_OFFSET is a 4-bit word.
Using Equation 11, DEV_OFFSET is calculated as follows:
DEV_OFFSET = log10(250 kHz/(0.745 Hz × 215))/log10(2) = 3.356
After rounding, DEV_OFFSET = 4.
From DEV_OFFSET, the resolution of the frequency deviation
can be calculated as follows:
SINGLE TRIANGULAR BURST
fDEV_RES = fRES × 2DEV_OFFSET
4
fDEV_RES = 0.745 Hz × 2 = 11.92 Hz
The single triangular burst is similar to the single ramp burst.
However, when the steps are completed, the ADF4159 begins
to decrement the N divider value by DEV × 2DEV_OFFSET on each
timeout interval.
Rev. B | Page 26 of 36
(12)
Data Sheet
ADF4159
OTHER WAVEFORMS
To calculate the DEV word, use Equation 13.
DEV =
(13)
Dual Ramps with Different Ramp Rates
The ADF4159 can be configured for two ramps with different
step and deviation settings. It also allows the ramp rate to be
reprogrammed while another ramp is running.
250 kH z
= 20,971.52
25 MHz 4
×2
2 25
Rounding this value to 20,972 and recalculating using Equation 7
to obtain the actual deviation frequency, fDEV, thus produces the
following:
Example
In this example, the PLL is locked to 5790 MHz and
fPFD = 25 MHz. Two ramps are configured, as follows:
•
fDEV = (25 MHz/225) × (20,972 × 24) = 250.006 kHz
Ramp 1 jumps 100 steps; each step lasts 10 µs and has a
frequency deviation of 100 kHz.
Ramp 2 jumps 80 steps; each step lasts 10 µs and has a
frequency deviation of 125 kHz.
The number of fDEV steps required to cover the 50 MHz range
is 50 MHz/250.006 kHz = 200. To cover the 50 MHz range in
2 ms, the ADF4159 must hop every 2 ms/200 = 10 µs.
•
Rearrange Equation 8 to set the timer value (and set CLK2 to 1):
To enable the two ramp rates, follow these steps:
1.
CLK1 = Timer × fPFD/CLK2 = 10 µs × 25 MHz/1 = 250
To summarize the settings,
•
•
•
•
DEV = 20,972
Number of steps = 200
CLK1 = 250
CLK2 = 1 (Bits DB[20:19] = 11, ramp divider, in Register R4)
Using these settings, program the ADF4159 to a center frequency
of 5800 MHz and enable the sawtooth ramp to produce the
required waveform. If a triangular ramp is used with the same
settings, the ADF4159 sweeps from 5800 MHz to 5850 MHz and
back down again, taking 4 ms for the entire sweep.
2.
•
•
3.
•
Ramp Programming Sequence
The setting of parameters described in the FMCW Radar Ramp
Settings Worked Example section and the activation of the ramp
described in the Activating the Ramp section must be completed
in the following register write order:
Register R5: set Bit DB23 = 1, Bits DB[18:3] = 20,972,
and Bits DB[22:19] = 3
Register R6: set Bit DB23 = 1 and Bits DB[22:3] = 80
Figure 39 shows the resulting ramp with two ramp rates. To
activate the ramp, see the Activating the Ramp section.
SWEEP RATE SET BY OTHER REGISTER
FREQUENCY
After setting all required parameters, the ramp must be activated by
choosing the desired type of ramp (Bits DB[11:10] in Register R3)
and starting the ramp (Bit DB31 = 1 in Register R0).
Register R5: set Bit DB23 = 0, Bits DB[18:3] = 16,777,
and Bits DB[22:19] = 3
Register R6: set Bit DB23 = 0 and Bits DB[22:3] = 100
Program the ramp rate for Ramp 2 by setting the following
values:
•
ACTIVATING THE RAMP
1.
2.
3.
4.
5.
6.
7.
8.
Activate the dual ramp rates mode by setting Bit DB24
in Register R5 to 1.
Program the ramp rate for Ramp 1 by setting the following
values:
Delay register (R7)
Step register (R6)
Deviation register (R5)
Clock register (R4)
Function register (R3)
R divider register (R2)
LSB FRAC register (R1)
FRAC/INT register (R0)
SWEEP RATE SET BY ONE REGISTER
TIME
Figure 39. Dual Ramp with Two Sweep Rates
Rev. B | Page 27 of 36
10849-134
DEV = fDEV/(fRES × 2DEV_OFFSET)
ADF4159
Data Sheet
Ramp Mode with Superimposed FSK Signal
Delayed Start
In traditional approaches, FMCW radars use either linear
frequency modulation (LFM) or FSK modulation. Used separately, these modulations introduce ambiguity between measured
distance and velocity, especially in multitarget situations. To overcome this issue and enable unambiguous (distance and velocity)
multitarget detection, use a ramp with FSK superimposed on it.
A delayed start can be used with two different parts to control
the start time. Figure 41 shows the theory of delayed start.
•
RAMP WITH
DELAYED START
TIME
Figure 41. Delayed Start of Sawtooth Ramp
The number of steps is set to 100; each step lasts 10 µs
and has a deviation of 100 kHz.
The FSK signal is 25 kHz.
•
Example
For example, to program a delayed start with two different parts
to control the start time, follow these steps:
To enable ramp mode with FSK superimposed on it, follow
these steps:
1.
2.
3.
1.
Set Bit DB23 in Register R5 and Bit DB23 in Register R6
to 0.
Program the ramp as described in the FMCW Radar Ramp
Settings Worked Example section.
Program FSK on the ramp to 25 kHz by setting the bits in
Register R5 as follows:
•
•
•
•
DB[18:3] = 4194 (deviation word)
DB[22:19] = 3 (deviation offset word)
DB23 = 1 (deviation word for FSK on the ramp)
DB25 = 1 (ramp with FSK enabled)
2.
Enable the delayed start of ramp option by setting Bit DB15
in Register R7 to 1.
Delay the ramp on the first part by 5 µs by setting Bit DB16
in Register R7 to 0 and setting the 12-bit delay start word
(Bits DB[14:3] in Register R7) to 125 (fPFD = 25 MHz). The
delay is calculated as follows:
Delay = tPFD × Delay Start Word
Delay = 40 ns × 125 = 5 µs
3.
Figure 40 shows an example of a ramp with FSK superimposed
on it. To activate the ramp, see the Activating the Ramp section.
Delay the ramp on the second part by 125 µs by setting
Bit DB16 in Register R7 to 1 and setting the 12-bit delay
start word (Bits DB[14:3] in Register R7) to 125. The delay
is calculated as follows:
Delay = tPFD × CLK1 × Delay Start Word
Delay = 40 ns × 25 × 125 = 125 µs
0
TIME
RAMP END
10849-135
LFMSTEP =
FREQUENCY
SWEEP/NUMBER
OF STEPS
FREQUENCY SWEEP
FREQUENCY
To activate the ramp, see the Activating the Ramp section.
FSK SHIFT
10849-034
In this example, the PLL is locked to 5790 MHz and fPFD =
25 MHz. The ramp with superimposed FSK is configured as
follows:
FREQUENCY
Example
RAMP WITHOUT
DELAYED START
Figure 40. Combined FSK and LFM Waveform
Rev. B | Page 28 of 36
Data Sheet
ADF4159
Delay Between Ramps
It is also possible to activate fast lock operation for the first
period of delay by setting Bit DB18 in Register R7 to 1. This
feature is useful for sawtooth ramps to mitigate the frequency
overshoot on the transition from one sawtooth to the next.
The ADF4159 can be configured to add a delay between bursts in
ramps. Figure 42, Figure 43, and Figure 44 show a delay between
ramps in sawtooth, triangular, and clipped triangular mode,
respectively.
To activate the ramp, see the Activating the Ramp section.
Dual Ramp Rates Mode with Delay
This mode combines the modes described in the Dual Ramps
with Different Ramp Rates section and the Delay Between
Ramps section (see Figure 45).
Figure 42. Delay Between Ramps for Sawtooth Mode
10849-140
TIME
FREQUENCY
10849-035
FREQUENCY
DELAY
FREQUENCY
TIME
Figure 45. Dual Ramp Rates Mode with Delay
10849-036
To enable this configuration,
TIME
Figure 43. Delay Between Ramps for Triangular Mode
1.
Program the two ramp rates mode as described in the
Dual Ramps with Different Ramp Rates section.
Program the delay as described in the Delay Between
Ramps section.
2.
Parabolic (Nonlinear) Ramp Mode
Example
For example, to add a delay between bursts in a ramp, follow
these steps:
1.
2.
Enable the delay between ramps option by setting Bit DB17
in Register R7 to 1.
Delay the ramp by 5 μs by setting Bit DB16 in Register R7
to 0 and setting the 12-bit delay start word (Bits DB[14:3] in
Register R7) to 125 (fPFD = 25 MHz). The delay is calculated
as follows:
Delay = tPFD × Delay Start Word
Delay = 40 ns × 125 = 5 μs
If a longer delay is needed, for example, 125 μs, set Bit DB16 in
Register R7 to 1, and set the 12-bit delay start word (Bits DB[14:3]
in Register R7) to 125. The delay is calculated as follows:
TIME
10849-141
10849-037
FREQUENCY
TIME
Figure 44. Delay Between Ramps for Clipped Triangular Mode
FREQUENCY
The ADF4159 is capable of generating a parabolic ramp (see
Figure 46).
DELAY
Figure 46. Parabolic Ramp
The output frequency is generated according to the following
equation:
fOUT(n + 1) = fOUT(n) + n × fDEV
where:
fOUT is the output frequency.
n is the step number.
fDEV is the frequency deviation.
Delay = tPFD × CLK1 × Delay Start Word
Delay = 40 ns × 25 × 125 = 125 μs
Rev. B | Page 29 of 36
(14)
ADF4159
Data Sheet
Example
To activate the fast ramp waveform, follow these steps:
This example describes how to set up and use the parabolic ramp
mode with the following parameters:
1.
•
•
•
•
fOUT = 5790 MHz
fDEV = 100 kHz
Number of steps = 50
Duration of a single step = 10 µs
Select the continuous triangular waveform by setting
Bits DB[11:10] in Register R3 to 01.
Enable the fast ramp by setting Bit DB19 in Register R7 to 1.
Program the up ramp as follows.
a. Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 0 for Ramp 1.
2.
3.
To set up the parabolic ramp mode, follow these steps:
1.
b.
Configure one of the following ramp modes:
•
•
Continuous triangular ramp (set Register R3,
Bits DB[11:10] to 01).
Single ramp burst (set Register R3, Bits DB[11:10]
to 11).
4.
Program the down ramp as follows.
a. Set Bit DB6 in Register R4 (CLK DIV SEL), Bit DB23
in Register R5 (DEV SEL), and Bit DB23 in Register R6
(STEP SEL) to 1 for Ramp 2.
For the continuous triangular ramp, the generated frequency
range is calculated as follows:
Δf = fDEV × (Number of Steps + 2) × (Number of Steps + 1)/2
= 132.6 MHz
For the single ramp burst, the generated frequency range is
calculated as follows:
Δf = fDEV × (Number of Steps + 1) × Number of Steps/2
= 127.5 MHz
4.
5.
Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
Start the ramp by setting Bit DB31 = 1 in Register R0.
Note that the total frequency change of the up and down ramps
must be equal for stability.
RAMP COMPLETE SIGNAL TO MUXOUT
Set the timer as described for the linear ramps in the
Timeout Interval section.
Activate the parabolic ramp by setting Bit DB28 in
Register R5 to 1.
Set the counter reset (Bit DB3 in Register R3) to 1 and then
set it to 0.
3.
b.
Figure 48 shows the ramp complete signal on MUXOUT.
FREQUENCY
2.
Calculate and program the timer, DEV, DEV_OFFSET,
and the step word as described in the FMCW Radar
Ramp Settings Worked Example section.
To activate the ramp, see the Activating the Ramp section.
TIME
TIME
Figure 48. Ramp Complete Signal on MUXOUT
TIME
10849-038
FREQUENCY
To activate this function, set Bits DB[30:27] in Register R0
to 1111, and set Bits DB[25:21] in Register R4 to 00011.
Figure 47. Fast Ramp Mode
Rev. B | Page 30 of 36
10849-039
The ADF4159 is capable of generating a fast ramp. The fast ramp
is a triangular ramp with two different slopes (see Figure 47).
The number of steps, time per step, and deviation per step are
programmable for both the up and down ramps.
VOLTAGE
Fast Ramp Mode
Data Sheet
ADF4159
When an interrupt takes place, the data, consisting of the INT
and FRAC values, can be read back via MUXOUT. The data
comprises 37 bits: 12 bits represent the INT value and 25 bits
represent the FRAC value. Figure 50 shows how single bits
are read back.
INTERRUPT MODES AND FREQUENCY READBACK
Interrupt modes are triggered from the rising edge of TXDATA.
To activate this function, set Bits DB[30:27] in Register R0 to
1111, and set Bits DB[25:21] in Register R4 to 00010. To select
and enable the interrupt mode, set Bits DB[27:26] in Register R5
as shown in Table 8.
DATA CLOCKED OUT ON POSITIVE EDGE OF CLK AND READ
ON NEGATIVE EDGE OF CLK READBACK WORD (37 BITS)
0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (0x1CF623A78)
Table 8. Interrupt Modes (Register R5)
TXDATA
Interrupt Mode
Interrupt is off
Interrupt on TXDATA, sweep continues
Interrupt on TXDATA, sweep stops
LE
CLK
MUXOUT
12-BIT INTEGER WORD
0000 1110 0111
0x0E7
231
Figure 49 shows the theory of frequency readback.
FREQUENCY
FREQUENCY AT WHICH INTERRUPT TOOK PLACE
1
25-BIT FRAC WORD
1 0110 0010 0011 1010 0111 1000
0x1623A78
23,214,712
RF = fPFD × (231 + 23,214,712/2 25) = 1.7922963GHz
2
Figure 50. Reading Back Single Bits to Determine the Output Frequency
at the Moment of Interrupt
For continuous frequency readback, the following sequence
must be used (see Figure 51).
TIME
TIME OF INTERRUPT
1.
2.
3.
4.
5.
6.
7.
8.
1. SWEEP CONTINUES MODE
2. SWEEP STOPS MODE
INTERRUPT SIGNAL
LOGIC HIGH
10849-040
LOGIC LOW
TIME
Register 0 write
LE high
Pulse on TXDATA
Frequency readback
Pulse on TXDATA
Register R4 write
Frequency readback
Pulse on TXDATA
Figure 51 shows the continuous frequency readback sequence.
Figure 49. Interrupt and Frequency Readback
TXDATA
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
CLK
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
MUXOUT
R0 WRITE
R4 WRITE
R4 WRITE
DATA
LE
10849-042
LOGIC LEVEL
LSB
MSB
10849-041
Bits DB[27:26]
00
01
11
Figure 51. Continuous Frequency Readback
Rev. B | Page 31 of 36
ADF4159
Data Sheet
FAST LOCK MODE
Fast Lock Loop Filter Topology
The ADF4159 can operate in fast lock mode. In this mode, the
charge pump current is boosted and additional resistors are
connected to maintain the stability of the loop.
To use fast lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter must
be reduced to ¼ of its value in wide bandwidth mode. This reduction is required because the charge pump current is increased
by 16 in wide bandwidth mode, and stability must be ensured.
Fast Lock Timer and Register Sequences
If the fast lock mode is used, a timer value must be loaded into
the PLL to determine the time spent in wide bandwidth mode.
When Bits DB[20:19] in Register R4 are set to 01 (fast lock
divider), the timer value is loaded via the 12-bit clock divider
value. Before fast lock is enabled, the initialization sequence
must be performed after the part is first powered up (see the
Initialization Sequence section). Note that the fast lock feature
does not work in ramp mode.
To use fast lock, the PLL must be written to in the following
sequence:
1.
2.
To further enhance stability and mitigate frequency overshoot
during a frequency change in wide bandwidth mode, Resistor R3
is connected (see Figure 52). During fast lock, the SW1 pin is
shorted to ground, and the SW2 pin is connected to CP (set
Bits DB[20:19] in Register R4 to 01 for fast lock divider).
The following two topologies can be used:
•
•
Set Bits DB[20:19] = 01 in Register R4 and set the fast lock
timer value (Bits DB[18:7]).
If a longer time in wide loop bandwidth is required, set the
CLK1 divider value (Bits DB[14:3]) in Register R2.
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 52).
Connect an extra resistor (R1A) directly from SW1 (see
Figure 53). The extra resistor must be selected such that the
parallel combination of an extra resistor and the damping
resistor (R1) is reduced to ¼ of the original value of R1.
For both topologies, the ratio R3:R2 must equal 1:4.
Note that the length of time that the PLL remains in wide bandwidth mode is equal to CLK1 × fast lock timer/fPFD, where CLK1
is the 12-bit CLK1 divider programmed in Register R2.
R3
SW2
R2
VCO
CP
C1
ADF4159
Fast Lock Example
C2
C3
R1
If the time period set for wide bandwidth mode is 40 µs, then
R1A
10849-047
In this example, the PLL has a reference frequency of 13 MHz
(fPFD = 13 MHz) and a required lock time of 50 µs with CLK1 = 10
(12-bit CLK1 divider in Register R2). In this case, the PLL is set
to wide bandwidth mode for 40 µs.
SW1
Figure 52. Fast Lock Loop Filter Topology 1
R3
Fast Lock Timer Value = Time in Wide Bandwidth × fPFD/CLK1
SW2
R2
VCO
CP
Fast Lock Timer Value = 40 µs × 13 MHz/10 = 52.
C1
ADF4159
Therefore, 52 must be loaded into the clock divider value
in Register R4 (Step 1 in the Fast Lock Timer and Register
Sequences section).
C2
C3
R1A
R1
10849-048
SW1
Figure 53. Fast Lock Loop Filter Topology 2
Rev. B | Page 32 of 36
Data Sheet
ADF4159
SPUR MECHANISMS
Low Frequency Applications
The fractional interpolator in the ADF4159 is a third-order Σ-Δ
modulator with a 25-bit fixed modulus (MOD). The Σ-Δ modulator is clocked at the PFD reference rate (fPFD), which allows PLL
output frequencies to be synthesized at a channel step resolution
of fPFD/CLK1. This section describes the various spur mechanisms
that are possible with fractional-N synthesizers and how they
affect the ADF4159.
The specification of the RF input is 0.5 GHz minimum; however,
RF frequencies lower than 0.5 GHz can be used if the minimum
slew rate specification of 400 V/µs is met. An appropriate driver—
for example, the ADCMP553—can be used to accelerate the edge
transitions of the RF signal before it is fed back to the ADF4159
RF input.
Fractional Spurs
A filter design and analysis program is available to help the user
implement PLL design. Visit http://www.analog.com/pll to download the free ADIsimPLL™ software. This software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter architectures are allowed.
In most fractional synthesizers, fractional spurs can appear
at the set channel spacing of the synthesizer. In the ADF4159,
these spurs do not appear. The high value of the fixed modulus
in the ADF4159 makes the Σ-Δ modulator quantization error
spectrum look like broadband noise, effectively spreading the
fractional spurs into noise.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corresponds to the beat note, or difference frequency, between an
integer multiple of the PFD and the VCO frequency.
These spurs are called integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD,
where the difference frequency can be inside the loop bandwidth.
These spurs are attenuated by the loop filter on channels far from
integer multiples of the PFD.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism is the feedthrough of low levels of on-chip reference switching
noise out through the RFINx pins back to the VCO, resulting in
reference spur levels as high as −90 dBc. Take care in the PCB
layout to ensure that the VCO is well separated from the input
reference to avoid a possible feedthrough path on the board.
FILTER DESIGN USING ADIsimPLL
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24-10) are rectangular.
The printed circuit board (PCB) pad for these lands must be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. Center the land on the pad to ensure
that the solder joint size is maximized.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as this exposed pad. On the PCB, there must be a clearance
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, incorporate them into the thermal pad at the 1.2 mm pitch grid. The
via diameter must be between 0.3 mm and 0.33 mm, and the
via barrel must be plated with 1 ounce of copper to plug the via.
Connect the PCB thermal pad to AGND.
Rev. B | Page 33 of 36
ADF4159
Data Sheet
APPLICATION OF THE ADF4159 IN FMCW RADAR
The PLL solution also has advantages over another method for
generating FMCW ramps: a DAC driving the VCO directly; this
method suffers from nonlinearities of the VCO tuning characteristics, requiring compensation. The PLL method produces highly
linear ramps without the need for calibration.
Figure 54 shows the application of the ADF4159 in a frequency
modulated continuous wave (FMCW) radar system. In the FMCW
radar system, the ADF4159 is used to generate the sawtooth or
triangle ramps that are necessary for this type of radar to operate.
Traditionally, the PLL was driven directly by a direct digital
synthesizer (DDS) to generate the required type of waveform. Due
to the waveform generating mechanism that is implemented on
the ADF4159, a DDS is no longer needed, which reduces cost.
NO DDS REQUIRED
WITH ADF4159
LINEAR
FREQUENCY
SWEEP
REFERENCE
OSCILLATOR
VCO
ADF4159
×2
Tx
ANTENNA
PA
MULT ×2
Rx
ANTENNAS
MICROCONTROLLER
DSP
16 BITS
ADSP-BF531
BUS
CAN/FLEXRAY
BASEBAND
HPF
ADC
10 BITS TO
12 BITS
MUX
MIXER
RANGE
COMPENSATION
FREQUENCY MODULATED CONTINUOUS WAVE
LONG RANGE RADAR
Figure 54. FMCW Radar with the ADF4159
Rev. B | Page 34 of 36
:
.
.
10849-043
AD8283
Data Sheet
ADF4159
OUTLINE DIMENSIONS
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
2.20
2.10 SQ
2.00
6
7
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
06-11-2012-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4159CCPZ
ADF4159CCPZ-RL7
EV-ADF4159EB2Z
EV-ADF4159EB3Z
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board (blank pads for Analog Devices VCO;
filter unpopulated)
Evaluation Board (set up for external, SMA connected
VCO board; filter unpopulated)
Z = RoHS Compliant Part.
Rev. B | Page 35 of 36
Package Option
CP-24-10
CP-24-10
ADF4159
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10849-0-6/13(B)
Rev. B | Page 36 of 36