Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs 8P79818 Datasheet Description Features The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. ▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks — Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz ▪ Select which of the two input clocks is to be used as the reference clock for which divider via pin or register selection — Switchover will not generate any runt clock pulses on the output ▪ Generates eight differential outputs or eight LVCMOS outputs, Bank A only — Differential outputs selectable as LVPECL, LVDS, CML or HCSL — Differential outputs support frequencies from 1PPS to 700MHz — LVCMOS outputs support frequencies from 1PPS to 200MHz — LVCMOS outputs in the same pair may be inverted or in-phase relative to one another ▪ Outputs arranged in 2 banks of 4 outputs each — Each bank supports a separate power supply of 3.3V, 2.5V or 1.8V — 1.5V output voltage is also supported for LVCMOS, Bank A only — One divider per output bank, supporting divide ratios of 2...511 or divider bypass ▪ Output enable control pin — Output enable or disable will not cause any runt pulses ▪ Register programmable via I2C / SPI serial port — Individual output enables, output type selection and output power-down control bits supported — Input mux selection control bit ▪ Core voltage supply of 3.3V, 2.5V or 1.8V ▪ -40°C to +85°C ambient operating temperature ▪ Lead-free (RoHS 6) packaging The 8P79818 supports two output banks, each with its own divider and power supply. All outputs in one bank would generate the same output frequency, but each output can be individually controlled for output type, output enable or even powered-off. The device supports a serial port for configuration of the parameters while in operation. The serial port can be selected to use the I2C or SPI protocol. After power-up, all outputs will come up in LVDS mode and may be programmed to other configurations over the serial port. Outputs may be enabled or disabled under control of the OE input pin. The device can operate over the -40°C to +85°C temperature range. ©2016 Integrated Device Technology, Inc. 1 December 19, 2016 8P79818 Datasheet Block Diagram Figure 1: Block Diagram Bank A QA0 nQA0 DIV A (2 to 511) QA1 nQA1 CLK_SEL PU QA2 Div‐by‐1 nQA2 PD CLK0 QA3 nQA3 nCLK0 PU/PD Bank B PD CLK1 DIV B (2 to 511) nCLK1 PU/PD OE SCLK PU Div‐by‐1 PU SDATA/SDI PU QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 Logic SA0/nCS PU nI2C/SPI PD 8P79818 transistor count: 33,394 ©2016 Integrated Device Technology, Inc. 2 December 19, 2016 8P79818 Datasheet Pin Assignment CLK0 nCLK0 VCC SDATA/SDI SCLK VCC nCLK1 CLK1 Figure 2: Pin Assignments for 5mm x 5mm 32-Lead VFQFN Package (Top View) 32 31 30 29 28 27 26 25 SDO 1 24 CLK_SEL QA0 2 23 QB0 nQA0 3 22 nQB0 QA1 4 21 QB1 nQA1 5 20 nQB1 VCCOA 6 19 VCCOB QA2 7 18 QB2 nQA2 8 17 nQB2 10 11 12 13 14 15 16 nI2C/SPI VCC SA0/nCS OE nQB3 QB3 QA3 9 nQA3 8P79818 Pin Description and Characteristic Tables Table 1: Pin Description Number Name Type[a] 1 SDO Output SPI mode data output signal. Unused in I2C mode. 2 QA0 Output Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details. 3 nQA0 Output Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details. 4 QA1 Output Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details. 5 nQA1 Output Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details. 6 VCCOA Power Output supply for output Bank A. 7 QA2 Output Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details. 8 nQA2 Output Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details. 9 QA3 Output Positive differential clock output. Included in Bank A. Refer to Output Drivers section for details. 10 nQA3 Output Negative differential clock output. Included in Bank A. Refer to Output Drivers section for details. Description Select protocol for serial port: 11 nI2C/SPI Input (PD) 0 = I2C mode 1 = SPI mode 12 VCC Power 13 SA0/nCS Input (PU) ©2016 Integrated Device Technology, Inc. Core logic supply. SPI chip select input (active low) in SPI mode. Base address bit 0 in I2C mode. 3 December 19, 2016 8P79818 Datasheet Table 1: Pin Description (Cont.) Master output enable control 14 OE Input (PU) 0 = All outputs high-impedance 1 = All outputs enabled or disabled under control of register bits 15 nQB3 Output Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details. 16 QB3 Output Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details. 17 nQB2 Output Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details. 18 QB2 Output Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details. 19 VCCOB Power Output supply for output Bank B. 20 nQB1 Output Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details. 21 QB1 Output Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details. 22 nQB0 Output Negative differential clock output. Included in Bank B. Refer to Output Drivers section for details. 23 QB0 Output Positive differential clock output. Included in Bank B. Refer to Output Drivers section for details. Input clock selection control pin. This pin may be disabled by register control, but if enabled (default) its function is: 24 CLK_SEL Input (PU) 25 CLK1 Input (PD) 26 nCLK1 Input (PU/ PD) 27 VCC Power 28 SCLK Input (PU) 29 SDATA/ SDI Input/Output (PU) Input (PU) 30 VCC Power 31 nCLK0 Input (PU/ PD) 32 CLK0 Input (PD) Non-inverting differential clock input. EP VEE Ground Must be connected to ground (GND). 0 = CLK0 is selected 1 = CLK1 is selected Non-inverting differential clock input. Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and pull-down resistors). Core logic supply. Serial port input clock for either SPI or I2C mode. In I2C mode, this is the bi-directional data signal for the serial port In SPI mode, this is the data input signal. Core logic supply. Inverting differential clock input. VCC/2 when left floating (set by the internal pull-up and pull-down resistors). a. Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pullup and Pulldown refer to internal input resistors. See Table 10, DC Input/ Output Characteristics, for typical values. ©2016 Integrated Device Technology, Inc. 4 December 19, 2016 8P79818 Datasheet Principles of Operation Input Selection The 8P79818 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either or both may be used as the source frequency for either output divider under control of the CLK_SEL input pin or under register control. The CLK_SEL pin is the default selection mechanism and selects whether both dividers are driven by the CLK0, nCLK0 input (CLK_SEL = Low) or by the CLK1, nCLK1 input (CLK_SEL = High). If the user enables register control via the SEL_REG control bit, then there are 4 selection options available as shown in Table 2. Table 2: Input Selection Register Control (SEL_REG = 1) CLK_SEL [1:0] Description 0 0 Divider A & B both driven from CLK0 0 1 Divider A driven from CLK1 & Divider B driven from CLK0 1 0 Divider A driven from CLK0 & Divider B driven from CLK1 1 1 Divider A & B both driven from CLK1 Output Dividers Each bank of outputs has its own divider. All outputs in the same bank will be driven by that divider and so will all have the same frequency. Divider A supplies the QA output bank and Divider B supplies the QB output bank. Each divider is capable of being driven by the same or a different input frequency. Each divider can pass that input frequency directly to the outputs or to divide it by any integer from 2 up to 511. Output Drivers The QA[0:3] and QB[0:3] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register, any of these outputs can support LVCMOS, LVPECL, CML, HCSL or LVDS logic levels. CML operation supports both a 400mV peak-peak swing and an 800mV peak-peak swing selection. The operating voltage ranges of each output bank is determined by its independent output power pin (VCCOA or VCCOB). Output voltage levels of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.5V VCCO. A global OE input pin is provided. If the OE pin is negated (Low), then all outputs will be in a high-impedance state. If the OE pin is asserted (High), then each output will behave as indicated by its individual register enable bit. Using the global OE pin to enable or disable outputs will not result in any ‘runt’ clock pulses on the outputs. Each output bank may be enabled or disabled using the SYNC_DISx register bit. Using these bits to enable or disable outputs will not result in any ‘runt’ clock pulses on the outputs. Individual outputs within a bank may be enabled or disabled using the DIS_Qxm register bits. These bits however may result in ‘runt’ pulses on the outputs if the output is otherwise enabled, so it is recommended that the entire bank be disabled via the appropriate SYNC_DISx register bit while an individual output is being enabled using the DIS_Qxm bit to avoid a possible ‘runt’ pulse on the output. If ‘runt’ pulses are not a concern, then the DIS_Qxm bits may be used directly. LVCMOS Operation When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to both the Q and nQ pins. When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another. Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power consumption. It is recommended that use of this selection be kept to a minimum. ©2016 Integrated Device Technology, Inc. 5 December 19, 2016 8P79818 Datasheet Power-Saving Modes To allow the device to consume the least power possible for a given application, the following functions are included under register control: ▪ Any unused output can be individually powered-off. ▪ If either bank is completely unused, all logic, including the dividers for that bank may be completely powered-off. ▪ Clock gating on logic that is not being used. Device Start-up Behavior The device will power-up with all outputs enabled in LVDS mode and all dividers bypassed. Serial Control Port Description Serial Control Port Configuration Description The device has a serial control port capable of responding as a slave in an I2C or SPI compatible configuration, to allow access to any of the internal registers for device programming or examination of internal status. All registers are configured to have default values. See the specifics for each register for details. Selection of I2C versus SPI protocol will be done via the nI2C/SPI input pin. SPI Mode Operation SPI mode can be enabled via pin selection from power-up. The following information assumes SPI mode has been selected. In a read operation (R/W bit is '1'), data on SDO will be clocked out on the falling edge of SCLK. In a write operation (R/W bit is '0'), data on SDI will be clocked in on the rising edge of SCLK. Figure 3: SPI Read Sequencing Diagram ©2016 Integrated Device Technology, Inc. 6 December 19, 2016 8P79818 Datasheet During SPI Write operations, the user may continue to hold nCS low and provide further bytes of data for up to a total of 16 bytes in a single block write. Data is written directly into the appropriate register as it is received. Figure 4: SPI Write Sequencing Diagram Figure 5: SPI Read/Write Timing Diagram tpwh tsu1 nCS th1 tpwl th2 tsu2 SCLK SDI R/W A0 td2 td1 SDO Hi‐Z Hi‐Z Table 3: Timing Characteristics in SPI Mode[a] Symbol Parameter Min Typ Max Unit tpw SCLK Period 20 ns tpw1 SCLK Pulse Width Low 8 ns tpw2 SCLK Pulse Width High 8 ns tsu1 Valid nCS to SCLK Rising Setup Time 10 ns th1 Valid nCS After Valid SCLK Hold Time (CLKE = 0/1) 10 ns tsu2 Valid SDI to SCLK Rising Setup Time 5 ns th2 Valid SDI after valid SCLK Hold Time 5 ns td1 SCLK falling (rising in CLKE = 1 case) to Valid Data Delay Time 5 ns td2 nCS rising edge to SDO High Impedance Delay Time 10 ns tcsh Time between Consecutive Read-Read or Read-Write Accesses (nCS rising edge to nCS falling edge) 20 ns a. Specifications guaranteed by design and characterization. ©2016 Integrated Device Technology, Inc. 7 December 19, 2016 8P79818 Datasheet I2C Mode Operation The I2C interface is designed to fully support v1.0 of the I2C specification for normal and fast mode operation. The device acts as a slave device on the I2C bus at 100kHz or 400kHz using an address of 110110x (binary), where the value of ‘x’ is set by the SA0/nCS input pin. The interface accepts byte-oriented block write and block read operations. One address byte specifies the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will be written to the registers directly as each byte is received. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 51k typical. Figure 6: Slave Read and Write Cycle Sequencing Current Read S Dev Addr + R A Data 0 A Data 1 A A Data n A P Sequential Read S Dev Addr + W A Offset Addr MSB A A Offset Addr MSB A Sr Dev Addr + R A Data 0 Data 1 A A Data 1 A A Data n A P Sequential Write S Dev Addr + W from master to slave from slave to master Data 0 A A Data n A P S = start Sr = repeated start A = acknowledge A = none acknowledge P = stop ©2016 Integrated Device Technology, Inc. 8 December 19, 2016 8P79818 Datasheet Register Descriptions Table 4: Register Blocks Register Ranges Offset (Hex) Register Block Description 01 Device control 25 Bank A control 69 Bank B control AB Reserved CF Divide ratios ©2016 Integrated Device Technology, Inc. 9 December 19, 2016 8P79818 Datasheet Table 5: Device Control Register Bit Field Locations Address (Hex) D7 0 CLKMODE 1 BKA_Vx Bit Field Name D6 D5 CLK_SEL[1:0] BKB_Vx Field Type SYNC_DISA D4 D3 D2 D1 D0 SEL_REG Rsvd Rsvd Rsvd DIV_SYNC SYNC_DISB PWR_DNA PWR_DNB DIS_DIVA DIS_DIVB Default Value Description Clock switchover mode selection: CLKMODE CLK_SEL[1:0] R/W R/W 0b 0 = Forced clock switch (may result in glitches as clocks switch) 1 = Glitch-less clock switch (may remain on original clock source if that source is no longer toggling) 00b Select which input clock is to be used as the reference clock. These bits are only in effect when SEL_REG = 1: 00 = CLK0, nCLK0 input drives both Divider A & Divider B 01 = CLK1, nCLK1 input drives Divider A & CLK0, nCLK0 drives Divider B 10 = CLK0, nCLK0 input drives Divider A & CLK1, nCLK1 drives Divider B 11 = CLK1, nCLK1 input drives both Divider A & Divider B SEL_REG R/W 0b Determines if input clock selection is to be performed by pin or register: 0 = CLK_SEL input pin controls reference selection mux 1 = CLK_SEL register bits controls reference selection mux Rsvd R/W Reserved. Always write ‘0’ to this bit location. Read values are not defined. Divider synchronization control: DIV_SYNC R/W 0b 0 = Dividers running normally 1 = Dividers in reset (output clocks halted) 1–>0 transition on this bit will synchronize the Bank A & Bank B output dividers Bank A voltage setting for optimal performance: BKA_Vx R/W 0b 0 = VCCOA is 3.3V 1 = VCCOA is 2.5V,1.8V, and 1.5V Bank B voltage setting for optimal performance: BKB_Vx R/W 0b 0 = VCCOB is 3.3V 1 = VCCOB is 2.5V,1.8V Glitch-free output enable bit for Bank A outputs: SYNC_DISA R/W 0b 0 = Outputs in Bank A are enabled glitch-lessly as indicated by their individual DIS_QAm bits 1 = All outputs for Bank A are high-impedance Glitch-free output enable bit for Bank B outputs: SYNC_DISB R/W ©2016 Integrated Device Technology, Inc. 0b 0 = Outputs in Bank B are enabled glitch-lessly as indicated by their individual DIS_QBm bits 1 = All outputs for Bank B are high-impedance 10 December 19, 2016 8P79818 Datasheet Bit Field Name Field Type Default Value Description Power-down control for Bank A outputs: PWR_DNA R/W 0b 0 = All outputs for Bank A are powered (SYNC_DISA should be 1 when powering-up the bank to prevent glitches on the output) 1 = All outputs in Bank A are powered-off Power-down control for Bank B outputs: PWR_DNB R/W 0b DIS_DIVA R/W 0b 0 = All outputs for Bank B are powered (SYNC_DISB should be 1 when powering-up the bank to prevent glitches on the output) 1 = All outputs in Bank B are powered-off Power-down output divider for Bank A (DIVA must be set to 000h to bypass): 0 = Output divider for Bank A is powered 1 = Output divider for Bank A is powered-down Power-down output divider for Bank B (DIVB must be set to 000h to bypass): DIS_DIVB R/W ©2016 Integrated Device Technology, Inc. 0b 0 = Output divider for Bank B is powered 1 = Output divider for Bank B is powered-down 11 December 19, 2016 8P79818 Datasheet Table 6: Bank A Control Register Bit Field Locations Address (Hex) D7 D6 2 D5 Rsvd D4 D3 D2 D1 D0 TERM_A QA_POL3 QA_POL2 QA_POL1 QA_POL0 3 Rsvd MODE_QA3[2:0] MODE_QA2[2:0] 4 Rsvd MODE_QA1[2:0] MODE_QA0[2:0] 5 DIS_QA3 Bit Field Name TERM_A DIS_QA2 Field Type R/W DIS_QA1 DIS_QA0 Rsvd Default Value Description 0b Indicates termination used on Bank A outputs when HCSL mode is selected: 0 = 33/ 50 1 = 50 Output polarity selection for output pair nQAm, QAm in LVCMOS mode: QA_POLm MODE_QAm[2:0] R/W R/W 0h 010b 0 = nQAm pin is inverted relative to QAm pin when in LVCMOS mode 1 = nQAm and QAm pins are in-phase when in LVCMOS mode Output driver mode of operation for output pair QAm, nQAm: 000 = high-impedance 001 = LVPECL 010 = LVDS (default) 011 = LVCMOS 100 = HCSL 101 = CML 400mV swing 110 = CML 800mV swing 111 = Reserved Disable output pair QAm, nQAm: DIS_QAm R/W 0b 0 = Output pair QAm, nQAm is enabled (disable output bank using SYNC_DISA to prevent runt pulses when enabling) 1 = Output pair QAm, nQAm is powered-down Rsvd R/W ©2016 Integrated Device Technology, Inc. Reserved. Always write 0 to this bit location. Read values are not defined. 12 December 19, 2016 8P79818 Datasheet Table 7: Bank B Control Register Bit Field Locations Address (Hex) D7 D6 6 D5 Rsvd D4 D3 D2 D1 D0 TERM_B Rsvd Rsvd Rsvd Rsvd 7 Rsvd MODE_QB3[2:0] MODE_QB2[2:0] 8 Rsvd MODE_QB1[2:0] MODE_QB0[2:0] 9 DIS_QB3 Bit Field Name TERM_B DIS_QB2 Field Type R/W DIS_QB1 DIS_QB0 Rsvd Default Value Description 0b Indicates termination used on Bank B outputs when HCSL mode is selected: 0 = 33/ 50 1 = 50 Output driver mode of operation for output pair QBm, nQBm: MODE_QBm[2:0] R/W 010b 000 = high-impedance 001 = LVPECL 010 = LVDS (default) 011 = Rsvd 100 = HCSL 101 = CML 400mV swing 110 = CML 800mV swing 111 = Reserved DIS_QBm R/W 0b Disable output pair QBm, nQBm: 0 = Output pair QBm, nQBm is enabled (disable output bank using SYNC_DISB to prevent runt pulses when enabling) 1 = Output pair QBm, nQBm is powered-down Rsvd R/W Reserved. Always write 0 to this bit location. Read values are not defined. ©2016 Integrated Device Technology, Inc. 13 December 19, 2016 8P79818 Datasheet Table 8: Divide Ratio Register Field Locations Address (Hex) D7 D6 D5 D4 D3 C DIVA[7:0] D DIVB[7:0] E D2 Rsvd F D1 D0 DIVB[8] DIVA[8] Rsvd Bit Field Name DIVA[8:0] Field Type R/W Default Value 000h Description Divider ratio for Bank A outputs: 00h 01h = Bypass divider and pass reference clock directly to the Bank A outputs 02h 1FFh = ratio to be used by the A divider is value written here. For example writing a 4 in this field will results in a divide ratio of 4 being used. Divider ratio for Bank B outputs: DIVB[8:0] R/W 000h 00h 01h = Bypass divider and pass reference clock directly to the Bank B outputs 02h 1FFh = ratio to be used by the B divider is value written here. For example writing a 4 in this field will results in a divide ratio of 4 being used. Rsvd R/W ©2016 Integrated Device Technology, Inc. Reserved. Always write 0 to this bit location. Read values are not defined. 14 December 19, 2016 8P79818 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 8P79818 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 9: Absolute Maximum Ratings Item Rating Supply voltage, VCCX[a] to GND 3.6V Inputs SCLK, SDATA/SDI, SA0/nCS, CLK_SEL, CLK0, nCLK0, CLK1, nCLK1, OE, nI2C/SPI 0.5V to 3.6V Outputs, IO QA[0:3], nQA[0:3], QB[0:3], nQB[0:3] Continuous current Surge current 40mA 60mA Outputs, VO QA[0:3], nQA[0:3], QB[0:3], nQB[0:3] 0.5V to 3.6V Outputs, VO SDO, SDATA/SDI 0.5V to 3.6V Operating junction temperature 125°C Storage temperature, TSTG 65°C to 150°C Lead temperature (Soldering, 10s) 260°C a. VCCx denotes VCC, VCCOA, or VCCOB. ©2016 Integrated Device Technology, Inc. 15 December 19, 2016 8P79818 Datasheet DC Characteristics Table 10: DC Input/ Output Characteristics Symbol Cin Parameter Test Conditions Input capacitance QA[0:3], nQA[0:3] CML 400mV QB[0:3], nQB[0:3] CPD CML 800mV Power Bank A dissipation LVCMOS capacitance LVPECL (per output) LVDS QA[0:3], nQA[0:3] CML 400mV QB[0:3], nQB[0:3] RPULLUP Bank A pF 1.2 pF 0.48 pF 0.44 pF 2.33 pF 1.4 pF 1.5 pF 0.53 pF 0.3 pF 2.1 pF 51 k 51 k LVCMOS output type selected VCCOA = 3.3V+5% 24 LVCMOS output type selected VCCOA = 2.5V+5% 15 LVCMOS output type selected VCCOA = 1.8V+5% 26 LVCMOS output type selected VCCOA = 1.5V+5% 46 VCCOX[a] = 3.465V or 2.625V VCCOA = 3.465V or 2.625V VCCOX = 1.89V VCCOA = 1.89V or 1.575V Input pull-up resistor Output impedance QA[3:0], nQA[3:0] Units 0.8 RPULLDOWN Input pull-down resistor ROUT Maximum pF CML 800mV LVCMOS Typical 0.5 LVPECL LVDS Minimum a. VCCOx denotes VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 16 December 19, 2016 8P79818 Datasheet Supply Voltage Characteristics , Table 11: Power Supply Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to +85°C[a], Symbol VCC VCCOA, VCCOB ICC Parameter Test Conditions Minimum Typical [b], [c] Maximum Units Core supply voltage 3.135 3.465 V Output supply voltage 1.71 VCC V 23 26 mA DIV-by-1 157 177 mA DIV A = DIV B = 2 125 140 mA 183 206 mA Core supply current ICCOA ICCOB Output supply current IEE Power supply current a. Internal dynamic switching current at maximum fOUT is included. b. All outputs configured for LVEPCL logic levels and not terminated. c. VCC VCCOA and VCCOB. Table 12: Power Supply Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to +85°C[a], Symbol VCC VCCOA, VCCOB ICC Parameter Test Conditions Minimum Typical [b], [c] Maximum Units Core supply voltage 2.375 2.625 V Output supply voltage 1.71 VCC V 18 20 mA DIV-by-1 156 175 mA DIV A = DIV B = 2 124 139 mA 177 199 mA Core supply current ICCOA ICCOB Output supply current IEE Power supply current a. Internal dynamic switching current at maximum fOUT is included. b. All outputs configured for LVEPCL logic levels and not terminated. c. VCC VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 17 December 19, 2016 8P79818 Datasheet Table 13: Power Supply Characteristics, VCC = 1.8V ±5%, VEE = 0V, TA = -40°C to +85°C[a], Symbol VCC VCCOA, VCCOB ICC Parameter Test Conditions Minimum Typical [b], [c] Maximum Units Core supply voltage 1.71 1.89 V Output supply voltage 1.71 VCC V 14 16 mA DIV-by-1 143 160 mA DIV A = DIV B = 2 117 132 mA 161 181 mA Core supply current ICCOA ICCOB Output supply current IEE Power supply current a. Internal dynamic switching current at maximum fOUT is included. b. All outputs configured for LVEPCL logic levels and not terminated. c. VCC VCCOA and VCCOB. VCCOx[d] = 1.5V VCCOx[d] = 1.5V 5% LVCMOS CML LVPECL LVDS HCSL LVCMOS CML (400mV) LVPECL LVDS HCSL LVCMOS CML (400mV) LVCMOS Units Test Conditions VCCOx[d] = 1.8V HCSL Bank B output supply current VCCOx[d] = 2.5V LVDS ICCOB Bank A output supply current VCCOx[d] = 3.3V LVPECL ICCOA Parameter[c] Symbol Table 14: Output Supply Current, VCC = 3.3V, 2.5V or 1.8V, VEE = 0V, TA = 25°C[a], [b] VCC = 3.3V, TA = 25°C 76 96 73 119 60 75 96 67 92 58 68 87 66 72 53 60 mA VCC = 3.3V 5%, TA = 85°C 88 114 87 149 70 88 113 85 111 67 80 104 78 86 63 71 mA VCC = 3.3V, TA = 25°C 76 96 73 119 60 75 96 67 92 58 68 87 66 72 53 60 mA VCC = 3.3V, TA = 85°C 88 114 87 149 70 88 113 85 111 67 80 104 78 86 63 71 mA a. All outputs not terminated. b. VCC VCCOA and VCCOB. c. Internal dynamic switching current at maximum fOUT is included. d. VCCOx denotes VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 18 December 19, 2016 8P79818 Datasheet DC Electrical Characteristics Table 15: LVCMOS/LVTTL Control / Status Signals DC Characteristics, VEE = 0V, TA = -40°C to +85°C Symbol VIH VIL IIH IIL VOH Parameter Test Conditions Input high voltage Input low voltage SA0/nCS, SDATA/SDI, SCLK, CLK_SEL, OE Input high current nI2C/SPI SA0/nCS, SDATA/SDI, SCLK, CLK_SEL,OE Input low current nI2C/SPI Output high voltage SDATA/SDI, SDO Minimum Typical Maximum Units VCC = 3.3V 2.20 VCC 0.3 V VCC = 2.5V 1.85 VCC 0.3 V VCC = 1.8V 1.25 VCC 0.3 V VCC = 3.3V –0.3 0.8 V VCC = 2.5V –0.3 0.7 V VCC = 1.8V –0.3 0.7 V 5 A 150 A VCC = VIN = 3.465V, 2.625V or 1.89V –150 A –5 A VCC = 3.3V ±5%, IOH = –5mA 2.6 V VCC = 2.5V ±5%, IOH = –5mA 1.8 V VCC = 3.465V, 2.625V or 1.89V, VIN = 0V VCC = 1.8V ±5%, IOH = –5mA VOL Output low voltage SDATA/SDI, SDO V VCC = 3.3V ±5% or 2.5V ±5% or 1.8V ±5%, IOL = 5mA 0.5 V , Table 16: Differential Input DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V, TA = -40°C to +85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 150 A IIH Input high current CLKx, nCLKx[a] VCC = VIN = 3.465V or 2.625V IIL Input low current CLKx[a] VCC = 3.465V or 2.625V, VIN = 0V –5 A nCLKx[a] VCC = 3.465V or 2.625V, VIN = 0V –150 A VPP VCMR Peak-to-peak voltage[b] Common mode input voltage[b], [c] 0.15 1.3 V 0 VCC V a. CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1. b. VIL should not be less than –0.3V. VIH should not be higher than VCC. c. Common mode voltage is defined as the cross-point. ©2016 Integrated Device Technology, Inc. 19 December 19, 2016 8P79818 Datasheet Table 17: LVPECL DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V, TA = -40°C to +85°C VCCOx[a] = 3.3V±5% Symbol Parameter Min Typ VCCOx[a] = 2.5V±5% Max Min Typ VCCOx[a] = 1.8V±5% Max Min Typ Max Units VOH Output high voltage[b] Qx, nQx[c] VCCOx 1.30 VCCOx 0.80 VCCOx 1.35 VCCOx 0.80 VCCOx 1.50 VCCOx 0.90 V VOL Output low voltage Qx, nQx[c] VCCOx 2.00 VCCOx 1.75 VCCOx 2.00 VCCOx 1.75 VEE 0.25 V a. VCCOx denotes VCCOA and VCCOB. b. Outputs terminated with 50 to VCCOx – 2V when VCCOx = 3.3V±5% or 2.5V±5%. Outputs terminated with 50 to ground when VCCOx = 1.8V±5%. c. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 18: LVDS DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C Symbol VOD VOD VOS VOS Parameter Test Conditions Differential output voltage Qx, nQx[a] VOD magnitude change Qx, nQx[a] [a] Offset voltage Qx, nQx VOS magnitude change Qx, nQx[a] Minimum Typical Maximum Units 480 mV 50 mV 1.375 V 50 mV 247 Terminated 100 across Qx and nQx 1.125 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 19: CML (400mV Swing) DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C Symbol Parameter VOH Output high voltage VOL Output low voltage VOUT Output voltage swing Test Conditions Qx, nQx[a] Qx, nQx[a] Qx, nQx[a] Terminated with 50 to VCCOx[b] Minimum Typical Maximum Units VCCOx[b] – 0.10 VCCOx[b] V VCCOx[b] – 0.50 VCCOx[b] – 0.30 V 300 500 mV a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. b. VCCOx denotes VCCOA and VCCOB. Table 20: CML (800mV Swing) DC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C Symbol Parameter Test Conditions Qx, nQx[a] VOH Output high voltage VOL Output low voltage Qx, nQx[a] VOUT Output voltage swing Qx, nQx[a] Terminated with 50 to VCCOx[b] Minimum Typical Maximum Units VCCOx[b] – 0.10 VCCOx V VCCOx[b] – 0.95 VCCOx[b] – 0.70 V 575 1000 mV a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3.nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. b. VCCOx denotes VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 20 December 19, 2016 8P79818 Datasheet Table 21: LVCMOS Clock Outputs DC Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, VEE = 0V, TA = -40°C to +85°C Test Conditions Symbol Parameter VOH Output high voltage QAx, nQAx[a] IOH = –8mA VOL Output low voltage QAx, nQAx[a] IOL = 8mA VCCOA = 3.3V±5% VCCOA = 2.5V±5% VCCOA = 1.8V ±5% VCCOA = 1.5V ±5% Min Typ Max 2.6 Min Typ Max 1.1 0.5 Min Typ Max 1.1 0.5 Min Typ Max Units 1.1 V 0.5 0.5 V a. QAm denotes QA0, QA1, QA2, QA3. nQAm denotes nQA0, nQA1, nQA2, nQA3. Table 22: Input Frequency Characteristics, VCC = 3.3V±5%, 2.5V±5% or 1.8V±5%, TA = -40°C to +85°C Symbol fIN idc fSCLK Parameter Input frequency, CLKx, nCLKx Input duty Test Conditions Minimum Maximum LVPECL, LVDS, HCSL, CML 1PPS 700MHz LVCMOS 1PPS 200MHz cycle[a] Serial port clock SCLK Typical 50 I2C operation 100 SPI operation Units % 400 kHz 50 MHz a. Any deviation from a 50% duty cycle on the input may be reflected in the output duty cycle. ©2016 Integrated Device Technology, Inc. 21 December 19, 2016 8P79818 Datasheet AC Electrical Characteristics Table 23: AC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C Parameter[a] Symbol Test Conditions LVPECL, LVDS fOUT Output frequency HCSL, CML[b] LVCMOS LVPECL LVDS tR / tF Output rise and fall times odc Bank skew[d], [e], [f] Output duty cycle[g] VCCOx = 3.3V 20% to 80% VCCOx[c] = 2.5V 20% to 80% VCCOx[c] = 1.8V 20% to 80% Maximum Units 1PPS 700MHz 1PPS 200MHz 125 700 ps 125 550 ps 175 550 ps 20% to 80% 100 675 ps CML, 800mV 20% to 80% 125 825 ps 200 800 ps 650 1300 ps LVPECL 15 50 ps LVDS 20 60 ps CML 10 35 ps HCSL 10 35 ps LVCMOS 50 100 ps VCCOA = 3.3V 20% to 80% VCCOA = 2.5V 20% to 80% VCCOA = 1.8V 20% to 80% VCCOA = 1.5V 20% to 80% LVPECL, LVDS, HCSL, CML Even divide ratios 45 50 55 % LVPECL, LVDS, HCSL, CML Odd divide ratios / bypass 43 50 57 % VCCOA = 3.3V, 2.5V, or 1.8V Even divide ratios 45 50 55 % LVCMOS Odd divide ratios / bypass 40 50 60 % Even divide ratios 40 50 60 % Odd divide ratios / bypass 38 50 62 % LVCMOS MUXISOL [c] Typical CML, 400mV LVCMOS tsk(b) 20% to 80% Minimum VCCOA = 1.5V Mux isolation 156.25MHz, VSWING = 800mV Noise floor Offset >10MHz from156.25MHz carrier 61 dB –154 dBc/Hz a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. b. CML denotes CML 400mV and CML 800mV, unless otherwise stated. c. VCCOx denotes VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 22 December 19, 2016 8P79818 Datasheet d. e. f. g. This parameter is guaranteed by characterization. Not tested in production. This parameter is defined in accordance with JEDEC Standard 65. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured using 50% duty cycle on input reference. Table 24: HCSL AC Characteristics, VCC = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, VCCOA = VCCOB = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%, TA = -40°C to +85°C Symbol Parameter[a] Test Conditions[b] tSLEW Rise/ fall edge rate[c] VMAX Absolute max. output voltage[d], [e] VMIN VCROSS VCROSS Absolute min. output voltage [d], [f] Total variation of VCROSS over all edges[g], [i] Typical Maximum Units VCCOx = 3.3V or 2.5V 0.6 4 V/ns VCCOx = 1.8V 0.45 4 V/ns 1150 mV VCCOx = 3.3V, 2.5V, 1.8V VCCOx = 3.3V, 2.5V, 1.8V Absolute crossing voltage[g], [h] Minimum –150 mV VCCOx = 3.3V, 2.5V, 1.8V 550 mV VCCOx = 3.3V, 2.5V, 1.8V 140 mV a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. b. VCCOx denotes VCCOA and VCCOB. c. Measured from –150mV to 150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. d. Measurement taken from single ended waveform. e. Defined as the maximum instantaneous voltage including overshoot. f. Defined as the minimum instantaneous voltage including undershoot. g. Measured at crossing point where the instantaneous voltage value of the rising edge of Qm equals the falling edge of nQm. h. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. i. Defined as the total variation of all crossing voltages of rising Qm and falling nQm, This is the maximum allowed variance in VCROSS for any particular system. ©2016 Integrated Device Technology, Inc. 23 December 19, 2016 8P79818 Datasheet Table 25: Additive Jitter, VCC = 3.3V, 2.5V or 1.8V, VCCOA = VCCOB = 3.3V, 2.5V, 1.8V or 1.5V (1.5V only supported for LVCMOS outputs), TA = 25°C Symbol Test Conditions[a] Parameter fOUT = 156.25MHz LVPECL fOUT = 625MHz fOUT = 156.25MHz tjit(f) RMS additive jitter (random); LVDS fOUT = 625MHz Integration range: 12kHz – 20MHz fOUT = 156.25MHz HCSL fOUT = 625MHz LVCMOS fOUT = 156.25MHz Typical Maximum Units VCCOx[b] = 3.3V or 2.5V 77 92 fs VCCOx[b] = 1.8V 90 117 fs [b] VCCOx = 3.3V or 2.5V 50 60 fs VCCOx[b] = 1.8V 60 84 fs [b] = 85 104 fs VCCOx[b] = 1.8V 126 185 fs VCCOx[b] = 3.3V or 2.5V 48 61 fs 57 84 fs 92 132 fs VCCOx = 1.8V 92 133 fs [b] = 61 73 fs VCCOx[b] = 1.8V 67 93 fs VCCOA = 3.3V or 2.5V 98 166 fs VCCOA = 1.8V 128 204 fs VCCOA = 1.5V 198 314 fs VCCOx VCCOx [b] = 3.3V or 2.5V 1.8V VCCOx[b] = 3.3V or 2.5V [b] VCCOx 3.3V or 2.5V Minimum a. All outputs configured for the specific output type, as shown in the table. b. VCCOx denotes VCCOA and VCCOB. ©2016 Integrated Device Technology, Inc. 24 December 19, 2016 8P79818 Datasheet Applications Information Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. It is recommended that there is no trace attached. LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. Differential Outputs All unused Differential outputs can be left floating. It is recommended that there is no trace attached. Power Dissipation and Thermal Considerations The 8P79818 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. The 8P79818 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your own specific configuration. ©2016 Integrated Device Technology, Inc. 25 December 19, 2016 8P79818 Datasheet Power Domains The 8P79818 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). Figure 7 below indicates the individual domains and the associated power pins. Figure 7: 8P79818 Power Domains ©2016 Integrated Device Technology, Inc. 26 December 19, 2016 8P79818 Datasheet Power Consumption Calculation Determining total power consumption involves several steps: 1.Determine the power consumption using maximum current values for core voltage from Table 11, Table 12 and Table 13, Page 18 for the appropriate case of how many dividers are enabled. 2.Determine the nominal power consumption of each enabled output path. a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 27 through Table 43 (depending on the chosen output protocol). b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output frequency by the FQ_Factor shown in Table 27 through Table 43. 3.All of the above totals are then summed. Example Calculations Table 26: Example 1. Common Customer Configuration (3.3V Core Voltage) Bank Configuration Frequency (MHz) VCCO Bank A LVDS 125 3.3V Bank B LVDS 125 2.5V ▪ ▪ ▪ ▪ ▪ Core supply current, ICC = 24.7mA (max.) Output supply current, Bank A = 0.06 125 71.615 = 79.115mA Output supply current, Bank B = 0.06 125 71.615 = 79.115mA Total device current = 24.7mA + 79.115mA 79.115mA = 182.93mA Total device power = 3.465V 183.93mA = 633.934mW With an ambient temperature of 85°C and no airflow, the junction temperature is: TJ = 85°C 35.23°C/W 0.634W = 107.3°C ©2016 Integrated Device Technology, Inc. 27 December 19, 2016 8P79818 Datasheet Thermal Considerations Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via conduction into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 44, Page 30. Please contact IDT for assistance in calculating results under other scenarios. Current Consumption Data and Equations Table 27: 3.3V LVDS Output Calculation Table Table 30: 3.3V LVPECL Output Calculation Table LVDS FQ_Factor (mA/MHz), per output Base_Current (mA) LVPECL FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.06 71.615 Qx, nQx[a] 0.05 53.475 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 28: 2.5V LVDS Output Calculation Table Table 31: 2.5V LVPECL Output Calculation Table LVDS FQ_Factor (mA/MHz), per output Base_Current (mA) LVPECL FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.06 71.544 Qx, nQx[a] 0.04 20.874 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 29: 1.8V LVDS Output Calculation Table Table 32: 1.8V LVPECL Output Calculation Table LVDS FQ_Factor (mA/MHz), per output Base_Current (mA) LVPECL FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.1 50.284 Qx, nQx[a] 0.04 19.962 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 33: 3.3V HCSL Output Calculation Table HCSL FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.05 54.911 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. ©2016 Integrated Device Technology, Inc. 28 December 19, 2016 8P79818 Datasheet Table 34: 3.3V CML Output (400mV) Calculation Table Table 39: 1.8V CML Output (800mV) Calculation Table CML FQ_Factor (mA/MHz), per output Base_Current (mA) CML FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.03 51.889 Qx, nQx[a] 0.02 47.334 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 35: 2.5V CML Output (400mV) Calculation Table Table 40: 3.3V LVCMOS Output Calculation Table LVCMOS CML FQ_Factor (mA/MHz), per output Base_Current (mA) Qx, nQx[a] 0.02 49.220 Qx, nQx LVCMOS Qx, Base_Current (mA) Qx, nQx[a] 0.02 47.326 Base_Current (mA) Qx, nQx[a] 0.02 51.474 Base_Current (mA) Qx, nQx[a] 0.02 48.906 LVCMOS Base_Current (mA) Qx, nQx[a] 47.745 Table 43: 1.5V LVCMOS Output Calculation Table LVCMOS Qx, nQx[a] Base_Current (mA) 41.485 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. Table 38: 2.5V CML Output (800mV) Calculation Table FQ_Factor (mA/MHz), per output 51.097 a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. CML Base_Current (mA) Table 42: 1.8V LVCMOS Output Calculation Table Table 37: 3.3V CML Output (800mV) Calculation Table FQ_Factor (mA/MHz), per output nQx[a] a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. CML 62.289 Table 41: 2.5V LVCMOS Output Calculation Table Table 36: 1.8V CML Output (400mV) Calculation Table CML Base_Current (mA) a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. FQ_Factor (mA/MHz), per output [a] a. Qx denotes QA0, QA1, QA2, QA3, QB0, QB1, QB2, QB3. nQx denotes nQA0, nQA1, nQA2, nQA3, nQB0, nQB1, nQB2, nQB3. ©2016 Integrated Device Technology, Inc. 29 December 19, 2016 8P79818 Datasheet Applying the values to the following equation will yield output current by frequency: (mA) = FQ_Factor Frequency (MHz) Base_Current where: Qx Current is the specific output current according to output type and frequency FQ_Factor is used for calculating current increase due to output frequency Base_Current is the base current for each output path independent of output frequency The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: TJ = TA (JA Pdtotal) where: TJ is the junction temperature (°C) TA is the ambient temperature (°C) JA is the thermal resistance value from Table 44, Page 30, dependent on ambient airflow (°C/W) Pdtotal is the total power dissipation of the 8P79818 under usage conditions, including power dissipated due to loading (W) Note that for LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 10, Page 16) and output frequency: PdOUT = CPD fOUT VCCO2 where: Pdout is the power dissipation of the output (W) CPD is the power dissipation capacitance (pF) fOUT is the output frequency of the selected output (MHz) VCCO is the voltage supplied to the appropriate output (V) Table 44: JA vs. Air Flow Table for a 32-lead 5mm x 5mm VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 0 1 2 35.23°C/W 31.6°C/W 30.0°C/W 30 December 19, 2016 8P79818 Datasheet Package Drawings www.IDT.com IDT Figure 8: Package Drawings ©2016 Integrated Device Technology, Inc. 31 December 19, 2016 8P79818 Datasheet www.IDT.com IDT Figure 9: Package Drawings (Continued) ©2016 Integrated Device Technology, Inc. 32 December 19, 2016 8P79818 Datasheet Marking Diagram 1. Line 1 is the prefix of the part number. 2. Line 2 and Line 3 is the part number. 3. Line 4 “YYWW$” a. “YY” are the last digits of the year and “WW” is the work week that the part was assembled. b. “$” denotes mark code. Ordering Information Table 45: Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8P79818NLGI IDT8P79818NLGI 32-lead VFQFN, Lead Free Tray -40°C to +85°C 8P79818NLGI8 IDT8P79818NLGI 32-lead VFQFN, Lead Free Tape & Reel -40°C to +85°C 8P79818NLGI/W IDT8P79818NLGI 32-lead VFQFN, Lead Free Tape & Reel -40°C to +85°C Table 46: Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION NLGI8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION NLGI/W CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED ©2016 Integrated Device Technology, Inc. 33 December 19, 2016 8P79818 Datasheet Revision History Revision Date December 19, 2016 Description of Change Initial datasheet. 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This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. ©2016 Integrated Device Technology, Inc 34 December 19, 2016