MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
D Low Supply-Voltage Range: 1.8 V to 3.6 V
D Ultra-Low Power Consumption:
D
D
D
D
D
D
D
D
D
Active Mode: 262 A at 1 MHz, 2.2 V
Standby Mode: 1.1 A
Off Mode (RAM Retention): 0.1 A
Five Power-Saving Modes
Wake-Up From Standby Mode in
Less Than 6 s
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Sigma-Delta Analog-to-Digital (A/D)
Converter With Internal Reference and Five
Differential Analog Inputs
Dual 12-Bit Digital-to-Analog (D/A)
Converter
Dual Configurable Operational Amplifiers
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
Two Universal Serial Communication
Interfaces (USCI)
USCI_A0
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
USCI_B0
-- I2C
-- Synchronous SPI
D Integrated LCD Driver With Contrast
D
D
D
D
D
D
D
D
D
D
Control for Up to 128 Segments
Brownout Detector
Basic Timer With Real-Time Clock Feature
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
On-Chip Comparator
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Bootstrap Loader
On-Chip Emulation Module
MSP430FG47x Family Members Include
MSP430FG477: 32KB+256B Flash Memory
2KB RAM
MSP430FG478: 48KB+256B Flash Memory
2KB RAM
MSP430FG479: 60KB+256B Flash Memory
2KB RAM
Available in 113-Ball BGA (ZQW) and
80-Pin QFP (PN) Packages (see Available
Options)
For Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 s.
The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock,
a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational
amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
AVAILABLE OPTIONS†
TA
PACKAGED DEVICES‡
PLASTIC 113-BALL BGA (ZQW)
PLASTIC 80-PIN QFP (PN)
MSP430FG477IZQW
MSP430FG478IZQW
MSP430FG479IZQW
MSP430FG477IPN
MSP430FG478IPN
MSP430FG479IPN
--40C to 85C
†
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
D Debugging and Programming Interface
--
MSP--FET430UIF (USB)
--
MSP--FET430PIF (Parallel Port)
D Debugging and Programming Interface with Target Board
--
MSP--FET430U80 (PN package)
D Production Programmer
--
2
MSP--GANG430
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
pin designation, MSP430FG47xIZQW
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
P6.6/OA1I1 (SW1A)
P6.5/OA0I2 (SW0B)
P6.4/A1-/OA1FB
P6.2/OA0I1 (SW0A)
P6.3/A1+/OA1O
P6.1/A0-/OA0FB
XT2OUT
P6.0/A0+/OA0O
TDO/TDI
XT2IN
TMS
TDI/TCLK
TCK
RST/NMI
P2.5/UCA0RXD/UCA0SOMI
P2.4/UCA0TXD/UCA0SIMO
DVSS2
P2.3/TB2
DVCC2
DVSS1
pin designation, MSP430FG47xIPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVCC1
1
60
VREF
P2.2/TB1
P2.1/TB0/S0
2
3
59
58
P6.7/OA1I2/SVSIN (SW1B)
P1.0/TA0/OA0RFB
P2.0/TA2/S1
4
57
P1.1/TA0/MCLK/OA1RFB
P2.6/CAOUT/S2
P2.7/S3
5
6
56
55
P1.2/TA1/A4-/OA0I3 (SW0C)
P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)
GND
7
54
P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1
XIN
XOUT
8
9
53
52
AVSS
AVCC
51
P1.5/TACLK/ACLK/A3+
50
49
P1.6/CA0/A2-/OA0I0/DAC0
P1.7/CA1/A2+
GND
10
P4.7/S4
P4.6/S5
11
12
80-pin
IPN PACKAGE
(TOP VIEW)
P4.5/S6
13
48
P3.7/S31
P4.4/S7
P4.3/S8
14
15
47
46
P3.6/S30
P3.5/S29
P4.2/S9
16
17
18
45
44
43
P3.4/S28
P4.1/S10
P4.0/S11
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL/S27
S12
19
42
P3.1/UCB0SIMO/UCB0SDA/S26
S13
20
41
P3.0/UCB0STE/UCA0CLK
4
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P5.7/R03
P5.5/R23
P5.6/LCDREF/R13
P5.4/COM3
LCDCAP/R33
P5.3/COM2
COM0
P5.2/COM1
S25
S24
S22
S23
P5.1/S21
P5.0/S20
S19
S18
S16
S17
S14
S15
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
functional block diagram
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC1/2
DVSS1/2
AVCC
AVSS
P1.x/P2.x
2x8
P3.x/P4.x
P5.x/P6.x
4x8
ACLK
Oscillators
FLL+
Flash
SMCLK
60kB
48kB
32kB
MCLK
CPU
64kB
MAB
incl. 16
Registers
MDB
EEM
Brownout
Protection
JTAG
Interface
SVS,
SVM
RAM
2kB
2kB
2kB
LCD_A
128
Segments
1,2,3,4
Mux
SD16_A
with
Buffer
1 Channel
SigmaDelta A/D
Converter
DAC12
12-Bit
OA0, OA1
2
Channels
Voltage
Out
2 OpAmps
Ports
P1/P2
Comparator
_A
Timer_B3
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
3 CC
Registers,
Shadow
Reg
2x8 I/O
Interrupt
capability
Basic
Timer &
RealTime
Clock
Ports
P3/P4
P5/P6
4x8 I/O
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
RST/NMI
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions
TERMINAL
NO.
NAME
I/O
DESCRIPTION
80
PIN
113
PIN
AVCC
52
F12
Analog supply voltage, positive terminal.
AVSS
53
E12
Analog supply voltage, negative terminal.
DVCC1
1
A1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
79
A3
Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2
80
A2
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2
78
B2
B3
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TA0/
OA0RFB
58
C11
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Range switch to OA0 output
BSL transmit
P1.1/TA0/MCLK/
OA1RFB
57
C12
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
Range switch to OA1 output
BSL receive
P1.2/TA1/A4--/
OA0I3 (SW0C)
56
D11
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
OA0, analog input I3
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2
SVS comparator output
SD16 positive analog input A4
OA1, analog input I3
I/O
General-purpose digital I/O pin/
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
OA1, analog input I0
DAC12.1 output
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3
P1.3/TBOUTH/
SVSOUT/A4+/
OA1I3 (SW1C)
P1.4/TBCLK/
SMCLK/A3--/
OA1I0/DAC1
P1.5/TACLK/
ACLK/A3+
55
54
51
D12
E11
F11
P1.6/CA0/A2--/
OA0I0/DAC0
50
G12
I/O
General-purpose digital I/O pin
Comparator_A input 0
SD16 negative analog input A2
OA0, analog input I0
DAC12.0 output
P1.7/CA1/A2+
49
G11
I/O
General-purpose digital I/O pin
Comparator_A input 1
SD16 positive analog input A2
P2.0/TA2/S1
4
C2
C3
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI2A/B input, compare: Out2 output
LCD segment output 1
P2.1/TB0/S0
3
C1
I/O
General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0
6
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
B1
I/O
General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
77
B4
I/O
General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
P2.4/UCA0TXD/
UCA0SIMO
76
A4
I/O
General-purpose digital I/O pin
USCIA transmit data output in UART mode, slave data in/master out in SPI mode
P2.5/UCA0RXD/
UCA0SOMI
75
D4
I/O
General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
P2.6/CAOUT/S2
5
D1
I/O
General-purpose digital I/O pin
Comparator_A output
LCD segment output 2
P2.7/S3
6
D2
I/O
General-purpose digital I/O pin
LCD segment output 3
P3.0/UCB0STE/
UCA0CLK
41
M12
I/O
General-purpose digital I/O pin
USCI B0 slave transmit enable/USCI A0 clock input/output
P3.1/UCB0SIMO/
UCB0SDA/S26
42
L12
I/O
General-purpose digital I/O pin
USCI B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
LCD segment output 26
P3.2/UCB0SOMI/
UCB0SCL/S27
43
K11
I/O
General-purpose digital I/O pin
USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
LCD segment output 27
P3.3/UCB0CLK/
UCA0STE
44
K12
I/O
General-purpose digital I/O
USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/S28
45
J11
I/O
General-purpose digital I/O pin
LCD segment output 28
P3.5/S29
46
J12
I/O
General-purpose digital I/O pin
LCD segment output 29
P3.6/S30
47
H11
I/O
General-purpose digital I/O pin
LCD segment output 30
P3.7/S31
48
H12
I/O
General-purpose digital I/O pin
LCD segment output 31
P4.0/S11
18
K2
I/O
General-purpose digital I/O pin
LCD segment output 11
P4.1/S10
17
K1
I/O
General-purpose digital I/O pin
LCD segment output 10
P4.2/S9
16
J2
I/O
General-purpose digital I/O pin
LCD segment output 9
P4.3/S8
15
J1
I/O
General-purpose digital I/O pin
LCD segment output 8
P4.4/S7
14
H2
I/O
General-purpose digital I/O pin
LCD segment output 7
P4.5/S6
13
H1
I/O
General-purpose digital I/O pin
LCD segment output 6
P4.6/S5
12
G2
I/O
General-purpose digital I/O pin
LCD segment output 5
P4.7/S4
11
G1
I/O
General-purpose digital I/O pin
LCD segment output 4
NAME
80
PIN
113
PIN
P2.2/TB1
2
P2.3/TB2
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
L8
O
Common output, COM0--3 are used for LCD backplanes
27
L5
I/O
General-purpose digital I/O pin
LCD segment output 20
P5.1/S21
28
M5
I/O
General-purpose digital I/O pin
LCD segment output 21
P5.2/COM1
34
M8
I/O
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.3/COM2
35
L9
I/O
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.4/COM3
36
M9
I/O
General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
LCDCAP/R33
37
J9
I/O
Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)
P5.5/R23
38
M10
I/O
General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
P5.6/LCDREF/
R13
39
L10
I/O
P5.7/R03
40
M11
I/O
P6.0/A0+/OA0O
67
B8
I/O
General-purpose digital I/O pin
SD16 positive analog input A0
OA0, output
P6.1/A0--/OA0FB
66
B9
I/O
General-purpose digital I/O pin
SD16 positive negative input A0
OA0, analog input feedback
P6.2/OA0I1
(SW0A)
65
A9
I/O
General-purpose digital I/O pin
OA0, analog input I1
P6.3/A1+/OA1O
64
D9
I/O
General-purpose digital I/O pin
SD16 positive analog input A1
OA1, output
P6.4/A1--/OA1FB
63
A10
I/O
General-purpose digital I/O pin
SD16 positive negative input A1
OA1, analog input feedback
P6.5/OA0I2
(SW0B)
62
B10
I/O
General-purpose digital I/O pin
OA0, analog input I2
P6.6/OA1I1
(SW1A)
61
A11
I/O
General-purpose digital I/O pin
OA1, analog input I1
P6.7/OA1I2/
SVSIN (SW1B)
59
B12
I/O
General-purpose digital I/O pin
OA1, analog input I2
SVS input
S12
19
L1
O
LCD segment output 12
S13
20
M1
O
LCD segment output 13
S14
21
M2
O
LCD segment output 14
S15
22
M3
O
LCD segment output 15
S16
23
L3
O
LCD segment output 16
NAME
80
PIN
113
PIN
COM0
33
P5.0/S20
8
General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)
General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)
POST OFFICE BOX 655303
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Terminal Functions (continued)
TERMINAL
NO.
NAME
I/O
DESCRIPTION
80
PIN
113
PIN
S17
24
L4
O
LCD segment output 17
S18
25
M4
O
LCD segment output 18
S19
26
J4
O
LCD segment output 19
S22
29
L6
O
LCD segment output 22
S23
30
M6
O
LCD segment output 23
S24
31
L7
O
LCD segment output 24
S25
32
M7
O
LCD segment output 25
GND
7
E2
XIN
8
E1
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
F1
O
Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
GND
10
F2
VREF
60
A12
O
Input for an external reference voltage/internal reference voltage output
RST/NMI
74
B5
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
TCK
73
A5
I
Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader
start.
TDI/TCLK
71
A6
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
70
B7
I/O
TMS
72
B6
I
Test mode select. TMS is used as an input port for device programming and test.
XT2OUT
68
A8
O
Output terminal of crystal oscillator XT2
I
Input port for crystal oscillator XT2
XT2IN
69
A7
Reserved
NA
B11,
D6, D7,
D8, E4,
E5, E6,
E7, E8,
E9, F4,
F5, F8,
F9, G4,
G5,G8,
G9, H4,
H5, H6,
H7, H8,
H9, J5,
J6, J7,
J8, L2,
L11
Ground. It is used to shield the oscillator. See Note 1.
Ground. It is used to shield the oscillator. See Note NO TAG.
Test data output port. TDO/TDI data output or programming data input terminal.
BGA package unused balls. Connection to DVSS/AVSS recommended.
NOTE 1: It is recommended to connect GND externally to DVss.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
short-form description
CPU
The MSP430 CPU has a 16--bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats, and Table 2 lists the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g., CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
EXAMPLE
F F
MOV & MEM, & TCDAT
OPERATION
R10
—> R11
M(2+R5)—> M(6+R6)
M(EDE) —> M(TONI)
M(MEM) —> M(TCDAT)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) —> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) —> R11
R10 + 2—> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
10
SYNTAX
D = destination
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#45
—> M(TONI)
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
--
All clocks are active
D Low-power mode 0 (LPM0)
--
CPU is disabled
--
ACLK and SMCLK remain active
--
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
--
CPU is disabled
--
ACLK and SMCLK remain active
--
FLL+ loop control is disabled
D Low-power mode 2 (LPM2)
--
CPU is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc generator remains enabled
--
ACLK remains active
D Low-power mode 3 (LPM3)
--
CPU is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc generator is disabled
--
ACLK remains active
D Low-power mode 4 (LPM4)
--
CPU is disabled
--
ACLK is disabled
--
MCLK, FLL+ loop control, and DCOCLK are disabled
--
DCO’s dc generator is disabled
--
Crystal oscillator is stopped
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power--up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out--of--Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset
0xFFFE
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2 and 4)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC
14
Timer_B3
TBCCR0 CCIFG0 (see Note 2)
Maskable
0xFFFA
13
Timer_B3
TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,
TBIFG (see Notes 1 and 2)
Maskable
0xFFF8
12
Comparator_A
CAIFG
Maskable
0xFFF6
11
Watchdog Timer+
WDTIFG
Maskable
0xFFF4
10
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 1 and 5)
Maskable
0xFFF2
9
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 1 and 6)
Maskable
0xFFF0
8
SD16_A
SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
0xFFEE
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0xFFEC
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0xFFEA
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0xFFE8
4
DAC12
DAC12_0IFG, DAC12_1IFG
Maskable
0xFFE6
3
Maskable
0xFFE4
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0xFFE2
1
Basic Timer1/RTC
BTIFG
Maskable
0xFFE0
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. Access and key violations, KEYV and ACCVIFG.
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
7
6
00h
5
4
ACCVIE
rw--0
3
2
1
0
NMIIE
OFIE
WDTIE
rw--0
rw--0
rw--0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE
Oscillator fault enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
Flash access violation interrupt enable
Address
01h
7
6
5
4
3
2
1
0
BTIE
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw--0
rw--0
rw--0
rw--0
rw--0
UCA0RXIE
USCI_A0 receive interrupt enable
UCA0TXIE
USCI_A0 transmit interrupt enable
UCB0RXIE
USCI_B0 receive interrupt enable
UCB0TXIE
USCI_B0 transmit interrupt enable
BTIE
Basic timer interrupt enable
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MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw--0
rw--(0)
rw--(1)
rw--1
rw--(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG
Power-on interrupt flag. Set on VCC power-up.
NMIIFG
Set via RST/NMI pin.
Address
7
03h
UCA0RXIFG
6
5
3
2
1
0
BTIFG
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw--0
rw--1
rw--0
rw--1
rw--0
USCI_A0 receive interrupt flag
UCA0TXIFG
USCI_A0 transmit interrupt flag
UCB0RXIFG
USCI_B0 receive interrupt flag
UCB0TXIFG
USCI_B0 transmit interrupt flag
BTIFG
Basic Timer1 interrupt flag
Legend
4
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
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MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
memory organization
MSP430FG477
MSP430FG478
MSP430FG479
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh to 0FFE0h
0FFFFh to 08000h
48KB
0FFFFh to 0FFE0h
0FFFFh to 04000h
60KB
0FFFFh to 0FFE0h
0FFFFh to 01100h
Information memory
Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory
Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
Size
2KB
09FFh to 0200h
2KB
09FFh to 0200h
2KB
09FFh to 0200h
16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION
PN PACKAGE PINS
ZQW PACKAGE PINS
Data Transmit
58 - P1.0
C11 - P1.0
Data Receive
57 - P1.1
C12 - P1.1
flash memory (Flash)
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A might contain calibration data. After reset, segment A is protected against programming or
erasing. It can be unlocked, but care should be taken not to erase this segment if this calibration data is
required.
D Flash content integrity check with marginal read modes.
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430FG47x is supported by the FLL+ module, which includes support for a
32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency
crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is
designed to meet the requirements of both low system cost and low power consumption. The FLL+ features
digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented, ports P1 through P6.
D
D
D
D
16
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
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watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.
LCD_A driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PN
ZQW
P1.5 -- 51
F11
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
F11
TAINCLK
INCLK
P1.0 -- 58
C11
TA0
CCI0A
P1.0 -- 58
C11
P1.1 -- 57
C12
TA0
CCI0B
P1.1 -- 57
C12
DVSS
GND
P1.2 -- 56
D11
P2.0 -- 4
C2
P1.5 -- 51
P1.2 -- 56
P2.0 -- 4
D11
C2
MODULE INPUT
NAME
MODULE
BLOCK
DEVICE INPUT
SIGNAL
DVCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
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PN
ZQW
TA1
TA2
17
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
PN
ZQW
DEVICE INPUT
SIGNAL
P1.4 -- 54
E11
TBCLK
MODULE INPUT
NAME
TBCLK
ACLK
ACLK
SMCLK
SMCLK
P1.4 -- 54
E11
TBCLK
(See Note 1)
INCLK
P2.1 -- 3
C1
TB0
CCI0A
P2.1 -- 3
C1
TB0
CCI0B
VSS
GND
VCC
VCC
P2.2 -- 2
B1
TB1
CCI1A
P2.2 -- 2
B1
TB1
CCI1B
VSS
GND
VCC
VCC
P2.3 -- 77
B4
TB2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
CCR2
OUTPUT PIN NUMBER
PN
ZQW
P2.1 -- 3
C1
P2.2 -- 2
B1
P2.3 -- 77
B4
TB0
TB1
TB2
NOTE 1: The inversion of TBCLK is done inside the module.
universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin), I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.
USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C.
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
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SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and a reference generator. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
DAC12
The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 may be used in 8-bit or 12-bit mode.
When multiple DAC12 modules are present, they may be grouped together for synchronous operation.
OA
The MSP430FG47x has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA0 SIGNAL CONNECTIONS
PN
ZQW
DEVICE
INPUT
SIGNAL
P1.6 -- 50
G12
OA0I0
OAxI0
P6.2 -- 65
A9
OA0I1
OAxI1
P6.5 -- 62
B10
OA0I2
OAxIA
P1.2 -- 56
D11
OA0I3
OAxIB
P1.4 -- 54
E11
OA1I0
OAxI0
P6.6 -- 61
A11
OA1I1
OAxI1
P6.7 -- 59
B12
OA1I2
OAxIA
P1.3 -- 55
D12
OA1I3
OAxIB
INPUT PIN NUMBER
MODULE
INPUT NAME
MODULE
OUTPUT
SIGNAL
MODULE
BLOCK
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OUTPUT PIN NUMBER
PN
ZQW
P6.0 -- 67
B8
P6.4 -- 64
A10
OA0O
OA1O
19
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B3
Capture/compare register 2
Capture/compare register 1
Capture/compare
p
/
p
register
g
0
TBCCR2
TBCCR1
TBCCR0
0196h
0194h
0192h
Timer_B
_ register
g
Capture/compare
p
p
control 2
Capture/compare control 1
Capture/compare control 0
TBR
TBCCTL2
TBCCTL1
TBCCTL0
0190h
0186h
0184h
0182h
Timer_B control
Timer_B interrupt vector
TBCTL
TBIV
0180h
011Eh
Capture/compare register 2
Capture/compare register 1
Capture/compare
p
/
p
register
g
0
TACCR2
TACCR1
TACCR0
0176h
0174h
0172h
Timer_A
_ register
g
Capture/compare
p
p
control 2
Capture/compare control 1
Capture/compare control 0
TAR
TACCTL2
TACCTL1
TACCTL0
0170h
0166h
0164h
0162h
Timer_A control
Timer_A interrupt vector
TACTL
TAIV
0160h
012Eh
Flash control 4
Fl h controll 3
Flash
Flash control 2
FCTL4
FCTL
FCTL3
FCTL2
01BEh
012Ch
Ch
012Ah
Flash control 1
FCTL1
0128h
DAC12_1 data
DAC12_1 control
DAC12_0
_ data
DAC12_1DAT
DAC12_1CTL
DAC12_0DAT
_
01CAh
01C2h
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
SD16_A
(see also:
P i h
Peripherals
l with
ith
Byte Access)
General control
Channel 0 control
Channel 0 conversion memoryy
SD16CTL
SD16CCTL0
SD16MEM0
0100h
0102h
0112h
Interrupt vector word register
SD16IV
0110h
OA switches
Switch control register 1
SWCTL_1
00CEh
OA switches
Switch control register
Switch control register 1
SWCTL
SWCTL1
00CFh
00CEh
OA1
Operational
p
amplifier
p
1 control register
g
1
Operational amplifier 1 control register 0
OA1CTL1
OA1CTL0
00C3h
00C2h
OA0
Operational
p
amplifier
p
0 control register
g
1
Operational amplifier 0 control register 0
OA0CTL1
OA0CTL0
00C1h
00C0h
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 input control
Analog enable
SD16INCTL0
SD16AE
0B0h
0B7h
Timer_A3
Flash
DAC12
PERIPHERALS WITH BYTE ACCESS
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peripheral file map (continued)
LCD voltage control 1
LCD voltage control 0
LCD voltage port control 1
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
0AFh
0AEh
0ADh
LCD voltage port control 0
LCD memory 20
:
LCD memory 16
LCDAPCTL0
LCDM20
:
LCDM16
0ACh
0A4h
:
0A0h
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM15
:
LCDM1
LCDACTL
09Fh
:
091h
090h
USCI A0 auto baud rate control
UCA0ABCTL
0x005D
USCI A0 transmit buffer
UCA0TXBUF
0x0067
USCI A0 receive buffer
UCA0RXBUF
0x0066
USCI A0 status
UCA0STAT
0x0065
USCI A0 modulation control
UCA0MCTL
0x0064
USCI A0 baud rate control 1
UCA0BR1
0x0063
USCI A0 baud rate control 0
UCA0BR0
0x0062
USCI A0 control 1
UCA0CTL1
0x0061
USCI A0 control 0
UCA0CTL0
0x0060
USCI A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI A0 IrDA transmit control
UCA0IRTCTL
0x005E
USCI B0 transmit buffer
UCB0TXBUF
0x006F
USCI B0 receive buffer
UCB0RXBUF
0x006E
USCI B0 status
UCB0STAT
0x006D
USCI B0 I2C Interrupt enable
UCB0CIE
0x006C
USCI B0 baud rate control 1
UCB0BR1
0x006B
USCI B0 baud rate control 0
UCB0BR0
0x006A
USCI B0 control 1
UCB0CTL1
0x0069
USCI B0 control 0
UCB0CTL0
0x0068
USCI B0 I2C slave address
UCB0SA
0x011A
USCI B0 I2C own address
UCB0OA
0x0118
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ control 1
FLL_CTL1
054h
FLL+ control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
LCD_A
USCI A0/B0
/
Comparator_A
p
_
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
RTC
(Basic Timer1)
Port P6
Port P5
Port P4
Port P3
Port P2
22
Real-time clock year high byte
Real-time clock year low byte
Real-time clock month
RTCYEARH
RTCYEARL
RTCMON
04Fh
04Eh
04Dh
Real-time clock day of month
Basic Timer1 counter
Basic Timer1 counter
Real-time counter 4
RTCDAY
BTCNT2
BTCNT1
RTCNT4
04Ch
047h
046h
045h
(Real-time clock day of week)
Real-time counter 3
(Real-time clock hour)
Real-time counter 2
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(Real-time clock minute)
Real-time counter 1
(Real-time clock second)
Real-time clock control
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
Basic Timer1 control
BTCTL
040h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
044h
043h
042h
041h
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Special functions
Port P1 selection 2 register
Port P1 selection
P1SEL2
P1SEL
057h
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
SFR iinterrupt
t
pt flflag
g1
SFR interrupt enable 2
IFG2
IFG1
IE2
003h
002h
001h
SFR interrupt enable 1
IE1
000h
POST OFFICE BOX 655303
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23
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
absolute maximum ratings over operating free-air temperature (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature, Tstg: (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . --55C to 150C
(programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 85C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC)
1.8
3.6
V
Supply voltage during flash memory programming,
VCC (AVCC = DVCC = VCC)
2.2
3.6
V
0
0
V
--40
85
C
Supply voltage, VSS (AVSS = DVSS = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 1)
LF selected,
XTS_FLL = 0
Watch crystal
XT1 selected,
XTS_FLL = 1
Ceramic resonator
XT1 selected,
XTS_FLL = 1
Crystal
32.768
0.45
6
MHz
1
6
MHz
0.45
8
1
8
VCC = 1.8 V
dc
4.15
VCC = 2.5 V
dc
8
Ceramic resonator
XT2 crystal frequency,
frequency f(XT2)
Crystal
System frequency,
frequency MCLK
MCLK, ACLK,
ACLK SMCLK , f(System)
kHz
MHz
MHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8 MHz
Supply voltage range,
MSP430FG47x, during
program execution
Supply voltage range, MSP430FG47x,
during flash memory programming
4.15 MHz
1.8
2.2
2.5
Supply Voltage - V
3.6
Figure 1. Frequency vs Supply Voltage, Typical Characteristics
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
TYP
MAX
2.2 V
262
295
3V
420
460
2.2 V
32
62
3V
51
77
2.2 V
5
9
3V
7
13
1.0
1.8
1.0
1.8
1.1
2.0
TA = 85C
2.3
4.0
TA = --40C
1.2
2.0
1.2
2.0
I(AM)
Active mode (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS = 0, SELM = (0,1)
40C to 85C
TA = --40C
I(LPM0)
Low power mode (LPM0)
Low-power
(see Note 1)
40C to 85C
TA = --40C
I(LPM2)
Low-power mode (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
MHz
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)
TA = --40C
40C to 85C
VCC
I(LPM3)
I(LPM3)
Low-power mode (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled , ACLK selected
LCD
LCD_A
A enabled, LCDCPEN = 0:
((4-mux mode,, fLCD = f(ACLK)//32))
(see Note 2 and Note 3)
TA = 25C
TA = 60C
TA = 25C
TA = 60C
I(LPM4)
3V
1.4
2.2
2.7
4.5
TA = --40C
1.0
3.0
1.1
3.2
TA = 85C
3.5
6.0
TA = --40C
1.8
3.3
TA = 25C
2.2 V
2.0
4.0
TA = 85C
4.2
7.5
TA = --40C
0.1
0.5
0.1
0.5
0.7
1.1
TA = 85C
1.7
3.0
TA = --40C
0.1
0.8
0.1
0.8
0.8
1.2
1.5
3.5
TA = 25C
Low-power mode (LPM4)
f(MCLK) = 0 MHz,
MHz f(SMCLK) = 0 MHz,
MHz
f(ACLK) = 0 Hz, SCG0 = 1 (see Note 2)
22V
2.2
TA = 85C
TA = 25C
TA = 60C
TA = 25C
TA = 60C
TA = 85C
UNIT
A
A
TA = --40C
Low-power mode (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled , ACLK selected
LCD
LCD_A
A enabled, LCDCPEN = 0:
((static mode , fLCD = f(ACLK)//32))
(see Note 2 and Note 3)
MIN
3V
22V
2.2
3V
A
A
A
A
A
A
A
A
A
A
NOTES: 1. Timer_A is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9pF) crystal and OSCCAPx = 01h.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 200 A/V (VCC – 2.2 V)
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
typical characteristics -- LPM4 current
ILPM4 -- Low-Power Mode 4 Current -- A
2.0
Vcc = 3.6 V
1.8
Vcc = 3.0 V
1.6
Vcc = 2.2 V
1.4
Vcc = 1.8 V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
--40.0 --20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- C
Figure 2. ILPM4 -- LPM4 Current vs Temperature
26
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MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs -- Ports P1, P2, P3, P4, P5, and P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER
VIT+
Positi e going input
Positive-going
inp t threshold voltage
oltage
VIT--
Negati e going input
Negative-going
inp t threshold voltage
oltage
Vhys
Input voltage hysteresis (VIT+ -- VIT-- )
TEST CONDITIONS
MIN
MAX
VCC = 2.2 V
1.1
1.55
VCC = 3 V
1.5
1.98
VCC = 2.2 V
0.4
0.9
VCC = 3 V
0.9
1.3
VCC = 2.2 V
0.3
1.1
VCC = 3 V
0.5
1
MAX
UNIT
V
V
V
inputs Px.y, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
62
3V
50
2.2 V
62
3V
50
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (see Note 1)
t(cap)
Timer A capture timing
Timer_A
TA0,
TA0 TA1,
TA1 TA2
f(TAext)
Timer_A clock frequency externally
applied to pin
TACLK INCLK: t(H) = t(L)
TACLK,
f(TAint)
Timer A clock frequency
Timer_A,
SMCLK or ACLK signal selected
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1, P2, P3, P4, P5, and P6 (see Note 1)
PARAMETER
Ilkg(Px.y)
Leakage current
TEST CONDITIONS
Port Px
V(Px.y) (see Note 2)
MIN
VCC = 2.2 V/3 V
MAX
UNIT
50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
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27
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High le el output
High-level
o tp t voltage
oltage
Low level output voltage
Low-level
TEST CONDITIONS
MIN
MAX
IOH(max) = --1.5 mA,
VCC = 2.2 V,
See Note 1
VCC --0.25
VCC
IOH(max) = --6 mA,
VCC = 2.2 V,
See Note 2
VCC --0.6
VCC
IOH(max) = --1.5 mA,
VCC = 3 V,
See Note 1
VCC --0.25
VCC
IOH(max) = --6 mA,
VCC = 3 V,
See Note 2
VCC --0.6
VCC
IOL(max) = 1.5 mA,
VCC = 2.2 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 2.2 V,
See Note 2
VSS
VSS+0.6
IOL(max) = 1.5 mA,
VCC = 3 V,
See Note 1
VSS
VSS+0.25
IOL(max) = 6 mA,
VCC = 3 V,
See Note 2
VSS
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
f(Px.y)
(x = 1, 2, 3, 4, 5, 6, 0 y 7)
CL = 20 pF,
IL = 1.5 mA
f(MCLK)
P1.1/TA0/MCLK
CL = 20 pF
t(Xdc)
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
28
POST OFFICE BOX 655303
VCC = 2.2 V / 3 V
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
DALLAS, TEXAS 75265
MIN
TYP
DC
MAX
UNIT
fSystem
MHz
fSystem
MHz
40%
60%
50%-15 ns
50%+
15 ns
50%
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs -- Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
VCC = 2.2 V
P1.0
25
TA = --40C
I OL -- Typical Low-level Output Current -- mA
I OL -- Typical Low-level Output Current -- mA
30
TA = 25C
TA = 85C
20
15
10
5
0
0.0
0.5
1.0
1.5
2.0
TA = --40C
VCC = 3 V
P1.0
45
TA = 25C
40
TA = 85C
35
30
25
20
15
10
5
0
0.0
2.5
0.5
VOL -- Low-Level Output Voltage -- V
1.0
Figure 3
0.0
VCC = 2.2 V
P1.0
I OH -- Typical High-level Output Current -- mA
I OH -- Typical High-level Output Current -- mA
0.0
--5.0
--10.0
--15.0
TA = 25C
TA = 85C
--25.0
TA = --40C
--30.0
0.0
0.5
1.0
2.0
2.5
3.0
3.5
Figure 4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
--20.0
1.5
VOL -- Low-Level Output Voltage -- V
1.5
2.0
2.5
VOH -- High-Level Output Voltage -- V
--5.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
VCC = 3 V
P1.0
--10.0
--15.0
--20.0
--25.0
--30.0
--35.0
--40.0
TA = 85C
TA = 25C
--45.0
--50.0
--55.0
0.0
TA = --40C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH -- High-Level Output Voltage -- V
Figure 5
Figure 6
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DALLAS, TEXAS 75265
29
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
s
6
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
VCC(start)
V(B_IT--)
Vhys(B_IT--)
dVCC/dt 3 V/s (see Figure 7)
Brownout
(see Note 2)
UNIT
2000
s
0.7 V(B_IT--)
dVCC/dt 3 V/s (see Figure 7 through Figure 9)
V
1.71
dVCC/dt 3 V/s (see Figure 7)
V
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V
t(reset)
MAX
2
s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--)
+ Vhys(B_IT--) is 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
FLL+ settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.
typical characteristics
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
1
0
t d(BOR)
Figure 7. POR/Brownout Reset (BOR) vs Supply Voltage
30
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DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics (continued)
VCC
3V
VCC(min) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- s
1 ns
tpw -- Pulse Width -- s
Figure 8. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
3V
VCC(min) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw -- Pulse Width -- s
tpw -- Pulse Width -- s
Figure 9. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
31
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 10)
5
dVCC/dt 30 V/ms
td(SVSon)
SVSON, switch from VLD = 0 to VLD 0, VCC = 3 V
tsettle
VLD 0‡
V(SVSstart)
VLD 0, VCC/dt 3 V/s (see Figure 10)
150
1.55
VLD = 1
VCC/dt 3 V/s (see Figure 10)
VLD = 2 .. 14
Vhys(SVS_IT--)
hys(SVS IT--)
VCC/dt 3 V/s (see Figure 10), External voltage applied
on A7
VCC/dt 3 V/s (see Figure 10 and Figure 11)
V(SVS_IT--)
(SVS IT )
VCC/dt 3 V/s (see Figure 10 and Figure 11), External
voltage applied on A7
ICC(SVS)
(see Note 1)
TYP
VLD = 15
70
120
MAX
UNIT
150
s
2000
s
300
s
12
s
1.7
V
210
mV
V(SVS_IT--)
x 0.001
V(SVS_IT--)
x 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61†
VLD = 13
3.24
3.5
3.76†
VLD = 14
3.43
3.7†
3.99†
VLD = 15
1.1
1.2
1.3
10
15
VLD 0, VCC = 2.2 V/3 V
†
mV
V
A
The recommended operating voltage range is limited to 3.6 V.
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
‡
32
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DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
typical characteristics
AVCC
V(SVS_IT--)
V(SVSstart)
Software sets VLD >0:
SVS is active
Vhys(SVS_IT--)
Vhys(B_IT--)
V(B_IT--)
VCC(start)
Brownout
Brownout
Region
Brownout
Region
1
0
SVS out
td(BOR)
1
0
td(SVSon)
Set POR
1
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT--)
td(SVSR)
undefined
0
Figure 10. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)
VCC(min) -- V
1.5
Triangular Drop
1
1 ns
1 ns
VCC
0.5
t pw
3V
0
1
10
100
tpw -- Pulse Width -- s
1000
VCC(min)
tf = tr
tf
tr
t -- Pulse Width -- s
Figure 11. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
33
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
TEST CONDITIONS
VCC
f(DCOCLK)
N(DCO) = 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0
f(DCO2)
FN 8 = FN_4
FN_8
FN 4 = FN_3
FN 3 = FN_2
FN 2 = 0 , DCOPLUS = 1
f(DCO27)
FN 8 = FN_4
FN_8
FN 4 = FN_3
FN 3 = FN_2
FN 2 = 0,
0 DCOPLUS = 1 (see Note 1)
f(DCO2)
FN 8 = FN_4
FN_8
FN 4 = FN_3
FN 3 = 0,
0 FN
FN_2
2=1
1, DCOPLUS = 1
f(DCO27)
FN 8 = FN_4
FN_8
FN 4 = FN_3
FN 3 = 0,
0 FN
FN_2
2 = 1,
1 DCOPLUS = 1 (see Note 1)
f(DCO2)
FN 8 = FN_4
FN_8
FN 4 = 0,
0 FN
FN_3
3 = 1,
1 FN_2
FN 2 = x, DCOPLUS = 1
f(DCO27)
FN 8 = FN_4
FN_8
FN 4 = 0,
0 FN
FN_3
3 = 1,
1 FN_2
FN 2 = x, DCOPLUS = 1 (see Note 1)
f(DCO2)
FN 8 = 0,
FN_8
0 FN
FN_4
4 = 1,
1 FN_3
FN 3 = FN_2
FN 2 = x, DCOPLUS = 1
f(DCO27)
FN 8 = 0,
FN_8
0 FN
FN_4
4 = 1,
1 FN
FN_3
3 = FN_2
FN 2 = x, DCOPLUS = 1 (see Note 1)
f(DCO2)
FN 8 = 1,
FN_8
1 FN
FN_4
4 = FN_3
FN 3 = FN_2
FN 2 = x, DCOPLUS = 1
f(DCO27)
FN 8 = 1,FN_4
FN_8
1 FN 4 = FN_3
FN 3 = FN_2
FN 2 = x, DCOPLUS = 1 (see Note 1)
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 13 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0
D = 2, DCOPLUS = 0 (see Note 2)
DV
Drift with VCC variation, N(DCO) = 01E0h, FN_8 = FN_4 = FN_3 =
FN_2 = 0, D = 2, DCOPLUS = 0 (see Note 2)
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MIN
2.2 V/3 V
TYP
MAX
1
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
2.2 V
UNIT
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
%_C
%/V
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO20C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC -- V
--40
--20
0
20
40
60
85
TA -- C
Figure 12. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
35
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 13. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 14. Five Overlapping DCO Ranges Controlled by FN_x Bits
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF
Oscillation allowance for
LF crystals
OALF
Integrated effective load
capacitance LF mode
capacitance,
(see Note 1)
CL,eff
fFault,LF
TEST CONDITIONS
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
1.8 V to 3.6 V
TYP
MAX
32,768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
UNIT
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0,
Measured at P1.5/ACLK,
fLFXT1,LF = 32,768Hz
2.2 V/3 V
30
Oscillator fault frequency,
LF mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
2.2 V/3 V
10
50
pF
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
37
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1, high frequency modes
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1
LFXT1 oscillator crystal frequency
Ceramic resonator
1.8 V to 3.6 V
0.45
8
MHz
fLFXT1
LFXT1 oscillator crystal frequency
Crystal resonator
1.8 V to 3.6 V
1
8
MHz
CL,eff
Integrated effective load
capacitance, HF mode
(see Note 1)
(see Note 2)
Duty cycle
1
Measured at P1.5/ACLK,
2.2 V/3 V
40
50
pF
60
%
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
crystal oscillator, XT2, high frequency modes
VCC
MIN
MAX
UNIT
fXT2
XT2 oscillator crystal frequency
PARAMETER
Ceramic resonator
1.8 V to 3.6 V
0.45
8
MHz
fXT2
XT2 oscillator crystal frequency
Crystal resonator
1.8 V to 3.6 V
1
8
MHz
CL,eff
Integrated effective load
capacitance, HF mode
(see Note 1)
(see Note 2)
Duty cycle
TEST CONDITIONS
TYP
1
Measured at P1.4/SMCLK,
2.2 V/3 V
40
50
pF
60
%
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD_A
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(LCD)
Supply Voltage Range
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
2.2
CLCD
Capacitor on LCDCAP (see Note 1)
Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000)
4.7
ICC(LCD)
Average Supply Current (see Note 2)
VLCD(typ) = 3 V, LCDCPEN = 1,
VLCDx = 1000, All segments on,
fLCD = fACLK/32, No LCD connected
(see Note 3), TA = 25C
fLCD
LCD frequency
VLCD
LCD voltage
VLCDx = 0000
VCC
V
VLCD
LCD voltage
VLCDx = 0001
2.60
V
VLCD
LCD voltage
VLCDx = 0010
2.66
V
VLCD
LCD voltage
VLCDx = 0011
2.72
V
VLCD
LCD voltage
VLCDx = 0100
2.78
V
VLCD
LCD voltage
VLCDx = 0101
2.84
V
VLCD
LCD voltage
VLCDx = 0110
2.90
V
VLCD
LCD voltage
VLCDx = 0111
2.96
V
VLCD
LCD voltage
VLCDx = 1000
3.02
V
VLCD
LCD voltage
VLCDx = 1001
3.08
V
VLCD
LCD voltage
VLCDx = 1010
3.14
V
VLCD
LCD voltage
VLCDx = 1011
3.20
V
VLCD
LCD voltage
VLCDx = 1100
3.26
V
VLCD
LCD voltage
VLCDx = 1101
3.32
V
VLCD
LCD voltage
VLCDx = 1110
3.38
VLCD
LCD voltage
VLCDx = 1111
3.44
RLCD
LCD Driver Output impedance
VLCD = 3 V, LCDCPEN = 1,
VLCDx = 1000, ILOAD = 10 A
2.2 V
3.6
F
3.8
A
1.1
2.2 V
V
kHz
V
3.60
10
V
k
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
3. Connecting an actual display will increase the current consumption depending on the size of the LCD.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
39
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON = 1,
1 CARSEL = 0
0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF =
1/2/3
1/2/3,
No load at P1.6/CA0 and P1.7/CA1
V(Ref025)
V(Ref050)
Voltage @ 0.25 V
V
CC
Voltage @ 0.5 V
V
TYP
MAX
VCC = 2.2 V
25
40
VCC = 3 V
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
80
node
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2 V / 3 V
0.23
0.24
0.25
node
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.5
CC
CC
MIN
CC
UNIT
A
A
A
A
V(RefVT)
See Figure 15 and
Figure 16
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0
P1 6/CA0 and P1
P1.7/CA1,
7/CA1
TA = 85C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
VIC
Common-mode input
voltage range
CAON = 1
VCC = 2.2 V / 3 V
0
VCC --1
Vp --VS
Offset voltage
See Note 2
VCC = 2.2 V / 3 V
--30
30
mV
Vhys
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
0
0.7
1.4
mV
TA = 25
25C,
C,
Overdrive 10 mV, without filter: CAF = 0
VCC = 2.2 V
80
165
300
VCC = 3 V
70
120
240
TA = 25
25C
C
Overdrive 10 mV, with filter: CAF = 1
VCC = 2.2 V
1.4
1.9
2.8
VCC = 3 V
0.9
1.5
2.2
t(response LH and HL), see Note 3
mV
V
ns
s
s
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON
is set at the same time, a settling time of up to 300ns is added to the response time.
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 2.2 V
600
VREF -- Reference Voltage -- mV
VREF -- Reference Voltage -- mV
VCC = 3 V
Typical
550
500
450
400
--45
--25
--5
15
35
55
75
600
Typical
550
500
450
400
--45
95
--25
TA -- Free-Air Temperature -- C
0
15
35
55
75
95
TA -- Free-Air Temperature -- C
Figure 15. V(RefVT) vs Temperature
0V
--5
Figure 16. V(RefVT) vs Temperature
VCC
CAF
1
CAON
Low-Pass Filter
V+
V--
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
2 s
Figure 17. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-400 mV
V+
t(response)
Figure 18. Overdrive Definition
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
41
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER
AVCC
ISD16
Analog supply
voltage
Analog supply
current including
internal reference
TEST CONDITIONS
Analog front-end
input clock
frequency
MIN
AVCC = DVCC
AVSS = DVSS = 0V
TYP
MAX
2.5
3.6
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
SD16BUFx = 00, GAIN: 1,2
3V
750
1050
SD16BUFx = 00, GAIN: 4,8,16
3V
830
1150
SD16BUFx = 00, GAIN: 32
3V
1150
1700
SD16LP = 1,
fSD16 = 0
0.5
5 MHz,
MHz
SD16OSR = 256
SD16BUFx = 00, GAIN: 1
3V
730
1030
SD16BUFx = 00, GAIN: 32
3V
830
1150
SD16BUFx = 01, GAIN: 1
3V
850
SD16BUFx = 10, GAIN: 1
3V
1000
SD16BUFx = 11, GAIN: 1
3V
1130
SD16LP = 0,
0
SD16OSR = 256
fSD16
VCC
SD16LP = 0 (Low power mode disabled)
3V
0.03
1
SD16LP = 1 (Low power mode enabled)
3V
0.03
0.5
1.1
UNIT
V
A
A
MH
MHz
SD16_A, input range
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VI
Absolute input
voltage range
SD16BUFx = 00
VIC
Common mode
Common-mode
input voltage range
SD16BUFx = 00
AVSS -0.1V
AVCC
SD16BUFx > 00
AVSS +0.2V
AVCC --1.2 V
VID,FSR
Differential full
scale input voltage
range
Bipolar mode, SD16UNI = 0
--VREF/2GAIN
+VREF/2GAIN
mV
+VREF/2GAIN
mV
VID
ZI
ZID
Differential input
voltage range for
specified
performance
(see Note 1)
Input impedance
(one input pin to
AVSS)
Differential input
impedance (IN+ to
IN--)
AVSS -0.1V
AVCC
SD16BUFx > 00
AVSS +0.2V
AVCC --1.2 V
Unipolar mode, SD16UNI = 1
SD16REFON = 1
fSD16 = 1 MHz,
SD16BUFx = 00
fSD16 = 1 MHz,
SD16BUFx = 01
fSD16 = 1 MHz,
SD16BUFx = 00
fSD16 = 1 MHz,
SD16BUFx > 00
0
SD16GAINx = 1
500
SD16GAINx = 2
250
SD16GAINx = 4
125
SD16GAINx = 8
62
SD16GAINx = 16
31
SD16GAINx = 32
15
SD16GAINx = 1
3V
200
SD16GAINx = 32
3V
75
SD16GAINx = 1
3V
10
SD16GAINx = 1
3V
300
400
SD16GAINx = 32
3V
100
150
SD16GAINx = 1
3V
10
V
V
mV
k
M
k
M
NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined
by VFSR+ = +(VREF/2)/GAIN and VFSR-- = --(VREF/2)/GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR-- .
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01)
PARAMETER
TEST CONDITIONS
VCC
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 256
MIN
TYP
3V
84
3V
84
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 1024
3V
84
Nominal gain
SD16GAINx = 1, SD16OSRx = 1024
3V
dG/dT
Gain temperature
drift
SD16GAINx = 1, SD16OSRx = 1024 (see Note 1)
3V
dG/dVCC
Gain supply voltage
drift
SD16GAINx = 1, SD16OSRx = 1024, VCC = 2.5 V to 3.6 V
(see Note 2)
SINAD
Signal-to-noise +
distortion ratio
SD16GAINx = 1,Signal Amplitude = 500mV
SD16OSRx = 512
fIN = 2.8Hz
0.97
1.00
MAX
UNIT
dB
1.02
15
ppm/_C
0.35
%/V
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))
2. Calculated using the box method: (MAX(2.5...3.6V) -- MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V -- 2.5 V)
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
SINAD
G
Signal to noise +
Signal-to-noise
distortion ratio
Nominal gain
EOS
Offset error
dEOS/dT
Offset error
temperature
coefficient
CMRR
PSRR
Common mode
Common-mode
rejection ratio
Power supply
rejection ratio
TEST CONDITIONS
VCC
MIN
TYP
MAX
SD16GAINx = 1,Signal Amplitude = 500mV
3V
83.5
85
SD16GAINx = 2,Signal Amplitude = 250mV
3V
81.5
84
3V
76
79.5
3V
73
76.5
SD16GAINx = 16,Signal Amplitude = 31mV
3V
69
73
SD16GAINx = 32,Signal Amplitude = 15mV
3V
62
69
SD16GAINx = 1
3V
0.97
1.00
1.02
SD16GAINx = 2
3V
1.90
1.96
2.02
SD16GAINx = 4
3V
3.76
3.86
3.96
SD16GAINx = 8
3V
7.36
7.62
7.84
SD16GAINx = 16
3V
14.56
15.04
15.52
SD16GAINx = 32
3V
27.20
28.35
29.76
SD16GAINx = 1
3V
0.2
SD16GAINx = 32
3V
1.5
SD16GAINx = 1
3V
4
20
100
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
fIN = 50Hz,
100Hz
SD16GAINx = 32
3V
20
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
3V
90
SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
3V
75
SD16GAINx = 1
3V
80
UNIT
dB
%FSR
ppm
FSR/_C
dB
dB
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C)) / MIN(--40...85_C) / (85_C -- (--40_C))
2. Calculated using the ADC output code and the box method:
(MAX-code(2.5...3.6V) -- MIN-code(2.5...3.6V)) / MIN-code(2.5...3.6V) / (3.6V -- 2.5 V)
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
43
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, linearity (fSD16 = 1MHz, SD16REFON = 1, SD16BUFx = 00)
PARAMETER
INL
Integral non
non-linearity
linearit
TEST CONDITIONS
VCC
MIN
TYP
SD16OSR = 256, SD16GAINx = 000b,
Signal Amplitude = 500 mV
3V
1.5
SD16OSR = 256, SD16GAINx = 101b,
Signal Amplitude = 15 mV
3V
6
SD16OSR = 1024, SD16GAINx = 000b,
Signal Amplitude = 500 mV
3V
0.8
SD16OSR = 1024, SD16GAINx = 101b,
Signal Amplitude = 15 mV
3V
3.5
MAX
UNIT
LSB
LSB
typical characteristics -- SD16_A SINAD performance over OSR
100.0
95.0
90.0
SINAD -- dB
85.0
80.0
75.0
70.0
65.0
60.0
55.0
50.0
10.00
100.00
1000.00
OSR
Figure 19. SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1
SD16_A, temperature sensor and built-in VCC sense
PARAMETER
TEST CONDITIONS
TCSensor
Sensor temperature
coefficient
See Note 1
VOffset,sensor
Sensor offset voltage
See Note 1
VSensor
VCC,Sense
Sensor output
S
t t voltage
lt
(see Note 3)
VCC divider at input 5
VCC
1.18
TYP
1.32
--100
MAX
UNIT
1.46
mV/K
100
mV
Temperature sensor voltage at TA = 85C
3V
435
475
515
Temperature sensor voltage at TA = 25C
3V
355
395
435
Temperature sensor voltage at TA = 0C (see Note 1)
3V
320
360
400
0.08
1/11
0.1
fSD16 = 32kHz, SD16OSRx = 256, SD16REFON = 1
NOTES: 1. Not production tested, limits characterized.
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [C] ) + VOffset,sensor [mV]
3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
44
MIN
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
mV
V
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, built-in voltage reference
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VREF
Internal reference
voltage
SD16REFON = 1, SD16VMIDON = 0
3V
IREF
Reference supply
current
SD16REFON = 1, SD16VMIDON = 0
3V
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
3V
CREF
VREF load capacitance
SD16REFON = 1, SD16VMIDON = 0 (see Note 2)
ILOAD
VREF(I) maximum load
current
SD16REFON = 1, SD16VMIDON = 0
3V
tON
Turn on time
SD16REFON = 0-->1, SD16VMIDON = 0,
CREF = 100nF
3V
5
PSRR
Line regulation
SD16REFON = 1, SD16VMIDON = 0
3V
100
1.14
MAX
UNIT
1.20
1.26
V
175
260
A
18
50
ppm/K
100
nF
200
nA
ms
uV/V
NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))
2. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VREF,BUF
Reference buffer output
voltage
SD16REFON = 1, SD16VMIDON = 1
3V
1.2
IREF,BUF
Reference Supply +
Reference output buffer
quiescent current
SD16REFON = 1, SD16VMIDON = 1
3V
385
CREF(O)
Required load
capacitance on VREF
SD16REFON = 1, SD16VMIDON = 1
ILOAD,Max
Maximum load current
on VREF
SD16REFON = 1, SD16VMIDON = 1
3V
Maximum voltage
variation vs load current
|ILOAD| = 0 to 1mA
3V
Turn on time
SD16REFON = 0-->1, SD16VMIDON = 1,
CREF = 470nF
3V
tON
MAX
UNIT
V
600
470
A
nF
--15
1
mA
+15
mV
100
s
SD16_A, external reference input
PARAMETER
TEST CONDITIONS
VCC
VREF(I)
Input voltage range
SD16REFON = 0
3V
IREF(I)
Input current
SD16REFON = 0
3V
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
V
50
nA
45
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, supply specifications
PARAMETER
AVCC
IDD
PSRR
Analog supply voltage
Supply current
(see Notes 1 and 2)
Power supply rejection
ratio (see Notes 3 and 4)
TEST CONDITIONS
VCC
AVCC = DVCC,
AVSS = DVSS = 0 V
MIN
TYP
2.20
MAX
UNIT
3.60
V
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
2.2 V/3 V
50
110
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
2.2 V/3 V
50
110
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
2.2 V/3 V
200
440
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, VREF,DAC12 = AVCC
2.2 V/3 V
700
1500
DAC12_xDAT = 800h, VREF,DAC12 = 1.2 V,
AVCC = 100 mV
2.7 V
70
A
A
dB
NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*logAVCC/VDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 20)
PARAMETER
INL
DNL
DNL
EO
TEST CONDITIONS
Integral nonlinearity
(see Note 1)
VCC
MIN
TYP
MAX
UNIT
2.0
8.0
LSB
0.4
+1.3
LSB
VREF,DAC12 = 1.2 V or VREF,ext = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
VREF,ext = 1.2 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
VREF,ext = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
0.4
1.0
LSB
Differential nonlinearity
(see Note 1)
VREF,DAC12 = 1.2 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
0.4
1.0
LSB
Offset voltage without
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2 V
DAC12AMPx = 7, DAC12IR = 1
2.7 V
Offset voltage with
calibration
(see Notes 1, 2)
VREF,DAC12 = 1.2 V
DAC12AMPx = 7, DAC12IR = 1
Differential nonlinearity
(see Note 1)
dE(O)/dT
Offset error temperature
coefficient (see Note 1)
EG
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
tOffset_Cal
Offset Cal
Time for offset calibration
(see Note 3)
--1
20
mV
2.7 V
2.5
2.7 V
VREF,DAC12 = 1.2 V
30
2.7 V
V/C
3.50
2.7 V
% FSR
ppm of
FSR/C
10
DAC12AMPx = 2
2.7 V
100
DAC12AMPx = 3,5
2.7 V
32
DAC12AMPx = 4,6,7
2.7 V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VREF,DAC12/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
= {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Ideal transfer
function
Gain Error
DAC Code
Figure 20. Linearity Test Load Conditions and Gain/Offset Definition
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
47
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
INL -- Integral Nonlinearity Error -- LSB
4
VCC = 2.2 V, VREF = 1.2 V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
--1
--2
--3
--4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT -- Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL -- Differential Nonlinearity Error -- LSB
2.0
VCC = 2.2 V, VREF = 1.2 V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
--0.5
--1.0
--1.5
--2.0
0
512
1024
1536
2048
2560
DAC12_xDAT -- Digital Code
48
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3072
3584
4095
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
VO
TEST CONDITIONS
Output voltage
range (see Note 1,
1
Figure 23)
CL(DAC12)
Max DAC12 load
capacitance
IL(DAC12)
Max DAC12 load
current
RO/P(DAC12)
Output resistance
(see Figure 23)
VCC
MIN
TYP
MAX
No Load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
0
0.005
No Load, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
AVCC --0.05
AVCC
RLoad = 3 k, VREF,DAC12 = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
0
0.1
RLoad = 3 k, VREF,DAC12 = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
AVCC --0.13
AVCC
UNIT
V
2.2 V/3 V
100
2.2V
--0.5
+0.5
3V
--1.0
+1.0
RLoad = 3 k, VO/P(DAC12) 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
2.2 V/3 V
150
250
RLoad = 3 k, VO/P(DAC12) AVCC --0.3 V
DAC12_xDAT = 0FFFh
2.2 V/3 V
150
250
RLoad = 3 k,
0.3V VO/P(DAC12) AVCC -- 0.3V
2.2 V/3 V
1
4
pF
mA
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
ILoad
Max
RLoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC --0.3V
VOUT
AV CC
Figure 23. DAC12_x Output Resistance Tests
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
49
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
VREF
Reference input
voltage range
Ri(VREF)
Reference input
resistance
NOTES: 1.
2.
3.
4.
5.
TYP
MAX
DAC12IR = 0 (see Notes 1 and 2)
2.2 V/3 V
VCC
MIN
AVCC/3
AVCC+0.2
DAC12IR = 1 (see Notes 3 and 4)
2.2 V/3 V
AVCC
AVCC+0.2
DAC12IR = 0, SD16VMIDON = 1
(see Note 5)
2.2 V/3 V
20
DAC12IR = 1, SD16VMIDON = 1
2.2 V/3 V
40
UNIT
V
M
48
56
k
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC -- VE(O)] / [3*(1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VREF = [AVCC -- VE(O)] / (1 + EG).
Characterized, not production tested
12-bit DAC, dynamic specifications (VREF,DAC12 = AVCC, DAC12IR = 1) (see Figure 24 and Figure 25)
PARAMETER
tON
tS(FS)
tS(C-C)
SR
TEST CONDITIONS
DAC12
on time
on-time
DAC12_xDAT = 800h,
ErrorV(O) < 0.5 LSB
(see Note 1, Figure 24)
Settling
time full scale
time,full-scale
DAC12_xDAT
DAC12
xDAT =
80h F7Fh 80h
Settling time,
time
code to code
DAC12_xDAT =
3F8h 408h
3F8h
408h 3F8h
BF8h C08h BF8h
Slew Rate
Glitch energy: full
full-scale
scale
DAC12 xDAT =
DAC12_xDAT
80h F7Fh 80h
DAC12_xDAT
DAC12
xDAT =
80h F7Fh 80h
VCC
MIN
TYP
MAX
DAC12AMPx = 0 {2, 3, 4}
2.2 V/3 V
60
120
DAC12AMPx = 0 {5, 6}
2.2 V/3 V
15
30
DAC12AMPx = 0 7
2.2 V/3 V
6
12
DAC12AMPx = 2
2.2 V/3 V
100
200
DAC12AMPx = 3,5
2.2 V/3 V
40
80
DAC12AMPx = 4,6,7
2.2 V/3 V
15
30
DAC12AMPx = 2
2.2 V/3 V
5
DAC12AMPx = 3,5
2.2 V/3 V
2
DAC12AMPx = 4,6,7
2.2 V/3 V
DAC12AMPx = 2
2.2 V/3 V
0.05
0.12
DAC12AMPx = 3,5
2.2 V/3 V
0.35
0.7
DAC12AMPx = 4,6,7
2.2 V/3 V
1.5
DAC12AMPx = 2
2.2 V/3 V
600
DAC12AMPx = 3,5
2.2 V/3 V
150
DAC12AMPx = 4,6,7
2.2 V/3 V
30
Conversion 1
ILoad
VOUT
RLoad = 3 k
Glitch
Energy
Conversion 2
RO/P(DAC12.x)
+/-- 1/2 LSB
CLoad = 100pF
Figure 24. Settling Time and Glitch Energy Testing
50
Conversion 3
AV CC
tsettleLH
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
s
s
V/s
2.7
+/-- 1/2 LSB
2
s
1
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 24.
2. Slew rate applies to output voltage steps > = 200 mV.
DAC Output
UNIT
tsettleHL
nV-ss
nV
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 25. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25C unless otherwise noted)
PARAMETER
BW --3dB
3 dB bandwidth,
3-dB
VDC = 1.5 V,
VAC = 0.1VPP
(see Figure 26)
TEST CONDITIONS
VCC
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
MIN
2.2 V/3 V
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1,
DAC12_xDAT = 800h
2.2 V/3 V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2 V/3 V
550
MAX
UNIT
kHz
NOTES: 1. RLOAD = 3 k, CLOAD = 100 pF
Ve REF+
ILoad
DAC12_x
AC
RLoad = 3 k
AV CC
2
DACx
CLoad = 100pF
DC
Figure 26. Test Conditions for 3-dB Bandwidth Specification
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
51
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA, supply specifications
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage range
MIN
Supply current (see Note 1)
Medium Mode
2.2 V/3 V
Slow Mode
PSRR
Power supply rejection ratio
MAX
180
290
110
190
50
80
2.2
Fast Mode
ICC
TYP
Non-inverting
2.2 V/3 V
3.6
70
UNIT
V
A
dB
NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively.
operational amplifier OA, input/output specification
PARAMETER
VI/P
IIkg
TEST CONDITIONS
VCC
Input voltage range
Input leakage current
(see Notes 1 and 2)
MIN
--0.1
TA = --40 to +55_C
2 2 V/3 V
2.2
TA = +55 to +85_C
Medium Mode
Voltage noise density,
densit I/P
5
--20
5
20
140
30
2.2 V/3 V
Offset voltage drift
with supply, I/P
0.3 V VIN VCC --1.0 V
VCC 10%, TA = 25C
2.2 V/3 V
Low level output voltage
Low-level
voltage, O/P
CMRR
NOTES: 1.
2.
3.
4.
52
Common-mode rejection ratio
Fast Mode, ISOURCE --500 A
Slow Mode, ISOURCE --150 A
Fast Mode, ISOURCE +500 A
Slow Mode, ISOURCE +150 A
Noninverting
2 2 V/3 V
2.2
2 2 V/3 V
2.2
2.2 V/3 V
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method
Specification valid for voltage-follower OAx configuration
POST OFFICE BOX 655303
nV/H
nV/Hz
65
2.2 V/3 V
see Note 3
VOL
nA
50
fV(I/P) = 10 kHz
Offset temperature drift, I/P
High level output voltage,
High-level
voltage O/P
V
80
Slow Mode
Offset voltage, I/P
VOH
UNIT
50
fV(I/P) = 1 kHz
Slow Mode
VIO
VCC --1.2
0.5
Fast Mode
Medium Mode
MAX
--5
Fast Mode
Vn
TYP
DALLAS, TEXAS 75265
10
10
1.5
VCC --0.2
VCC
VCC --0.1
VCC
VSS
0.2
VSS
0.1
70
mV
V/C
mV/V
V
V
dB
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA, dynamic specifications
PARAMETER
SR
TEST CONDITIONS
Slew rate
VCC
MIN
TYP
Fast Mode
1.2
Medium Mode
0.8
Slow Mode
0.3
Open-loop voltage gain
m
UNIT
V/s
100
dB
Phase margin
CL = 50 pF
60
deg
Gain margin
CL = 50 pF
20
dB
Noninverting, Fast Mode,
RL = 47 k, CL = 50 pF
2.2
Noninverting, Medium Mode,
RL = 300 k, CL = 50pF
Gain-bandwidth product
(see Figure 27 and Figure 28)
GBW
MAX
1.4
2.2 V/3 V
Non-inverting, Slow Mode,
RL = 300 k, CL = 50pF
ten(on)
Enable time on
ten(off)
Enable time off
MHz
0.5
ton, Noninverting, Gain = 1
2.2 V/3 V
10
2.2 V/3 V
20
s
1
s
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
0
140
120
100
--50
Fast Mode
Fast Mode
60
40
Phase -- degrees
Gain -- dB
80
Medium Mode
20
0
Slow Mode
--20
--100
Medium Mode
--150
Slow Mode
--40
--200
--60
--80
1
10
100
1000
10000
100000
Input Frequency -- kHz
--250
1
10
100
1000
10000
100000
Input Frequency -- kHz
Figure 27
Figure 28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
53
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
switches between OA terminals and pins
PARAMETER
VCC
TEST CONDITIONS
Supply voltage range
Ilkg
Input leakage current
(see Note 1)
TA = --40C to 55C
IIN
Input current
Input switched to ON
RON
On resistance
IIN = 100 A
VCC
MIN
--
2.2
TYP
MAX
1
10
UNIT
3.6
TA = 55C to 85C
V
nA
50
0
100
A
1
k
NOTES: 1. ESD damage can degrade input current leakage.
typical characteristics
RON vs VCOM
RON vs VCOM
3000.0
1700.0
2750.0
2500.0
2250.0
2000.0
1750.0
Typical
TA = 25C
VCC = 2.2 V
1400.0
VCC = 2.7 V
VCC = 3 V
VCC = 3.6 V
1300.0
1200.0
1250.0
1100.0
1000.0
1000.0
750.0
900.0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
VCOM -- Common Mode Input Voltage (V)
800.0
0.0
TA = 85C
TA = 25C
TA = --40C
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
VCOM -- Common Mode Input Voltage (V)
Figure 29
54
VCC = 3V
1500.0
1500.0
500.0
0.0
Typical
1600.0
Figure 30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3.6
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer A clock frequency
Timer_A
Internal: SMCLK, ACLK,
External: TACLK,
TACLK INCLK
INCLK,
Duty cycle = 50% 10%
tTA,cap
Timer_A, capture timing
TA0, TA1, TA2
VCC
MIN
MAX
2.2 V
8
3V
10
2.2 V/3 V
20
UNIT
MHz
ns
Timer_B
PARAMETER
TEST CONDITIONS
fTB
Timer B clock frequency
Timer_B
Internal: SMCLK, ACLK,
External: TBCLK
TBCLK,
Duty cycle = 50% 10%
tTB,cap
Timer_B, capture timing
TB0, TB1, TB2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCC
MIN
MAX
2.2 V
8
3V
10
2.2 V/3 V
20
UNIT
MHz
ns
55
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (see
Note 1)
t
UART receive deglitch time
(see Note NO TAG)
MAX
UNIT
fSYSTEM
MHz
2.2V /3 V
2
MHz
2.2 V
50
150
ns
3V
50
100
ns
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 31 and Figure 32)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
NOTE:
TEST CONDITIONS
SIMO output data valid time
f UCxCLK =
1
2t LO∕HI
with
VCC
MIN
SMCLK, ACLKm
Duty cycle = 50% 10%
UCLK edge to SIMO valid
valid, CL = 20 pF
MAX
UNIT
fSYSTEM
MHz
2.2 V
110
ns
3V
75
ns
2.2 V
0
ns
3V
0
ns
2.2 V
30
ns
3V
20
ns
t LO∕HI ≥ max(t VALID,MO(USCI) + t SU,SI(Slave), t SU,MI(USCI) + t VALID,SO(Slave)).
For the slave’s parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 33 and Figure 34)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input
inp t data setup
set p time
tHD,SI
SIMO inp
inputt data hold time
tVALID,SO
NOTE:
SOMI o
output
tp t data valid
alid time
f UCxCLK =
1
2t LO∕HI
with
UCLK edge to SOMI valid,
CL = 20 pF
50
10
ns
2.2 V
20
ns
3V
15
ns
2.2 V
10
ns
3V
10
ns
2.2 V
75
110
ns
3V
50
75
ns
t LO∕HI ≥ max(t VALID,MO(Master) + t SU,SI(USCI), t SU,MI(Master) + t VALID,SO(USCI)).
For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master.
56
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ns
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 31. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 32. SPI Master Mode, CKPH = 1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
57
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 33. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
SOMI
Figure 34. SPI Slave Mode, CKPH = 1
58
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
tSTE,DIS
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 35)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
2.2 V/3 V
0
fSCL 100kHz
2.2 V/3 V
4.0
s
fSCL > 100kHz
2.2 V/3 V
0.6
s
fSCL 100kHz
2.2 V/3 V
4.7
s
fSCL > 100kHz
2.2 V/3 V
0.6
s
ns
tHD,STA
Hold time (repeated) START
tSU,STA
Set p time for a repeated START
Setup
tHD,DAT
Data hold time
2.2 V/3 V
0
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V/3 V
4.0
s
tSP
Pulse width of spikes suppressed by
input filter
2.2 V
50
150
600
ns
3V
50
100
600
ns
tHD,STA
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 35. I2C Mode Timing
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
59
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
VCC
MIN
TYP
MAX
UNIT
Program and Erase supply voltage
2.2
3.6
V
fFTG
Flash Timing Generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.5 V/3.6V
3
5
mA
IERASE
Supply current from DVCC during erase
2.5 V/3.6V
3
7
mA
tCPT
Cumulative program time
see Note 1
2.5 V/3.6V
10
ms
tCMErase
Cumulative mass erase time
see Note 2
2.5 V/3.6V
ERASE)
200
104
Program/Erase endurance
TJ = 25C
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for 1st byte or word
30
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
cycles
100
years
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
See Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
See Note 2
VCC
MIN
2.2 V
0
3V
0
2.2 V/ 3 V
25
TYP
MAX
UNIT
5
MHz
10
MHz
60
90
k
MIN
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TA = 25C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
60
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.0, input/output with Schmitt trigger
CAPD.0
P1DIR.0
0
P1SEL2.0
1
Direction
0: Input
1: Output
Pad Logic
0
Module X OUT
1
P1OUT.0
1
0
P1.0/TA0/OA0RFB
P1SEL.0
Bus
Keeper
EN
P1IN.0
EN
Module X IN
D
P1IE.0
P1IRQ.0
EN
Q
SWCTL1.SWCTL8
Set
P1IFG.0
OA0
P1SEL.0
P1IES.0
Interrupt
Edge Select
Port P1 (P1.0) pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TA0/OA0RFB
/
/
X
0
FUNCTION
CONTROL BITS / SIGNALS
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.x (I/O)
0
I: 0, O: 1
0
0
Timer_A3.CCI0A
0
0
1
0
Timer_A3.TA0
0
1
1
0
OA0RFB
x
x
1
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
61
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.1, input/output with Schmitt trigger
CAPD.1
P1DIR.1
0
P1SEL2.1
1
Module X OUT
0
MCLK
1
Direction
0: Input
1: Output
Pad Logic
1
P1OUT.1
0
P1.1/TA0/MCLK/
OA1RFB
Bus
Keeper
EN
P1SEL.1
P1IN.1
EN
Module X IN
D
P1IE.1
EN
P1IRQ.1
Q
SWCTL1.SWCTL12
Set
P1IFG.1
OA1
P1SEL.1
P1IES.1
Interrupt
Edge Select
Port P1 (P1.1) pin functions
PIN NAME (P1.X)
(P1 X)
P1.1/TA0/MCLK
/
/
OA1RFB
62
X
1
FUNCTION
CONTROL BITS / SIGNALS
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x
P1.x (I/O)
0
I: 0, O: 1
0
0
Timer_A3.CCI0A
0
0
1
0
Timer_A3.TA0
0
1
1
0
OA1RFB
x
0
1
1
MCLK
0
1
1
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.2 input/output with Schmitt trigger
INCH
Pad Logic
1
A4-
DV SS
0
SD16AE.2
CAPD.2
P1DIR.2
0
Direction
0: Input
1: Output
1
P1OUT.2
0
Module X OUT
1
P1.2/TA1/A4-/OA0I3
Bus
Keeper
EN
P1SEL.2
P1IN.2
EN
D
Module X IN
P1IE.2
EN
P1IRQ.2
Q
Set
P1IFG.2
P1SEL.2
P1IES.2
OA0
Interrupt
Edge Select
Port P1 (P1.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
P1.2/TA1/A4--/OA0I3
/
/
/
2
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
OAN (OA0)
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
xx
0
Timer_A3.CCI1A
0
0
1
xx
0
Timer_A3.TA1
0
1
1
xx
0
A4--
x
x
x
xx
1
OA0I3
x
x
x
10
1
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
63
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.3, input/output with Schmitt trigger
INCH =4
Pad Logic
A4+
SD16AE.3
CAPD.3
P1DIR.3
0
Direction
0: Input
1: Output
1
P1OUT.3
0
Module X OUT
1
P1.3/TBOUTH/
SVSOUT/A4+/OA1I3
Bus
Keeper
EN
P1SEL.3
P1IN.3
EN
D
Module X IN
P1IE.3
EN
P1IRQ.3
Q
Set
P1IFG.3
P1SEL.3
OA1
Interrupt
Edge Select
P1IES.3
Port P1 (P1.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
P1.3/TBOUTH/
/
/
SVSOUT/A4+/OA1I3
3
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
OAN (OA1)
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
xx
0
TBOUTH
0
0
1
xx
0
SVSOUT
0
1
1
xx
0
A4+
x
x
x
xx
1
OA1I3
x
x
x
10
1
NOTES: 1. x: Don’t care.
64
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.4, input/output with Schmitt trigger
Pad Logic
DAC12_1OUT
DAC12OPS
INCH=3
1
A3-
0
DV SS
SD16AE.4
CAPD.4
P1DIR.4
0
Direction
0: Input
1: Output
1
P1OUT.4
0
Module X OUT
1
P1.4/TBCLK/
SMCLK/A3-/
OA1I0/DAC1
Bus
Keeper
EN
P1SEL.4
P1IN.4
EN
Module X IN
D
P1IE.4
P1IRQ.4
EN
Q
Set
P1IFG.4
P1SEL.4
OA1
Interrupt
Edge Select
P1IES.4
Port P1 (P1.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
P1.4TBCLK/SMCLK/
/
/
A3--/OA1I0/DAC1
4
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1SEL2.x = 0
OAP (OA1)
P1SEL2.x = 0
DAC12OPS
(DAC12_1)
I: 0, O: 1
0
0
xx
0
TBCLK
0
1
0
xx
0
SMCLK
1
1
0
xx
0
A3--
x
x
1
xx
0
OA1I0
x
x
1
00
0
DAC1
x
x
x
xx
1
FUNCTION
P1.x (I/O)
CAPD.x
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
65
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.5, input/output with Schmitt trigger
INCH =3
Pad Logic
Ax+
SD16AE.5
CAPD.5
P1DIR.5
0
Direction
0: Input
1: Output
1
P1OUT.5
0
Module X OUT
1
P1.5/TACLK/ACLK/A3+
Bus
Keeper
EN
P1SEL.5
P1IN.5
EN
D
Module X IN
P1IE.5
EN
P1IRQ.5
Q
Set
P1IFG.5
P1SEL.5
P1IES.5
Interrupt
Edge Select
Port P1 (P1.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
P1.5/TACLK/ACLK/
/
/
/
A3+
5
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1SEL2.x = 0
SD16AE.x
P1.x (I/O)
0
I: 0, O: 1
0
0
TACLK
0
0
1
0
ACLK
0
1
1
0
A3+
x
x
x
1
NOTES: 1. x: Don’t care.
66
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.6, input/output with Schmitt trigger
Pad Logic
To Comparator_A
From Comparator_A
CAPD.6
DAC12_0OUT
DAC12OPS
1
A20
DVSS
INCH=2
SD16AE.6
P1DIR.6
0
Direction
0: Input
1: Output
1
P1OUT.6
0
0/1
1
P1.6/CA0/A2-/
OA0I0/DAC0
Bus
Keeper
EN
P1SEL.6
P1IN.6
EN
Module X IN
D
P1IE.6
P1IRQ.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
OA0
Interrupt
Edge Select
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
67
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Port P1 (P1.6) pin functions
CONTROL BITS / SIGNALS
P1DIR.x
P1SEL.x
P1SEL2.x = 0
CAPD.x
P1SEL2.x = 0
SD16AE.x
P1SEL2.x = 0
OAP (OA0)
P1SEL2.x = 0
DAC12OPS
(DAC12_0)
I: 0, O: 1
0
0
0
xx
0
CA0
x
x
1 or selected
x
xx
x
A2--
x
x
x
1
xx
x
OA0I0
x
x
x
x
00
x
DAC0
x
x
x
x
xx
1
PIN NAME (P1.X)
X
FUNCTION
P1.6/CA0/A2--/OA0I0/
/
/
/
/
DAC0
6
P1.x (I/O)
NOTES: 1. x: Don’t care.
68
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P1 pin schematic: P1.7, input/output with Schmitt trigger
Pad Logic
To Comparator_A
From Comparator_A
CAPD.7
SD16AE.7
INCH=2
A2+
P1DIR.7
0
Direction
0: Input
1: Output
1
P1OUT.7
0
0/1
1
P1.7/CA1/A2+
Bus
Keeper
EN
P1SEL.7
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge Select
Port P1 (P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
P1.7/CA1/A2+
/
/
X
7
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x = 0
CAPD.x
P1SEL2.x = 0
SD16AE.x
I: 0, O: 1
0
0
0
CA1
x
x
1 or selected
x
A2+
x
x
x
1
P1.x (I/O)
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
69
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt trigger
Pad Logic
LCDS0
Segment Sx
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
0
Module X OUT
1
P2.0/TA2/S1
P2.1/TB0/S0
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.0 to P2.1) pin functions
PIN NAME (P2.X)
(P2 X)
P2.0/TA2/S1
/
/
P2.1/TB0/S0
/
/
X
0
1
CONTROL BITS / SIGNALS
FUNCTION
P2.x (I/O)
P2SEL.x
LCDS0
I: 0, O: 1
0
0
Timer_A3.CCI2A
0
1
0
Timer_A3.TA2
1
1
0
S1
x
x
1
I: 0, O: 1
0
0
Timer_B3.CCI0A
0
1
0
Timer_B3.TB0
1
1
0
S0
x
x
1
P2.x (I/O)
NOTES: 1. x: Don’t care.
70
P2DIR.x
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.2 to P2.3, input/output with Schmitt trigger
P2DIR.x
0
Direction
0: Input
1: Output
1
Module X OUT
0
P2OUT.x
1
Pad Logic
P2.2/TB1
P2.3/TB2
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.2 to P2.3) pin functions
PIN NAME (P2.X)
(P2 X)
P2.2/TB1
/
X
2
FUNCTION
P2.x (I/O)
Timer_B3.CCI1A
Timer_B3.TB1
P2.3/TB2
/
3
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
Timer_B3.CCI2A
0
1
TimerB3.TB2
1
1
P2.x (I/O)
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
71
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.4 and P2.5, input/output with Schmitt trigger
P2DIR.x
0
Module
direction
1
P2OUT.x
0
Module X OUT
Direction
0: Input
1: Output
Pad Logic
1
P2.4/UCA0TXD/UCA0SIMO
P2.5/UCA0RXD/UCA0SOMI
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Port P2 (P2.4 and P2.5) pin functions
PIN NAME (P2.X)
(P2 X)
X
P2.4/UCA0TXD/
/
/
UCA0SIMO
4
P2.5/UCA0RXD/
/
/
UCA0SOMI
5
FUNCTION
P2.x (I/O)
UCA0TXD/UCA0SIMO (see Notes 2)
P2.x (I/O)
UCA0RXD/UCA0SOMI (see Notes 2)
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
72
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.x
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P2 pin schematic: P2.6 and P2.7, inpututput with Schmitt trigger
LCDS0
Pad Logic
Segment Sy
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
0
0/1
1
P2.6/CAOUT/S2
P2.7/S3
Bus
Keeper
EN
P2SEL.x
P2IN.x
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
Interrupt
Edge Select
P2IES.x
Port P2 (P2.6 and P2.7) pin functions
PIN NAME (P2.X)
(P2 X)
P2.6/CAOUT/S2
/
/
P2.7/S3
/
X
6
7
CONTROL BITS / SIGNALS
FUNCTION
P2.x (I/O)
P2DIR.x
P2SEL.x
LCDS0
I: 0, O: 1
0
0
CAOUT
1
1
0
S2
x
x
1
P2.x (I/O)
I: 0, O: 1
0
0
Vss
1
1
0
S3
x
x
1
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
73
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.0 and P3.3, input/output with Schmitt trigger
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
Pad Logic
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK
P3.3/UCB0CLK/UCA0STE
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3 (P3.0 and P3.3) pin functions
PIN NAME (P3.X)
(P3 X)
X
P3.0/UCB0STE/
/
/
UCA0CLK
0
P3.3/UCB0CLK/
/
/
UCA0STE
3
FUNCTION
P3.x (I/O)
UCB0STE/UCA0CLK (see Note 2)
P3.x (I/O)
UCB0CLK/UCA0STE (see Note 2)
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
74
POST OFFICE BOX 655303
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CONTROL BITS / SIGNALS
P3DIR.x
P3SEL.x
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.1 and P3.2, input/output with Schmitt trigger
Pad Logic
LCDS24
Segment Sy
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA/S26
P3.2/UCB0SOMI/UCB0SCL/S27
Bus
Keeper
EN
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3 (P3.1 and P3.2) pin functions
PIN NAME (P3.X)
(P3 X)
P3.1/UCB0SIMO/
/
/
UCB0SDA/S26
P3.2/UCB00SOMI/
/
/
UCB0SCL/S27
X
1
2
CONTROL BITS / SIGNALS
FUNCTION
P3.x (I/O)
P3DIR.x
P3SEL.x
LCDS24
I: 0, O: 1
0
0
UCB0SIMO/UCB0SDA (see Notes 2 and 3)
x
1
0
S26
x
x
1
P3.x (I/O)
I: 0, O: 1
0
0
UCB0SOMI/UCB0SCL (see Notes 2 and 3)
x
1
0
S27
x
x
1
NOTES: 1. x: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
75
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P3 pin schematic: P3.4 to P3.7, input/output with Schmitt trigger
LCDS28
Pad Logic
Segment Sy
P3DIR.x
0
Direction
0: Input
1: Output
1
P3OUT.x
0
Module X Out
1
P3.4/S28
P3.5/S29
P3.6/S30
P3.7/S31
Bus
Keeper
EN
P3SEL.x
P3IN.x
Port P3 (P3.4 to P3.7) pin functions
PIN NAME (P3.X)
(P3 X)
X
P3.4/S28
/
4
P3.5/S29
/
5
CONTROL BITS / SIGNALS
FUNCTION
P3.x (I/O)
S28
P3.x (I/O)
S29
P3.6/S30
/
6
P3.x (I/O)
S30
P3.7/S31
/
7
P3.x (I/O)
S31
NOTES: 1. x: Don’t care.
76
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
P3DIR.x
P3SEL.x
LCDS28
I: 0, O: 1
0
0
x
x
1
I: 0, O: 1
0
0
x
x
1
I: 0, O: 1
0
0
x
x
1
I: 0, O: 1
0
0
x
x
1
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
LCDS4/8
Pad Logic
Segment Sy
P4DIR.x
0
Direction
0: Input
1: Output
1
P4OUT.x
0
0/1
1
P4.0/S11
P4.1/S10
P4.2/S9
P4.3/S8
P4.4/S7
P4.5/S6
P4.6/S5
P4.7/S4
Bus
Keeper
EN
P4SEL.x
P4IN.x
Port P4 (P4.0 and P4.7) pin functions
PIN NAME (P4.X)
(P4 X)
P4.0/S11
/
X
0
CONTROL BITS / SIGNALS
FUNCTION
P4.x (I/O)
S11
P4.1/S10
/
1
P4.2/S9
/
2
P4.x (I/O)
S10
P4.x (I/O)
S9
P4.3/S8
/
3
P4.x (I/O)
S8
P4.4/S7
/
4
P4.5/S6
/
5
P4.6/S5
/
6
P4.x (I/O)
S7
P4.x (I/O)
S6
P4.x (I/O)
S5
P4.7/S4
/
7
P4.x (I/O)
S4
P4DIR.x
P4SEL.x
LCDS4/8
I: 0, O: 1
0
0 (LCDS8)
x
x
1 (LCDS8)
I: 0, O: 1
0
0 (LCDS8)
x
x
1 (LCDS8)
I: 0, O: 1
0
0 (LCDS8)
x
x
1 (LCDS8)
I: 0, O: 1
0
0 (LCDS8)
x
x
1 (LCDS8)
I: 0, O: 1
0
0 (LCDS4)
x
x
1 (LCDS4)
I: 0, O: 1
0
0 (LCDS4)
x
x
1 (LCDS4)
I: 0, O: 1
0
0 (LCDS4)
x
x
1 (LCDS4)
I: 0, O: 1
0
0 (LCDS4)
x
x
1 (LCDS4)
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
77
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P5 pin schematic: P5.0 and P5.1, input/output with Schmitt trigger
LCDS20
Pad Logic
Segment Sy
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
0
0/1
1
P5.0/S20
P5.1/S21
Bus
Keeper
EN
P5SEL.x
P5IN.x
Port P5 (P5.0 and P5.1) pin functions
PIN NAME (P5.X)
(P5 X)
P5.0/S20
/
X
0
CONTROL BITS / SIGNALS
FUNCTION
P5.x (I/O)
S20
P5.1/S21
/
1
P5.x (I/O)
S21
NOTES: 1. x: Don’t care.
78
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
P5DIR.x
P5SEL.x
LCDS20
I: 0, O: 1
0
0
x
x
1
I: 0, O: 1
0
0
x
x
1
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P5 pin schematic: P5.2 to P5.7, input/output with Schmitt trigger
Pad Logic
LCD Signal
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
0
0/1
1
Bus
Keeper
EN
P5SEL.x
P5IN.x
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R23
P5.6/LCDREF/R13
P5.7/R03
Port P5 (P5.2 to P5.7) pin functions
PIN NAME (P5.X)
(P5 X)
P5.2/COM1
/
X
2
FUNCTION
P5.x (I/O)
COM1
P5.3/COM2
/
3
P5.4/COM3
/
4
P5.x (I/O)
COM2
P5.x (I/O)
COM3
P5.5/R23
/
5
P5.x (I/O)
R23
P5.6/LCDREF/R13
/
/
6
P5.7/R03
/
7
P5.x (I/O)
R13 or LCDREF
P5.x (I/O)
R03
CONTROL BITS / SIGNALS
P5DIR.x
P5SEL.x
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
79
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.0 and P6.3, input/output with Schmitt trigger
INCH=y
Pad Logic
Ay+
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
0
Module X OUT
1
P6.0/A0+/OA0O
P6.3/A1+/OA1O
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.0 and P6.3) pin functions
PIN NAME (P6.X)
(P6 X)
P6.0/A0+/OA0O
/
/
P6.3/A1+/OA1O
/
/
X
0
3
FUNCTION
P6DIR.x
P6SEL.x
I: 0, O: 1
0
A0+
x
1
OA0O
x
1
P6.x (I/O)
P6.x (I/O)
I: 0, O: 1
0
A1+
x
1
OA1O
x
1
NOTES: 1. x: Don’t care.
80
CONTROL BITS / SIGNALS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.1 and P6.4, input/output with Schmitt trigger
Pad Logic
Ay-
INCH=y
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
0
0/1
1
P6.1/A0-/OA0FB
P6.4/A1-/OA1FB
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.1 and P6.4) pin functions
PIN NAME (P6.X)
(P6 X)
P6.1/A0--/OA0FB
/
/
P6.4/A1--/OA1FB
/
/
X
1
4
FUNCTION
P6.x (I/O)
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
I: 0, O: 1
0
A0--
x
1
OA0FB
x
1
P6.x (I/O)
I: 0, O: 1
0
A1--
x
1
OA1FB
x
1
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
81
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.2, P6.5 and P6.6, input/output with Schmitt trigger
P6DIR.x
0
Direction
0: Input
1: Output
1
P6OUT.x
0
0/1
1
Pad Logic
P6.2/OA0I1 (SW0A)
P6.5/OA0I2 (SW0B)
P6.6/OA1I1 (SW1A)
Bus
Keeper
EN
P6SEL.x
P6IN.x
OAx
Port P6 (P6.2, P6.5 and P6.6) pin functions
PIN NAME (P6.X)
(P6 X)
X
P6.2/OA0I1
/
2
P6.5/OA0I2
/
5
FUNCTION
P6.x (I/O)
OA0I1
P6.x (I/O)
OA0I2
P6.6/OA1I1
/
6
P6.x (I/O)
OA1I1
NOTES: 1. x: Don’t care.
82
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P6DIR.x
P6SEL.x
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
I: 0, O: 1
0
x
1
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Port P6 pin schematic: P6.7, input/output with Schmitt trigger
VLDx = 1111
To SVS Mux
P6DIR.7
0
1
P6OUT.7
0
Module X OUT
1
Pad Logic
Direction
0: Input
1: Output
P6.7/OA1I2/SVSIN
(SW1B)
Bus
Keeper
EN
P6SEL.7
P6IN.7
OAx
Port P6 (P6.7) pin functions
PIN NAME (P6.X)
(P6 X)
X
P6.7/OA1I2/SVSIN
/
/
7
CONTROL BITS / SIGNALS
FUNCTION
P6.x (I/O)
P6DIR.x
P6SEL.x
VLDx
x
I: 0, O: 1
0
OA1I2
x
1
x
SVSIN
x
1
1111
NOTES: 1. x: Don’t care.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
83
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
Segment pin schematic: Sx, dedicated Segment Pins
LCDS12/16/20/24
Pad Logic
Segment Sx
Sx
Sx pin functions
PIN NAME
X
CONTROL BITS /
SIGNALS
FUNCTION
LCDSy
Sx
12
Sx
13
Sx
14
Sx
15
Sx
16
Sx
17
Sx
18
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCDS12)
3-state
0 (LCDS12)
Sx
1 (LCD16)
3-state
0 (LCD16)
Sx
1 (LCD16)
3-state
0 (LCD16)
Sx
1 (LCD16)
3-state
Sx
19
Sx
22
Sx
23
Sx
24
Sx
25
0 (LCD16)
Sx
1 (LCDS16)
3-state
0 (LCDS16)
Sx
1 (LCDS20)
3-state
0 (LCDS20)
Sx
1 (LCDS20)
3-state
0 (LCDS20)
Sx
1 (LCDS24)
3-state
0 (LCDS24)
Sx
1 (LCDS24)
3-state
0 (LCDS24)
Segment pin schematic: COM0, dedicated COM0 pin
Pad Logic
COM0
COM0
Sx pin functions
PIN NAME
COM0
84
X
--
FUNCTION
COM0
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
and
DVCC
Emulation
Module
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
JTAG fuse check mode
For details on the JTAG fuse check mode, see the MSP430 Memory Programming User’s Guide (SLAU265)
chapter ”Fuse Check and Reset of the JTAG State Machine (TAP Controller)”.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
85
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
Data Sheet Revision History
LITERATURE
NUMBER
SLAS580
SLAS580A
SLAS580B
SLAS580C
SLAS580D
86
SUMMARY
Product Preview release
Changes throughout to update Product Preview
Production Data release
In recommended operating conditions table, changed maximum LFXT1 crystal frequency, f(LFXT1), with XT1 selected
from 8 MHz to 6 MHz (page 24)
Changed limits on td(SVSon) parameter (page 32)
Corrected measurement pin name for “Duty cycle, LF mode” parameter (page 37)
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430A138IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG479
MSP430FG477IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG477
MSP430FG477IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG477
MSP430FG477IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG477
MSP430FG478IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG478
MSP430FG478IZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG478
MSP430FG478IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG478
MSP430FG479IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG479
MSP430FG479IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG479
MSP430FG479IZQW
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG479
MSP430FG479IZQWR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430FG479
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FG477IZQWR
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG478IZQWR
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG479IZQWR
BGA MI
CROSTA
R JUNI
OR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FG477IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG478IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
MSP430FG479IZQWR
BGA MICROSTAR
JUNIOR
ZQW
113
2500
336.6
336.6
28.6
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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• DALLAS, TEXAS 75265
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