Mitsubishi M5M4V4S40CTP-15 4m (2-bank x 131072-word x 16-bit) synchronous dram Datasheet

MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
DESCRIPTION
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 83MHz / 67MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by BA(Bank Address)
- /CAS latency- 1/2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Sequential and interleave burst (programmable)
- Byte control by DQMU and DQML
- Random column access
- Auto precharge / All bank precharge controlled by A8
- Auto and self refresh
- 1024 refresh cycles /16.4ms
CLK
- LVTTL Interface
CKE
- 400-mil, 50-pin Thin Small Outline Package
/CS
(TSOP II) with 0.8mm lead pitch
/RAS
Max.
Frequency
CLK Access
Time
M5M4V4S40CTP-12
83MHz
8ns
M5M4V4S40CTP-15
67MHz
9ns
Vdd
DQ0
DQ1
VssQ
DQ2
DQ3
VddQ
DQ4
DQ5
VssQ
DQ6
DQ7
VddQ
DQML
/WE
/CAS
/RAS
/CS
BA
A8
A0
A1
A2
A3
Vdd
/CAS
/WE
DQ0-15
DQMU
DQML
A0-8
BA
Vdd
VddQ
Vss
VssQ
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8
9
10
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13
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15
16
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19
20
21
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23
24
25
400mil 50pin TSOP(II)
The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V4S40CTP achieves very high speed data rates up to
83MHz, and is suitable for main memory or graphic memory
in computer systems.
PIN CONFIGURATION
(TOP VIEW)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
VddQ
DQ11
DQ10
VssQ
DQ9
DQ8
VddQ
NC
DQMU
CLK
CKE
NC
NC
NC
A7
A6
A5
A4
Vss
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Upper Output Disable/ Write Mask
: Lower Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
1
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BLOCK DIAGRAM
DQ0-15
I/O Buffer
Memory Array
Memory Array
Bank #0
Bank #1
Mode
Register
Control Circuitry
Address Buffer
A0-8
BA
Control Signal Buffer
Clock Buffer
CLK
/CS /RAS /CAS /WE
DQML DQMU
CKE
Type Designation Code
These rules are only applied to the Synchronous DRAM family.
M 5M 4 V 4 S 4 0 C TP - 12
Cycle Time (min.) 12: 12ns, 15: 15ns
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2 n 4: x16
Synchronous DRAM
Density 4:4M bits
Interface V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls the internal clock. When CKE is low, the
internal clock for the following cycle is disabled. CKE is also used to select
auto and self refresh. After self-refresh mode is started, CKE acts as an
asynchronous input to maintain and exit the mode.
/CS
Input
Chip Select: When /CS is high, all commands are inhibited.
/RAS, /CAS, /WE
Input
/RAS, /CAS, and /WE are used to define basic commands.
A0-8
Input
A0-8 specify the Row and Column addresses within the selected bank.
The Row Address is set by A0-8 and the Column Address is set by A0-7.
A8 is also used to indicate the precharge option. When A8 is high during
read or write command, an auto precharge is performed. When A8 is
high during a precharge command, both banks are precharged.
BA
Input
Bank Address: BA is not simply A9. BA specifies the bank to which a
command is applied. BA must be set during the ACT, PRE, READ,
and WRITE commands.
DQ0-15
Input / Output
Data In and data out are referenced to the rising edge of CLK.
Input
Lower Din(0-7) Mask; Lower Dout(0-7) Disable; When DQML is high
during burst write Din(0-7) for the current cycle is masked. When DQML
is high during burst read Dout(0-7) is disabled two cycles later.
DQMU
Input
Upper Din(8-15) Mask; Upper Dout(8-15) Disable; When DQMU is high
during burst write Din(8-15) for the current cycle is masked. When DQMU
is high during burst read Dout(8-15) is disabled two cycles later.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
Power Supply for the output buffers only.
DQML
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V4S40CTP has the following basic functions, bank (row) activate, burst read/write, bank
(row) precharge, and auto/self refresh. Each command is defined by the control signals (/RAS, /CAS and
/WE) at the rising edge of CLK. The inputs /CS ,CKE and A8 are used for chip select, refresh options, and
precharge options, respectively.
Please see the command truth table for detailed definitions.
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A8
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
The ACT command activates a row in an idle bank. The bank address, BA, is used to select which of
the two banks will be activated.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
The READ command starts burst read from the active bank indicated by BA. The first output data
appears after /CAS latency. If A8 =H when READ is issued the bank is automatically precharged after
the last burst read (READA). Note: READA is not valid for FP burst operations.
Write (WRITE) [/RAS =H, /CAS =/WE =L]
The WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. If A8 =H when WRITE is issued the bank is automatically precharged
after the last burst write (WRITEA). Note: WRITEA is not valid for FP burst operations.
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
The PRE command deactivates the active bank indicated by BA. This command also terminates burst
read and write operations. If A8 =H when PRE is issued both banks are automatically precharged (PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
The REFA command starts an auto-refresh cycle. The refresh address, including the bank address, is
generated internally. After this command, the banks are precharged automatically.
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
/WE
BA
A8
A0-7
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with AutoPrecharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
V
L
V*1
H=High Level, L=Low Level, V=Valid, X=Don’t Care, n=CLK cycle number
NOTE:
1. A7 =0, A0-A6 =Mode Address
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE
Current State
/CS
/RAS
/CAS
/WE
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A8
L
H
L
L
BA, CA, A8
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A8
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A8
L
H
L
L
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW ACTIVE
READ
Address
Command
Action
READ / WRITE ILLEGAL*2
Bank Active, Latch RA
NOP*4
Begin Read, Latch CA,
READ / READA Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge*3
WRITE /
WRITEA
MITSUBISHI ELECTRIC
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
6
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
(continued)
FUNCTION TRUTH TABLE
Current State
/CS
/RAS
/CAS
/WE
WRITE
H
X
X
X
L
H
H
L
H
H
L
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
H
L
Command
Action
X
DESEL
NOP (Continue Burst to END)
H
X
NOP
NOP (Continue Burst to END)
L
X
TBST
Terminate Burst
H
Address
BA, CA, A8
Terminate Burst, Latch CA,
READ / READA Begin Read, Determine AutoPrecharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
L
H
L
L
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A8
L
H
L
L
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A8
L
H
L
L
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
READ / READA ILLEGAL
WRITE /
WRITEA
MITSUBISHI ELECTRIC
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
7
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
PRE CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A8
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A8
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A8
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
WRITE RECOVERING
Address
Command
Action
READ / WRITE ILLEGAL*2
ILLEGAL*2
NOP*4 (Idle after tRP)
READ / WRITE ILLEGAL*2
READ / WRITE ILLEGAL*2
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
REFRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A8
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A8
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A8
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
Address
Command
Action
READ / WRITE ILLEGAL
READ / WRITE ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don’t Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
ANY STATE
other than
listed above
CKE
n-1
CKE
n
/CS
H
X
X
X
L
H
H
L
H
L
/RAS /CAS
/WE
Add
Action
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don’t Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be
satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
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SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
TBST(for Full Page)
TBST(for Full Page)
ROW
ACTIVE
WRITE
READ
WRITEA
READA
CKEL
WRITE
SUSPEND
CKEL
READ
WRITE
READ
WRITE
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
SUSPEND
POWER
APPLIED
READ
SUSPEND
CKEL
PRE
WRITEA
CKEH
POWER
ON
PRE
PRE
READA
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operations, the following power on sequence is necessary to prevent the SDRAM
from damage and malfunctions.
1. Apply power and start the clock, CLK. Attempt to maintain CKE high, DQMU/DQML high and NOP
conditions on the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks (PRE or PREA).
4. After all banks reach an idle state and after the row the precharge time (tRP) issue 8 or more auto-refresh
commands.
5. Finally, issue a mode register set (MRS) command to initialize the mode register.
After tRSC from the MRS command, the SDRAM will be in an idle state and ready for normal operations.
MODE REGISTER
Burst Length, Burst Type, and /CAS Latency can be programmed by setting the mode register (MRS). The
mode register stores this data until the next MRS command. An MRS command can only be issued when
both banks are idle. After tRSC from an MRS operation, the SDRAM is ready for new commands.
CLK
/CS
/RAS
BA
A8 A7
OPCODE
0
A6
A5 A4
LTMODE
A3
A2 A1
BT
BL
A0
/CAS
/WE
V
BA, A8 -A0
LATENCY
MODE
OPCODE
OP
00
01
10
11
CL
/CAS LATENCY
BL
000
001
010
011
1XX
R
1
2
3
R
000
001
010
011
100
101
110
111
Burst read / Burst write
R
Burst read / Single write
R
BURST
LENGTH
BURST
TYPE
0
1
BT= 0 BT= 1
1
2
4
8
R
R
R
F.P.
1
2
4
8
R
R
R
R
SEQUENTIAL
INTERLEAVED
R is Reserved for Future Use
F.P. = Full Page (256)
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of
CLK determines which CL should be used. The DRAM column access, tCAC, determines the CL timing
requirements.
/CAS Latency Timing (BL=4)
CLK
Command
ACT
READ
tRCD
Address
X
Y
DQ
Q0
DQ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
DQ
CL=1
CL=2
Q3
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be automatically
performed after the initial write or read command. For BL=1,2,4,8 the output data is tristated (Hi-Z) after
the last read. For BL=FP (Full Page) the TBST (Burst Terminate) command must be used to stop the output
of data.
tRCD
Burst Length Timing (CL=2)
CLK
Command
Address
ACT
READ
X
Y
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1
Q2
Q3
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
BL=1
BL=2
BL=4
BL=8
Q8
Q255
Q0
Q1
BL=FP
Full Page counter rolls over and continues to count.
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ BURST ADDRESS SEQUENCE ]
CLK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
Q1
/CAS Latency
Q2
D0
Q3
D1
Burst Length
D2
D3
Burst Length
Internal addresses are determined by Burst Type.
Initial Address BL
A2
Column Addressing / Burst Type
A1 A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
Note: For FP Burst the Burst Type must be set to sequential.
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank
address (BA). A row inside the bank is selected by the row address A8-0. The minimum activation interval
between one bank and the opposite bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all
command (PREA, PRE + A8=H) can be used to deactivate them at the same time. After tRP from the
precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
ACT
A0-7
Xa
A8
BA
ACT READ
tRRD
PRE
ACT
tRAS
Xb
Y
Xa
Xb
0
0
1
0
tRP
Xb
tRCD
DQ
Xb
1
1
Qa0
Qa1
Qa2
Qa3
Precharge all
READ
A READ command can be issued after tRCD from bank activation (ACT). Output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive output data (Burst Length = BL). The
start address is specified by A7-0, and the address sequence of the burst data is defined by the Burst Type. A
READ command may be applied to any active bank. This allows the row precharge time (tRP) to be hidden
behind continuous output data (in case of BL=4) by interleaving the dual banks. When A8 is high at a READ
command, the auto-precharge (READA) is performed. During READA the READ, WRITE, PRE, and ACT
commands to the same bank are inhibited until the internal precharge is complete. Internal precharge start
timing depends on /CAS Latency. The next ACT command can be issued after tRP from the precharge (PRE).
Note: READA is not allowed for FP burst length operations. The SDRAM must be manually precharged.
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CLK
Command
ACT
A0-7
Xa
Y
Xb
Y
A8
Xa
0
Xb
0
0
BA
0
0
1
1
0
Qa1
Qa2
READ ACT
READ PRE
tRCD
DQ
Qa0
/CAS latency
Qa3
Qb0
Qb1
Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
ACT
READ
ACT
tRCD
tRP
A0-7
Xa
Y
Xa
A8
Xa
1
Xa
BA
0
0
0
DQ
Qa0
Qa1
Qa2
Qa3
Internal Precharge Begins
READ Auto-Precharge Timing (BL=4)
CLK
Command
CL=3
DQ
CL=2
DQ
CL=1
DQ
ACT
READ
Qa0
Qa0
Qa1
Qa2
Qa0
Qa1
Qa2
Qa3
Qa1
Qa2
Qa3
Qa3
Internal Precharge Begins
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE
A WRITE command can be issued after tRCD from the bank activation (ACT). Input data is written to the
SDRAM beginning on the rising edge of CLK in the same cycle that the WRITE command is applied.
The remaining input data will be clocked in on the subsequent CLK cycles. The number of writes depends
on the BL set in the mode register. The start address is specified by A7-0 and the address sequence is
defined by the Burst Type. A WRITE command may be applied to any active bank. This allows the row
precharge time (tRP) to be hidden behind continuous input data. Write recovery time (tWR) is required
between the last write and subsequent precharge (PRE) inside of a bank.
When A8 is high during a WRITE command (WRITEA) , an auto precharge is performed after the last data
is input. All commands (READ, WRITE, PRE, ACT) to the same bank are inhibited until the internal
precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT
command can be issued after tRP. WRITEA cannot be used for FP burst length operations.
The Mode Register can be programmed for burst read and single write. In this mode the write data is only
clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data
burst length is unaffected while in this mode.
Dual Bank Interleaving WRITE (BL=4)
CLK
Command
ACT
A0-7
Xa
Write
ACT
tRCD
Write
PRE
tRCD
Y
Xb
Y
tWR
A8
Xa
0
Xb
0
0
BA
0
0
1
1
0
Da0
Da1
Db0
Db1
DQ
Da2
Da3
Db2
Db3
Burst Length
WRITE with Auto-Precharge (BL=4)
CLK
Command
ACT
Write
ACT
tRCD
tRP
A0-7
Xa
Y
Xa
A8
Xa
1
Xa
BA
0
0
0
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge begins
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SDRAM (Rev. 0.3)
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
A burst read operation can be interrupted by a new read of the same or opposite bank. M5M4V4S40CTP
allows random column accesses. READ to READ interval is a minimum of one CLK.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
READ READ
READ
READ
A0-7
Yi
Yj
Yk
Yl
A8
0
0
0
0
BA
0
0
1
0
DQ
Qai0
Qaj0
Qaj1 Qbk0 Qbk1 Qbk2
Qal0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
A burst read operation can be interrupted by a write to the same or opposite bank. For this operation,
the DQ’s should be controlled by using DQMU and DQML to prevent bus contention. The output is
disabled two cycles automatically after WRITE assertion. Random column access is allowed.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
Read
Write
A0-7
Yi
Yj
A8
0
0
BA
0
0
DQMU
DQML
Q
D
Qai0
Daj0
Daj1
Daj2
DQMU/DQML control
MITSUBISHI ELECTRIC
Daj3
Write control
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M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank. The READ to PRE interval is
a minimum of one CLK. A PRE command disables the data output, depending on the /CAS latency. The
figures below show examples of how the output data is terminated with a PRE command.
Read Interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
Q0
DQ
Command
READ
Q1
Q2
Q1
Q2
Q3
PRE
CL=3
Q0
DQ
Command
READ
PRE
DQ
Command
Q0
READ
PRE
DQ
Command
Q0
READ
Q1
Q2
Q3
PRE
CL=2
Q0
DQ
Command
READ
Q2
PRE
DQ
Command
Q1
Q0
READ
DQ
PRE
Q0
Q1
Q2
Q3
CL=1
Command
DQ
READ
PRE
Q0
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation and
disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly used to
interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CLK
Command
READ
TBST
Q0
DQ
Command
READ
Q1
Q2
Q1
Q2
Q3
TBST
CL=3
DQ
Command
Q0
READ
TBST
Q0
DQ
Command
READ
TBST
DQ
Command
Q0
READ
Q1
Q2
Q3
TBST
CL=2
Q0
DQ
Command
READ
Q0
READ
DQ
CL=1
Command
DQ
Q2
TBST
DQ
Command
Q1
TBST
Q0
READ
Q1
Q2
Q3
TBST
Q0
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Write ]
A burst write operation can be interrupted by a new write to the same or opposite bank. Random column
access is allowed. WRITE to WRITE interval is a minimum of one CLK.
Write Interrupted by Write (BL=4)
CLK
Command
Write Write
Write
Write
A0-7
Yi
Yj
Yk
Yl
A8
0
0
0
0
BA
0
0
1
0
DQ
Dai0
Daj0
Daj1
Dbk0 Dbk1 Dbk2 Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
A burst write operation can be interrupted by a read of the same or opposite bank. Random column access
is allowed. WRITE to READ interval is a minimum of one CLK. The input data on DQ at the interrupting
READ cycle is "don’t care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
Write READ
Write
READ
A0-7
Yi
Yj
Yk
Yl
A8
0
0
0
0
BA
0
0
0
1
DQMU
DQML
DQ
Dai0
Qaj0
Qaj1
Dak0 Dak1
MITSUBISHI ELECTRIC
Qbl0
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SDRAM (Rev. 0.3)
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Precharge ]
A burst write operation can be interrupted by precharging (PRE) the same bank. Write recovery time
(tWR) is required between the last input data and the next PRE. This may require DQMU/DQML control
depending on the CLK frequency and tWR timing. See the example below.
Write Interrupted by Precharge (BL=4)
CLK
Command
Write
PRE
tWR
ACT
tRP
A0-7
Yi
A8
0
0
Xb
BA
0
0
0
Xb
DQMU
DQML
DQ
Dai0
Dai1
This data should be masked to satisfy tWR requirement.
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case, the
write recovery time is not required and the bank remains active (Please see the waveforms below). The
WRITE to TERM minimum interval is one CLK.
Write Interrupted by Burst Terminate (BL=4)
CLK
Command
A0-7
Write
TERM
Yi
A8
0
BA
0
DQMU
DQML
DQ
Dai0
Dai1
Dai2
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AUTO REFRESH
Auto-refresh is initiated with a REFA command (/CS= /RAS= /CAS= L, /WE= /CKE= H). The refresh
address is generated internally. 1024 REFA cycles issued within 16.4ms will refresh the entire 4Mbit
memory array. The auto-refresh is alternately performed on each bank (ping-pong). Before performing an
auto-refresh, both banks must be in the idle state. Subsequent commands (except NOP or DESELECT)
must not be asserted before tRC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-8
BA
Auto Refresh on Bank 0
Auto Refresh on Bank 1
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SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once initiated, the self-refresh is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and all other inputs including CLK are disabled and ignored. Disabling all inputs
except CKE during self-refresh reduces power consumption. To exit the self-refresh, supply a stable CLK
input, issue a DESEL or NOP command, and set CKE=H (REFSX). After tRC from REFSX both banks
will be in the idle state new commands can be issued. Until the tRC time has expired, only DESELor NOP
commands may be asserted after an REFSX command.
Self-Refresh
CLK
Stable CLK
/CS
NOP
/RAS
/CAS
/WE
CKE
new command
A0-8
X
BA
0
Self Refresh Entry
Self Refresh Exit
MITSUBISHI ELECTRIC
minimum tRC
for recovery
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SDRAM (Rev. 0.3)
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
CLK SUSPEND
CKE controls the internal CLK in the following cycle. The figure below shows how CKE works. When
CKE=L the next internal CLK is suspended. CLK suspend is used to power down, suspend the outputs, and
to suspend the inputs. Except during the self-refresh mode, CKE is a synchronous input. CLK suspend can
be performed either when the banks are active or idle; however, all commands issued in the following cycle
are ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP NOP
NOP NOP
Active Power Down
CKE
Command
NOP NOP NOP
ACT
NOP NOP
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
DQ
Write
D0
READ
D1
D2
D3
MITSUBISHI ELECTRIC
Q0
Q1
Q2
Q3
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SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
DQMU / DQML CONTROL
DQMU and DQML are used to mask write data and disable read data. During write operations, DQMU
and DQML mask the upper and lower bytes of input, respectively. The DQMU and DQML write mask is
applied in the same clock cycle. During read operations, DQMU and DQML are used to “Hi-Z” the upper
and lower bytes of output data, respectively. The DQMU and DQML to output “Hi-Z” latency is two, i.e.,
the output will be “Hi-Z” at the rising edge of second clock after DQM is applied.
DQMU/DQML Function
CLK
Command
Write
READ
DQML
DQ(0-7)
D0
D2
D3
Q0
masked by DQML=High
Q1
Q3
disabled by DQML=High
DQMU
DQ(8-15)
D0
D1
D3
masked by DQMU=High
Q0
Q2
Q3
disabled by DQMU=High
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SDRAM (Rev. 0.3)
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Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ 5.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
1000
mW
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-65 ~ 150
°C
Ta = 25 °C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH*1
High-Level Input Voltage all inputs
2.0
5.5
V
VIL*2
Low-Level Input Voltage all inputs
-0.3
0.8
V
NOTES:
1. VIH (max) = 5.75V for pulse width less than 5ns.
2. VIL (min) = -1.0V for pulse width less than 5ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
CI(K)
Input Capacitance, CLK pin
CI/O
Input Capacitance, I/O pin
Test Condition
VI=Vss
f=1MHz
Vi=25mVrms
MITSUBISHI ELECTRIC
Limits (max.)
Unit
5
pF
5
pF
5
pF
7
pF
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SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits(max)
Symbol
Parameter
Test Conditions
Unit
-12
-15
Icc1s*1 operating current, single bank tRC=min, tCLK=min, BL=1, CL=3
90
75
mA
Icc1d*1
operating current, dual bank
tRC=min, tCLK=min, BL=1, CL=3
130
110
mA
Icc2h
standby current, CKE=H
both banks idle, tCLK=min, CKE=H
18
16
mA
Icc2l
standby current, CKE=L
both banks idle, tCLK=min, CKE=L
2
2
mA
Icc3
active standby current
both banks active, tCLK=min, CKE=H
35
30
mA
burst current
tCLK=min, BL=4, CL=3, 1 bank idle
120
100
mA
Icc5
auto-refresh current
tRC=min, tCLK=min
60
50
mA
Icc6
self-refresh current
CKE <0.2v
1
1
mA
Icc4*1
NOTES:
1. Icc (max) is specified at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
Min.
VOH (DC) High-Level Output Voltage (DC)
IOH=-2mA
VOL (DC)
Low-Level Output Voltage (DC)
IOL= 2mA
IOZ
Off-state Output Current
Q floating VO=0 ~ VddQ
II
Input Current
VIH = 0 ~ VddQ+0.3V
MITSUBISHI ELECTRIC
Max.
2.4
V
0.4
V
-10
10
µA
-10
10
µA
28
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels :
0.8V to 2.0V
Input Timing Measurement Level : 1.4V
Limits
Symbol Parameter
-12
Min.
tCLK
CLK cycle time
-15
Max.
Min.
Unit
Max.
CL=1
30
30
ns
CL=2
15
15
ns
CL=3
12
15
ns
tCH
CLK High pulse width
4
4
ns
tCL
CLK Low pulse width
4
4
ns
tT
Transition time of CLK
1
tIS
Input Setup time (all inputs)
3
3
ns
tIH
Input Hold time (all inputs)
1
1.5
ns
tRC
Row Cycle time
100
120
ns
tRCD
Row to Column Delay
30
30
ns
tRAS
Row Active time
70
tRP
Row Precharge time
30
40
ns
tWR
Write Recovery time
12
15
ns
tRRD
Act to Act Delay time
24
30
ns
tRSC
Mode Register Set
Cycle time
24
30
ns
tPDE
Power Down Exit time
12
15
ns
tREF
Refresh Interval time
10
10000
16.4
CLK
1.4V
Signal
1.4V
MITSUBISHI ELECTRIC
1
10
75
10000
16.4
ns
ns
ms
Any AC timing is
referenced to the input
signal passing through
1.4V.
29
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol Parameter
-12
Min.
tAC
Access time from CLK
-15
Max.
Min.
Unit
Max.
CL=1
27
30
ns
CL=2
9.5
12
ns
CL=3
8
9
ns
tCAC
Column Access Time
24.5
30
ns
tRAC
Row Access Time
54.5
60
ns
tOH
Output Hold time from
CLK
3
3
ns
tOLZ
Delay time, output low
impedance from CLK
0
0
ns
tOHZ
Delay time, output high
impedance from CLK
3
8
3
10
ns
Output Load Condition
VTT=1.4V
50 ohm
CLK
1.4V
VREF =1.4V
DQ
1.4V
VOUT
50pF
Output Timing Measurement
Reference Point
CLK
1.4V
DQ
1.4V
tAC
tOH
tOHZ
MITSUBISHI ELECTRIC
30
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE CYCLE (single bank)
BL=4
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
X
A8
X
Y
X
X
BA
tWR
D
DQ
ACT
WRITE
D
D
D
PRE
MITSUBISHI ELECTRIC
ACT
31
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE CYCLE (dual bank)
BL=4
CLK
tRC
/CS
tRAS
tRP
tRRD
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
Xa
A8
Xa
Y
Xb
Y
Xb
BA
tWR
Da
DQ
ACTa
Da
WRITEa ACTb
Da
Da
Db
tWR
Db
Db
WRITEb PREa
MITSUBISHI ELECTRIC
Db
PREb
32
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
READ CYCLE (single bank)
BL=4, CL=3
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
X
A8
X
Y
X
X
BA
DQ
tCAC
Q
Q
Q
Q
tRAC
ACT
READ
PRE
MITSUBISHI ELECTRIC
ACT
33
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
READ CYCLE (dual bank)
BL=4, CL=3
CLK
tRC
/CS
tRAS
tRP
tRRD
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
Xa
A8
Xa
Y
Xb
Y
Xa
Xb
Xa
BA
Qa
DQ
Qa
tCAC
tRAC
ACTa
Qa
Qa
Qb
Qb
Qb
Qb
tCAC
tRAC
READa ACTb
READb PREa
MITSUBISHI ELECTRIC
PREb ACTa
34
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE to READ (single bank)
BL=4, CL=3
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
X
A8
X
Y
Y
BA
D
DQ
D
D
D
Q
Q
Q
Q
tCAC
ACT
WRITE
READ
MITSUBISHI ELECTRIC
PRE
35
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE to READ (dual bank)
BL=4, CL=3
CLK
tRC
/CS
tRAS
tRP
tRRD
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
A8
Xa
Y
Xa
Xb
Y
Xa
Xb
Xa
BA
tWR
Da
DQ
Da
Da
Da
Qb
Qb
Qb
Qb
tCAC
ACTa
WRITEa ACTb
READb PREa
MITSUBISHI ELECTRIC
PREb ACTa
36
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
DQM Byte control for WRITE to READ (single bank)
BL=4,CL=3
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE
DQML
DQMU
A0-7
X
A8
X
Y
Y
BA
DQ
(0-7)
DQ
(8-15)
D
D
D
D
D
Q
Q
D
Q
Q
Q
Q
tCAC
ACT
WRITE
READ
MITSUBISHI ELECTRIC
PRE
37
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
READ to WRITE (single bank)
BL=4, CL=3
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE
for output disable
DQMU
DQML
A0-7
X
A8
X
Y
Y
BA
tWR
Q
DQ
Q
D
D
D
D
tCAC
tRAC
ACT
READ
WRITE
MITSUBISHI ELECTRIC
PRE
38
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
READ to WRITE (dual bank)
BL=4, CL=3
CLK
tRC
/CS
tRAS
tRP
tRRD
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
for output disable
DQMU
DQML
A0-7
Xa
A8
Xa
Y
Xb
Y
Xa
Xb
Xa
BA
tWR
Qa
DQ
ACTa
tCAC
tRAC
READa ACTb
Qa
PREa
MITSUBISHI ELECTRIC
Db
Db
WRITEb
Db
ACTa
Db
PREb
39
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BL=4
WRITE with AUTO-PRECHARGE (WRITEA)
CLK
tRC
/CS
tWR + tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
X
A8
X
Y
X
X
BA
D
DQ
ACT
D
D
D
WRITEA
ACT
internal precharge starts
this timing depends on BL
Note: WRITEA should not be used for Full Page (FP) burst operations.
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
READ with AUTO-PRECHARGE (READA)
BL=4, CL=3
CLK
tRC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMU
DQML
A0-7
A8
X
Y
X
X
X
BA
Q
DQ
Q
Q
Q
tCAC
tRAC
ACT
READA
ACT
internal precharge starts
this timing depends on BL
Note: READA should not be used for Full Page (FP) burst operations.
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AUTO-REFRESH
CLK
tRC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQMU
DQML
A0-7
A8
BA
DQ
PREA
REFA
REFA
if any bank is active, it must be precharged
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SELF-REFRESH ENTRY
CLK
/CS
tRP
/RAS
/CAS
/WE
CKE
DQMU
DQML
A0-7
A8
BA
DQ
PREA
REFS
if any bank is active, it must be precharged
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
Feb ‘97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SELF-REFRESH EXIT
CLK
/CS
NOP or DESEL
/RAS
/CAS
/WE
tRC
CKE
DQMU
DQML
A0-7
X
A8
X
BA
DQ
ACT
internal CLK re-start
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs
SDRAM (Rev. 0.3)
M5M4V4S40CTP-12, -15
Feb ‘97 Preliminary
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MODE REGISTER SET
BL=4, CL=3
CLK
/CS
tRP
tRSC
tRCD
/RAS
/CAS
/WE
CKE
DQMU
DQML
A0-7
A8
mode
X
Y
X
BA
Q
DQ
Q
Q
tCAC
tRAC
if any bank is active, it must be precharged
MITSUBISHI ELECTRIC
45