IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – – – Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40°C to +85°C VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. Drive Features for LVC16373A: – High Output Drivers: ±24mA – Reduced system switching noise The LVC16373A has been designed with a ± 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems Functional Block Diagram 1 OE 1 LE 1D 1 1 2 OE 48 2 LE 47 D C Q 2D 1 2 24 25 36 D 13 C Q 1Q 1 2Q 1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS EXTENDED COMMERCIAL TEMPERATURE RANGE MARCH 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4624/1 IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE 1 OE 1 (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION 48 1 LE Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 Unit V VTERM(3) Terminal Voltage with Respect to GND – 0.5 to +6.5 V TSTG Storage Temperature – 65 to +150 °C IOUT DC Output Current – 50 to +50 mA Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through – 50 mA ±100 mA each VCC or GND 1Q 1 2 47 1D 1 1Q 2 3 46 1D 2 GND 4 45 GND IIK IOK ICC 1Q 3 5 44 1D 3 ISS 1Q 4 6 V CC 7 42 V CC 1Q 5 8 41 1D 5 1Q 6 9 40 1D 6 GND 10 39 GND 1Q 7 11 38 1D 7 37 1D 8 2Q 1 SO48-1 12 SO48-2 13 SO48-3 36 2D 1 Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF 2Q 2 14 35 2D 2 COUT VOUT = 0V 6.5 8 pF GND 15 34 GND VIN = 0V 6.5 8 pF 16 33 2D 3 Output Capacitance I/O Port Capacitance 1Q 8 2Q 3 43 17 32 2D 4 18 31 V CC 2Q 5 19 30 2D 5 2Q 6 20 29 2D 6 GND 21 28 GND 2Q 7 22 27 2D 7 23 26 2D 8 24 25 2 LE 2Q 4 V CC 2Q 8 2 OE LVC Link 1D 4 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25OC, f = 1.0MHz) CI/O LVC Link NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names xDx Description Data Inputs xLE Latch Enable Input (Active HIGH) xOE Output Enable Inputs (Active LOW) xQx 3-State Outputs FUNCTION TABLE(1) Inputs xLE xOE Outputs xQx H H L H L H L L X L L Q0 X X H Z xDx SSOP/ TSSOP/ TVSOP TOP VIEW NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance Q0 = Output level of Q before the indicated steady-state input conditions were established. c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Test Conditions VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 ∆ICC Quiescent Power Supply Current Variation — — 500 VCC = 0V, VIN or VO ≤ 5.5V One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3.0V Output LOW Voltage Max. — VCC = 2.3V VCC = 2.7V VOL Min. VCC – 0.2 2.4 — VCC = 3.0V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3.0V IOL = 24mA — 0.55 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. 3 IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per latch Outputs enabled CPD Power Dissipation Capacitance per latch Outputs disabled SWITCHING CHARACTERISTICS Test Conditions CL = 0pF, f = 10Mhz Typical 39 Unit pF 6 pF (1) VCC = 2.7V VCC = 3.3V±0.3V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Parameter Propagation Delay xDx to xQx Propagation Delay xLE to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Set-up Time Data before LE↓ HIGH or LOW Min. — Max. 4.9 Min. 1.6 Max. 4.2 Unit ns — 5.3 2.1 4.6 ns — 5.7 1.3 4.7 ns — 6.3 2.5 5.9 ns 1.7 — 1.7 — ns tH Hold Time Data after LE↓ HIGH or LOW 1.2 — 1.2 — ns tW Pulse Width LE HIGH 3.3 — 3.3 — ns Output Skew (2) — — — 500 ps tSK(o) NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 V IH VT 0V SAME PHASE INPUT TRANSITION tPLH tPHL tPLH tPHL V OH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF LVC Link LVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 Ω Pulse Generator (1, 2) V IN GND tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. V LOAD/2 V OL+ V LZ V OL tPHZ V OH V OH-V HZ VT 0V 0V SET-UP, HOLD, AND RELEASE TIMES DATA INPUT Switch VLOAD tSU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIMING INPUT tREM ASYNCHRONOUS CONTROL GND Open SYNCHRONOUS CONTROL LVC Link OUTPUT SKEW - tsk (x) V IH tSU tH PULSE WIDTH VT 0V tPHL1 V LOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION tPLH1 0V tPLZ LVC Link NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT CONTROL INPUT V OUT RT INPUT DISABLE ENABLE Open LVC Link V OH OUTPUT 1 tSK (x) VT V OL tSK (x) LOW-HIGH-LOW PULSE V OH tW VT V OL OUTPUT 2 tPLH2 VT HIGH-LOW-HIGH PULSE tPHL2 VT LVC Link tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LVC Temp. Range X XX XXXX XX Bus-Hold Family Device Type Package PV PA PF Shrink Sm all Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Sm all Outline Package (SO48-3) 373A 16-Bit Transparent D-Type Latch with 3-State Outputs 16 Double-Density with Resistors, ±24mA Blank No Bus-hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6