Supertex inc. AT9933 Hysteretic Boost-Buck (Ćuk) LED Driver IC Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► General Description Constant current LED Driver Steps input voltage up or down Low EMI Variable frequency operation Internal 75V linear regulator Input and output current sensing Input current limit Enable & PWM dimming Ambient temperature rating up to 125°C Meets AEC-Q100 requirements The AT9933 is a variable frequency PWM controller IC, designed to control an LED lamp driver using a low-noise boost-buck (Ćuk) topology. The AT9933 uses patent-pending hysteretic current-mode control to regulate both the input and the output currents. This enables superior input surge immunity without the necessity for complex loop compensation. Input current control enables current limiting during startup, input under-voltage and output overload conditions. The AT9933 provides a low-frequency PWM dimming input that can accept an external control signal with a duty cycle of 0 - 100% and a high dimming ratio. Applications The AT9933 based LED driver is ideal for automotive LED lamps. The part is rated for up to 125°C ambient temperatures and is AEC-Q100 compliant. ►► Automotive LED Lighting Reference Documents ►► AEC-Q100 Rev. F, 7/18/2003 ►► SAE J1752-3 Typical Application Circuit C1 D2 (optional) L2 L1 VDC RD - CD D3 D1 Q1 VO + RCS1 RCS2 RS1 C2 VIN GATE RREF1 VDD PWMD CS1 CS2 GND REF AT9933 Doc.# DSFP-AT9933 B061710 RS2 RREF2 C3 Supertex inc. www.supertex.com AT9933 Ordering Information 8-Lead SOIC Device 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch AT9933 AT9933LG-G -G indicates package is RoHS compliant (‘Green’) Pin Configuration Absolute Maximum Ratings Parameter Value VIN to GND -0.5V to +75V CS1, CS2, PWMD, GATE to GND -0.3V to (VDD + 0.3V) VDD(MAX) 8 REF CS1 2 7 CS2 GND 3 6 VDD 12V Continuous Power Dissipation (TA = +25°C) 8-Pin SOIC 700mW Junction temperature +150°C Storage temperature range GATE 4 -65°C to +150°C (top view) Product Marking YWW 9933 Thermal Resistance LLLL Package θja 8-Lead SOIC 128 OC/W 5 PWMD 8-Lead SOIC (LG) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 8-Lead SOIC (LG) Electrical Characteristics (Specifications are at T A Sym VIN 1 Parameter = 25°C. VIN = Open, VDD = 7.5V unless otherwise noted) Min Typ Max Units Conditions Input VINDC Input DC supply voltage range1 * (2) - 75 V DC input voltage IINSD Shut-down mode supply current1 - - 0.5 1.0 mA PWMD connected to GND, VIN = 12V Internally regulated voltage * 7.0 7.5 9.0 V VIN = 8 - 75V, IDD(ext) = 0, 500pF capacitor at GATE, PWMD = GND UVLO VDD undervoltage lockout threshold * 6.35 6.70 7.05 V VDD rising ∆UVLO VDD undervoltage lockout hysteresis - - 500 - mV Internal Regulator VDD --- Notes: 1. Also limited by package power dissipation limit, whichever is lower. 2. Depends on the current drawn by the part - see application section. * Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization. Doc.# DSFP-AT9933 B061710 2 Supertex inc. www.supertex.com AT9933 Electrical Characteristics (cont.)(Specifications are at T A Sym Description = 25°C. VIN = Open, VDD = 7.5V unless otherwise noted) Min Typ Max Units Conditions Reference REF bypassed with a 0.1µF capacitor to GND, IREF = 0, PWMD = 5.0V REF pin voltage 0°C < TA < +85°C - 1.212 1.25 1.288 REF pin voltage -40°C < TA < 125°C - 1.187 1.25 1.312 Line regulation of reference voltage - 0 - 20 mV REF bypassed with a 0.1µF capacitor to GND, IREF = 0, VDD = 7.0 - 9.0V, PWMD = 5.0V Reference output current range - -0.01 - 500 µA REF bypassed with a 0.1µF capacitor to GND, IREF = 0; VDD = 7.0 - 9.0V, PWMD = 5.0V Load regulation of reference voltage - 0 - 10 mV REF bypassed with a 0.1µF capacitor to GND, IREF = 0 - 500µA, PWMD = 5.0V PWM Dimming VPWMD(lo) PWMD input low voltage * - - 0.8 V VDD = 7.0 - 9.0V VPWMD(hi) PWMD input high voltage * 2.0 - - V VDD = 7.0 - 9.0V PWMD pull-down resistance - 50 100 150 kΩ VPWMD = 5.0V GATE short circuit current - 0.165 - - A VGATE = 0V ISINK GATE sinking current - 0.165 - - A VGATE = VDD TRISE GATE output rise time - - 30 50 ns CGATE = 500pF TFALL GATE output fall time - - 30 50 ns CGATE = 500pF VREF VREFLINE IREF VREFLOAD RPWMD GATE ISOURCE V Input Current Sense Comparator VTURNON1 Voltage required to turn GATE on * 85 100 115 mV VTURNOFF1 Voltage required to turn GATE off * -15 0 15 mV TD1,ON Delay to output (turn on) - - 150 250 ns TD1,OFF Delay to output (turn off) - - 150 250 ns CS2 = 200mV; CS1 increasing; GATE goes LOW to HIGH CS2 = 200mV; CS1 decreasing; GATE goes HIGH to LOW CS2 = 200mV; CS1 = 50mV to +200mV step CS2 = 200mV; CS1 = 50mV to -100mV step Output Current Sense Comparator VTURNON2 Voltage required to turn GATE on * 85 100 115 mV VTURNOFF2 Voltage required to turn GATE off * -15 0 15 mV TD2,ON Delay to output (turn on) - - 150 250 ns TD2,OFF Delay to output (turn off) - - 150 250 ns CS1 = 200mV; CS2 increasing; GATE goes LOW to HIGH CS1 = 200mV; CS2 decreasing; GATE goes HIGH to LOW CS1 = 200mV; CS2 = 50mV to +200mV step CS1 = 200mV; CS2 = 50mV to -100mV step Notes: 1. Also limited by package power dissipation limit, whichever is lower. 2. Depends on the current drawn by the part - see application section. * Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization. Doc.# DSFP-AT9933 B061710 3 Supertex inc. www.supertex.com AT9933 Pin Description Pin Number Name Description 1 VIN This pin is the input of a 8.0 - 75V voltage regulator. 2 CS1 7 CS2 These pins are used to sense the input and output currents of the boost-buck converter. They are the non-inverting inputs of the internal comparators. 3 GND Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train. 4 GATE This pin is the output gate driver for an external N-channel power MOSFET. 5 PWMD When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to a voltage greater than 2.0V will enable the gate drive output. 6 VDD This is a power supply pin for all internal circuits. It must be bypassed to GND with a low ESR capacitor greater than 0.1µF. 8 REF This pin provides accurate reference voltage. It must be bypassed with a 0.01 - 0.1µF capacitor to GND. Block Diagram Regulator VIN VDD 7.5V Input Comparator CS1 100mV GATE 0mV CS2 Output Comparator 1.25V PWMD REF GND AT9933 Doc.# DSFP-AT9933 B061710 4 Supertex inc. www.supertex.com AT9933 Functional Description Power Topology voltages at the VIN pin can be determined using the maximum voltage drop across the linear regulator as a function of the current drawn. This data is shown in Fig. 1 for ambient temperatures of 25ºC and 125ºC. The AT9933 is optimized to drive a continuous conduction mode (CCM) boost-buck DC/DC converter topology commonly referred to as “Ćuk converter” (see Circuit Diagram on page 1). This power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (HB LED). These advantages include step-up or step-down voltage conversion ratio and low input and output current ripple. The output load is decoupled from the input voltage with a capacitor making the driver inherently failuresafe for the output load. Voltage Drop (V) The AT9933 offers a simple and effective control technique for use with a boost-buck LED driver. It uses two hysteretic mode controllers – one for the input and one for the output. The outputs of these two hysteretic comparators are ANDED and used to drive the external FET. This control scheme gives accurate current control and constant output current in the presence of input voltage transients without the need for complicated loop design. 2.5 2.0 125OC 1.5 25OC 1.0 0.5 0 1 2 3 4 IIN (mA) 5 6 7 Fig. 1. Maximum Voltage Drop vs. Input Current Assume an ambient temperature of 125°C. Assuming the IC is driving a 15nC gate charge FET at 300kHz, the total input current is estimated to be 5.5mA (using Eqn. 1). At this input current, the maximum voltage drop from Fig. 1 can be approximately estimated to be VDROP = 2.7V. However, before the IC starts switching the current drawn will be 1.0mA. At this current level, the voltage drop is approximately VDROP1 = 0.5V. Thus, the start/stop VIN voltages can be computed to be: VIN-START = UVLOMAX + VDROP1 = 6.95V + 0.5V = 7.45V VIN-STOP = UVLOMAX - ΔUVLO + VDROP = 6.95 - 0.5V + 2.7V = 9.15V The AT9933 can be powered directly from its VIN pin that takes a voltage up to 75V. When a voltage is applied at the VIN pin, the AT9933 seeks to regulate a constant 7.5V (typ) at the VDD pin. The regulator also has a built in under-voltage lockout which shuts off the IC if the voltage at the VDD pin falls below the UVLO threshold. The VDD pin must be bypassed by a low ESR capacitor (≥0.1μF) to provide a low impedance path for the high frequency current of the output gate driver. The input current drawn from the VIN pin is a sum of the 1mA current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switching frequency and the gate charge of the external FET). Note that in this case, since the gate drive draws too much current, VIN-START is less than VIN-STOP. In such cases, the control IC will oscillate between on and off if the input voltage is between the start and stop voltages. In these circumstances, it is recommended that the input voltage be kept higher than VIN-STOP (in this case the IC will operate normally if the input voltage is kept higher than 9.2V). (1) In the above equation, fS is the switching frequency and QG is the gate charge of the external FET (which can be obtained from the datasheet of the FET). In case of input transients that reduce the input voltage below 8.0V (like cold crank condition in an automotive system), the VIN pin of the AT9933 can be connected to the drain of the MOSFET through a switching diode with a small (1.0nF) capacitor between VIN and GND (as long as the drain voltage does not exceed 75V). Since the drain of the FET is at a voltage equal to the sum of the input and output voltages, the IC will still be operational when the input goes below 8V. In these cases, a larger capacitor is needed to the VDD pin to supply power to the IC when the MOSFET is on. Minimum Input Voltage at VIN pin The minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. The internal linear regulator will regulate the voltage at the VDD pin when VIN is between 8.0 and 75V. However, when VIN is less than 8.0V, the converter will still function as long as VDD is greater than the under voltage lockout. Thus, under certain conditions, the converter will be able to start at VIN voltages of less than 8.0V. The start/stop Doc.# DSFP-AT9933 B061710 3.0 0 Input Voltage Regulator IIN = 1.0mA + QG•fS Voltage Drop vs. IIN 3.5 5 Supertex inc. www.supertex.com AT9933 The flying capacitor in the Ćuk converter (C1) is initially charged to the input voltage VDC (through diodes D1 and D2). When the circuit is turned on and reaches steady state, the voltage across C1 will be VDC+VO. In the absence of diode D2, when the circuit is turned off, capacitor C1 will discharge through the LEDs and the input voltage source VDC. Thus, during PWM dimming, if capacitor C1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. By adding diode D2, the voltage across capacitor C1 is held at VDC+VO even when the circuit is turned off enabling the circuit to return quickly to its steady state (and bypassing the start-up stage) upon being enabled. In this case VDD UVLO cannot be relied upon to turn off the IC at low input voltages when input current levels can get too large. The input current limit must then be designed to limit the input current to safe levels during input undervoltage conditions. Reference An internally trimmed voltage reference of 1.25V is provided at the REF pin. The reference can supply a maximum output current of 500μA to drive external resistor dividers. This reference can be used to set the current thresholds of the two comparators as shown in the Typical Application Circuit. Application Information Current Comparators Over-voltage Protection The AT9933 features two identical comparators with a builtin 100mV hysteresis. When the GATE is low, the inverting terminal is connected to 100mV and when the GATE is high, it is connected to GND. One comparator is used for the input current control and the other for the output current control. Over-voltage protection can be added by splitting the output side resistor RS2 into two components and adding a zener diode D3 (see the Design Example Circuit on the following page). When there is an open LED condition, the diode D3 will clamp the output voltage and the zener diode current will be regulated by the sum of RS2A and RCS2. The input side hysteretic controller is in operation during start-up, overload and input undervoltage conditions. This ensures that the input current never exceeds the designed value. During normal operation, the input current will be less than the programmed current and hence, the output of the input side comparator will be HIGH. The output of the AND gate will then be dictated by the output current controller. Damping Circuit The Ćuk converter is inherently unstable when the output current is being controlled. An uncontrolled input current will lead to an un-damped oscillation between L1 and C1 causing excessively high voltages across C1. To prevent these oscillations, a damping circuit consisting of RD and CD is applied across the capacitor C1. This damping circuit will stabilize the circuit and help in the proper operation of the AT9933 based Ćuk converter. The output side hysteretic comparator will be in operation during the steady state operation of the circuit. This comparator turns the MOSFET on and off based on the LED current. Design and Operation of the Boost-Buck Converter PWM Dimming PWM Dimming can be achieved by applying a TTL-compatible square wave signal at the PWM pin. When the PWMD pin is pulled high, the gate driver is enabled and the circuit operates normally. When the PWMD pin is left open or connected to GND, the gate driver is disabled and the external MOSFET turns off. The IC is designed so that the signal at the PWMD pin inhibits the driver only and the IC need not go through the entire start-up cycle each time ensuring a quick response time for the output current. The recommended PWM Dimming frequency range is from 100Hz to a few kilo hertz. Doc.# DSFP-AT9933 B061710 For details on the design for a Boost-Buck converter using the AT9933 and the calculation of the damping components, please refer to Application Note AN-H51 and AN-H58. 6 Supertex inc. www.supertex.com AT9933 Design Example Circuit C1 D2 (optional) L2 L1 RD VDC - CD CO D1 Q1 VO + RCS2 RCS1 RS1 RS2A C2 VDD VIN RS2B PWMD GATE RREF1 D3 CS1 CS2 GND REF RREF2 C3 AT9933 Design Example Current Limits The parameters of the power circuit are: The current sense resistor (RCS1), combined with the other resistors (RS1 & RREF1), determines the input current limits. The choice of the resistor dividers to set the input and output current levels is illustrated by means of the design example given below. The current sense resistor (RCS2), combined with the other resistors (RS2 & RREF2), determines the output current limits. The resistors can be chosen using the following equations: I X RCS = 1.2V X (RS / RREF) - 0.05V (2) VIN MIN = 9.01V VIN MAX = 16V VO = 28V IO = 0.35A fS MIN = 300kHz ΔI X RCS = 0.1V X (RS / RREF) + 0.1V Using these parameters, the values of the power stage inductors and capacitor can be computed as (see Application Note AN-H51 for details): Where I is the current (either IO or IIN) and ΔI is the peak-topeak ripple in the current (either ΔIO or ΔIIN). L1 = 82µH L2 = 150µH C1 = 0.22µF For the input side, the current level used in the equations should be larger than the maximum input current so that it does not interfere with the normal operation of the circuit. The peak input current can be computed as: The input and output currents for this design are: IIN,PK = IIN,MAX + (ΔIIN / 2) IIN MAX = 1.6A ΔIIN = 0.21A IO = 350mA ΔIO = 87.5mA Doc.# DSFP-AT9933 B061710 (3) = 1.706A 7 (4) Supertex inc. www.supertex.com AT9933 Assuming a 30% peak-to-peak ripple when the converter is in input current limit mode, the minimum value of the input current will be: ILIM,MIN = 0.85 • IIN,LIM (5) (6) Choose the following values for the resistors: RCS2 = 1.65Ω, 1/4W, 1% RREF2 = 10kΩ, 1/8W, 1% RS2A = 100Ω, 1/8W, 1% RS2B = 5.23kΩ, 1/8W, 1% Setting ILIM,MIN = 1.05 • IIN,PK The current sense resistor needs to be at least a 1/4W, 1% resistor. The current level to limit the converter can then be computed. Similarly, using IIN = 2.1A and ΔIIN = 0.3xIIN = 0.63 in (1) and (2): IIN,LIM = (1.05 / 0.85) X IIN,PK = 2.1A RS1 / RREF1 = 0.442 RCS1 = 0.228Ω PRCS1 = I2IN,LIM • RCS1 = 1W (7) Using IO = 350mA and ΔIO = 87.5mA in (1) and (2), Choose the following values for the resistors: RCS2 = 1.78Ω RCS1 = parallel combination of three 0.68Ω, 1/2W, 5% resistors RREF1 = 10kΩ, 1/8W, 1% RS1 = 4.42kΩ, 1/8W, 1% RS2 / RREF2 = 0.5625 Before the design of the output side is complete, over voltage protection has to be included in the design. For this application, choose a 33V zener diode. This is the voltage at which the output will clamp in case of an open LED condition. For a 350mW diode, the maximum current rating at 33V works out to about 10mA. Using a 2.5mA current level during open LED conditions, and assuming the same RS2/RREF2 ratio, RCS2 + RS2A = 120Ω Doc.# DSFP-AT9933 B061710 (8) 8 Supertex inc. www.supertex.com AT9933 8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch θ1 D 8 Note 1 (Index Area D/2 x E1/2) E1 E L2 L 1 θ L1 Top View View B Note 1 Gauge Plane Seating Plane View B h A h A A2 Seating Plane A1 e b Side View View A-A A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 1.04 REF L2 0.25 BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-AT9933 B061710 9 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com