MOTOROLA MPC9350 Low voltage pll clock driver Datasheet

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc...
Low Voltage PLL Clock Driver
MPC9350
The MPC9350 is a 2.5V and 3.3V compatible, PLL based clock
generator targeted for high performance clock distribution systems. With
output frequencies of up to 200 MHz and maximum output skews of 150
ps the MPC9350 is ideal for the most demanding clock tree designs. The
device offers 9 low skew clock outputs, each is configurable to support the
clocking needs of the various high-performance microprocessors
including the PowerQuicc II integrated communication microprocessor.
The extended temperature range of the MPC9350 supports
telecommunication and networking requirements. The devices employs a
fully differential PLL design to minimize cycle-to-cycle and long-term jitter.
Features
• 9 outputs LVCMOS PLL clock generator
•
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Order Number: MPC9350/D
Rev 3, 01/2002
LOW VOLTAGE
3.3V AND 2.5V PLL
CLOCK GENERATOR
25 – 200 MHz output frequency range
2.5V and 3.3V compatible
Compatible to various microprocessor such as PowerQuicc II
Supports networking, telecommunications and computer applications
Fully integrated PLL
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
Oscillator or crystal reference inputs
Internal PLL feedback
Output disable
PLL enable/disable
Low skew characteristics: maximum 150 ps output-to-output
32 lead LQFP package
Temperature range –40°C to +85°C
Functional Description
The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference
clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference
clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable
PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects
between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match
the VCO frequency range. With the available feedback output dividers the internal VCO of the MPC9350 is running at either 16x
or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one
eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD
pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal
oscillator inputs or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode
when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to
the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test
mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting
the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is
fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external
components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the
outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated
transmission lines, each of the MPC9350 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The
device is packaged in a 7x7 mm2 32-lead LQFP package.
W
 Motorola, Inc. 2002
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MPC9350
XTAL1
XTAL2
0
0
Ref
TCLK
REF_SEL
(pulldown)
÷2
PLL
0
÷4
1
1
÷8
D
Q
QA
D
Q
QB
1
(pulldown)
FB
÷16
200 - 400 MHz
0
÷32
1
0
FBSEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
QC0
(pulldown)
0
(pullup)
D
(pulldown)
Q
QC1
1
(pulldown)
QD0
(pulldown)
(pulldown)
QD1
0
D
Q
QD2
1
QD3
QD4
OE
(pulldown)
QC0
VCCO
QC1
GND
QD0
VCCO
QD1
GND
Figure 1. MPC9350 Logic Diagram
24
23
22
21
20
19
18
17
GND
25
16
QD2
QB
26
15
VCCO
VCCO
27
14
QD3
QA
28
13
GND
MPC9350
GND
29
12
QD4
TCLK
30
11
VCCO
PLL_EN
31
10
OE
REF_SEL
32
2
3
4
5
6
7
8
FBSEL
FSELA
FSELB
FSELC
FSELD
GND
XTAL1
9
1
VCCA
Freescale Semiconductor, Inc...
1
XTAL2
Figure 2. Pinout: 32–Lead Package Pinout (Top View)
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MPC9350
PIN CONFIGURATION
Freescale Semiconductor, Inc...
Pin
I/O
Type
Function
XTAL1, XTAL2
Input
Analog
Crystal oscillator terminals
TCLK
Input
LVCMOS
Single ended reference clock signal or test clock
FBSEL
Input
LVCMOS
Selects feedback divider ratio
REF_SEL
Input
LVCMOS
Selects input reference source
FSELA
Input
LVCMOS
Output A divider selection
FSELB
Input
LVCMOS
Output B divider selection
FSELC
Input
LVCMOS
Outputs C divider selection
FSELD
Input
LVCMOS
Outputs D divider selection
OE
Input
LVCMOS
Output enable/disable
QA
Output
LVCMOS
Bank A clock output
QB
Output
LVCMOS
Bank B clock output
QC0, QC1
Output
LVCMOS
Bank C clock outputs
QD0 - QD4
Output
LVCMOS
Bank D clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
Positive power supply for the PLL
VCC
Supply
VCC
Positive power supply for I/O and core
FUNCTION TABLE
Control
Default
REF_SEL
0
Selects XTAL
0
Selects TCLK
1
PLL_EN
1
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
FBSEL
0
Selects feedback divider ÷ 32
VCO = 32 * Input reference clock
Selects feedback divider ÷ 16
VCO = 16 * Input reference clock
OE
0
Outputs enabled
Outputs disabled
FSELA
0
QA = VCO ÷ 2
QA = VCO ÷ 4
FSELB
0
QB = VCO ÷ 4
QB = VCO ÷ 8
FSELC
0
QC = VCO ÷ 4
QC = VCO ÷ 8
FSELD
0
QD = VCO ÷ 4
QD = VCO ÷ 8
ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
4.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
VOUT
DC Output Voltage
-0.3
VCC+0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage temperature
125
°C
-40
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
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MPC9350
DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)
Freescale Semiconductor, Inc...
Symbol
Max
Unit
VIH
Input high voltage
Characteristics
Min
2.0
Typ
VCC + 0.3
V
LVCMOS
Condition
VIL
Input low voltage
-0.3
0.8
V
LVCMOS
VOH
Output High Voltage
2.4
V
IOH=-24 mA1.
VOL
Output Low Voltage
0.55
0.30
V
V
IOL= 24 mA
IOL= 12 mA
IIN
Input Current
200
µA
ZOUT
Output impedance
14 - 17
W
VIN = 0V or VIN = VCC
CIN
Input capacitance
4.0
pF
CPD
Power Dissipation Capacitance
10
pF
Per Output
ICCA
Maximum PLL Supply Current
10
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
VTT
Output termination voltage
VCC÷2
V
1. The MPC9350 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
AC CHARACTERISTICS (VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Symbol
fref
a.
Characteristics
Min
Input Frequency
÷ 16 feedback
÷ 32 feedback
Static Test Mode
Typ
12.5
6.25
0
Max
Unit
Condition
25
12.5
300
MHz
MHz
MHz
FBSEL = 1
FBSEL = 0
PLL_EN = 0
fXTAL
Crystal Oscillator Frequency
10
25
MHz
XTAL inputs
fVCO
VCO Frequency
200
400
MHz
PLL_EN = 1
fMAX
Maximum Output Frequency
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
200
100
50
MHz
MHz
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
TLCK Input Rise/Fall Time
1.0
1.0
ns
ns
tsk(o)
Output-to-output Skew
150
ps
tPW
Output Duty Cycle
45
50
55
ps
T=Clock period
tr, tf
Output Rise/Fall Time
0.1
0.5
1.0
ns
see Figure 10.
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
BW
PLL closed loop bandwidth
÷ 16 feedback (VCC = 3.3V)
÷ 16 feedback (VCC = 2.5V)
÷ 32 feedback (VCC = 3.3V)
÷ 32 feedback (VCC = 2.5V)
tJIT(CC)
Cycle-to-cycle jitter
tJIT(PER)
Period Jitter
tLOCK
Maximum PLL Lock Time
VCC = 2.5V
VCC = 3.3V
45
MHz
MHz
MHz
MHz
single frequency
multiple frequencies
30
100
200
300
ps
ps
÷ 16 feedback
÷ 32 feedback
30
80
150
200
ps
ps
1
ms
tJIT(∅)
I/O Phase Jitter (RMS)
AC characteristics apply for parallel output termination of 50Ω to VTT
MOTOROLA
2.0 – 8.0
1.0 – 4.0
1.5 – 3.5
0.7 – 2.0
5 – 20
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0.7V to 1.7V
0.8V to 2.0V
ps
RMS value
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Freescale Semiconductor, Inc.
MPC9350
DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Freescale Semiconductor, Inc...
Symbol
a.
Max
Unit
VIH
Input high voltage
Characteristics
Min
1.7
Typ
VCC + 0.3
V
LVCMOS
VIL
Input low voltage
-0.3
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH=-15 mAa
VOL
Output Low Voltage
V
IOL= 15 mA
ZOUT
Output impedance
IIN
Input Current
CIN
Input capacitance
4.0
pF
CPD
Power Dissipation Capacitance
10
pF
Per Output
ICCA
Maximum PLL Supply Current
10
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
0.6
W
17 - 20
200
µA
Condition
VIN = 0V or VIN = VCC
VTT
Output termination voltage
VCC÷2
V
The MPC9350 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
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MPC9350
APPLICATIONS INFORMATION
Programming the MPC9350
The MPC9350 clock driver outputs can be configured into
several divider modes, in addition the internal feedback of the
device allows for flexibility in establishing two input to output
frequency relationships. The output division settings establish
the output frequency relationship. The output divider of the
four output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship FBSEL = 1, (VC0 = 32 * CLK)”
and “Output Frequency Relationship FBSEL = 0, (VC0 = 16 *
CLK)” illustrate the various output configurations. The tables
describes the outputs using the input clock frequency CLK as
a reference.
In addition, it must be ensured that the VCO will be stable
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to 400
MHz and should not be exceeded for stable operation.
Freescale Semiconductor, Inc...
Output Frequency Relationshipa FBSEL = 1, (VC0 = 32 * CLK)
Inputs
FSELA
a.
FSELB
Outputs
FSELC
FSELD
QA
QB
QC0, QC1
QD0-QD4
0
0
0
0
16 * CLK
8 * CLK
8 * CLK
8 * CLK
0
0
0
1
16 * CLK
8 * CLK
8 * CLK
4 * CLK
0
0
1
0
16 * CLK
8 * CLK
4 * CLK
8 * CLK
0
0
1
1
16 * CLK
8 * CLK
4 * CLK
4 * CLK
0
1
0
0
16 * CLK
4 * CLK
8 * CLK
8 * CLK
0
1
0
1
16 * CLK
4 * CLK
8 * CLK
4 * CLK
0
1
1
0
16 * CLK
4 * CLK
4 * CLK
8 * CLK
0
1
1
1
16 * CLK
4 * CLK
4 * CLK
4 * CLK
1
0
0
0
8 * CLK
8 * CLK
8 * CLK
8 * CLK
1
0
0
1
8 * CLK
8 * CLK
8 * CLK
4 * CLK
1
0
1
0
8 * CLK
8 * CLK
4 * CLK
8 * CLK
1
0
1
1
8 * CLK
8 * CLK
4 * CLK
4 * CLK
1
1
0
0
8 * CLK
4 * CLK
8 * CLK
8 * CLK
1
1
0
1
8 * CLK
4 * CLK
8 * CLK
4 * CLK
1
1
1
0
8 * CLK
4 * CLK
4 * CLK
8 * CLK
1
1
1
1
8 * CLK
4 * CLK
4 * CLK
4 * CLK
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 datasheet more input to output
relationships in external feedback mode.
Output Frequency Relationshipa FBSEL = 0, (VC0 = 16 * CLK)
Inputs
FSELA
a.
FSELB
Outputs
FSELC
FSELD
QA
QB
QC0, QC1
QD0-QD4
0
0
0
0
8 * CLK
4 * CLK
4 * CLK
4 * CLK
0
0
0
1
8 * CLK
4 * CLK
4 * CLK
2 * CLK
0
0
1
0
8 * CLK
4 * CLK
2 * CLK
4 * CLK
0
0
1
1
8 * CLK
4 * CLK
2 * CLK
2 * CLK
0
1
0
0
8 * CLK
2 * CLK
4 * CLK
4 * CLK
0
1
0
1
8 * CLK
2 * CLK
4 * CLK
2 * CLK
0
1
1
0
8 * CLK
2 * CLK
2 * CLK
4 * CLK
0
1
1
1
8 * CLK
2 * CLK
2 * CLK
2 * CLK
1
0
0
0
4 * CLK
4 * CLK
4 * CLK
4 * CLK
1
0
0
1
4 * CLK
4 * CLK
4 * CLK
2 * CLK
1
0
1
0
4 * CLK
4 * CLK
2 * CLK
4 * CLK
1
0
1
1
4 * CLK
4 * CLK
2 * CLK
2 * CLK
1
1
0
0
4 * CLK
2 * CLK
4 * CLK
4 * CLK
1
1
0
1
4 * CLK
2 * CLK
4 * CLK
2 * CLK
1
1
1
0
4 * CLK
2 * CLK
2 * CLK
4 * CLK
1
1
1
1
4 * CLK
2 * CLK
2 * CLK
2 * CLK
Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351datasheet for more input to output
relationships in external feedback mode.
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MPC9350
Power Supply Filtering
The MPC9350 is a mixed analog/digital product and as such
it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen on
the power supply pins. The MPC9350 provides separate
power supplies for the output buffers (VCCO) and the
phase-locked loop (VCCA) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board this level of isolation
is sufficient. However, in a digital system environment where
it is more difficult to minimize noise on the power supplies a
second level ofisolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
MPC9350. Figure 3. illustrates a typical power supply filter
scheme. The MPC9350 is most susceptible to noise with
spectral content in the 10kHz to 5MHz range. Therefore the
filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the
DC voltage drop that will be seen between the VCC supply and
the VCCA pin of the MPC9350. From the data sheet the IVCCA
current (the current sourced through the VCCA pin) is typically
10 mA (15 mA maximum), assuming that a minimum of 3.0V
must be maintained on the VCCA pin. Very little DC voltage
drop can be tolerated when a 3.3V VCC supply is used. The
resistor shown in Figure 3. “Power Supply Filter” must have
a resistance of 10-15 to meet the voltage drop criteria for
VCC=3.3V. For VCC=2.5V operation, RS must be selected to
maintain the minimum VCC specification of 2.375V for the PLL
supply pin for proper operation. The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above 20 kHz.
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. It is recommended that the user start
with an 8-10 Ω resistor to avoid potential VCC drop problems
and only move to the higher value resistors when a higher level
of attenuation is shown to be needed.
W
Although the MPC9350 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most
designs.
Driving Transmission Lines
The MPC9350 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 15Ω the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred
to Motorola application note AN1091. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point scheme
either series terminated or parallel terminated transmission
lines can be used. The parallel technique terminates the signal
at the end of the line with a 50Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9350 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can
drive multiple series terminated lines. Figure 4. “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC9350
clock driver is effectively doubled due to its capability to drive
multiple lines.
MPC9350
OUTPUT
BUFFER
IN
14Ω
RS = 36Ω
ZO = 50Ω
OutA
2.5V or 3.3V
MPC9350
OUTPUT
BUFFER
RS=5–15Ω
VCCA
IN
22µF
MPC9350
RS = 36Ω
OutB0
14Ω
RS = 36Ω
0.01µF
ZO = 50Ω
ZO = 50Ω
OutB1
VCC
0.01µF
Figure 4. Single versus Dual Transmission Lines
Figure 3. Power Supply Filter
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The waveform plots in Figure 5. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9350 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9350. The output waveform in Figure 5. “Single versus
Dual Line Termination Waveforms” shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36Ω series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 17Ω
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.25V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.5V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 6. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
MPC9350
OUTPUT
BUFFER
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
3.0
2.5
VOLTAGE (V)
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MPC9350
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
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MPC9350
MPC9350 DUT
PULSE
GENERATOR
Z = 50
ZO = 50Ω
ZO = 50Ω
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 7. TCLK MPC9350 AC test reference for Vcc = 3.3V and Vcc = 2.5V
VCC
VCC 2
VCC
VCC 2
B
B
Freescale Semiconductor, Inc...
GND
GND
tP
VCC
VCC 2
B
T0
GND
DC = tP /T0 x 100%
tSK(O)
The pin–to–pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
Figure 9. Output Duty Cycle (DC)
Figure 8. Output–to–output Skew tSK(O)
tF
VCC=3.3V
2.4
VCC=2.5V
1.8V
0.55
0.6V
tR
The time from the maximum low level voltage to minimum high level of a
clock signal, expressed in ns
Figure 10. Transition Time Test Reference
TN
TN+1
TJIT(CC) = |TN –TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
Figure 11. Cycle–to–cycle Jitter
TIMING SOLUTIONS
TJIT(P) = |TN –1/f0 |
T0
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 12. Period Jitter
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MPC9350
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
A
4X
A1
32
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
DETAIL Y
V1
17
8
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
–T–, –U–, –Z–
S
DETAIL AD
G
–AB–
SEATING
PLANE
–AC–
0.10 (0.004) AC
8X
AE
M_
P
R
AE
C E
X
DETAIL AD
BASE
METAL
Q_
ÉÉ
ÉÉ
ÉÉ
N
F
J
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
M
K
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
D
0.20 (0.008)
W
0.250 (0.010)
H
AC T–U Z
DETAIL Y
GAUGE PLANE
Freescale Semiconductor, Inc...
B1
SECTION AE–AE
MOTOROLA
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9350
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MPC9350
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MPC9350/D
TIMING
SOLUTIONS