STMicroelectronics M28F101-150P6 1 mb 128k x 8, chip erase flash memory Datasheet

M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
5V ±10% SUPPLY VOLTAGE
12V PROGRAMMING VOLTAGE
FAST ACCESS TIME: 70ns
BYTE PROGRAMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Stand-by Current: 100µA max
10,000 ERASE/PROGRAM CYCLES
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUTS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 07h
DESCRIPTION
The M28F101 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is organised as 128K bytes of 8 bits. It uses a command
register architecture to select the operating modes
and thus provides a simple microprocessor interface. The M28F101 FLASH Memory is suitable for
applications where the memory has to be reprogrammed in the equipment. The access time of
70ns makes the device suitable for use in high
speed microprocessor systems.
32
1
PLCC32 (K)
PDIP32 (P)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC
VPP
17
8
A0-A16
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
April 1997
W
DQ0-DQ7
M28F101
E
G
VSS
AI00666B
1/23
M28F101
Figure 2A. DIP Pin Connections
VCC
W
NC
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A12
A15
A16
VPP
VCC
W
NC
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
M28F101
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
9
M28F101
25
A14
A13
A8
A9
A11
G
A10
E
DQ7
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 2B. LCC Pin Connections
AI00668
AI00667
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
Figure 2D. TSOP Reverse Pin Connections
A11
A9
A8
A13
A14
NC
W
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
8
9
32
M28F101
(Normal)
16
25
24
17
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
1
8
9
M28F101
(Reverse)
16
AI00669B
Warning: NC = Not Connected.
2/23
25
24
17
AI00670C
Warning: NC = Not Connected.
A11
A9
A8
A13
A14
NC
W
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
M28F101
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
Value
–40 to 125
Unit
°C
Storage Temperature
–65 to 150
°C
VIO
Input or Output Voltages
–0.6 to 7
V
VCC
Supply Voltage
–0.6 to 7
V
VA9
A9 Voltage
–0.6 to 13.5
V
VPP
Program Supply Voltage, during Erase
or Programming
–0.6 to 14
V
TSTG
Note: Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above
those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION
The M28F101 FLASH Memory employs a technology similar to a 1 Megabit EPROM but adds to the
device functionality by providing electrical erasure
and programming. These functions are managed
by a command register. The functions that are
addressed via the command register depend on
the voltage applied to the VPP, program voltage,
input. When VPP is less than or equal to 6.5V, the
command register is disabled and M28F101 functions as a read only memory providing operating
modes similar to an EPROM (Read, Output Disable, Electronic Signature Read and Standby).
When VPP is raised to 12V the command regsiter
is enabled and this provides, in addition, Erase and
Program operations.
Output Disable Mode. When the Output Enable
(G) is High the outputs are in a high impedance
state.
Electronic Signature Mode. This mode allows the
read out of two binary codes from the device which
identify the manufacturer and device type. This
mode is intended for use by programming equipment to automatically select the correct erase and
programming algorithms. The Electronic Signature
Mode is active when a high voltage (11.5V to 13V)
is applied to address line A9 with E and G Low. With
A0 Low the output data is the manufacturer code,
when A0 is High the output is the device type code.
All other address lines should be maintained Low
while reading the codes. The electronic signature
may also be accessed in Read/Write modes.
READ ONLY MODES, VPP ≤ 6.5V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
Standby Mode this input is don’t care.
Read Mode. The M28F101 has two enable inputs,
E and G, both of which must be Low in order to
output data from the memory. The Chip Enable (E)
is the power control and should be used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independant of the device selection.
Standby Mode. In the Standby Mode the maximum supply current is reduced. The device is
placed in the Standby Mode by applying a High to
the Chip Enable (E) input. When in the Standby
Mode the outputs are in a high impedance state,
independant of the Output Enable (G) input.
READ/WRITE MODES, 11.4V ≤ VPP ≤ 12.6V
When VPP is High both read and write operations
may be performed. These are defined by the contents of an internal command register. Commands
may be written to this register to set-up and execute, Erase, Erase Verify, Program, Program Verify
and Reset modes. Each of these modes needs 2
cycles. Eah mode starts with a write operation to
set-up the command, this is followed by either read
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
data at any location in the memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
Electronic Signature Read mode is set-up with one
cycle and followed by a read cycle to output the
manufacturer or device codes.
3/23
M28F101
Table 3. Operations
(1)
VPP
Read Only
Read/Write
(2)
Operation
E
G
W
A9
DQ0 - DQ7
Read
VIL
VIL
VIH
A9
Data Output
Output Disable
VIL
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Electronic Signature
VIL
VIL
VIH
VID
Codes
Read
VIL
VIL
VIH
A9
Data Output
Write
VIL
VIH
VIL Pulse
A9
Data Input
Output Disable
VIL
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
VPPL
VPPH
Notes: 1. X = VIL or VIH.
2. Refer also to the Command table.
Table 4. Electronic Signature
Identifier
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
0
0
0
0
0
1
1
1
07h
Table 5. Commands (1)
Command
1st Cycle
Cycles
2nd Cycle
Operation
A0-A16
DQ0-DQ7
Read
1
Write
X
00h
Electronic
Signature (2)
2
Write
X
90h
Setup Erase/
2
Write
X
Setup Program/
2
2
A0-A16
DQ0-DQ7
Read
00000h
20h
Read
00001h
07h
Write
X
20h
Read
X
Data Output
Write
A0-A16
Data Input
20h
Erase
Erase Verify
Operation
Write
A0-A16
A0h
Write
X
40h
Program
Program Verify
2
Write
X
C0h
Read
X
Data Output
Reset
2
Write
X
FFh
Write
X
FFh
Notes: 1. X = VIL or VIH.
2. Refer also to the Electronic Signature table.
4/23
M28F101
Table 6. AC Measurement Conditions
SRAM Interface Levels
EPROM Interface Levels
Input Rise and Fall Times
≤ 10ns
≤ 10ns
Input Pulse Voltages
0 to 3V
0.45V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
EPROM Interface
2.4V
OUT
CL = 30pF or 100pF
2.0V
0.8V
0.45V
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
AI01275
CL includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
COUT
Parameter
Test Condition
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Input Capacitance
Output Capacitance
Min
Note: 1. Sampled only, not 100% test.ed
READ/WRITE MODES (cont’d)
A write to the command register is made by bringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage VCC and the program voltage
VPP can be applied in any order. When the device
is powered up or when VPP is ≤ 6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addition a specific command may be used to set the
command register to 00h for reading the memory.
The system designer may chose to provide a constant high VPP and use the register commands for
all operations, or to switch the VPP from low to high
only when needing to erase or program the memory. All command register access is inhibited when
VCC falls below the Erase/Write Lockout Voltage
(VLKO) of 2.5V.
If the device is deselected during Erasure, Programming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the operation. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
5/23
M28F101
Table 8. DC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
ICC
ICC1
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
Output Leakage Current
0V ≤ VOUT ≤ VCC
±10
µA
Supply Current (Read)
E = VIL, f = 6MHz
30
mA
E = VIH
1
mA
E = VCC ± 0.2V
50
µA
During Programming
10
mA
During Verify
15
mA
During Erasure
15
mA
During Erase Verify
15
mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
ICC2
(1)
Supply Current (Programming)
ICC3
(1)
Supply Current (Program Verify)
ICC4
(1)
Supply Current (Erase)
ICC5
(1)
Supply Current (Erase Verify)
ILPP
Program Leakage Current
VPP ≤ VCC
±10
µA
IPP
Program Current (Read or
Standby)
VPP > VCC
120
µA
VPP ≤ VCC
±10
µA
VPP = VPPH, During Programming
30
mA
Program Current (Program
Verify)
VPP = VPPH, During Verify
5
mA
Program Current (Erase)
VPP = VPPH, During Erase
30
mA
VPP = VPPH, During Erase Verify
5
mA
–0.5
0.8
V
2
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
IOL = 5.8mA (grade 1)
0.45
V
IOL = 2.1mA (grade 6)
0.45
V
IPP1(1)
IPP2
(1)
IPP3(1)
IPP4
(1)
VIL
VIH
Program Current (Programming)
Program Current (Erase Verify)
Input Low Voltage
Input High Voltage TTL
Input High Voltage CMOS
VOL
VOH
Output Low Voltage
Output High Voltage CMOS
Output High Voltage TTL
VPPL
Program Voltage (Read
Operations)
VPPH
VID
IID
(1)
VLKO
IOH = –100µA
4.1
V
IOH = –2.5mA
0.85 VCC
V
IOH = –2.5mA
2.4
V
0
6.5
V
Program Voltage (Read/Write
Operations)
11.4
12.6
V
A9 Voltage (Electronic Signature)
11.5
13
V
200
µA
A9 Current (Electronic Signature)
Supply Voltage, Erase/Program
Lock-out
Note: 1. Not 100% tested. Characterisation Data available.
6/23
Min
A9 = VID
2.5
V
M28F101
Table 9A. Read Only Mode AC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)
M28F101
-70
Symbol
Alt
Parameter
Test Condition
-90
VCC=5V±5%
SRAM
Interface
Min
Write Enable High to
Output Enable Low
tWHGL
Max
-100
VCC=5V±10% VCC=5V±10%
EPROM
Interface
Min
Max
µs
70
90
100
ns
E = VIL, G = VIL
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL
Chip Enable High to
Output Hi-Z
G = VIL
0
30
0
45
tDF
Output Enable High to
Output Hi-Z
E = VIL
0
30
0
30
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
0
tAXQX
Max
6
Read Cycle Time
(1)
Min
6
tRC
tGHQZ
EPROM
Interface
6
tAVAV
tEHQZ (1)
Unit
70
0
90
0
70
0
100
0
90
0
40
0
ns
100
0
40
ns
ns
ns
45
ns
0
45
ns
0
30
ns
0
ns
Note: 1. Sampled only, not 100% tested
Read Mode. The Read Mode is the default at
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
output data from the memory. The memory remains
in the Read Mode until a new command is written
to the command register.
Electronic Signature Mode. In order to select the
correct erase and programming algorithms for onboard programming, the manufacturer and device
codes may be read directly. It is not neccessary to
apply a high voltage to A9 when using the command register. The Electronic Signature Mode is
set-up by writing 90h to the command register. The
following read cycles, with address inputs 00000h
or 00001h, output the manufacturer or device type
codes. The command is terminated by writing another valid command to the command register (for
example Reset).
7/23
M28F101
Table 9B. Read Only Mode AC Characteristics
((TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)
M28F101
-120
Symbol
Alt
Parameter
Test Condition
-150
VCC=5V±10% VCC=5V±10% VCC=5V±10%
EPROM
Interface
Min
Write Enable High to
Output Enable Low
tWHGL
-200
Max
EPROM
Interface
Min
Max
µs
120
150
200
ns
E = VIL, G = VIL
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL
Chip Enable High to
Output Hi-Z
G = VIL
0
55
0
55
tDF
Output Enable High to
Output Hi-Z
E = VIL
0
30
0
35
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
0
tAXQX
Max
6
Read Cycle Time
(1)
Min
6
tRC
tGHQZ
EPROM
Interface
6
tAVAV
tEHQZ (1)
Unit
120
0
150
0
120
0
200
0
150
0
50
0
ns
200
0
55
ns
ns
ns
60
ns
0
60
ns
0
40
ns
0
ns
Note: 1. Sampled only, not 100% tested
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the command register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an addressed byte.
8/23
Erase Verify Mode is set-up by writing A0h to the
command register and at the same time supplying
the address of the byte to be verified. The rising
edge of W during the set-up of the first Erase Verify
Mode stops the Erase operation. The following
read cycle is made with an internally generated
margin voltage applied; reading FFh indicates that
all bits of the addressed byte are fully erased. The
whole contents of the memory are verified by repeating the Erase Verify Operation, first writing the
set-up code A0h with the address of the byte to be
verified and then reading the byte contents in a
second read cycle.
M28F101
Figure 5. Read Mode AC Waveforms
tAVAV
A0-A16
tAVQV
tAXQX
E
tELQV
tEHQZ
tELQX
G
tGLQV
tGHQZ
tGLQX
DQ0-DQ7
DATA OUT
AI00671
Figure 6. Read Command Waveforms
VPP
tVPHEL
VALID
A0-A16
tAVQV
tAXQX
E
tELWL
tWHEH
tELQV
tEHQZ
G
tGHWL
tWHGL
tGHQZ
W
tWLWH
tGLQV
tDVWH
DQ0-DQ7
tWHDX
COMMAND
READ SET-UP
DATA OUT
READ
AI00672
9/23
M28F101
Figure 7. Electronic Signature Command Waveforms
VPP
tVPHEL
00000h-00001h
A0-A16
tAVQV
tAXQX
E
tELWL
tWHEH
tELQV
tEHQZ
G
tWHGL
tGHWL
tGHQZ
W
tGLQV
tWLWH
tDVWH
DQ0-DQ7
tWHDX
COMMAND
READ ELECTRONIC
SIGNATURE SET-UP
DATA OUT
READ
MANUFACTURER
OR DEVICE
AI00673
READ/WRITE MODES (cont’d)
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not FFh, another
Erase operation is performed and verification continues from the address of the last verifiedbyte. The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
Program and Program Verify Modes. The Program Mode is set-up by writing 40h to the command
register. This is followed by a second write cycle
which latches the address and data of the byte to
be programmed. The rising edge of W during this
secind cycle starts the programming operation.
Programming is followed by a Program Verify of the
data written.
10/23
ProgramVerify Mode is set-up by writing C0h to the
command register. The rising edge of W during the
set-up of the Program Verify Mode stops the Programming operation. The following read cycle, of
the address already latched during programming,
is made with an internally generated margin voltage applied,reading valid data indicates that all bits
have been programmed.
Reset Mode. This command is used to safely abort
Erase or Program Modes. The Reset Mode is
set-up and performed by writing FFh two times to
the command register. The command should be
followed by writing a valid command to the the
command register (for example Read).
M28F101
Table 10A. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F101
Symbol
Alt
Parameter
-70
-90
-100
VCC=5V±5%
VCC=5V±10%
VCC=5V±10%
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
VPP High to Chip Enable Low
tVPHEL
Max
1
Min
Max
1
Min
Unit
Max
µs
1
VPP High to Write Enable Low
1
1
1
µs
tWHWH3
tWC
Write Cycle Time
70
90
100
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
0
ns
Address Valid to Chip Enable Low
0
0
0
ns
Write Enable Low to Address Transition
40
40
40
ns
Chip Enable Low to Address Transition
50
60
60
ns
tVPHWL
tAVEL
tWLAX
tAH
tELAX
Chip Enable Low to Write Enable Low
10
15
15
ns
tWLEL
Write Enable Low to Chip Enable Low
0
0
0
ns
tGHWL
Output Enable High to Write Enable
Low
0
0
0
µs
tELWL
tCS
Output Enable High to Chip Enable Low
0
0
0
µs
Input Valid to Write Enable High
30
40
40
ns
tDVEH
Input Valid to Chip Enable High
30
35
40
ns
tWLWH
Write Enable Low to Write Enable High
(Write Pulse)
35
40
40
ns
Chip Enable Low to Chip Enable High
(Write Pulse)
35
45
45
ns
Write Enable High to Input Transition
10
10
10
ns
tGHEL
tDVWH
tDS
tWP
tELEH
tWHDX
tDH
tEHDX
Chip Enable High to Input Transition
10
10
10
ns
tWHWH1
Duration of Program Operation
9.5
9.5
9.5
µs
tEHEH1
Duration of Program Operation
9.5
9.5
9.5
µs
tWHWH2
Duration of Erase Operation
9.5
9.5
9.5
ms
Write Enable High to Chip Enable High
0
0
0
ns
Chip Enable High to Write Enable High
0
0
0
ns
tWHEH
tCH
tEHWH
Write Enable High to Write Enable Low
20
20
20
ns
tEHEL
Chip Enable High to Chip Enable Low
20
20
20
ns
tWHGL
Write Enable High to Output Enable
Low
6
6
6
µs
Chip Enable High to Output Enable Low
6
tWHWL
tWPH
tEHGL
tAVQV
tELQX
(1)
tELQV
tGLQX
(1)
tGLQV
tEHQZ
(1)
tGHQZ
(1)
tAXQX
tACC
Addess Valid to data Output
6
70
0
µs
6
90
0
100
tLZ
Chip Enable Low to Output Transition
tCE
Chip Enable Low to Output Valid
tOLZ
Output Enable Low to Output Transition
tOE
Output Enable Low to Output Valid
40
40
45
ns
70
0
0
ns
90
0
ns
100
0
ns
ns
Chip Enable High to Output Hi-Z
30
40
40
ns
tDF
Output Enable High to Output Hi-Z
30
30
30
ns
tOH
Address Transition to Output Transition
0
0
0
ns
Note: 1. Sampled only, not 100% tested.
11/23
M28F101
Table 10B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F101
Symbol
Alt
Parameter
-120
-150
-200
VCC=5V±10%
VCC=5V±10%
VCC=5V±10%
EPROM
Interface
EPROM
Interface
EPROM
Interface
Min
VPP High to Chip Enable Low
tVPHEL
1
µs
ns
Address Valid to Write Enable Low
0
0
0
ns
Address Valid to Chip Enable Low
0
0
0
ns
Write Enable Low to Address Transition
60
60
75
ns
Chip Enable Low to Address Transition
80
80
80
ns
tAS
Chip Enable Low to Write Enable Low
20
20
20
ns
tWLEL
Write Enable Low to Chip Enable Low
0
0
0
ns
tGHWL
Output Enable High to Write Enable
Low
0
0
0
µs
tELWL
tCS
µs
200
tAVWL
tAH
Max
1
1
Write Cycle Time
tELAX
Min
150
tWC
tWLAX
Max
1
1
tWHWH3
tAVEL
Min
120
VPP High to Write Enable Low
tVPHWL
Max
1
Unit
Output Enable High to Chip Enable Low
0
0
0
µs
Input Valid to Write Enable High
50
50
50
ns
tDVEH
Input Valid to Chip Enable High
50
50
50
ns
tWLWH
Write Enable Low to Write Enable High
(Write Pulse)
60
60
60
ns
Chip Enable Low to Chip Enable High
(Write Pulse)
70
70
70
ns
Write Enable High to Input Transition
10
10
10
ns
tGHEL
tDVWH
tDS
tWP
tELEH
tWHDX
tDH
tEHDX
Chip Enable High to Input Transition
10
10
10
ns
tWHWH1
Duration of Program Operation
9.5
9.5
9.5
µs
tEHEH1
Duration of Program Operation
9.5
9.5
9.5
µs
tWHWH2
Duration of Erase Operation
9.5
9.5
9.5
ms
tWHEH
tCH
tEHWH
0
0
0
ns
Chip Enable High to Write Enable High
0
0
0
ns
Write Enable High to Write Enable Low
20
20
20
ns
tEHEL
Chip Enable High to Chip Enable Low
20
20
20
ns
tWHGL
Write Enable High to Output Enable
Low
6
6
6
µs
Chip Enable High to Output Enable Low
6
tWHWL
tWPH
Write Enable High to Chip Enable High
tEHGL
tAVQV
tELQX
(1)
tELQV
tGLQX
(1)
tGLQV
tEHQZ
(1)
tGHQZ
(1)
tAXQX
tACC
Addess Valid to data Output
0
µs
6
150
0
200
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
tOLZ
Output Enable Low to Output Transition
tOE
Output Enable Low to Output Valid
50
55
60
ns
120
0
0
ns
tCE
150
0
ns
200
0
ns
ns
Chip Enable High to Output Hi-Z
50
55
60
ns
tDF
Output Enable High to Output Hi-Z
30
35
40
ns
tOH
Address Transition to Output Transition
Note: 1. Sampled only, not 100% tested.
12/23
6
120
0
0
0
ns
tVPHEL
COMMAND
ERASE SET-UP
tDVWH
tWLWH
tGHWL
tELWL
DQ0-DQ7
W
G
E
A0-A16
VPP
COMMAND
ERASE SET-UP
(REPEAT OF 1st CYCLE)
tWHDX
tWHWL
tWHEH
tWHWH3
tWLAX
COMMAND
tWHEH
ERASE VERIFY
SET-UP
tDVWH
tWLWH
tWHWH2
tELWL
tAVWL
VALID
ERASE OPERATION
tWHDX
tWHGL
tELQV
VERIFY
READ
DATA OUT
tGLQV
AI00674
tGHQZ
tEHQZ
M28F101
Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled
13/23
14/23
tGHEL
tWLEL
DQ0-DQ7
E
G
W
A0-A16
VPP
COMMAND
ERASE SET-UP
tDVEH
tELEH
tVPHWL
COMMAND
ERASE SET-UP
(REPEAT OF 1st CYCLE)
tEHDX
tEHEL
tEHWH
tWHWH3
tELAX
COMMAND
tEHWH
ERASE VERIFY
SET-UP
tDVEH
tELEH
tEHEH2
tWLEL
tAVEL
VALID
ERASE OPERATION
tEHDX
tELQV
tEHGL
tGLQV
VERIFY
READ
DATA OUT
AI01313
tEHQZ
tGHQZ
M28F101
Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled
tVPHEL
tWHDX
tWHWL
tELWL
DATA IN
tWLWH
tWLAX
ADDRESS AND
DATA LATCH
tDVWH
tWHEH
VALID
tWHWH3
tAVWL
COMMAND
tWHEH
PROGRAM SET-UP
tDVWH
tWLWH
tGHWL
tELWL
DQ0-DQ7
W
G
E
A0-A16
VPP
tWHDX
tWHWH1
tELWL
tWHGL
tELQV
tWHDX
tWLWH
COMMAND
PROGRAM
VERIFY SET-UP
tDVWH
tWHEH
PROGRAM OPERATION
VERIFY
READ
DATA OUT
tGLQV
AI00675
tGHQZ
tEHQZ
M28F101
Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled
15/23
16/23
tVPHEL
tEHDX
tEHEL
tWLEL
DATA IN
tELEH
tELAX
ADDRESS AND
DATA LATCH
tDVEH
tEHWH
VALID
tWHWH3
tAVEL
COMMAND
tEHWH
PROGRAM SET-UP
tDVEH
tELEH
tGHEL
tWLEL
DQ0-DQ7
E
G
W
A0-A16
VPP
tEHDX
tEHEH1
tWLEL
tELEH
COMMAND
PROGRAM
VERIFY SET-UP
tDVEH
tEHWH
PROGRAM OPERATION
tEHDX
tELQV
tEHGL
VERIFY
READ
DATA OUT
tGLQV
AI00676
tEHQZ
tGHQZ
M28F101
Figure 11. Program Set-up and Program Verify Commands Waveforms, E Controlled
M28F101
Figure 12. Erasing Flowchart
Figure 13. Programming Flowchart
VPP = 12V
VPP = 12V
PROGRAM ALL
BYTES TO 00h
n=0
n=0, Addr=00000h
NO
YES
VPP < 6.5V
FAIL
ERASE SET-UP
PROGRAM SET-UP
Latch Addr, Data
Wait 10ms
Wait 10µs
NO
ERASE VERIFY
Latch Addr.
++n
LIMIT
YES
PROGRAM VERIFY
++n
= 25
Wait 6µs
Wait 6µs
VPP < 6.5V
FAIL
READ DATA OUTPUT
READ DATA OUTPUT
NO
NO
Data
OK
Addr++
Data
OK
Addr++
YES
YES
Last
Addr
Last
Addr
NO
NO
YES
YES
READ COMMAND
READ COMMAND
VPP < 6.5V, PASS
VPP < 6.5V, PASS
AI00677
AI00678
Limit: 1000 at grade 1; 6000 at grades 3 & 6.
PRESTO F ERASE ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithm first programms all bytes to 00h in order
to ensure uniform erasure. The programming follows the PRESTO F Programming Algorithm.
Erase is set-up by writing 20h to the command
register, the erasure is started by repeating this
write cycle. Erase Verify is set-up by writing A0h to
the command register together with the address of
the byte to be verified. The subsequent read cycle
reads the data which is compared to FFh. Erase
Verify begins at address 0000h and continues to
the last address or until the comparison of the data
to 0FFh fails. If this occurs, the address of the last
byte checked is stored and a new Erase operation
performed. Erase Verify then continues from the
address of the stored location.
PRESTO F PROGRAM ALGORITHM
The PRESTO F Programming Algorithm applies a
series of 10µs programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-up by writing 40h to the command register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected. During Program and Program Verify operations a MARGIN MODE circuit is activated to
guaranteethat the cell is programmed with a safety
margin.
17/23
M28F101
ORDERING INFORMATION SCHEME
Example:
M28F101
-70
X
N
1
TR
Option
Operating Voltage
F
R
5V
Reverse Pinout
TR Tape & Reel
Packing
Speed
Power Supplies
Temp. Range
Package
-70
70ns
blank
VCC ± 10%
P
PDIP32
1
0 to 70 °C
-90
90ns
X
VCC ± 5%
K
PLCC32
3
–40 to 125 °C
-100
100ns
N
TSOP32
8 x 20mm
6
–40 to 85 °C
-120
120ns
-150
150ns
-200
200ns
Devices are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the SGS-THOMSON Sales Office nearest to you.
18/23
M28F101
PDIP32 - 32 pin Plastic DIP, 600 mils width
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
4.83
A1
0.38
–
–
–
B
0.41
B1
Max
0.190
0.015
–
–
–
0.51
0.016
0.020
1.14
1.40
0.045
0.055
C
0.20
0.30
0.008
0.012
D
41.78
42.04
1.645
1.655
E
15.24
15.88
0.600
0.625
E1
13.46
13.97
0.530
0.550
A2
–
–
e1
2.54
–
–
0.100
–
–
eA
15.24
–
–
0.600
–
–
L
3.18
3.43
0.125
0.135
S
1.78
2.03
0.070
0.080
α
0°
15°
0°
15°
N
32
32
PDIP32
A2
A1
B1
B
A
L
α
e1
eA
C
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
19/23
M28F101
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Symb
Typ
inches
Min
Max
A
2.54
A1
Min
Max
3.56
0.100
0.140
1.52
2.41
0.060
0.095
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
e
1.27
Typ
0.050
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
PLCC32
D
D1
A1
1 N
B1
E1 E
Ne
e
D2/E2
B
A
Nd
PLCC
Drawing is not to scale.
20/23
CP
M28F101
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Symb
Typ
inches
Min
Max
A
1.04
A1
Min
Max
1.24
0.041
0.049
0.05
0.20
0.002
0.008
A2
0.95
1.06
0.037
0.042
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.90
20.12
0.783
0.792
D1
18.24
18.49
0.718
0.728
E
7.90
8.10
0.311
0.319
–
–
–
–
L
0.30
0.70
0.012
0.028
α
0°
5°
0°
5°
N
32
e
0.50
Typ
0.020
32
CP
0.10
0.004
TSOP32
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
21/23
M28F101
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Symb
Typ
inches
Min
Max
A
1.04
A1
Min
Max
1.24
0.041
0.049
0.05
0.20
0.002
0.008
A2
0.95
1.06
0.037
0.042
B
0.15
0.27
0.006
0.011
C
0.10
0.21
0.004
0.008
D
19.90
20.12
0.783
0.792
D1
18.24
18.49
0.718
0.728
E
7.90
8.10
0.311
0.319
–
–
–
–
L
0.30
0.70
0.012
0.028
α
0°
5°
0°
5°
N
32
e
0.50
Typ
0.020
32
CP
0.10
0.004
TSOP32
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-b
Drawing is not to scale.
22/23
A1
α
L
M28F101
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
 1997 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
23/23