FEATURES CONNECTION DIAGRAM –IN1 +IN1 NC ADA4859-3 16 15 14 13 12 +IN2 +VS 1 11 –IN2 C1_a 2 10 OUT2 CPO 4 6 7 8 –IN3 OUT3 5 +IN3 9 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD, CONNECT TO GROUND. PD 07715-001 C1_b 3 CHARGE PUMP +VS Integrated charge pump Supply range: 3 V to 5.5 V Output range: −3.3 V to −1.8 V 50 mA maximum output current at −3 V for external use High speed amplifiers −3 dB bandwidth: 195 MHz Slew rate: 740 V/µs 0.1 dB gain flatness: 60 MHz 0.1% settling time: 20 ns Low power Total quiescent current: 38 mA Power-down feature High input common-mode voltage range −1.8 V to +3.8 V at +5 V supply Current feedback architecture Differential gain error: 0.01% Differential phase error: 0.02° Available in 16-lead LFCSP OUT1 Data Sheet Single-Supply, Fixed G = 2, High Speed, Video Amplifier with Charge Pump ADA4859-3 Figure 1. APPLICATIONS Professional video Consumer video Imaging Active filters GENERAL DESCRIPTION The ADA4859-3 (triple) is a single-supply, high speed current feedback amplifier with an integrated charge pump that eliminates the need for negative supplies in order to output negative voltages or output a 0 V level for video applications. The 195 MHz, large signal −3 dB bandwidth at a fixed gain of 2, as well as the 740 V/µs slew rate, make this amplifier ideal for high resolution professional and consumer video applications. The amplifier also has a wide input common-mode voltage range that extends from 1.8 V below ground to 1.2 V below the positive rail at 5 V supply. Rev. A This triple video amplifier is designed to operate on supply voltages of 3.3 V to 5 V, using only 38 mA total quiescent current, including the charge pump. To further reduce the power consumption, it is equipped with a power-down feature that lowers the total supply current to as low as 2 mA when the amplifier is not being used. Even in power-down mode, the charge pump can be used to power external components. The maximum output current for external use is 50 mA at −3 V. The ADA4859-3 is available in a 16-lead LFCSP, and it is designed to work over the industrial temperature range of −40°C to +105°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4859-3* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Materials View a parametric search of comparable parts Tutorials • MT-032: Ideal Voltage Feedback (VFB) Op Amp • MT-033: Voltage Feedback Op Amp Gain and Bandwidth • MT-047: Op Amp Noise • MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth • MT-049: Op Amp Total Output Noise Calculations for Single-Pole System • MT-050: Op Amp Total Output Noise Calculations for Second-Order System • MT-052: Op Amp Noise Figure: Don't Be Misled • MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR • MT-056: High Speed Voltage Feedback Op Amps • MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps • MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters • MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps Evaluation Kits • ADA4859-3 Evaluation Board Documentation Application Notes • AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps • AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems • AN-581: Biasing and Decoupling Op Amps in Single Supply Applications Data Sheet • ADA4859-3: Single-Supply, Fixed G=2, High Speed, Video Amplifier with Charge Pump Data Sheet User Guides • UG-140: Universal Evaluation Board for Triple, High Speed Op Amps with Charge Pump Offered in 16-Lead, 4 mm × 4 mm LFCSP Packages Tools and Simulations • Power Dissipation vs Die Temp • VRMS/dBm/dBu/dBV calculators Design Resources • • • • ADA4859-3 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all ADA4859-3 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. ADA4859-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Overview ..................................................................................... 12 Connection Diagram ....................................................................... 1 Charge Pump Operation ........................................................... 12 General Description ......................................................................... 1 Applications Information .............................................................. 13 Revision History ............................................................................... 2 Using the ADA4859-3 in Gains Equal to +1, −1........................ 13 Specifications..................................................................................... 3 Video Line Driver ....................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Power-Down ............................................................................... 14 Maximum Power Dissipation ..................................................... 5 Layout Considerations ............................................................... 14 ESD Caution .................................................................................. 5 Power Supply Bypassing ............................................................ 14 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 15 REVISION HISTORY 11/12—Rev. 0 to Rev. A Changes to Power-Down Section ................................................. 14 11/08—Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet ADA4859-3 SPECIFICATIONS TA = 25°C, VS = 5 V, G = 2, RF = 550 Ω, RL = 150 Ω, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion (HD2/HD3) Crosstalk Total Output Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Output Offset Voltage +Input Bias Current Closed-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Output Overdrive Recovery Time Maximum Linear Output Current @ VO = 1 VPEAK POWER-DOWN Input Voltage Bias Current Turn-On Time Turn-Off Time POWER SUPPLY Operating Range Total Quiescent Current Amplifier Charge Pump Total Quiescent Current When Powered Down Amplifier Charge Pump Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Charge Pump Output Voltage Charge Pump Sink Current Conditions Min Typ Max Unit VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p, CL = 6 pF VOUT = 2 V step VOUT = 2 V step 265 195 60 740 20 MHz MHz MHz V/µs ns fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 5 MHz f = 1 MHz f = 1 MHz −84/−93 −70/−83 −80 17 2 0.01 0.02 dBc dBc dBc nV/√Hz pA/√Hz % Degrees −25 −2 1.9 +IN +IN +9 +0.7 2 +25 +2 2.1 mV µA V/V +3.8 MΩ pF V 15 1.5 −1.8 −1.4 to +3.6 Rise/fall, f = 5 MHz fC = 1 MHz, HD2 ≤ −50 dBc −1.7 to +3.8 15 19 V ns mA Enabled Powered down 1.9 2 +0.1 V V µA µs µs 5.5 V −0.1 0.5 2 3 15 17 21 21 mA mA 0.15 0.25 4 −55 −51 −3 0.3 mA mA dB dB V mA Referred to output Referred to output −3.2 Rev. A | Page 3 of 16 −50 −47 −2.5 150 ADA4859-3 Data Sheet TA = 25°C, VS = 3.3 V, G = 2, RF = 550 Ω, RL = 150 Ω, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk Total Output Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Output Offset Voltage +Input Bias Current Closed-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Output Overdrive Recovery Time Maximum Linear Output Current @ VO = 1 VPEAK POWER-DOWN Input Voltage Bias Current Turn-On Time Turn-Off Time POWER SUPPLY Operating Range Total Quiescent Current Amplifier Charge Pump Total Quiescent Current When Powered Down Amplifier Charge Pump Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Charge Pump Output Voltage Charge Pump Sink Current Conditions Min Typ Max Unit VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p, CL = 6 pF VOUT = 2 V step, RL = 150 Ω VOUT = 2 V step 260 165 65 530 20 MHz MHz MHz V/µs ns fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 5 MHz f = 1 MHz f = 1 MHz −84/−86 −73/−77 −80 17 2 0.02 0.03 dBc dBc dBc nV/√Hz pA/√Hz % Degrees −25 −2 1.9 +IN +IN +9 +0.7 2 +25 +2 2.1 mV µA V/V +2.2 MΩ pF V 15 1.5 −0.9 Rise/fall, f = 5 MHz fC = 1 MHz, HD2 ≤ −50 dBc −0.7 to +2.1 −1 to +2.3 15 18 V ns mA Enabled Powered down 1.25 1.35 +0.1 V V µA µs µs 5.5 V −0.1 0.5 2 3 14 17 19 20 mA mA 0.15 0.25 2 −54 −50 −2 0.3 mA mA dB dB V mA Referred to output Referred to output −2.1 Rev. A | Page 4 of 16 −50 −47 −1.8 45 Data Sheet ADA4859-3 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. See Figure 2 (−VS − 0.2 V) to (+VS − 1.8 V) ±VS Observe power derating curves −65°C to +125°C −40°C to +105°C 300°C The maximum power that can be safely dissipated by the ADA4859-3 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power derating curves in Figure 2. 2.5 Specification is for device in free air. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION (W) 1 Rating 6V 2.0 1.5 1.0 0.5 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. A | Page 5 of 16 07715-002 Parameter Supply Voltage Internal Power Dissipation1 16-Lead LFCSP Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) ADA4859-3 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADA4859-3 OUT1 –IN1 +IN1 NC TOP VIEW (Not to Scale) 16 15 14 13 12 +IN2 +VS 1 11 –IN2 C1_a 2 10 OUT2 CPO 4 6 7 8 –IN3 OUT3 +VS 5 +IN3 9 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD, CONNECT TO GROUND. PD 07715-003 C1_b 3 CHARGE PUMP Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (EPAD) Mnemonic +VS C1_a C1_b CPO +VS +IN3 −IN3 OUT3 PD OUT2 −IN2 +IN2 NC +IN1 −IN1 OUT1 Exposed Pad (EPAD) Description Positive Supply for Charge Pump. Charge Pump Capacitor Side a. Charge Pump Capacitor Side b. Charge Pump Output. Positive Supply. Noninverting Input 3. Inverting Input 3. Output 3. Power Down. Output 2. Inverting Input 2. Noninverting Input 2. No Connect. Noninverting Input 1. Inverting Input 1. Output 1. The exposed pad must be connected to the ground plane. Rev. A | Page 6 of 16 Data Sheet ADA4859-3 TYPICAL PERFORMANCE CHARACTERISTICS 2 2 1 1 NORMALIZED CLOSED-LOOP GAIN (dB) 0 –1 –2 –3 –4 –5 VS = 5V –6 –7 0 –1 –2 –3 –4 VS = 5V –5 –6 –7 1 10 100 1000 FREQUENCY (MHz) –8 07715-004 –8 100 1000 FREQUENCY (MHz) Figure 4. Small Signal Frequency Response vs. Supply Voltage Figure 7. Large Signal Frequency Response vs. Supply Voltage 0.2 0.2 0.1 0.1 CL = 10pF 0 NORMALIZED GAIN (dB) 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.1 CL = 16pF –0.2 CL = 10pF –0.3 CL = 14pF –0.4 –0.5 –0.6 –0.6 VS = 5V –0.7 –0.7 VS = 3.3V –0.8 1 10 100 1000 FREQUENCY (MHz) –0.8 07715-005 NORMALIZED CLOSED-LOOP GAIN (dB) 10 1 07715-007 VS = 3.3V VS = 3.3V 1 100 10 1000 FREQUENCY (MHz) Figure 5. Large Signal 0.1 dB Flatness vs. Supply Voltage 07715-008 NORMALIZED CLOSED-LOOP GAIN (dB) VS = 5 V, G = 2, RF = 550 Ω, RL = 150 Ω, large signal VOUT = 2 V p-p, small signal VOUT = 0.1 V p-p, and T = 25ºC, unless otherwise noted. Figure 8. Large Signal 0.1 dB Flatness vs. Capacitive Load 0 0 –10 –10 –20 –20 –30 –30 DISTORTION (dBc) –40 –50 HD2 –60 –70 –40 –50 HD2 –60 –70 HD3 –80 –80 HD3 –100 1 10 FREQUENCY (MHz) 100 Figure 6. Harmonic Distortion vs. Frequency –100 1 10 FREQUENCY (MHz) Figure 9. Harmonic Distortion vs. Frequency Rev. A | Page 7 of 16 100 07715-009 –90 –90 07715-006 DISTORTION (dBc) VS = 3.3V ADA4859-3 Data Sheet 0 0.2 0.1 –10 CL = 16pF NORMALIZED GAIN (dB) 0 PSRR (dB) –20 –30 –40 –50 –0.1 CL = 10pF –0.2 CL = 110pF CL = 14pF –0.3 –0.4 –0.5 –0.6 –60 –0.7 10 100 400 FREQUENCY (MHz) 1 1000 FREQUENCY (MHz) Figure 10. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 13. Large Signal 0.1 dB Flatness vs. Capacitive Load –40 –30 –40 –50 –50 –60 CROSSTALK (dB) –70 –80 –60 –70 –80 –90 –90 10 1 100 400 FREQUENCY (MHz) –100 0.1 07715-011 –100 0.1 1 10 100 400 FREQUENCY (MHz) Figure 11. Forward Isolation vs. Frequency 07715-014 FORWARD ISOLATION (dB) 100 10 07715-013 1 VS = 3.3V –0.8 07715-010 –70 0.1 Figure 14. Crosstalk vs. Frequency 250 20 INPUT CURRENT NOISE (pA/ Hz) 200 150 100 50 16 14 12 10 8 6 4 1k 10k 100k FREQUENCY (Hz) 1M Figure 12. Total Output Voltage Noise vs. Frequency 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 15. Noninverting Input Current Noise vs. Frequency Rev. A | Page 8 of 16 07715-015 2 0 100 07715-012 OUTPUT VOLTAGE NOISE (nV/ Hz) 18 Data Sheet ADA4859-3 0.15 1.5 VOUT = 200mV p-p CL = 10pF 1.0 CL = 4pF OUTPUT VOLTAGE (V) 0.05 0 –0.05 CL = 4pF 0.5 0 –0.5 CL = 6pF 07715-016 CL = 10pF –0.15 TIME (5ns/DIV) –1.5 TIME (5ns/DIV) Figure 16. Small Signal Transient Response vs. Capacitive Load Figure 19. Large Signal Transient Response vs. Capacitive Load 0.15 1.5 2.0 VOUT = 200mV p-p 0.05 0 –0.05 VS = 5V 1.0 0.5 0 07715-017 VS = 3.3V TIME (5ns/DIV) VS = 5V 0.5 –0.10 –0.15 1.5 –0.5 0 –1.0 –0.5 07715-020 OUTPUT VOLTAGE, VS = 5V (V) OUTPUT VOLTAGE (V) 1.0 OUTPUT VOLTAGE, VS = 3.3V (V) VS = 3.3V 0.10 –1.0 –1.5 TIME (5ns/DIV) Figure 17. Small Signal Transient Response vs. Supply Voltage, CL = 4 pF Figure 20. Large Signal Transient Response vs. Supply Voltage, CL = 4 pF 1100 900 1000 VS = 3.3V 800 RISE 900 700 RISE SLEW RATE (V/µs) 800 700 FALL 600 500 400 600 FALL 500 400 300 300 200 200 100 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE (V p-p) 2.5 07715-018 SLEW RATE (V/µs) 07715-019 –1.0 –0.10 Figure 18. Slew Rate vs. Output Voltage 100 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE (V p-p) Figure 21. Slew Rate vs. Output Voltage Rev. A | Page 9 of 16 2.5 07715-021 OUTPUT VOLTAGE (V) 0.10 CL = 6pF ADA4859-3 Data Sheet 3.0 2.5 VIN 4 2.0 3 1.5 2 1.0 1 0.5 0 0 1.5 VIN VS = 3.3V 2.5 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) 1.0 1.5 1.0 0.5 0.5 0 0 –0.5 –0.5 –2 –0.5 –1.0 VOUT –1.0 –1.5 –3 VOUT –1.5 TIME (20ns/DIV) –2.0 07715-025 –1 07715-022 OUTPUT VOLTAGE (V) 2.0 INPUT VOLTAGE (V) 5 –1.0 TIME (20ns/DIV) Figure 22. Output Overdrive Recovery Figure 25. Output Overdrive Recovery 2.0 0.5 2.0 0.5 0.4 1.6 0.4 1.2 0.3 1.2 0.3 0.8 0.2 0.8 0.4 0.1 1.6 ERROR –0.8 –1.2 –0.3 –1.2 –1.6 –0.4 –1.6 15 20 25 30 35 –0.5 40 TIME (ns) –0.4 –2.0 –5 0 25 30 14 OUTPUT VOLTAGE (V) 16 –2.4 –0.5 40 6 5 VOUT CURRENT (mA) 18 AMPLIFIER CURRENT 35 VPD 0.5 4 0 3 –0.5 2 –1.0 1 12 OUTPUT VOLTAGE –2.8 3.0 3.5 4.0 10 4.5 8 5.0 CHARGE PUMP SUPPLY VOLTAGE (V) 07715-024 CHARGE PUMP OUTPUT VOLTAGE (V) 20 1.5 20 –1.6 –3.2 2.5 15 1.0 –1.2 –2.0 10 TIME (ns) 22 CHARGE PUMP CURRENT –0.8 5 Figure 26. Settling Time, (Fall) 24 –0.4 –0.3 OUTPUT Figure 23. Settling Time (Rise) 0 –0.2 INPUT POWER-DOWN VOLTAGE (V) 10 –0.1 0 –1.5 Figure 24. Charge Pump Voltage and Current vs. Supply Voltage TIME (400ns/DIV) Figure 27. Enable/Power-Down Time Rev. A | Page 10 of 16 07715-027 5 0 ERROR (%) 0 –0.2 0 0.1 –0.4 –0.8 –2.0 –5 0.2 ERROR 0.4 07715-026 –0.1 AMPLITUDE (V) 0 0 –0.4 ERROR (%) INPUT 07715-023 AMPLITUDE (V) OUTPUT Data Sheet ADA4859-3 –100 –105 –110 –110 –115 –115 POWER (dBm) –105 –120 –125 –130 –120 –125 –130 –135 –135 –140 –140 –145 –145 –150 –150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (MHz) 4.5 5.0 07715-100 POWER (dBm) VS = 3.3V CHARGE PUMP HARMONICS CHARGE PUMP HARMONICS Figure 28. Output Spectrum vs. Frequency Rev. A | Page 11 of 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FREQUENCY (MHz) Figure 29. Output Spectrum vs. Frequency 4.5 5.0 07715-101 –100 ADA4859-3 Data Sheet THEORY OF OPERATION OVERVIEW Φ1 +VS The ADA4859-3 is a fixed gain of two, current feedback amplifier designed for exceptional performance as a triple video amplifier. Its specifications make it especially suitable for SD and HD video applications. The ADA4859-3 provides HD video output on a single supply as low as 3.0 V while only consuming 13 mA per amplifier. It also features a power-down pin (PD) that reduces the quiescent current to 4 mA when activated. CHARGE PUMP OPERATION The on-board charge pump creates a negative supply for the amplifier. It provides different negative voltages depending on the power supply voltage. For a +5 V supply, the negative supply generated is equal to −3 V with 150 mA of output supply current, and for a +3.3 V supply, the negative supply is equal to −2 V with 45 mA of output supply current. Figure 30 shows the charging cycle when the supply voltage, +VS, charges C1 through Φ1 to ground. During this cycle, C1 quickly charges to reach the +VS voltage. The discharge cycle then begins with switching Φ1 off and switching Φ2 on, as shown in Figure 31. When C1 = C2, the charge in C1 is divided between the two capacitors and slowly increases the voltage in C2 until it reaches a predetermined voltage (−3 V for the +5 V supply and −2 V for the +3.3 V supply). The typical charge pump charging and discharging frequency is 550 kHz with a 150 Ω load and no input signal. This frequency changes with the load current, and it can get much slower if the amplifier is powered down and no external current is used. b C2 Φ1 07715-137 C1 CPO Figure 30. Charging Cycle a +VS Φ2 C1 CPO C2 Φ2 b 07715-138 The ADA4859-3 can be used in applications that require both ac- and dc-coupled inputs and outputs. The output stage on the ADA4859-3 is capable of driving 2 V p-p video signals into two doubly terminated video loads (150 Ω each) on a single 5 V supply. The input range of the ADA4859-3 includes ground, whereas the output range is limited by the output headroom set by the voltage drop across two diodes from each rail, which occurs 1.2 V from the positive and negative supply rails. a Figure 31. Discharging Cycle The ADA4859-3 specifications make it especially suitable for SD and HD video applications. It also allows dc-coupled video signal with its black level set to 0 V and its sync tip down to −300 mV for YPbPr video. The charge pump is always on, even when the power-down pin (PD) is enabled and the amplifier is off. However, it would be in an idle state if the negative current were not used. Each amplifier needs −6.3 mA of current, which totals −19 mA for all three amplifiers. This means additional negative current may be available by the charge pump for external use. Pin 4 (CPO) is the charge pump output, which provides access to the negative supply generated by the charge pump. Placing a 1 µF charge capacitor at the CPO pin is essential to hold the charge and regulate the ripple. If the negative supply is used to power another device in the system, it is only possible for the 5 V supply operation. In the 3.3 V supply operation, the charge pump output current is very limited. The capacitor at the CPO pin, which regulates the ripple of the negative voltage, can be used as a coupling capacitor for the external device. However, the charge pump current should be limited to a maximum of 50 mA for external use. When powering down the ADA4859-3, the charge pump is not affected and its output voltage and current remain available for external use. Rev. A | Page 12 of 16 Data Sheet ADA4859-3 APPLICATIONS INFORMATION USING THE ADA4859-3 IN GAINS EQUAL TO +1, −1 +VS 10µF The ADA4859-3 was designed to offer outstanding video performance, simplify applications, and minimize board area. 0.1µF The ADA4859-3 is a triple amplifier with on-chip feedback and gain set resistors. The gain is fixed internally at G = +2. The inclusion of the on-chip resistors not only simplifies the design of the application but also eliminates six surface-mount resistors, saving valuable board space and lowering assembly costs. Although the ADA4859-3 has a fixed gain of G = +2, it can be used in other gain configurations, such as G = −1 and G = +1. RF RG VOUT VIN 07715-131 RT GAIN OF +1 Figure 33. Unity Gain of Option 2 Inverting Unity-Gain Operation Unity-Gain Operation Option 1 There are two options for obtaining unity gain (G = +1). The first is shown in Figure 32. In this configuration, the −IN input pin is tied to the output. (Feedback is provided through the two internal 550 Ω resistors in parallel), and the input is applied to the noninverting input. The noise gain for this configuration is 1. In this configuration, the noninverting input is tied to ground and the input signal is applied to the inverting input. The noise gain for this configuration is +2, see Figure 34. +VS 10µF 0.01µF +VS 10µF VIN VOUT RT 07715-132 0.1µF GAIN OF –1 Figure 34. Inverting Configuration (G = −1) VOUT VIN Figure 35 shows the small signal frequency response for both gain of +1 (Option 1 and Option 2) and gain of −1 configurations. It is clear that the G = +1 Option 2 has better flatness and no peaking compared to Option 1. 07715-130 RT GAIN OF +1 Figure 32. Unity Gain of Option 1 Option 2 3 R + RG + V IN F RG 0 G = +1, OPTION 2 –3 G = –1 –6 VS = 5V VOUT = 2V p-p RL = 100Ω –9 (1) 1 10 100 FREQUENCY (MHz) Figure 35. Large Signal, G = +1 and G = −1 which simplifies to VOUT = VIN. Rev. A | Page 13 of 16 1000 07715-031 − RF VOUT = V IN RG G = +1, OPTION 1 CLOSED-LOOP GAIN (dB) Another option exists for running the ADA4859-3 as a unitygain amplifier. In this configuration, the noise gain is +2, see Figure 33. The frequency response and transient response for this configuration closely match the gain of +2 plots because the noise gains are equal. This method does have twice the noise gain of Option 1; however, in applications that do not require low noise, Option 2 offers less peaking and ringing. By tying the inputs together, the net gain of the amplifier becomes +1. Equation 1 shows the transfer characteristic for the schematic shown in Figure 33. ADA4859-3 Data Sheet VIDEO LINE DRIVER POWER-DOWN The ADA4859-3 was designed to excel in video driver applications. Figure 36 shows a typical schematic for a video driver operating on bipolar supplies. The ADA4859-3 is equipped with a PD (power-down) pin for all three amplifiers. This allows the user the ability to reduce the quiescent supply current when an amplifier is not active. The power-down threshold levels are derived from ground level. The amplifiers are powered down when the voltage applied to the PD pin is greater than a certain voltage from ground. In a 5 V supply application, the voltage is greater than 2 V, and in a 3.3 V supply application, the voltage is greater than 1.5 V. The amplifier is enabled whenever the PD pin is connected to ground. If the PD pin is not used, it is best to connect it to ground. Note that the power-down feature does not control the charge pump output voltage and current. VIN (R) 75Ω VOUT (R) 75Ω 16 15 14 13 12 1 2 1µF VIN (G) 75Ω 11 CHARGE PUMP 3 10 75Ω 4 9 VOUT (G) Table 5. Power-Down Voltage Control PD 1µF 10µF + 5 6 0.1µF 7 8 75Ω VIN (B) VOUT (B) 07715-134 +VS PD Pin Not Active Active 75Ω In applications that require multiple video loads be driven simultaneously, the ADA4859-3 can deliver. Figure 37 shows the ADA4859-3 configured with two video loads, and Figure 38 shows the large signal performance for multiple video loads. 10µF 75Ω 75Ω CABLE VOUT1 75Ω 0.1µF – 75Ω 75Ω CABLE 75Ω CABLE VOUT2 75Ω 07715-135 + VIN 75Ω Figure 37. Video Driver Schematic for Two Video Loads 6.5 5.5 5.0 RL = 150Ω 4.5 RL = 75Ω 4.0 3.5 As is the case with all high speed applications, careful attention to printed circuit board (PCB) layout details prevents associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane on all layers from the area near the input and output pins reduces stray capacitance. Locate termination resistors and loads as close as possible to their respective inputs and outputs. Keep input and output traces as far apart as possible to minimize coupling (crosstalk) through the board. Adherence to microstrip or stripline design techniques for long signal traces (greater than about 1 inch) is recommended. POWER SUPPLY BYPASSING Careful attention must be paid to bypassing the power supply pins of the ADA4859-3. Use high quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs), to minimize supply voltage ripple and power dissipation. A large, usually tantalum, 10 µF to 47 µF capacitor located in proximity to the ADA4859-3 is required to provide good decoupling for lower frequency signals. In addition, locate 0.1 µF MLCC decoupling capacitors as close to each of the power supply pins as is physically possible, no more than 1/8-inch away. The ground returns should terminate immediately into the ground plane. Locating the bypass capacitor return close to the load return minimizes ground loops and improves performance. 3.0 2.5 1 10 100 1000 FREQUENCY (MHz) 07715-034 CLOSED-LOOP GAIN (dB) 6.0 3.3 V <1 V >1.5 V LAYOUT CONSIDERATIONS Figure 36. Video Driver Schematic +VS 5V <1.5 V >2 V Figure 38. Large Signal Frequency Response for Various Loads Rev. A | Page 14 of 16 Data Sheet ADA4859-3 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 0.60 MAX 12° MAX 1.00 0.85 0.80 0.65 BSC TOP VIEW 3.75 BSC SQ 0.75 0.60 0.50 8 5 4 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 9 0.80 MAX 0.65 TYP 0.35 0.30 0.25 16 13 12 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072808-A PIN 1 INDICATOR (BOTTOM VIEW) COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 39.16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4859-3ACPZ-R2 ADA4859-3ACPZ-R7 ADA4859-3ACPZ-RL ADA4859-3ACP-EBZ 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 15 of 16 Package Option CP-16-4 CP-16-4 CP-16-4 Ordering Quantity 250 1,500 5,000 ADA4859-3 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07715-0-11/12(A) Rev. A | Page 16 of 16